Military 5.0V pASIC 1 Family Military 5.0V pASIC 1 Family - Very-High-Speed CMOS FPGA Military 5.0V pASIC 1 Family DEVICE HIGHLIGHTS FEATURES Device Highlights Features Very High Speed ■ ViaLink“ metal-to-metal programmable technology, allows counter speeds over 150 MHz and logic cell delays of under 2 ns at 5V, and over 80 MHz at 3.3V operation. High Usable Density ■ Up to a 24-by-32 array of 768 logic cells provides 22,000 usable PLD gates in 208-pin PQFP and 208-pin CQFP packages. PCI-Output Drive ■ Total of 180 I/O pins ■ Fully PCI 2.1 compliant input/output capability. (including drive current) Device ASIC Gates PLD Gates QL8x12B QL12x16B QL16x24B 1,000 2,000 4,000 2,000 4,000 7,000 QL24x32B 8,000 14,000 ■ -172 Bidirectional Input/Output pins ■ -6 Dedicated Input/High-Drive pins ■ -2 Clock/Dedicated input pins with fanoutindependent, low-skew clock networks ■ -PCI 2.1 Compliant I/Os ■ Input + logic cell + output delays under 6 ns ■ Chip-to-chip operating frequencies up to 110 MHz ■ Internal state machine frequencies up to 150 MHz ■ Clock skew < 0.5 ns ■ Input hysteresis provides high noise immunity ■ Built-in scan path permits 100% factory testing of logic and I/O cells and functional testing with Automatic Test Vector Generation (ATVG) software after programming ■ 208 pin PQFP pin for pin compatible with the 208 CQFP ■ 0.65µ CMOS process with ViaLink programming technology Package Max I/O Qualification Level SMD 5962- 68CPGA 84CPGA 144CPGA 160 CQFP 208CQFP 208PQFP 64 76 122 122 180 180 M M, /883 M, /883 M, /883 M, /883 M 96836 95599 95599 96837 M = Military Temperature (-55 to +125 degrees C) /883 = MIL-STD-883 qualified TABLE 1: Selector Table Rev B 8-7 Military 5.0V pASIC 1 Family PRODUCT SUMMARY Product Summary The pASIC 1 Family is a very-high-speed CMOS user-programmable ASIC devices. The 768 logic cell field-programmable gate array (FPGA) features 22,000 usable PLD gates of high-performance general-purpose logic in a 208-pin PQFP and CQFP package. Low-impedance, metal-to-metal, ViaLink interconnect technology provides nonvolatile custom logic capable of operating above 150 MHz. Logic cell delays under 2 ns, combined with input delays of under 1.5 ns and output delays under 3 ns, permit high-density programmable devices to be used with today’s fastest microprocessors and DSPs. Designs can be entered using QuickLogic’s QuickWorks Toolkit or most popular third-party CAE tools. QuickWorks combines Verilog/VHDL design entry and simulation tools with device-specific place & route and programming software. Ample on-chip routing channels allow fast, fully automatic place and route of designs using up to 100% of the logic and I/ O cells, while maintaining fixed pin-outs. PINOUT DIAGRAM 68-PIN CPGA Pinout Diagram 68-Pin CPGA PIN FUNC PIN FUNC PIN FUNC PIN B10 IO B2 IO K2 IO K10 IO A10 IO B1 IO L2 IO K11 IO B9 IO C2 IO K3 IO J10 IO A9 IO C1 IO L3 IO J11 IO B8 IO D2 IO K4 IO H10 IO A8 IO D1 IO L4 IO H11 IO B7 I/(SCLK) E2 IO K5 I/(SI) G10 IO A7 I/CLK/(SM) E1 IO L5 I/CLK G11 IO B6 VCC F2 GND K6 VCC F10 GND A6 I F1 IO L6 I F11 IO B5 I G2 IO K7 I/(SO) E10 IO A5 IO G1 IO L7 IO E11 IO B4 IO H2 IO K8 IO D10 IO A4 IO H1 IO L8 IO D11 IO B3 IO J2 IO K9 IO C10 IO A3 IO J1 IO L9 IO C11 IO A2 IO K1 IO L10 IO B11 IO TABLE 2: CPGA 68 Function/Connector Pin Table 8-8 8 FUNC Preliminary Military 5.0V pASIC 1 Family PINOUT DIAGRAM 84-PIN CPGA Pinout Diagram 84-pin CPGA PIN FUNC PIN FUNC PIN FUNC PIN FUNC B10 IO B2 IO K2 IO K10 IO B9 IO C2 IO K3 IO J10 IO A10 IO B1 IO L2 IO K11 IO A9 IO C1 IO L3 IO J11 IO B8 IO D2 IO K4 IO H10 IO A8 IO D1 IO L4 IO H11 IO A7 IO E1 IO L5 IO G11 IO C7 GND E3 GND J5 GND G9 GND A6 IO E2 IO L6 IO G10 IO B7 I/(SCLK) F1 IO K5 I/(SI) F11 IO C6 I/CLK/(SM) F2 IO J6 I/CLK F10 IO B6 I(P) F3 IO K6 I F9 IO B5 I G1 IO K7 I/(SO) E11 IO C5 VCC G3 VCC J7 VCC E9 VCC A5 IO G2 IO L7 IO E10 IO A4 IO H1 IO L8 IO D11 IO B4 IO H2 IO K8 IO D10 IO A3 IO J1 IO L9 IO C11 IO A2 IO K1 IO L10 IO B11 IO B3 IO J2 IO K9 IO C10 IO A1 IO L1 IO L11 IO A11 IO TABLE 3: CPGA 84 Function/Connector Pin Table 8-9 Military 5.0V pASIC 1 Family PINOUT DIAGRAM 144-PIN CPGA Pinout Diagram 144-pin CPGA PIN FUNC PIN FUNC PIN FUNC PIN FUNC A2 B3 C4 A3 B4 A4 C3 B5 A5 C6 B6 A6 A7 B7 C5 A8 B8 C8 C7 A9 B9 C11 A10 A11 B10 IO IO IO IO IO IO VCC IO IO IO IO IO IO IO GND IO I/(SCLK) I/CLK/(SM) VCC I/(P) I VCC IO IO IO B15 C14 D13 C15 D14 E13 D15 E14 E15 F13 F14 F15 G15 C13 G14 H15 H14 G13 H13 J15 J14 J13 K15 L15 K14 IO IO IO IO IO VCC IO IO IO IO IO IO IO GND IO IO IO GND IO IO IO VCC IO IO IO R14 P13 N12 R13 P12 R12 N13 P11 R11 N10 P10 R10 R9 P9 N11 R8 P8 N8 N9 R7 P7 N5 R6 R5 P6 IO IO IO IO IO IO VCC IO IO IO IO IO IO IO GND IO I/(SI) I/CLK VCC I I/(SO) VCC IO IO IO P1 N2 M3 N1 M2 L3 M1 L2 L1 K3 K2 K1 J1 N3 J2 H1 H2 J3 H3 G1 G2 G3 F1 E1 F2 IO IO IO IO IO VCC IO IO IO IO IO IO IO GND IO IO IO GND IO IO IO VCC IO IO IO TABLE 4: CPGA 144 Function/Connector Table (Cont’d on next page) 8-10 10 Preliminary Military 5.0V pASIC 1 Family CPGA 144 Function/Connector Table (Cont’d) A12 B11 C10 A13 C9 B12 A14 B13 C12 A15 B14 IO IO IO IO GND IO IO IO IO IO IO M15 L14 K13 N15 L13 M14 P15 N14 M13 R15 P14 IO IO IO IO GND IO IO IO IO IO nc R4 P5 N6 R3 N7 P4 R2 P3 N4 R1 P2 IO IO IO IO GND IO IO IO IO IO IO D1 E2 F3 C1 E3 D2 B1 C2 D3 A1 B2 IO IO IO IO GND IO IO IO IO IO nc PINOUT DIAGRAM 160-PIN CPGA QL16x24B-1CF160M 8-11 Military 5.0V pASIC 1 Family PINOUT DIAGRAM 208-PIN CPGA Pinout Diagram 208-pin CPGA Pin #157 Pin #1 pASIC QL24X32B-1PQ208M Pin #105 Pin #53 8-12 12 Preliminary Military 5.0V pASIC 1 Family PQFP/CQFP 208 FUNCTION/CONNECTOR TABLE PQFP/CQFP 208 Function/Connector Table PIN FUN PIN FUN PIN FUN PIN FUN PIN FUN PIN FUN PIN FUN PIN FUN 1 I/O 27 VCC 53 I/O 79 I/O 105 I/O 131 VCC 157 I/O 183 I/O 2 I/O 28 I/P 54 I/O 80 I/O 106 I/O 132 I 158 I/O 184 I/O 3 I/O 29 I 55 I/O 81 I/O 107 I/O 133 I/SO 159 I/O 185 I/O 4 I/O 30 VCC 56 I/O 82 I/O 108 I/O 134 VCC 160 I/O 186 I/O 5 I/O 31 I/O 57 I/O 83 VCC 109 I/O 135 I/O 161 I/O 187 VCC 6 I/O 32 I/O 58 I/O 84 I/O 110 I/O 136 I/O 162 I/O 188 I/O 7 I/O 33 I/O 59 GND 85 I/O 111 I/O 137 I/O 163 GND 189 I/O 8 I/O 34 I/O 60 I/O 86 I/O 112 I/O 138 I/O 164 I/O 190 I/O 9 I/O 35 I/O 61 VCC 87 I/O 113 I/O 139 I/O 165 VCC 191 I/O 10 VCC 36 I/O 62 I/O 88 I/O 114 VCC 140 I/O 166 I/O 192 I/O 11 I/O 37 I/O 63 I/O 89 I/O 115 I/O 141 I/O 167 I/O 193 I/O 12 GND 38 I/O 64 I/O 90 I/O 116 GND 142 I/O 168 I/O 194 I/O 13 I/O 39 I/O 65 I/O 91 I/O 117 I/O 143 I/O 169 I/O 195 I/O 14 I/O 40 I/O 66 I/O 92 I/O 118 I/O 144 I/O 170 I/O 196 I/O 15 I/O 41 VCC 67 I/O 93 I/O 119 I/O 145 VCC 171 I/O 197 I/O 16 I/O 42 I/O 68 I/O 94 I/O 120 I/O 146 I/O 172 I/O 198 I/O 17 I/O 43 GND 69 I/O 95 GND 121 I/O 147 GND 173 I/O 199 GND 18 I/O 44 I/O 70 I/O 96 I/O 122 I/O 148 I/O 174 I/O 200 I/O 19 I/O 45 I/O 71 I/O 97 VCC 123 I/O 149 I/O 175 I/O 201 VCC 20 I/O 46 I/O 72 I/O 98 I/O 124 I/O 150 I/O 176 I/O 202 I/O 21 I/O 47 I/O 73 GND 99 I/O 125 I/O 151 I/O 177 GND 203 I/O 22 I/O 48 I/O 74 I/O 100 I/O 126 I/O 152 I/O 178 I/O 204 I/O 23 GND 49 I/O 75 I/O 101 I/O 127 GND 153 I/O 179 I/O 205 I/O 24 I/O 50 I/O 76 I/O 102 I/O 128 I/O 154 I/O 180 I/O 206 I/O 25 I/Sck 51 I/O 77 I/O 103 I/O 129 I/SI 155 I/O 181 I/O 207 I/O 26 I/Clk 52 I/O 78 GND 104 I/O 130 I/Clk 156 I/O 182 GND 208 I/O 8-13 Military 5.0V pASIC 1 Family ABSOLUTE MAXIMUM RATINGS Supply Voltage ........................-0.5 to 7.0V Input Voltage................ -0.5 to VCC +0.5V ESD Pad Protection .................... ±2000V DC Input Current .......................±20 mA Latch-up Immunity .................. ±200 mA Storage Temperature .......-65°C to +150°C Lead Temperature ...........................300°C 5 Volt OPERATING RANGE Symbol VCC TA TC K Parameter Supply Voltage Ambient Temperature Case Temperature Delay Factor -0 Speed Grade -1 Speed Grade Military Min Max 4.5 5.5 -55 125 0.39 1.82 0.39 1.56 Unit V °C °C DC CHARACTERISTICS over 5V operating range Symbol VIH VIL Parameter Input HIGH Voltage Input LOW Voltage Conditions Min 2.0 Max 0.8 VOH Output HIGH Voltage VOL Output LOW Voltage II IOZ CI IOS Input Leakage Current 3-State Output Leakage Current Input Capacitance [1] Output Short Circuit Current [2] ICC D.C. Supply Current [3] IOH = -4 mA IOH = 16 mA IOH = -10 µA IOL = 8 mA IOL = 10 µA VI = VCC or GND VI = VCC or GND VO = GND VO = VCC VI, VIO = VCC or GND 3.7 2.4 VCC-0.1 -10 -10 -10 40 0.4 0.1 10 10 10 -90 160 20 Unit V V V V V V V µA µA pF mA mA mA Notes: [1] Capacitance is sample tested only. CI = 20 pF max on I/(SI). [2] Only one output at a time. Duration should not exceed 30 seconds. [3] Maximum Icc for military grade is 20 mA. For AC conditions use the formula described in the databook, Section 9 - Power vs Operating Frequency. [4] Stated timing for worst case Propagation Delay over process variation at VCC = 5.0V and TA = 25°C. Multiply by the appropriate Delay Factor, K, for speed grade, voltage and temperature settings as specified in the Operating Range. [5] These limits are derived from a representative selection of the slowest paths through the pASIC logic cell including net delays. Worst case delay values for specific paths should be determined from timing analysis of your particular design. 8-14 14 Preliminary Military 5.0V pASIC 1 Family QL8X12B QL8X12B AC CHARACTERISTICS at VCC = 5V, TA = 25°C (K = 1.00) Logic Cell Symbol tPD tSU tH tCLK tCWHI tCWLO tSET tRESET tSW tRW Parameter 1 1.7 2.1 0.0 1.0 2.0 2.0 1.7 1.5 1.9 1.8 Combinatorial Delay [5] Setup Time [5] Hold Time Clock to Q Delay Clock High Time Clock Low Time Set Delay Reset Delay Set Width Reset Width Propagation Delays (ns) Fanout 2 3 4 2.1 2.6 3.0 2.1 2.1 2.1 0.0 0.0 0.0 1.5 1.9 2.3 2.0 2.0 2.0 2.0 2.0 2.0 2.1 2.6 3.0 1.8 2.2 2.5 1.9 1.9 1.9 1.8 1.8 1.8 8 4.8 2.1 0.0 4.2 2.0 2.0 4.8 3.9 1.9 1.8 Input Cells Symbol tIN tINI tIO tGCK tGCKHI tGCKLO Propagation Delays (ns) [4] Parameter High Drive Input Delay [6] High Drive Input, Inverting Delay [6] Input Delay (bidirectional pad) Clock Buffer Delay [7] Clock Buffer Min High [7] Clock Buffer Min Low [7] 1 2.1 2.1 1.4 2.7 2.0 2.0 2 2.2 2.2 1.8 2.7 2.0 2.0 3 2.3 2.3 2.2 2.8 2.0 2.0 4 2.4 2.5 2.6 2.9 2.0 2.0 6 2.6 2.8 3.4 3.0 2.0 2.0 8 2.9 3.1 4.2 Output Cell Symbol tOUTLH tOUTHL tPZH tPZL tPHZ tPLZ Parameter Output Delay Low to High Output Delay High to Low Output Delay Tri-state to High Output Delay Tri-state to Low Output Delay High to Tri-state [8] Output Delay Low to Tri-state [8] 30 2.7 2.8 4.0 3.6 2.9 3.3 Propagation Delays (ns) [4] Output Load Capacitance (pF) 50 75 100 3.4 4.2 5.0 3.7 4.7 5.6 4.9 6.1 7.3 4.2 5.0 5.8 150 6.7 7.6 9.7 7.3 Notes: [6] See High Drive Buffer Table for more information. [7] Clock buffer fanout refers to the maximum number of flip flops per half column. The number of half columns used does not affect clock buffer delay. [8] The following loads are used for tPXZ: 8-15 Military 5.0V pASIC 1 Family High Drive Buffer Symbol Parameter tIN High Drive Input Delay tINI High Drive Input, Inverting Delay Clock Drivers Wired Together 1 2 3 4 1 2 3 4 Propagation Delays (ns) [4] Fanout 12 24 48 72 96 4.0 4.9 3.5 5.0 4.0 4.8 5.6 4.1 4.8 4.2 5.1 3.7 5.2 4.2 5.0 5.8 4.3 5.0 [4] Stated timing for worst case Propagation Delay over process variation at VCC = 5.0V and TA = 25°C. Multiply by the appropriate Delay Factor, K, for speed grade, voltage and temperature settings as specified in the Operating Range. 8-16 16 Preliminary Military 5.0V pASIC 1 Family QL12x16B QL12X16B AC CHARACTERISTICS at VCC = 5V, TA = 25°C (K = 1.00) Logic Cell Symbol tPD tSU tH tCLK tCWHI tCWLO tSET tRESET tSW tRW Parameter 1 1.7 2.1 0.0 1.0 2.0 2.0 1.7 1.5 1.9 1.8 Combinatorial Delay [5] Setup Time [5] Hold Time Clock to Q Delay Clock High Time Clock Low Time Set Delay Reset Delay Set Width Reset Width Propagation Delays (ns) Fanout 2 3 4 2.2 2.6 3.2 2.1 2.1 2.1 0.0 0.0 0.0 1.5 1.9 2.5 2.0 2.0 2.0 2.0 2.0 2.0 2.1 2.6 3.2 1.9 2.2 2.7 1.9 1.9 1.9 1.8 1.8 1.8 8 5.2 2.1 0.0 4.6 2.0 2.0 5.2 4.3 1.9 1.8 Input Cells Symbol tIN tINI tIO tGCK tGCKHI tGCKLO Propagation Delays (ns) [4] Parameter High Drive Input Delay [6] High Drive Input, Inverting Delay [6] Input Delay (bidirectional pad) Clock Buffer Delay [7] Clock Buffer Min High [7] Clock Buffer Min Low [7] 1 2.4 2.5 1.4 2.7 2.0 2.0 2 2.5 2.6 1.9 2.8 2.0 2.0 3 2.6 2.7 2.2 2.8 2.0 2.0 4 2.7 2.8 2.8 2.9 2.0 2.0 6 3.0 3.1 3.7 2.9 2.0 2.0 8 3.3 3.4 4.6 3.0 2.0 2.0 Output Cell Symbol tOUTLH tOUTHL tPZH tPZL tPHZ tPLZ Parameter Output Delay Low to High Output Delay High to Low Output Delay Tri-state to High Output Delay Tri-state to Low Output Delay High to Tri-state [8] Output Delay Low to Tri-state [8] 30 2.7 2.8 4.0 3.6 2.9 3.3 Propagation Delays (ns) [4] Output Load Capacitance (pF) 50 75 100 3.4 4.2 5.0 3.7 4.7 5.6 4.9 6.1 7.3 4.2 5.0 5.8 150 6.7 7.6 9.7 7.3 Notes: [6] See High Drive Buffer Table for more information. [7] Clock buffer fanout refers to the maximum number of flip flops per half column. The number of half columns used does not affect clock buffer delay. [8] The following loads are used for tPXZ: 8-17 Military 5.0V pASIC 1 Family High Drive Buffer Symbol Parameter tIN High Drive Input Delay tINI High Drive Input, Inverting Delay Clock Drivers Wired Together 1 2 3 4 1 2 3 4 Propagation Delays (ns) [4] Fanout 12 24 48 72 96 4.5 5.4 3.9 5.6 4.5 5.3 6.3 4.6 5.3 4.7 5.6 4.0 5.8 4.6 5.5 6.4 4.8 5.5 [4] Stated timing for worst case Propagation Delay over process variation at VCC = 5.0V and TA = 25°C. Multiply by the appropriate Delay Factor, K, for speed grade, voltage and temperature settings as specified in the Operating Range. 8-18 18 Preliminary Military 5.0V pASIC 1 Family QL16x24B QL16X24B AC CHARACTERISTICS at VCC = 5V, TA = 25°C (K = 1.00) Logic Cell Symbol tPD tSU tH tCLK tCWHI tCWLO tSET tRESET tSW tRW Parameter 1 1.7 2.1 0.0 1.0 2.0 2.0 1.7 1.5 1.9 1.8 Combinatorial Delay [5] Setup Time [5] Hold Time Clock to Q Delay Clock High Time Clock Low Time Set Delay Reset Delay Set Width Reset Width Propagation Delays (ns) Fanout 2 3 4 2.2 2.6 3.2 2.1 2.1 2.1 0.0 0.0 0.0 1.5 1.9 2.6 2.0 2.0 2.0 2.0 2.0 2.0 2.2 2.6 3.2 1.9 2.2 2.7 1.9 1.9 1.9 1.8 1.8 1.8 8 5.3 2.1 0.0 4.7 2.0 2.0 5.3 4.4 1.9 1.8 Input Cells Symbol tIN tINI tIO tGCK tGCKHI tGCKLO Propagation Delays (ns) [4] Parameter High Drive Input Delay [6] High Drive Input, Inverting Delay [6] Input Delay (bidirectional pad) Clock Buffer Delay [7] Clock Buffer Min High [7] Clock Buffer Min Low [7] 1 2.8 3.0 1.4 2.7 2.0 2.0 2 2.9 3.1 1.9 2.8 2.0 2.0 3 3.0 3.2 2.2 2.9 2.0 2.0 4 3.1 3.3 2.9 3.0 2.0 2.0 6 4.0 4.1 4.7 3.1 2.0 2.0 8 5.3 5.7 6.5 3.3 2.0 2.0 Output Cell Symbol tOUTLH tOUTHL tPZH tPZL tPHZ tPLZ Parameter Output Delay Low to High Output Delay High to Low Output Delay Tri-state to High Output Delay Tri-state to Low Output Delay High to Tri-state [8] Output Delay Low to Tri-state [8] 30 2.7 2.8 4.0 3.6 2.9 3.3 Propagation Delays (ns) [4] Output Load Capacitance (pF) 50 75 100 3.4 4.2 5.0 3.7 4.7 5.6 4.9 6.1 7.3 4.2 5.0 5.8 150 6.7 7.6 9.7 7.3 Notes: [6] See High Drive Buffer Table for more information. [7] Clock buffer fanout refers to the maximum number of flip flops per half column. The number of half columns used does not affect clock buffer delay. [8] The following loads are used for tPXZ: 8-19 Military 5.0V pASIC 1 Family High Drive Buffer Symbol Parameter tIN High Drive Input Delay tINI High Drive Input, Inverting Delay Clock Drivers Wired Together 1 2 3 4 1 2 3 4 Propagation Delays (ns) [4] Fanout 12 24 48 72 96 5.3 6.7 4.5 6.6 5.3 6.2 7.2 5.4 6.2 5.7 7.2 4.6 6.8 5.5 6.4 7.4 5.6 6.4 [4] Stated timing for worst case Propagation Delay over process variation at VCC = 5.0V and TA = 25°C. Multiply by the appropriate Delay Factor, K, for speed grade, voltage and temperature settings as specified in the Operating Range. 8-20 20 Preliminary Military 5.0V pASIC 1 Family QL24x32B QL24X32B AC CHARACTERISTICS at VCC = 5V, TA = 25°C (K = 1.00) Logic Cell Symbol tPD tSU tH tCLK tCWHI tCWLO tSET tRESET tSW tRW Parameter 1 1.7 2.1 0.0 1.0 2.0 2.0 1.7 1.5 1.9 1.8 Combinatorial Delay [5] Setup Time [5] Hold Time Clock to Q Delay Clock High Time Clock Low Time Set Delay Reset Delay Set Width Reset Width Propagation Delays (ns) Fanout 2 3 4 2.1 2.7 3.3 2.1 2.1 2.1 0.0 0.0 0.0 1.5 1.9 2.7 2.0 2.0 2.0 2.0 2.0 2.0 2.2 2.7 3.3 1.9 2.3 2.8 1.9 1.9 1.9 1.8 1.8 1.8 8 5.5 2.1 0.0 4.9 2.0 2.0 5.5 4.6 1.9 1.8 Input Cells Symbol tIN tINI tIO tGCK tGCKHI tGCKLO Propagation Delays (ns) [4] Parameter High Drive Input Delay [6] High Drive Input, Inverting Delay [6] Input Delay (bidirectional pad) Clock Buffer Delay [7] Clock Buffer Min High [7] Clock Buffer Min Low [7] 1 3.1 3.3 1.4 2.7 2.0 2.0 2 3.2 3.4 1.9 2.8 2.0 2.0 3 3.3 3.5 2.3 2.9 2.0 2.0 4 3.4 3.6 3.0 3.0 2.0 2.0 8 4.4 4.6 4.8 3.1 2.0 2.0 12 5.8 6.0 6.7 3.3 2.0 2.0 16 6.5 6.7 8.5 3.4 2.0 2.0 Output Cell Symbol tOUTLH tOUTHL tPZH tPZL tPHZ tPLZ Parameter Output Delay Low to High Output Delay High to Low Output Delay Tri-state to High Output Delay Tri-state to Low Output Delay High to Tri-state [8] Output Delay Low to Tri-state [8] 30 2.7 2.8 2.1 2.6 2.9 3.3 Propagation Delays (ns) [4] Output Load Capacitance (pF) 50 75 100 3.3 3.8 4.3 3.6 4.5 5.3 2.6 3.1 3.7 3.3 4.1 4.9 150 5.4 6.9 4.8 6.5 Notes: [6] See High Drive Buffer Table for more information. [7] Clock buffer fanout refers to the maximum number of flip flops per half column. The number of half columns used does not affect clock buffer delay. [8] The following loads are used for tPXZ: 8-21 Military 5.0V pASIC 1 Family High Drive Buffer Clock Drivers Wired Together Symbol Parameter tIN High Drive Input Delay tINI High Drive Input, Inverting Delay 1 2 3 4 1 2 3 4 Propagation Delays (ns) [4] Fanout 12 24 48 72 96 5.8 7.2 5.0 7.1 5.8 6.7 7.7 5.9 6.8 6.0 7.4 5.2 7.3 6.0 6.9 7.9 6.1 7.0 [4] Stated timing for worst case Propagation Delay over process variation at VCC = 5.0V and TA = 25°C. Multiply by the appropriate Delay Factor, K, for speed grade, voltage and temperature settings as specified in the Operating Range. AC Performance Propagation delays depend on routing, fanout, load capacitance, supply voltage, junction temperature, and process variation. The AC Characteristics are a design guide to provide initial timing estimates at nominal conditions. Worst case estimates are obtained when nominal propagation delays are multiplied by the appropriate Delay Factor, K, as specified in the Delay Factor table (Operating Range). The effects of voltage and temperature variation are illustrated in the graphs on the following pages, K Factor versus Voltage and Temperature. The pASIC Development Tools incorporate data sheet AC Characteristics into the QDIF database for pre-place-and-route timing analysis. The SpDE Delay Modeler extracts specific timing parameters for precise path analysis or simulation results following place and route. ORDERING INFORMATION QL 24x32B - 1 CF208 M QuickLogic pASIC device Operating Range M = Military M/883C = MIL STD 883 pASIC device part number B = 0.65 micron CMOS 8x12B 12x16B 16x24B 24x32B Package Code CG68 = 68-pin CPGA CG84 = 84-pin CPGA CG144 = 144-pin CPGA CF160 = 160-pin CQFD PQ208 = 208-pin PQFP CF208 = 208-pin CQFP Speed Grade 0 = fast 1 = faster 8-22 22 Preliminary