QL2007 3.3V and 5.0V pASIC 2 FPGA Combining Speed, Density, Low Cost and Flexibility Rev. E pASIC 2 HIGHLIGHTS Ultimate Verilog/VHDL Silicon Solution -Abundant, high-speed interconnect eliminates manual routing -Flexible logic cell provides high efficiency and performance -Design tools produce fast, efficient Verilog/VHDL synthesis Speed, Density, Low Cost and Flexibility in One Device Advanced Logic Cell and I/O Capabilities -Complex functions (up to 16 inputs) in a single logic cell -High synthesis gate utilization from logic cell fragments -Full IEEE Standard JTAG boundary scan capability -Individually-controlled input/feedback registers and OEs on all I/O pins Other Important Family Features -3.3V and 5.0V operation with low standby power -I/O pin-compatibility between different devices in the same packages -PCI compliant (at 5.0V), full speed 33 MHz implementations -High design security provided by security fuses QL2007 Block Diagram 480 Logic Cells 3-25 3 pASIC 2 … 7,000 usable ASICgates, 174 I/O pins -16-bit counter speeds exceeding 200 MHz -7,000 usable ASIC gates, 11,000 usable PLD gates, 174 I/Os -3-layer metal ViaLink process for small die sizes -100% routable and pin-out maintainable QL2007 PRODUCT SUMMARY The QL2007 is a 7,000 usable ASIC gate, 11,000 usable PLD gate member of the pASIC 2 family of FPGAs. pASIC 2 FPGAs employ a unique combination of architecture, technology, and software tools to provide high speed, high usable density, low price, and flexibility in the same devices. The flexibility and speed make pASIC 2 devices an efficient and high performance silicon solution for designs described using HDLs such as Verilog and VHDL, as well as schematics. The QL2007 contains 480 logic cells. With 174 maximum I/Os, the QL2007 is available in 84-pin PLCC, 144-pin TQFP, and 208-pin PQFP packages. Software support for the complete pASIC families, including the QL2007, is available through three basic packages. The turnkey QuickWorks package provides the most complete FPGA software solution from design entry to logic synthesis (by Synplicity, Inc.), to place and route, to simulation. The QuickToolsTM and QuickChipTM packages provide a solution for designers who use Cadence, Mentor, Synopsys, Viewlogic, Veribest, or other thirdparty tools for design entry, synthesis, or simulation. FEATURES Total of 174 I/O Pins - 166 bidirectional input/output pins, PCI-compliant at 5.0V in -1/-2 speed grades - 4 high-drive input-only pins - 4 high-drive input/distributed network pins Four Low-Skew (less than 0.5ns) Distributed Networks - Two array networks available to logic cell flip-flop clock, set, and reset - each driven by an input-only pin - Two global clock/control networks available to F1 logic input, and logic cell flip-flop clock, set, reset; input and I/O register clock, reset, enable; and output enable controls - each driven by an input-only pin, or any input or I/O pin, or any logic cell output or I/O cell feedback High Performance - Input + logic cell + output delays under 6 ns - Datapath speeds exceeding 225 MHz - Counter speeds over 200 MHz 3-26 QL2007 PINOUT DIAGRAM 84-PIN PLCC 3 pASIC 2 3-27 QL2007 PINOUT DIAGRAMS PIN # 109 PIN # 1 144-PIN TQFP pASIC QL2007-1PF144C PIN # 73 PIN # 37 208-PIN PQFP PIN # 157 PIN # 1 pASIC QL2007-1PQ208C PIN # 105 PIN # 53 3-28 QL2007 PQFP 208 and TQFP 144 Pinout Table 208 144 PQFP TQFP Function 208 144 PQFP TQFP Function 208 144 PQFP TQFP Function 208 144 PQFP TQFP Function NC 1 2 3 NC 4 5 NC 6 7 NC NC 8 NC 9 NC 10 11 12 13 NC 14 15 16 17 18 19 20 21 22 23 NC 24 NC 25 NC 26 27 28 NC I/O I/O I/O I/O I/O I/O I/O I/O I/O VCC I/O GND I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O GND I/O I ACLK / I VCC I GCLK / I VCC I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 30 31 NC 32 33 34 NC 35 36 NC 37 38 39 NC 40 NC NC 41 42 43 NC 44 45 NC 46 47 48 NC 49 NC 50 51 52 NC 53 54 55 56 NC 57 GND I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O TDI I/O I/O I/O I/O GND I/O VCC I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O GND I/O I/O I/O I/O GND I/O I/O I/O I/O 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 60 61 NC 62 63 NC NC 64 NC 65 66 67 NC NC 68 69 NC 70 71 72 NC 73 NC 74 75 76 77 NC 78 79 80 NC 81 82 NC 83 NC 84 85 NC I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O GND I/O VCC I/O I/O I/O I/O I/O TRSTB TMS I/O I/O I/O I/O I/O I/O I/O I/O I/O VCC I/O GND I/O I/O I/O I/O I/O I/O I/O I/O 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 87 88 89 90 91 92 93 94 95 NC 96 NC 97 98 NC 99 NC 100 NC 101 102 103 104 105 106 NC 107 NC 108 NC 109 110 111 NC 112 113 NC NC 114 115 GND I/O I ACLK / I VCC I GCLK / I VCC I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O VCC I/O GND I/O I/O I/O I/O I/O I/O I/O I/O I/O TCK STM I/O I/O I/O I/O GND I/O VCC I/O 41 42 NC 29 VCC I/O 83 84 58 59 VCC I/O 125 126 86 NC I/O I/O 167 168 116 NC I/O I/O 3-29 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 117 118 119 120 NC NC 121 NC 122 123 124 NC 125 126 127 128 129 NC 130 131 132 NC 133 134 NC 135 136 NC 137 NC 138 139 NC 140 NC 141 142 NC 143 144 Function I/O I/O I/O I/O I/O I/O I/O I/O GND I/O I/O I/O I/O GND I/O I/O I/O I/O VCC I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O GND I/O VCC I/O I/O I/O I/O I/O TDO I/O 3 pASIC 2 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 208 144 PQFP TQFP QL2007 PIN DESCRIPTIONS Pin TDI Function Test Data In for JTAG TRSTB Active low Reset for JTAG TMS Test Mode Select for JTAG TCK Test Clock for JTAG TDO Test data out for JTAG Description Hold HIGH during normal operation. Connect to VCC if not used for JTAG. Hold LOW during normal operation. Connect to ground if not used for JTAG. Hold HIGH during normal operation. Connect to VCC if not used for JTAG. Hold HIGH or LOW during normal operation. Connect to VCC or ground if not used for JTAG. Output that must be left unconnected if not used for JTAG. STM Special Test Mode Must be grounded during normal operation. I/ACLK Can be configured as either or both. I High-drive input and/or array network driver High-drive input and/or global network driver High-drive input Use for input signals with high fanout. I/O Input/Output pin Can be configured as an input and/or output. I/GCLK Can be configured as either or both. VCC Power supply pin Connect to 3.3V supply. GND Ground pin Connect to ground. ORDERING INFORMATION QL 2007 - 1 PQ208 C QuickLogic pASIC device Operating Range C = Commercial I = Industrial pASIC 2 device part number Package Code PL84 = 84-pin PLCC PF144 = 144-pin TQFP PQ208 = 208-pin PQFP Speed Grade X = quick 0 = fast 1 = faster 2 = fastest 3-30 QL2007 ABSOLUTE MAXIMUM RATINGS Supply Voltage ……………….. -0.5 to 7.0V Input Voltage ……….… -0.5 to VCC +0.5V ESD Pad Protection ….…………… ±2000V DC Input Current ….……………… ±20 mA Latch-up Immunity ………………. ±200 mA Storage Temperature……..…….. -65°C to + 150°C Lead Temperature ………….………………. 300°C 5 Volt OPERATING RANGE Symbol Supply Voltage Ambient Temperature Case Temperature -X Speed Grade Delay Factor -0 Speed Grade -1 Speed Grade -2 Speed Grade K Industrial Min Max 4.5 5.5 -40 85 Commercial Min Max 4.75 5.25 0 70 0.4 0.4 0.4 0.4 0.46 0.46 0.46 0.46 2.75 2.00 1.61 1.35 3 Unit V °C °C pASIC 2 VCC TA TC Parameter 2.55 1.85 1.50 1.25 DC CHARACTERISTICS over 5V operating range Symbol VIH VIL Parameter Input HIGH Voltage Input LOW Voltage VOH Output HIGH Voltage VOL Output LOW Voltage II IOZ CI IOS Input Leakage Current 3-State Output Leakage Current Input Capacitance [2] Output Short Circuit Current [3] ICC D.C. Supply Current [4] Conditions Min 2.0 Max 0.8 IOH = -4 mA IOH = -24 mA/-16 mA [1] IOH = -10 µA IOL = 24 mA/16 mA [1] IOL = 10 µA VI = VCC or GND VI = VCC or GND VO = GND VO = VCC VI, VIO = VCC or GND 3.7 2.4 VCC-0.1 -10 -10 -15 40 2 (typ) 0.45 0.1 10 10 10 -120 210 10 Unit V V V V V V V µA µA pF mA mA mA Notes: [1] [2] [3] [4] -24 mA IOH and 24 mA IOL apply only to -1/-2 commercial grade devices. These speed grades are also PCI-compliant. All other devices have -16 mA IOH and 16 mA IOL specifications. Capacitance is sample tested only. Only one output at a time. Duration should not exceed 30 seconds. For -0/-1/-2 commercial grade devices only. Maximum ICC is 20 mA for -X commercial grade devices and 15mA for all industrial grade devices. For AC conditions, contact QuickLogic customer engineering. 3-31 QL2007 3.3 Volt OPERATING RANGE Symbol VCC TA Parameter Supply Voltage Ambient Temperature -0 Speed Grade Delay Factor -1 Speed Grade -2 Speed Grade K Industrial Min Max 3.0 3.6 -40 85 0.56 2.74 0.56 2.21 0.56 1.85 Commercial Min Max 3.0 3.6 0 70 0.61 2.65 0.61 2.14 0.61 1.79 Unit V °C DC CHARACTERISTICS over 3.3V operating range Symbol VIH VIL VOH Parameter Input HIGH Voltage Input LOW Voltage Output HIGH Voltage VOL Output LOW Voltage IIH II IOZ CI IOS Input High Current Sink (for tolerance to 5V devices) Input Leakage Current 3-State Output Leakage Current Input Capacitance [5] Output Short Circuit Current [6] ICC D.C. Supply Current [7] Conditions Min 2.0 Max 0.4 0.1 12 Unit V V V V V V mA 10 10 10 -70 130 3 µA µA pF mA mA mA 0.8 IOH = -2.4 mA IOH = -10 µA IOL = 4 mA IOL = 10 µA 5.5V > VI > VCC 2.4 VCC-0.1 VI = VCC or GND VI = VCC or GND -10 -10 VO = GND VO = VCC VI, VIO = VCC or GND -10 25 0.5 (typ) Notes: [5] [6] [7] Capacitance is sample tested only. Only one output at a time. Duration should not exceed 30 seconds. For commercial grade devices only. Maximum ICC is 5 mA for all industrial grade devices. For AC conditions, contact QuickLogic customer engineering. 3-32 QL2007 AC CHARACTERISTICS at VCC = 5V, TA = 25°°C (K = 1.00) Propagation delays depend on routing, fanout, load capacitance, supply voltage, junction temperature, and process variation. The AC Characteristics are a design guide to provide initial timing estimates at nominal conditions. Worst case estimates are obtained when nominal propagation delays are multiplied by the appropriate Delay Factor, K, as specified in the Delay Factor table (Operating Range). The QuickChip/QuickTools/QuickWorks software incorporates data sheet AC Characteristics into the design database for precise path analysis or simulation results following place and route. Logic Cells Symbol Combinatorial Delay [9] Setup Time [9] Hold Time Clock to Q Delay Clock High Time Clock Low Time Set Delay Reset Delay Set Width Reset Width 1 1.4 1.8 0.0 0.8 2.0 2.0 1.4 1.2 1.9 1.8 3 8 3.5 1.8 0.0 2.9 2.0 2.0 3.5 3.3 1.9 1.8 Input-Only Cells Symbol tIN tINI tISU tIH tlCLK tlRST tlESU tlEH Parameter High Drive Input Delay High Drive Input, Inverting Delay Input Register Set-Up Time Input Register Hold Time Input Register Clock To Q Input Register Reset Delay Input Register clock Enable Set-Up Time Input Register Clock Enable Hold Time 1 2.5 2.6 4.8 0.0 0.9 0.8 4.1 0.0 Propagation Delays (ns) Fanout [8] 2 3 4 8 12 2.6 2.6 2.7 3.5 4.6 2.7 2.7 2.8 3.6 4.7 4.8 4.8 4.8 4.8 4.8 0.0 0.0 0.0 0.0 0.0 1.0 1.0 1.1 1.9 3.0 0.9 0.9 1.0 1.8 2.9 4.1 4.1 4.1 4.1 4.1 0.0 0.0 0.0 0.0 0.0 24 5.8 5.9 4.8 0.0 4.2 4.1 4.1 0.0 Notes: [8] [9] Stated timing for worst case Propagation Delay over process variation at VCC=5.0V and TA=25°C. Multiply by the appropriate Delay Factor, K, for speed grade, voltage and temperature settings as specified in the Operating Range. These limits are derived from a representative selection of the slowest paths through the pASIC 2 logic cell including typical net delays. Worst case delay values for specific paths should be determined from timing analysis of your particular design. 3-33 pASIC 2 tPD tSU tH tCLK tCWHI tCWLO tSET tRESET tSW tRW Propagation Delays (ns) Fanout [8] 2 3 4 1.7 2.0 2.3 1.8 1.8 1.8 0.0 0.0 0.0 1.1 1.4 1.7 2.0 2.0 2.0 2.0 2.0 2.0 1.7 2.0 2.3 1.5 1.8 2.1 1.9 1.9 1.9 1.8 1.8 1.8 Parameter QL2007 Clock Cells Symbol tACK tGCKP tGCKB Parameter 1 2.2 1.2 1.5 Array Clock Delay Global Clock Pin Delay Global Clock Buffer Delay Propagation Delays (ns) Loads per Half Column [10] 2 3 4 8 10 2.2 2.3 2.4 2.5 2.6 1.2 1.2 1.2 1.2 1.2 1.6 1.6 1.7 1.8 1.9 13 1.2 2.0 I/O Cells Symbol Parameter tI/O tISU tIH tlOCLK tlORST tlESU tlEH Input Delay (bidirectional pad) Input Register Set-Up Time Input Register Hold Time Input Register Clock To Q Input Register Reset Delay Input Register clock Enable Set-Up Time Input Register Clock Enable Hold Time Symbol Parameter tOUTLH tOUTHL tPZH tPZL tPHZ tPLZ 1 1.8 4.8 0.0 0.8 0.7 4.1 0.0 30 2.6 2.8 2.1 2.6 2.9 3.3 Output Delay Low to High Output Delay High to Low Output Delay Tri-state to High Output Delay Tri-state to Low Output Delay High to Tri-State [11] Output Delay Low to Tri-State [11] Propagation Delays (ns) Fanout [8] 2 3 4 8 2.1 2.4 2.7 3.9 4.8 4.8 4.8 4.8 0.0 0.0 0.0 0.0 1.1 1.4 1.7 2.9 1.0 1.3 1.6 2.8 4.1 4.1 4.1 4.1 0.0 0.0 0.0 0.0 10 4.6 4.8 0.0 3.6 3.5 4.1 0.0 Propagation Delays (ns) Output Load Capacitance (pF) 50 75 100 3.0 3.6 4.1 3.3 3.9 4.5 2.6 3.1 3.7 3.3 4.1 4.9 150 5.2 5.7 4.8 6.5 Notes: [10] The array distributed networks consist of 48 half columns and the global distributed networks consist of 52 half columns, each driven by an independent buffer. The number of half columns used does not affect clock buffer delay. The array clock has up to 10 loads per half column. The global clock has up to 13 loads per half column. [11] The following loads are used for tPXZ: tPHZ 1KΩ 5 pF 1KΩ tPLZ 5 pF 3-34