ETC SPFD54126B

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Evaluation Only. Created with Aspose.Pdf.Kit. Copyright 2002-2005 Aspose Pty Ltd
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SPFD54126B
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528-channel 6-bit Source Driver with
System-on-chip for Color
Amorphous TFT-LCDs
Preliminary
NOV. 20, 2006
Version 0.2
ORISE Technology reserves the right to change this documentation without prior notice. Information provided by ORISE Technology is believed to be
accurate and reliable. However, ORISE Technology makes no warranty for any errors which may appear in this document.
Contact ORISE Technology to
obtain the latest version of device specifications before placing your order. No responsibility is assumed by ORISE Technology for any infringement of patent
or other rights of third parties which may result from its use. In addition, ORISE products are not authorized for use as critical components in life support
devices/ systems or aviation devices/systems, where a malfunction or failure of the product may reasonably be expected to result in significant injury to the
user, without the express written approval of ORISE.
Evaluation Only. Created with Aspose.Pdf.Kit. Copyright 2002-2005 Aspose Pty Ltd
Preliminary
SPFD54126B
Table of Contents
PAGE
TABLE OF CONTENTS .......................................................................................................................................................................................... 2
1. GENERAL DESCRIPTION .......................................................................................................................................................................... 6
2. FEATURE .................................................................................................................................................................................................... 6
3. ORDERING INFORMATION........................................................................................................................................................................ 6
4. BLOCK DIAGRAM ...................................................................................................................................................................................... 7
4.1. BLOCK FUNCTION .................................................................................................................................................................................. 7
4.1.1. System Interface ....................................................................................................................................................................... 8
4.1.2. External Display Interface ......................................................................................................................................................... 8
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4.1.3. Address Counter (AC)............................................................................................................................................................... 8
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4.1.4. Graphics RAM (GRAM) ............................................................................................................................................................ 8
4.1.5. Grayscale Voltage Generating Circuit....................................................................................................................................... 8
4.1.6. Timing Controller....................................................................................................................................................................... 8
4.1.7. Oscillator (OSC) ........................................................................................................................................................................ 8
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4.1.8. Source Driver Circuit................................................................................................................................................................. 8
4.1.9. Gate Driver Circuit .................................................................................................................................................................... 9
LCD Driving Power Supply Circuit........................................................................................................................................ 9
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4.1.10.
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5. SIGNAL DESCRIPTIONS.......................................................................................................................................................................... 10
6. INSTRUCTIONS ........................................................................................................................................................................................ 15
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6.1. OUTLINE .............................................................................................................................................................................................. 15
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6.1.1. System Function Command List and Description ................................................................................................................... 15
6.1.2. Panel Function Command List and Description...................................................................................................................... 18
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6.2. SYSTEM COMMAND DESCRIPTION ........................................................................................................................................................ 23
6.2.1. NOP (00h) ............................................................................................................................................................................... 23
6.2.2. SWRESET (01h): Software Reset .......................................................................................................................................... 24
6.2.3. RDDID (04H): Read Display ID............................................................................................................................................... 25
6.2.4. RDDST (09H): Read Display Status ....................................................................................................................................... 26
6.2.5. RDDPM (0AH): Read Display Power Mode............................................................................................................................ 28
6.2.6. RDDMADCTR (0BH): Read Display MADCTR....................................................................................................................... 29
6.2.7. RDDCOLMOD (0CH): Read Display Pixel Format ................................................................................................................. 30
6.2.8. RDDIM (0DH): Read Display Image Mode ............................................................................................................................. 31
6.2.9. RDDSM (0EH): Read Display Signal Mode ............................................................................................................................ 32
6.2.10.
RDDSDR (0FH): Read Display Self-Diagnostic Result ...................................................................................................... 33
6.2.11.
SLPIN (10H): Sleep In ........................................................................................................................................................ 34
6.2.12.
SLPOUT (11H): Sleep Out ................................................................................................................................................. 36
6.2.13.
PTLON (12H): Partial Display Mode On............................................................................................................................. 38
6.2.14.
NORON (13H): Normal Display Mode On .......................................................................................................................... 39
6.2.15.
INVOFF (20H): Display Inversion Off ................................................................................................................................. 40
6.2.16.
INVON (21H): Display Inversion On ................................................................................................................................... 41
6.2.17.
GAMSET (26H): Gamma Set ............................................................................................................................................. 42
6.2.18.
DISPOFF (28H): Display Off .............................................................................................................................................. 43
6.2.19.
DISPON (29H): Display On ................................................................................................................................................ 45
6.2.20.
CASET (2AH): Column Address Set .................................................................................................................................. 47
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Preliminary
SPFD54126B
RASET (2BH): Row Address Set........................................................................................................................................ 49
6.2.22.
RAMWR (2CH): Memory Write........................................................................................................................................... 51
6.2.23.
RGBSET (2DH): Colour Setting ......................................................................................................................................... 53
6.2.24.
RAMHD (2EH): Memory Read ........................................................................................................................................... 54
6.2.25.
PTLAR (30H): Partial Area ................................................................................................................................................. 55
6.2.26.
SCRLAR (33H): Scroll Area................................................................................................................................................ 58
6.2.27.
TEOFF (34H): Tearing Effect Line OFF.............................................................................................................................. 62
6.2.28.
TEON (35H): Tearing Effect Line ON ................................................................................................................................. 63
6.2.29.
MADCTR (36H): Memory Data Access Control.................................................................................................................. 64
6.2.30.
VSCSAD (37H): Vertical Scroll Start Address of RAM ....................................................................................................... 66
6.2.31.
IDMOFF (38H): Idle Mode Off ............................................................................................................................................ 68
6.2.32.
IDMON (39H): Idle Mode On .............................................................................................................................................. 69
6.2.33.
COLMOD (3AH): Interface Pixel Format ............................................................................................................................ 71
6.2.34.
RDID1 (DAH): Read ID1 Value........................................................................................................................................... 72
6.2.35.
RDID2 (DBH): Read ID2 Value........................................................................................................................................... 73
6.2.36.
RDID3 (DCH): Read ID3 Value .......................................................................................................................................... 74
6.2.37.
SRGBOFF (AAH): Separate RGB Gamma OFF ................................................................................................................ 75
6.2.38.
SRGBOFF (ABH): Separate RGB Gamma ON.................................................................................................................. 76
6.2.39.
VSYNCOFF (ACH): VSYNC Interface OFF ....................................................................................................................... 77
6.2.40.
VSYNCON (ADH): VSYNC Interface ON ........................................................................................................................... 78
6.2.41.
VSCTR1 (AEH): VSYNC Interface function control 1......................................................................................................... 79
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6.2.21.
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6.3. PANEL COMMAND DESCRIPTION ........................................................................................................................................................... 80
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6.3.1. RGBCTR (B0H): RGB signal control ...................................................................................................................................... 80
6.3.2. FRMCTR1 (B1h): Frame Rate Control (In normal mode/ Full colors)..................................................................................... 81
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6.3.3. FRMCTR2 (B2h): Frame Rate Control (In Idle mode/ 8-colors) ............................................................................................. 83
6.3.4. FRMCTR3 (B3h): Frame Rate Control (In Partial mode/ full colors)....................................................................................... 85
6.3.5. INVCTR (B4h): Display Inversion Control............................................................................................................................... 87
6.3.6. RGBBPCTR (B5h): RGB Interface Blanking Porch setting..................................................................................................... 88
6.3.7. DISSET5 (B6h): Display Function set 5.................................................................................................................................. 89
6.3.8. PWCTR1 (C0H): Power Control 1 .......................................................................................................................................... 91
6.3.9. PWCTR2 (C1H): Power Control 2 .......................................................................................................................................... 93
6.3.10.
PWCTR3 (C2H): Power Control 3 (in Normal mode/ Full colors)....................................................................................... 94
6.3.11.
PWCTR4 (C3H): Power Control 4 (in Idle mode/ 8-colors) ................................................................................................ 96
6.3.12.
PWCTR5 (C4H): Power Control 5 (in Partial mode/ full-colors) ......................................................................................... 98
6.3.13.
VMCTR1 (C5H): VCOM Control 1.................................................................................................................................... 100
6.3.14.
VMCTR2 (C6H): VCOM Control 2.................................................................................................................................... 102
6.3.15.
RDVMOF (C8H): Read the VCOM Offset Value NV memory .......................................................................................... 104
6.3.16.
WRID2 (D1h): Write ID2 Value ......................................................................................................................................... 105
6.3.17.
WRID3 (D2h): Write ID3 Value ......................................................................................................................................... 106
6.3.18.
RDID4 (D3h): Read the ID4 value .................................................................................................................................... 107
6.3.19.
NVFCTR1 (D9h): NV Memory Function Controller 1 ....................................................................................................... 108
6.3.20.
NVFCTR2 (DEh): NV Memory Function Controller 2 ........................................................................................................110
6.3.21.
NVFCTR3 (DFh): NV Memory Function Controller 3 ........................................................................................................111
6.3.22.
GMCTRP1 (E0H): Gamma (‘+’polarity for Red color) Correction Characteristics Setting.................................................112
6.3.23.
GMCTRN1 (E1H): Gamma (‘-’polarity for Red color) Correction Characteristics Setting .................................................114
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Preliminary
SPFD54126B
6.3.24.
GMCTRP2 (E2H): Gamma (‘+’polarity) for Green color Correction Characteristics Setting .............................................116
6.3.25.
GMCTRN2 (E3H): Gamma (‘-’polarity) for Green color Correction Characteristics Setting ..............................................118
6.3.26.
GMCTRP3 (E4H): Gamma (‘+’polarity) for Blue color correction Characteristics Setting ................................................ 120
6.3.27.
GMCTRN3 (E5H): Gamma (‘-’polarity) for Blue color Correction Characteristics Setting................................................ 122
7. FUNCTION DESCRIPTION ..................................................................................................................................................................... 124
7.1. MCU & RGB INTERFACE ................................................................................................................................................................... 124
7.2. MPU INTERFACE ............................................................................................................................................................................... 126
7.2.1. Interface Type Selection........................................................................................................................................................ 126
7.2.2. 8080-Series Parallel interface(P68=’0’) ................................................................................................................................ 126
7.2.3. 6800-Series Parallel Interface (P68=’1’) ............................................................................................................................... 129
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7.2.4. Serial Peripheral interface (SPI) ........................................................................................................................................... 132
7.2.5. Data Transfer Break and Recovery....................................................................................................................................... 134
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7.2.6. Data Transfer Pause ............................................................................................................................................................. 136
7.2.7. Data Transfer Modes ............................................................................................................................................................ 137
7.3. MCU DATA COLOUR CODING ............................................................................................................................................................. 138
7.3.1. MCU Data Colour Coding for RAM data Write...................................................................................................................... 138
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7.3.2. MCU Data Colour Coding for RAM data Read ..................................................................................................................... 149
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7.3.3. Serial Interface (IM2 = ‘0’)..................................................................................................................................................... 154
7.4. RGB INTERFACE ................................................................................................................................................................................ 157
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7.4.1. General Description .............................................................................................................................................................. 157
7.4.2. General Timing Diagram ....................................................................................................................................................... 158
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7.4.3. Updating Order on Display Active Area (Normal Display Mode On + Sleep Out)................................................................. 159
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7.4.4. RGB Interface Bus Width set ................................................................................................................................................ 161
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7.4.5. RGB Interface Mode Set....................................................................................................................................................... 161
7.4.6. RGB Interface Timing Diagram ............................................................................................................................................. 162
7.4.7. RGB Data Color Coding........................................................................................................................................................ 173
7.5. DISPLAY DATA RAM ........................................................................................................................................................................... 176
7.5.1. Configuration......................................................................................................................................................................... 176
7.5.2. Memory to Display Address Mapping ................................................................................................................................... 177
7.5.3. Normal Display On or Partial Mode On, Vertical Scroll Off ................................................................................................... 180
7.5.4. Vertical Scroll Mode .............................................................................................................................................................. 183
7.5.5. Vertical Scroll Example ......................................................................................................................................................... 185
7.6. ADDRESS COUNTER........................................................................................................................................................................... 186
7.7. MEMORY DATA WRITE/ READ DIRECTION ............................................................................................................................................ 187
7.8. TEARING EFFECT OUTPUT LINE .......................................................................................................................................................... 189
7.8.1. Tearing Effect Line Modes .................................................................................................................................................... 189
7.8.2. Tearing Effect Line Timings ................................................................................................................................................... 190
7.8.3. Example 1: MPU Write is faster than panel read. ................................................................................................................. 191
7.8.4. Example 2: MPU write is slower than panel read. ................................................................................................................ 192
7.9. PRESET VALUES ................................................................................................................................................................................ 193
7.10. POWER ON/OFF SEQUENCE ............................................................................................................................................................. 193
7.10.1.
Case 1 – RESX Line is held High or Unstable by Host at Power On ............................................................................... 193
7.10.2.
Case 2 – RESX Line is Held Low by Host at Power On................................................................................................... 194
7.10.3.
Uncontrolled Power Off .................................................................................................................................................... 194
7.11. POWER LEVEL DEFINITION ................................................................................................................................................................. 195
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SPFD54126B
7.11.1.Power Level .......................................................................................................................................................................... 195
7.11.2.Power Flow Chart ................................................................................................................................................................. 196
7.12. GAMMA CURVES ................................................................................................................................................................................ 197
7.13. RESET ............................................................................................................................................................................................... 198
7.13.1.
Reset Value ...................................................................................................................................................................... 198
7.13.2.
Module Input/Output Pins ................................................................................................................................................. 201
7.13.3.
Reset Timing..................................................................................................................................................................... 202
7.14. COLOUR DEPTH CONVERSION LOOK UP TABLES ................................................................................................................................. 203
7.14.1.
4096 and 65536 Colour to 262,144 Colour ...................................................................................................................... 203
7.15. SLEEP OUT-COMMAND AND SELF-DIAGNOSTIC FUNCTIONS OF THE DISPLAY MODULE .......................................................................... 207
Register Loading Detection .............................................................................................................................................. 207
7.15.2.
Functionality Detection ..................................................................................................................................................... 208
7.15.3.
Chip Attachment Detection ............................................................................................................................................... 209
7.15.4.
Display Glass Break Detection ......................................................................................................................................... 210
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7.15.1.
7.16. OSCILLATOR .......................................................................................................................................................................................211
7.17. SYSTEM COLCK GENERATOR ..............................................................................................................................................................211
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7.18. INSTRUCTION DECODER AND REGISTER ...............................................................................................................................................211
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7.19. SOURCE DRIVER.................................................................................................................................................................................211
7.20. GATE DRIVER .....................................................................................................................................................................................211
Gate Driver ........................................................................................................................................................................211
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7.20.1.
7.21. Γ-CORRECTION FUNCTION .......................................................................................................................................................... 212
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7.22. VSYNC INTERFACE ........................................................................................................................................................................... 212
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8. ELECTRICAL SPECIFICATIONS ........................................................................................................................................................... 216
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8.1. DC CHARACTERISTICAC CHARACTERISTIC (VDD=2.6V~3.0V, VDDIO = 1.6V~3.0V, TA = -40℃ ~ 85℃) ......................................... 216
8.2. AC TIMING CHARACTERISTICS ............................................................................................................................................................ 217
8.2.1. Parallel Interface Characteristics 18, 16 ,9 or 8-bits bus (8080-series MCU) ....................................................................... 217
8.3. PARALLEL INTERFACE CHARACTERISTICS 18, 16 ,9 OR 8-BITS BUS (6800-SERIES MCU) ...................................................................... 219
8.4. SERIAL INTERFACE CHARACTERISTICS (3-PIN SERIAL)......................................................................................................................... 220
9. PAD LOCATIONS ................................................................................................................................................................................... 221
9.1. PAD ASSIGNMENT ............................................................................................................................................................................. 221
9.2. PAD LOCATIONS ................................................................................................................................................................................ 222
9.3. WIRING RESISTANCE.......................................................................................................................................................................... 229
10. DISCLAIMER........................................................................................................................................................................................... 231
10. REVISION HISTORY............................................................................................................................................................................... 232
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Preliminary
SPFD54126B
528-CHANNEL DRIVER WITH SYSTEM-ON-CHIP (SOC)
FOR COLOR AMORPHOUS TFT LCD
1. GENERAL DESCRIPTION
The SPF54126B, a 262144-color System-on-Chip (SoC) driver
„ System interfaces
LSI designed for small and medium sizes of TFT LCD display, is
− High-speed interfaces to 8-, 9-, 16-, and 18-bit parallel ports
capable of supporting up to 176xRGBx220 in resolution which can
− Serial Peripheral Interface (SPI)
be achieved by the designated RAM for graphic data.
The
„ Interfaces for moving picture display
− 6-, 16-, and 18-bit RGB interfaces
528-channel source driver has true 6-bit resolution, which
generates 64 Gamma-corrected values by an internal D/A
„ Diverse RAM accessing for functional display
− Window address function to display at any area on the
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converter. The source driver of SPFD54126B adopts OP-AMP
structure to enhance display quality and it cooperates with
screen via a moving picture display interface
− Window address function to limit the data rewriting area
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advanced circuitry techniques to reduce power consumption.
and reduce data transfer
− Moving and still picture can display at the same time
The SPFD54126B is able to operate with low IO interface power
− Vertical scrolling function
supply up to 1.6V and incorporate with several charge pumps to
− Partial screen display
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generate various voltage levels that form an on-chip power
management system for gate driver and common driver.
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„ Power supply
The built-in timing controller in SPFD54126B can support several
interfaces for the diverse request of medium or small size portable
− Logic power supply voltage (VDD): 2.6 ~ 3.5 V
− I/O interface supply voltage (VDDI): 1.6 ~ 3.6 V
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„ On-chip power management system
− Power saving mode (standby / 8-color mode, etc)
8-/9-/16-/18-bit parallel interfaces and 9-bit serial interface (SPI),
− Low power consumption OP-AMP structure for source
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display. SPFD54126B provides system interfaces, which include
to configure system. Not only can the system interfaces be used to
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driver.
configure system, they can also access RAM at high speed for still
„ Built-in Charge Pump circuits
− Source driver voltage level : 2 times (x2) of Vci1
and 18-bit RGB interfaces for picture movement display. The
− Gate driver voltage level (VGH, VGL) up to 6 times (x6) and
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picture display. In addition, the SPFD54126B incorporates 6, 16,
SPFD54126B also supports a function to display eight colors and
minus 5 times (x-5) Vci1
a standby mode for power control consideration.
„ Built-in internal oscillator and hardware reset
„ Built–in One-Time-Programming (OTP) function for VCOM
2. FEATURE
amplitude and VcomH voltage adjustment.
„ Built-in separate three-gamma curves (RGB) controller to fine
„ One-chip solution for amorphous TFT-LCD.
tune display quality.
„ Supports resolution up to 176xRGBx220, incorporating a
528-channel source driver and a 220-channel gate driver
„ Outputs 64 γ -corrected values using an internal true 6-bit
3. ORDERING INFORMATION
resolution D/A converter to achieve 262K colors
„ 528-channel source driver adopts OP-AMP structure
„ Built-in 87120 bytes internal RAM
Product Number
Package Type
SPFD54126B-C
Chip Form With Gold Bump
„ Line Inversion AC drive / frame inversion AC drive
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SPFD54126B
4. BLOCK DIAGRAM
4.1. Block Function
S1
P68
DCX/SCL
SDA
IM[2:0]
CSX
RDX
WRX
OTP
Memory
S2
S527
S528
Source Driver (528 channels)
System
Interface
True 6-bit D/A Converter
6
6
6
6
Level Shifter (528 x 6bits)
LUT
RGB
Interface
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6
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Graphics
RAM
87120
bytes
18
18
Data Latch (176 x 3 x 6bits x2)
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D[17:0]
DE
PCLK
VS
HS
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VREF
VDD
VDDI
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Timing
Signal
Generator
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TE
RESX
EXTC
IDM
GM[1:0]
LCM[1:0]
RCM[1:0]
SRGB
SMX
SMY
SHUT
REV
RL
TB
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Shift Register (176 bits)
CLK
Clock
Generator
Regulator
VCI1
C11P/N
C12P/N
64
AVDD
Gamma
Voltage
Generator
VCI1
AVDD
GVDD
VCOMH
VCOM
VCOM
VCOML
Gate
Power
Charge
Pump
C21P/N
C22P/N
C23P/N
VGL
VGH
Gate
Driver
G[220:1]
VCL
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SPFD54126B
4.1.1. System Interface
The SPFD54126B supports three high-speed system interfaces:
1. 80-system high-speed interfaces with 8-, 9-, 16-, 18-bit parallel ports.
2. 68-system high-speed interfaces with 8-, 9-, 16-, 18-bit parallel ports.
3. 3-pin 9-bits Serial Peripheral Interface (SPI).
The SPFD54126B has a 16-bit index register (IR) and two 18-bit data registers, a write-data register (WDR) and a read-data register (RDR).
The IR register is used to store index information from control registers. The WDR register is used to temporarily store data to be written for
register control and internal GRAM. The RDR register is used to temporarily store data read from the GRAM. When graphic data is written
to the internal GRAM from MCU/graphic engine, the data is first written to the WDR and then automatically written to the internal GRAM in
internal operation. When graphic data read operation is executed, graphic data is read via the RDR from the internal GRAM. Therefore,
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invalid data is first read out to the data bus when the SPFD54126B executes the 1 read operation.
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the SPFD54126B executes the 2 read operation.
Thus, valid data can be read out after
4.1.2. External Display Interface
The SPFD54126B supports external RGB interface for picture movement display.
The SPFD54126B allows switching between one of the external display interfaces and the system interface via pin configuration so that the
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optimum interface is selected for still / moving picture displayed on the screen.
When the RGB interface is chosen, display operations are synchronized with external supplied signals, VSYNC, HSYNC, and DOTCLK.
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Moreover, valid display data (DB17-0) is written to GRAM, which synchronized with signal (DE) enabling.
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4.1.3. Address Counter (AC)
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SPFD54126B features an Address Counter (AC) giving an address to the internal GRAM. The address in the AC is automatically updated
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plus or minus 1. The window address function enables writing data only in the rectangular area arbitrarily set by users on the GRAM.
4.1.4. Graphics RAM (GRAM)
SPFD54126B features a 87120-byte (176 x 220x 18/8) Graphic RAM (GRAM).
4.1.5. Grayscale Voltage Generating Circuit
SPFD54126B has true 6-bit resolution D/A converter, which generates 64 Gamma-corrected values and cooperates with OP-AMP structure
to enhance display quality. The grayscale voltage can be adjusted by grayscale data set in the γ-correction register.
For details, see the
“γ-Correction Function” section.
4.1.6. Timing Controller
SPFD54126B has a timing controller which can generate a timing signal for internal circuit operation such as gate output timing, RAM
accessing timing, etc.
4.1.7. Oscillator (OSC)
The SPFD54126B also features an internal oscillator to generate RC oscillation with an internal resistor. In standby mode, RC oscillation is
halted to reduce power consumption.
See “Oscillator” for details.
4.1.8. Source Driver Circuit
SPFD54126B consists of a 528-output source driver circuit (S1 ~ S528).
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Data in the GRAM are latched when the 528 bit data is input.
The latched data controls the source driver and generates a drive waveform.
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SPFD54126B
4.1.9. Gate Driver Circuit
SPFD54126B consists of a 220-output gate driver circuit (G1~G220). The gate driver circuit outputs gate driver signals at either VGH or
VGL level.
4.1.10. LCD Driving Power Supply Circuit
The LCD driving power supply circuit generates the voltage levels AVDD, VGH, VGL and VCOM for driving an LCD. All this voltages can be
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adjusted by register setting.
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SPFD54126B
5. SIGNAL DESCRIPTIONS
Signal
Pin No.
I/O
Connected with
Function
DGND/ VDDI
Select system interface mode.
System Configuration Input Signal
I
P68
IM2
IM1
IM0
0
0
-
-
3-Pin Serial interface
0
1
0
0
8080 MCU 8-bits Parallel interface
0
1
0
1
8080 MCU 16-bits Parallel interface
0
1
1
0
8080 MCU 9-bits Parallel interface
0
1
1
1
8080 MCU 18-bits Parallel interface
1
0
-
-
3-Pin Serial interface
1
1
0
0
6800 MCU 8-bits Parallel interface
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P68, IM2~0
1
1
1
1
0
1
6800 MCU 16-bits Parallel interface
1
1
0
6800 MCU 9-bits Parallel interface
1
1
1
6800 MCU 18-bits Parallel interface
RESX
1
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Must connect to the GND or VDDI level when not used.
MPU or
Reset pin. This is an active low signal.
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external
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RC circuit
EXTC
DGND/ VDDI
Extend command set access
2
I
DGND/ VDDI
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GM1~0
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Low: Extend command set is not accessible.
RCM1~0
IDM
2
1
I
I
DGND/ VDDI
MCU
High: Extend command set is accessible.
If this is not used. Open it (This pin is internally pull low).
Resolution selection:
GM1
GM0
Resolution
0
0
176*RGB*220
0
1
176*RGB*176
1
0
Reserved
1
1
176*RGB*132
Interface selection:
RCM1
RCM0
Interface
0
0
MCU Interface
0
1
MCU Interface
1
0
RGB Interface
1
1
RGB Interface
In RGB interface mode:
(a) Low: Normal Display.
(b) High: Idle Mode (8-color mode).
This pin can be only used when RGB mode is selected.
LCM
2
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I
DGND/ VDDI
Liquid Crystal Type selection:
LCM1
LCM0
LC type selection
0
0
Normally black type1
0
1
Normally white type1
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Preliminary
SPFD54126B
Signal
SRGB
Pin No.
1
I/O
I
Connected with
DGND/ VDDI
Function
1
0
Normally black type2
1
1
Normally white type2
RGB arrangement selection:
RGB
SRGB
RGB filter order for CF default setting
0
0
S1, S2, S3 fit ‘R’, ‘G’, ‘B
0
1
S1, S2, S3 fit ‘B’, ‘G’, ‘R
1
0
S1, S2, S3 fit ‘B’, ‘G’, ‘R
1
1
S1, S2, S3 fit ‘R’, ‘G’, ‘B
The RGB is the D4 for Command 36H
1
I
DGND/ VDDI
Display on/off selection when RGB mode is selected.
m
SHUT
nd
.co
(a) Low: Display On.
(b) High: Display Off.
This pin can be only used when RGB mode is selected.
REV
1
I
DGND/ VDDI
Data reverse for source driver selection when RGB mode is selected.
(a) Low: Reverse Off.
re
(b) High: Reserve On.
I
DGND/ VDDI
Source driver output direction selection:
I
DGND/ VDDI
w
1
w
SMY
w
.m
1
bt
This pin can be only used when RGB mode is selected.
SMX
RL
1
I
DGND/ VDDI
SMX
Source output direction
0
S1 => S528
1
S528=>S1
Gate driver output direction selection:
SMY
GM=”00”
GM=”01”
GM=”11”
0
G1 =>G220
G1=>G176
G1=>G132
1
G220=>G1
G176=>G1
G132=>G1
Source driver output direction selection:
SMX
RL
Source output direction
0
0
S1 => S528
0
1
S528 => S1
1
0
S528 => S1
1
1
S1 => S528
This pin can be only used when RGB mode is selected.
TB
1
I
DGND/ VDDI
Gate driver output direction selection:
SMY
TB
GM=”00”
GM=”01”
GM=”11”
0
0
G1 =>G220
G1=>G176
G1=>G132
0
1
1
G220 =>G1
G176 =>G1
G132=>G1
0
G220 =>G1
G176 =>G1
G132=>G1
1
1
G1 =>G220
G1=>G176
G1=>G132
This pin can be only used when RGB mode is selected.
Interface input Signals
CSX
1
I
MPU
Chip select signal.
Low: the SPFD54126B is accessible
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Preliminary
SPFD54126B
Signal
Pin No.
I/O
Connected with
Function
High: the SPFD54126B is not accessible
This pin has can be permanently fixed “Low” in MCU interface mode only.
D/CX
1
I
MPU
Display data / Command selection pin in parallel interface
(SCL)
Low: Command data
High: Display data
In SPI I/F, this is used as SCL pin.
Must connect to the GND or VDDI level when not used.
WRX
1
I
MPU
(A) In 80-system interface mode, a write strobe signal can be input via this pin
(R/WX)
and initializes a write operation when the signal is low.
(B) In 68-system interface mode, a write or read control signal can be input via
m
this pin and initializes a write or read operation.
RDX
1
I
nd
.co
Must connect to the GND or VDDI level when not used.
MPU
(A) In 80-system interface mode, a read strobe signal can be input via this pin
(E)
and initializes a read operation when the signal is low.
(B) In 68system interface mode, a strobe signal can be input via this pin and
initializes a write or read operation when the signal is low.
I
Must connect to the GND or VDDI level when not in use.
(A) When RCM [1:0] = ‘01’
Chip select pin for SPI (Low active)
(B) When RCM [1:0] = ‘00’ or ‘1X’
re
1
MPU
bt
SPI_CSX
.m
This pin is not used, and fix at VDDI or DGND level.
I
MPU
SDA
1
w
w
1
w
If not used, please fix this pin at VDDI or DGND level.
SCL
I/O
MPU
(A) When RCM [1:0] = ‘01’
Serial clock signal pin for SPI
(B) When RCM [1:0] = ‘00’ or ‘1X’
This pin is not used, and fix at VDDI or DGND level.
If not used, please fix this pin at VDDI or DGND level.
(A) When RCM [1:0] = ‘01’ or ‘1X’
Serial input/ output signal in serial I/F mode.
The data is input on the rising edge of the SCL signal.
The data is output on the falling edge of the SCL signal.
(B) When RCM [1:0] = ‘00’
This pin is not used, and fix at VDDI or DGND level.
If not used, please fix this pin at VDDI or DGND level.
DB0-DB17
2*18
I/O
MPU
(A) When RCM [1:0] = ‘1X’ (RGB I/F),
D[17:0] are used for RGB interface data bus
(B) When RCM [1:0] = ‘00’ (MCU I/F),
D[17:0] are used to MCU parallel interface data bus
In SPI I/F, D0 is used as Serial input/ output signal.
In SPI I/F, D[17:1] not used, please fix this pin at VDDI or DGND level.
(C) When RCM [1:0] = ‘01’ (MCU I/F),
D[17:0] are used for MCU interface data bus
In SPI I/F, D[17:0] not used, please fix this pin at VDDI or DGND level.
VS
1
I
MPU
In RGB I/F or VSYNC I/F mode, served as a vertical synchronize signal input
Must connect to the VDDI or DGND level when not in use.
HS
1
I
MPU
In RGB I/F mode, served as a horizontal synchronized signal input
Must connect to the VDDI or DGND level when not in use.
DE
1
I
MPU
In RGB I/F mode, polarity of DE signal is synchronized with valid graphic data
input.
High: Valid data on DB17-DB0
Low: Invalid data on DB17-DB0
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Preliminary
SPFD54126B
Signal
Pin No.
I/O
Connected with
Function
Must connect to the VDDI or DGND level when not in use.
PCLK
1
I
MPU
In RGB I/F mode, served as a pixel clock signal.
Must connect to the VDDI or DGND level when not in use.
Charge Pump and Power Supply Signal
4/4
C12P/N
4/4
C21P/N,
3/3
C22P/N
3/3
C23P/N
3/3
VCI1
5
-
Step-up
Connect boost capacitors for the internal DC/DC converter circuit to these
capacitor
pins.
Leave the pins open when DC/DC converter circuits are not used.
O
Stabilizing
An internal reference voltage level, which is regulated from VDD. The
capacitor
amplitude of VCI1 is from VDD-GND. Place a stabilizing capacitor between
m
C11P/N,
VGH
3
O
VGL
3
O
VCL
VCC
3
5
O
O
Stabilizing
Output 2x VCI1 voltage level from the step-up circuit 1. Place a stabilizing
capacitor
capacitor between GND. AVDD = 4.5 ~ 5.5V
Stabilizing
An output voltage from the step-up circuit 2x, 4x ~ 6x of the VCI1 level.
capacitor
Connect with a stabilizing capacitor.
Stabilizing
An output voltage from the step-up circuit –2x, -3x ~ -5x of the VCI1 level.
capacitor
Connect with a stabilizing capacitor.
Stabilizing
An output voltage from the step-up circuit 2, –1x of the VCI1 level.
capacitor
Connect with a stabilizing capacitor.
Stabilizing
w
capacitor
re
O
bt
6
.m
AVDD
nd
.co
GND.
5
O
GVDD
4
I/O
Connect with a stabilizing capacitor
Stabilizing
Reference voltage for power block
capacitor
Connect with a stabilizing capacitor.
w
w
VREF
Reference voltage for Internal logic block
Stabilizing
Output source driver grayscale reference voltage level.
capacitor
Source/Gate Driver and VCOM Signals
G1~G220
220
O
LCD
S1~S528
528
O
LCD
Output gate driver signals, which has the swing from VGH to VGL
Output source driver signals. The D/A converted 64-gray-scale analog voltage
is output.
VCOM
VcomH
6
4
O
O
TFT panel
Output a square wave signal with the swing from VcomH - VcomL to the
common
common electrode of TFT panel. The alternating cycle can be set to frame
electrode
inversion or 1-line inversion.
Stabilizing
Output the high level of VCOM voltage. Connect with a capacitor to stabilize.
capacitor
VcomL
4
O
Stabilizing
Output the low level of VCOM voltage. Connect with a capacitor to stabilize.
capacitor
or open
VDDIO
5
O
DGNDO
10
O
VDD
10
I
Stabilizing
VDDI input voltage for control pins using
DGND input voltage for control pins using
Power supply Input for analog and booster system
capacitor
VDDI
8
DGND
12
I
Stabilizing
Power supply Input for I/O system
capacitor
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Digital ground pin.
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Preliminary
SPFD54126B
Signal
AGND
Pin No.
I/O
Connected with
15
Function
Analog ground pin.
Misc. Signal
DRV
2
O
Drive signal for the power transistor of the LED booster converter
FB
1
I
TE
1
O
VOTP
2
I
LED booster regulator feedback input.
Connect feedback resistive divider to GND. FB threshold is 0.6V normal.
Tearing effect output pin to synchronies MCU to frame writing, activated by
S/W command.
When this pin is not activated (TE function OFF), this pin is DGND level.
Power supply input for OTP function
MPU
PADA0
1
I
This pin is used for glass break detection
PADB0
1
O
This pin is used for glass break detection
PADA1/PADB1
8
m
This pin is used for chip attachment detection
nd
.co
PADA2/PADB2
PADA3/PADB3
PADA4/PADB4
TEST
18
T
Test pin. If not used, please open this pin.
Dummy
22
D
Dummy pin. If not used, please open this pin.
1
D
Dummy pin. If not used, please open this pin.
OSC
1
I
External oscillator frequency input pin for oscillator testing
bt
re
PREG
w
w
w
.m
If not used, please open this pin.
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Preliminary
SPFD54126B
6. INSTRUCTIONS
6.1. Outline
The SPFD54126B supports 18-bit data bus interface to configure system via accessing command register. When the command register is
executed, sending the command information to specify which index register would be accessed and following the data to that control
register. Moreover, register accessing operation should cooperate with DC/X, WRX, RDX signal for SPFD54126B to recognize the control
instruction. And command instruction can be accomplished using all system interfaces (18-bit, 16-bit, 9-bit, 8-bit 80- or 68-system and SPI)..
6.1.1. System Function Command List and Description
Table 5.1.1 list all the system function command. After the H/W reset by RESX pin or S/W reset by SWRESET command, each internal
register becomes default state (Refer “RESET TABLE” section). Commands 10h, 12h, 13h, 20h, 21h, 26h, 28h, 29h, 30h, 33h, 36h (ML
m
parameter only), 37h, 38h and 39h are updated during V-sync when Module is in Sleep Out Mode to avoid abnormal visual effects. During
Sleep In mode, these commands are updated immediately. Read status (09h), Read Display Power Mode (0Ah), Read Display MADCTR
nd
.co
(0Bh), Read Display Pixel Format (0Ch), Read Display Image Mode (0Dh), Read Display Signal Mode (0Eh) and Read Display Self
Diagnostic Result (0Fh) of these commands are updated immediately both in Sleep In mode and Sleep Out mode.
RDDST
RDDPM
RDD
MADCTR
RDD
COLMOD
RDDIM
RDDSM
RDDSDR
1
1
↑
-
0
1
1
0
1
1
0
1
1
0
1
1
0
1
1
↑
1
1
1
-
↑
1
1
1
1
1
↑
1
↑
1
1
↑
1
1
↑
1
1
↑
1
1
↑
↑
↑
↑
1
↑
↑
↑
↑
↑
1
↑
↑
1
↑
↑
1
↑
↑
1
↑
↑
1
↑
↑
D7
D6
D5
D4
0
0
0
-
0
0
0
-
0
0
0
-
0
0
0
-
D3
D2
D1
D0
0
0
1
-
0
0
0
-
0
1
0
-
BSTON IDMON PTLON SLPOUT NORON DISON
D1
D0
1
-
1
-
0
0
0
-
(Hex)
Function
(00h) No Operation
(01h) Software reset
(04h) Read Display ID
Dummy read
ID17 ID16 ID15 ID14 ID13 ID12 ID11 ID10
ID1 read
ID27 ID26 ID25 ID24 ID23 ID22 ID21 ID20
ID2 read
ID37 ID36 ID35 ID34 ID33 ID32 ID31 ID30
ID3 read
0
0
0
0
1
0
0
1
(09h) Read Display Status
Dummy read
BSTON MY
MX
MV
ML
RGB
ST25 ST24
ST23 IFPF2 IFPF1 IFPF0 IDMON PTLON SLOUT NORON
VSSON ST14 INVON ST12 ST11 DISON TEON GCS2
GCS1 GCS0 TELOM HSON VSON PCKON DEON ST0
0
0
0
0
1
0
1
0
(0Ah) Read Display Power Mode
Dummy read
bt
↑
-
1
1
1
.m
↑
↑
↑
1
1
1
1
w
RDDID
0
0
0
1
1
1
1
0
1
1
1
1
1
0
1
w
NOP
SWRESET
w
Instruction D/CX WRX RDX D17-8
re
Table 6.1.1 System Function command List (1)
0
-
0
-
0
-
0
-
1
-
0
-
-
(0Bh) Read Display MADCTR
Dummy read
MX
MY
MV
ML
RGB
D2
D1
D0
0
0
0
0
1
1
0
0
(0Ch) Read Display Pixel Format
Dummy read
D7
D6
D5
D4
D3
IFPF2 IFPF1 IFPF0
0
0
0
0
1
1
0
1
(0Dh) Read Display Image Mode
Dummy read
VSSON D6
INVON
D4
D3 GCS2 GCS1 GCS0
0
0
0
0
1
1
1
0
(0Eh) Read Display Signal Mode
Dummy read
TEON TELOM HSON VSON PCKON DEON D1
D0
0
0
0
0
1
1
1
1
(0Fh) Read Display Self-diagnostic result
Dummy read
RELD FUND ATTD BRD
D3
D2
D1
D0
-
“-“: Don＇t care, can be set to VDDI or DGND level
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Preliminary
SPFD54126B
Table 6.1.1 System Function command List (2)
RAMWR
RAMHD
RGBSET
D3
D2
D1
D0
(Hex)
0
0
0
0
0
0
0
GC3
1
1
1
XS11
XS3
XE11
XE3
1
YS11
YS3
YE11
YE3
0
0
0
0
0
0
1
GC2
0
0
0
XS10
XS2
XE10
XE2
0
YS10
YS2
YE10
YE2
0
0
1
1
0
0
1
GC1
0
0
1
XS9
XS1
XE9
XE1
1
YS9
YS1
YE9
YE1
0
1
0
1
0
1
0
GC0
0
1
0
XS8
XS0
XE8
XE0
1
YS8
YS0
YE8
YE0
(10h)
(11h)
(12h)
(13h)
(20h)
(21h)
(26h)
-
1
1
1
1
0
0
0
GC4
0
0
0
XS12
XS4
XE12
XE4
0
YS12
YS4
YE12
YE4
1
-
0
0
1
1
1
0
0
1
1
D17-8
D17-8
-
D7
0
D7
0
R007
:
Ra7
G007
:
Gb7
B007
:
Bc7
D6
0
D6
0
R006
:
Ra6
G006
:
Gb6
B006
:
Bc6
D3
1
D3
1
R003
:
Ra3
G003
:
Gb3
B003
:
Bc3
D2
1
D2
1
R002
:
Ra2
G002
:
Gb2
B002
:
Bc2
D1
1
D1
0
R001
:
Ra1
G001
:
Gb1
B001
:
Bc1
1
0
1
1
0
1
1
1
1
1
1
1
1
1
↑
↑
1
1
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
1
1
1
1
1
1
1
1
1
1
0
D5
1
D5
1
R005
:
Ra5
G005
:
Gb5
B005
:
Bc5
D4
0
D4
0
R004
:
Ra4
G004
:
Gb4
B004
:
Bc4
m
↑
Function
Sleep in & booster off
Sleep out & booster on
Partial mode on
Partial off (Normal)
Display inversion off (normal)
Display inversion on
Gamma curve select
(28h) Display off
(29h) Display on
(2Ah) Column address set
nd
.co
0
re
RASET
D4
0
0
0
0
1
1
1
GC5
1
1
1
XS13
XS5
XE13
XE5
1
YS13
YS5
YE13
YE5
-
bt
CASET
D5
0
0
0
0
0
0
0
GC6
0
0
0
XS14
XS6
XE14
XE6
0
YS14
YS6
YE14
YE6
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
.m
DISPOFF
DISPON
D6
0
0
0
0
0
0
0
GC7
0
0
0
XS15
XS7
XE15
XE7
0
YS15
YS7
YE15
YE7
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
w
GAMSET
D7
0
0
0
0
0
0
0
1
0
0
0
1
1
1
1
0
1
1
1
1
w
SLPIN
SLPOUT
PTLON
NORON
INVOFF
INVON
w
Instruction D/CX WRX RDX D17-8
X address start: 0 ≤ XS ≤ 0xAF
X address end: XS ≤ XE ≤ 0xAF
(2Bh) Row address set
Y address start: 0 ≤ YS ≤ 0xDB
Y address end: YS ≤ YE ≤ 0xDB
(2Ch)
Memory write
D0
Write data
0
(2Eh) Memory read
Dummy read
D0
Read data
1 (2Dh) LUT for 4k,65k , 262K color display
R000
Red tone 0
:
: Ra0
Red tone “31”
G000
Green tone 0
:
: Gb0
Green tone “63”
B000
Blue tone 0
:
: Bc0
Blue tone “31”
“-“: Don’t care, can be set to VDDI or DGND level
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Preliminary
SPFD54126B
Table 6.1.1 System Function command List (3)
IDMOFF
IDMON
COLMOD
RDID1
RDID2
RDID3
SRGBOFF
SRGBON
VSUNCOFF
VDUNCON
VSCTRI
↑
1
1
↑
1
1
↑
↑
↑
↑
↑
↑
↑
↑
1
↑
↑
1
↑
↑
1
1
1
1
1
1
D5
D4
D3
D2
D1
D0
0
1
1
0
0
0
0
(Hex)
Function
(30h) Partial start/end address set
PSL15 PSL14 PSL13 PSL12 PSL11 PSL10 PSL9 PSL8
Partial start address (0,1,2, .., 219)
PSL7 PSL6 PSL5 PSL4 PSL3 PSL2 PSL1 PSL0
Partial end address (0,1,2, .., 219)
PEL15 PEL14 PEL13 PEL12 PEL11 PEL10 PEL9 PEL8
PEL7 PEL6 PEL5 PEL4 PEL3 PEL2 PEL1 PEL0
0
0
1
1
0
0
1
1
TFA15 TFA14 TFA13 TFA12 TFA11 TFA10 TFA9 TFA8
(33h) Scroll area set
Top fixed area (0,1,2, .., 220)
TFA7 TFA6 TFA5 TFA4 TFA3 TFA2 TFA1 TFA0
Vertical scroll area (0,1,2, ..,220)
VSA15 VSA14 VSA13 VSA12 VSA11 VSA10 VSA9 VSA8
VSA7 VSA6 VSA5 VSA4 VSA3 VSA2 VSA1 VSA0
Bottom fixed area (0,1,2, ..,220)
BFA15 BFA14 BFA13 BFA12 BFA11 BFA10 BFA9 BFA8
0
0
0
0
1
1
1
1
0
0
1
1
0
0
0
1
m
BFA7 BFA6 BFA5 BFA4 BFA3 BFA2 BFA1 BFA0
(34h) Tearing effect line off
(35h) Tearing effect mode set & on
0
0
0
0
0
0
0 TELOM
M=”0”: Mode1, M=”1”: Mode2
0
0
1
1
0
1
1
0
(36h) Memory data access control
MY
MX
MV
ML RGB
0
0
0
0
0
1
1
0
1
1
1
(37h) Scroll start address of RAM
SSA15 SSA14 SSA13 SSA12 SSA11 SSA10 SSA9 SSA8
SSA = 0, 1, 2, …, 219
nd
.co
VSCSAD
D6
0
re
MADCTR
D7
SSA7 SSA6 SSA5 SSA4 SSA3 SSA2 SSA1 SSA0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
0
0
0
0
0
1
0
1
0
(38h) Idle mode off
(39h) Idle mode on
(3Ah) Interface pixel format
IFPF2 IFPF1 IFPF0
0
0
0
0
0
Interface format
1
1
0
1
1
0
1
0
(DAh) Read ID1
Dummy read
ID17 ID16 ID15 ID14 ID13 ID12 ID11 ID10
Read parameter
1
1
0
1
1
0
1
1
(DBh) Read ID2
Dummy read
ID27 ID26 ID25 ID24 ID23 ID22 ID21 ID20
Read parameter
1
1
0
1
1
1
0
0
(DCh) Read ID3
Dummy read
ID37 ID36 ID35 ID34 ID33 ID32 ID31 ID30
Read parameter
1
0
1
0
1
0
1
0
(AAh) Separate RGB γ function OFF
1
0
1
0
1
0
1
1
(ABh) Separate RGB γ function ON
bt
TEON
-
.m
TEOFF
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
w
SCRLAR
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
1
1
w
PTLAR
0
1
1
1
1
0
1
1
1
1
1
1
0
0
1
0
1
0
1
1
0
0
0
1
0
1
1
0
1
1
0
1
1
0
0
0
0
0
1
w
Instruction D/CX WRX RDX D17-8
1
0
1
0
1
1
0
0
1
0
1
0
1
1
0
1
1
0
1
0
1
1
1
0
VSFP3 VSFP2VSFP1VSFP0 VSBP3 VSBP2 VSBP1 VSBP0
(ACh) VSYNC interace function OFF
(ADh) VSYNC interace function ON
(AEh) VSYNC interace control
VS porch setting
“-“: Don’t care, can be set to VDDI or DGND level
© ORISE Technology Co., Ltd.
Proprietary & Confidential
17
Apr. 25, 2006
Preliminary Version: 0.1
Evaluation Only. Created with Aspose.Pdf.Kit. Copyright 2002-2005 Aspose Pty Ltd
Preliminary
SPFD54126B
6.1.2. Panel Function Command List and Description
Table 6.1.2 list all the panel function command. Panel function command is only accessible when EXTC is pulled high state (by VDDIO).
Table 6.1.2 Panel Function command List (1)
INVCTR
RGB
PRCTR
DISSET5
D3
D2
D1
D0
1
0
1
1
0
0
0
0
1
↑
1
-
0
0
0
ICM
DP
EP
0
↑
1
-
1
0
1
1
1
↑
1
-
-
-
1
↑
1
-
1
↑
1
-
0
↑
1
-
1
0
1
↑
1
-
1
↑
1
-
1
↑
1
-
0
↑
1
-
1
↑
1
-
1
↑
1
-
1
↑
1
-
0
1
0
↑
↑
↑
1
1
1
-
1
↑
1
-
0
1
↑
↑
1
1
1
↑
1
ICM: RGB data ascess select
DP,HSP,VSP:PCLK,HS,VS polarity set
(B1h)
In normal mode (Full colors)
FP0: Front porch in normal mode
BP0: Back porch in normal mode
RTN0: Number of clock / one line
m
0
0
0
1
FP0 FP0 FP0 FP0
[3]
[2]
[1]
[0]
BP0 BP0 BP0 BP0
[3]
[2]
[1]
[0]
RTN0 RTN0 RTN0 RTN0
[3]
[2]
[1]
[0]
1
1
0
0
1
0
FP1 FP1 FP1 FP1
[3]
[2]
[1]
[0]
BP1 BP1 BP1 BP1
[3]
[2]
[1]
[0]
RTN1 RTN1 RTN1 RTN1
[3]
[2]
[1]
[0]
1
1
0
0
1
1
FP2 FP2 FP2 FP2
[3]
[2]
[1]
[0]
BP2 BP2 BP2 BP2
[3]
[2]
[1]
[0]
RTN2 RTN2 RTN2 RTN2
[3]
[2]
[1]
[0]
1
1
0
1
0
0
0
0
0
NLA NLB NLC
1
1
0
1
0
1
VBP VBP VBP VBP
[3]
[2]
[1]
[0]
1
1
0
1
1
1
NO1 NO0 SDT1 STD0 EQ1 EQ0
(B2h)
nd
.co
0
Function
(B0h) Set RGB signal control
HSP VSP
re
1
(Hex)
1
0
1
0
0
0
-
-
-
1
0
0
0
-
0
0
0
0
PTG1 PTG0 PT1
PT0
In Idle mode (8-colors)
FP1: Front porch in idle mode
BP1: Back porch in idle mode
RTN1: Number of clock / one line
(B3h)
In partial mode + Full colors
FP2: Front porch in partial mode
BP2: Back porch in partial mode
RTN2: Number of clock / one line
bt
FRMCTR3
D4
-
.m
FRMCTR2
D5
1
w
FRMCTR1
D6
↑
w
RGBCTR
D7
0
w
Instruction D/CX WRX RDX D17-8
(B4h) Display inversion control
NLA, NLB, NLC: set inversion
(B5h)
RGB I/F Blanking porch setting
Vertical back porch in RGB mode
(B6h) Display function setting
NO: the amount of non-overlap
SDT: set amount of source delay
PT: No display area source/ VCOM/
Gate output control
EQ: set EQ period
“-“: Don’t care, can be set to VDDI or DGND level
© ORISE Technology Co., Ltd.
Proprietary & Confidential
18
Apr. 25, 2006
Preliminary Version: 0.1
Evaluation Only. Created with Aspose.Pdf.Kit. Copyright 2002-2005 Aspose Pty Ltd
Preliminary
SPFD54126B
Table 6.1.2 Panel Function Command List (2)
PWCTR4
PWCTR5
VMCTR1
VMCTR2
1
↑
1
-
0
1
1
0
↑
↑
↑
↑
1
1
1
1
-
1
↑
1
-
0
1
1
0
↑
↑
↑
1
1
1
1
↑
-
1
1
↑
-
D7
D6
D5
1
0
0
1
0
1
0
0
1
0
0
0
0
0
0
0
0
0
0
0
1
0
0
1
0
1
0
0
1
0
1
0
0
0
D4
D3
D2
D1
D0
1
0
0
0
0
VRH4 VRH3 VRH2 VRH1 VRH0
0
0
VC2 VC1 VC0
1
0
0
0
1
0
0
BT2 BT1 BT0
1
0
0
1
0
0
0 APA2 APA1 APA0
0
0 DCA2 DCA1 DCA0
1
0
0
1
1
0
0 APB2 APB1 APB0
(Hex)
Function
(C0h) Power control setting
VRH: Set the GVDD voltage
VC : Set the VCI1 voltage
Power control setting
(C1h) BT: set AVDD/VCL/ VGH/ VGL voltage
(C2h) n normal mode (Full colors)
APA: adjust the operational amplifier
DCA: adjust the booster circuit for Idle
mode
(C3h) In Idle mode (8-colors)
APB: adjust the operational amplifier
DCB: adjust the booster circuit for Idle
mode
0
0
0
0
0 DCB2 DCB1 DCB0
I
1
0
1
1
0
1
0
0
(C4h) In partial mode + Full colors
APC: adjust the operational amplifier
0
0
0
0
0 APC2 APC1 APC0
DCC: adjust the booster circuit for Idle
mode
0
0
0
0
0 DCC2 DCC1 DCC0
1
0
1
1
0
1
0
1
(C5h) VCOM control 1
nVM: VCOM input select
VMH: VCOMH voltage control
nVM VMH6 VMH 5 VMH4 VMH3 VMH2 VMH1 VMH0
1
1
0
1
1
0
(C6h)
VMA5 VMA4 VMA3 VMA2 VMA1 VMA0
VCOM control 2
VMA: VCOMAC voltage control
nVM VMF6 VMF5 VMF4 VMF3 VMF2 VMF1 VMF0
1
nVM
0
1
1
1
0
0
0
(C8h) VCOM control 4
RVMF RVMF RVMF RVMF RVMF RVMF RVMF
Read the VMOF value form NV memory
6
5
4
3
2
1
0
.m
RVMOF
CTR
-
-
m
PWCTR3
1
1
1
1
1
1
1
1
1
1
nd
.co
PWCTR2
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
re
PWCTR1
0
1
1
0
1
0
1
1
0
1
bt
Instruction D/CX WRX RDX D17-8
w
“-“: Don’t care, can be set to VDDI or DGND level
Instruction D/CX WRX RDX D17-8
↑
1
1
↑
1
-
D7
D6
D5
D4
D3
D2
D1
D0
1
1
0
1
0
0
0
1
w
WRID2
0
w
Table 6.1.2 Panel Function Command List (3)
-
1
ID26 ID25 ID24 ID23 ID22 ID21 ID20
(Hex)
Function
(D1h) Panel version code
Write ID2 value to NV memory
Set the LCM version code at ID2
(D2h) Driver maker Project code
Write ID3 value to NV memory
Set the project code at ID3
0
↑
1
-
WRID3
1
↑
1
-
ID37 ID36 ID35 ID34 ID33 ID32 ID31 ID30
↑
1
1
1
1
1
1
RDID4
0
1
1
1
1
1
0
-
1
1
0
1
0
0
1
1
(D3h)
IC Vender Coder
Dummy read
ID417 ID416 ID415 ID414 ID413 ID412 ID411 ID410
ID41:IC Vender Coder
ID427 ID426 ID425 ID424 ID423 ID422 ID421 ID420
ID42: IC Part Number Coder
ID43 & ID44: Chip version coder
ID437 ID436 ID435 ID434 ID43 ID432 ID431 ID430
ID447 ID446 ID445 ID444 ID443 ID442 ID441 ID440
1
1
0
1
1
0
0
1
(D9h) NV memory function controller 1
NVCTR1
NVCTR2
NVCTR3
↑
↑
↑
↑
↑
↑
1
1
1
0
1
0
0
1
0
0
↑
1
-
1
↑
1
-
0
↑
1
-
1
↑
1
-
1
1
0
1
1
1
1
0
1
1
0
1
1
1
1
1
Please refer to ‘OTP programming
procedure’ for details.
(DEh) NV memory function controller 2
Please refer to ‘OTP programming
procedure’ for details.
(DFh) NV memory function controller 3
Please refer to ‘OTP programming
procedure’ for details.
“-“: Don’t care, can be set to VDDI or DGND level
© ORISE Technology Co., Ltd.
Proprietary & Confidential
19
Apr. 25, 2006
Preliminary Version: 0.1
Evaluation Only. Created with Aspose.Pdf.Kit. Copyright 2002-2005 Aspose Pty Ltd
Preliminary
SPFD54126B
Table 6.1.2 Panel Function Command List (4)
Instruction D/CX WRX RDX D17-8 D7 D6
D4
D3
D2
D1
D0
1
0
0
0
0
0
-
R_PVR1V0[4]
R_PVR1V0[3]
R_PVR1V0[2]
R_PVR1V0[1]
R_PVR1V0[0]
R_PVR1V1[5]
R_PVR1V1[4]
R_PVR1V1[3]
R_PVR1V1[2]
R_PVR1V1[1]
R_PVR1V1[0]
1
-
1
1
1
↑
1
-
-
-
1
↑
1
-
-
-
1
↑
1
-
-
-
R_PVR1V2[5]
R_PVR1V2[4]
R_PVR1V2[3]
R_PVR1V2[2]
R_PVR1V2[1]
R_PVR1V2[0]
1
↑
1
-
-
-
R_PVR1V61[5]
R_PVR1V61[4]
R_PVR1V61[3]
R_PVR1V61[2]
R_PVR1V61[1]
R_PVR1V61[0]
1
↑
1
-
-
-
R_PVR1V62[5]
1
↑
1
-
-
1
↑
1
-
1
↑
1
1
↑
1
1
R_PVR1V62[3]
R_PVR1V62[2]
R_PVR1V62[1]
R_PVR1V62[0]
-
R_PVR1V63[4]
R_PVR1V63[3]
R_PVR1V63[2]
R_PVR1V63[1]
R_PVR1V63[0]
-
-
-
R_PVR2V13[4]
R_PVR2V13[3]
R_PVR2V13[2]
R_PVR2V13[1]
R_PVR2V13[0]
-
-
-
-
R_PVR2V50[4]
R_PVR2V50[3]
R_PVR2V50[2]
R_PVR2V50[1]
R_PVR2V50[0]
1
-
-
-
-
-
R_PVR3V4[3]
R_PVR3V4[2]
R_PVR3V4[1]
R_PVR3V4[0]
↑
1
-
-
-
-
-
R_PVR3V8[3]
R_PVR3V8[2]
R_PVR3V8[1]
R_PVR3V8[0]
↑
1
-
-
-
-
-
R_PVR3V20[3]
R_PVR3V20[2]
R_PVR3V20[1]
R_PVR3V20[0]
1
↑
1
-
-
-
-
-
R_PVR3V27[3]
R_PVR3V27[2]
R_PVR3V27[1]
R_PVR3V27[0]
1
↑
1
-
-
-
-
-
R_PVR3V36[3]
R_PVR3V36[2]
R_PVR3V36[1]
R_PVR3V36[0]
1
↑
1
-
-
-
-
-
R_PVR3V43[3]
R_PVR3V43[2]
R_PVR3V43[1]
R_PVR3V43[0]
1
↑
1
-
-
-
-
-
R_PVR3V55[3]
R_PVR3V55[2]
R_PVR3V55[1]
R_PVR3V55[0]
1
↑
1
-
-
-
-
-
R_PVR3V59[3]
R_PVR3V59[2]
R_PVR3V59[1]
R_PVR3V59[0]
↑
1
-
1
1
1
↑
1
-
-
-
1
↑
1
-
-
1
↑
1
-
-
1
↑
1
-
1
↑
1
-
1
↑
1
1
↑
1
1
↑
1
1
↑
1
1
D3
D2
D1
D0
0
0
0
0
1
(Hex) Function
R_NVR1V0[4]
R_NVR1V0[3]
R_NVR1V0[2]
R_NVR1V0[1]
R_NVR1V0[0]
R_NVR1V1[5]
R_NVR1V1[4]
R_NVR1V1[3]
R_NVR1V1[2]
R_NVR1V1[1]
R_NVR1V1[0]
-
R_NVR1V2[5]
R_NVR1V2[4]
R_NVR1V2[3]
R_NVR1V2[2]
R_NVR1V2[1]
R_NVR1V2[0]
R_NVR1V61[4]
R_NVR1V61[3]
R_NVR1V61[2]
R_NVR1V61[1]
R_NVR1V61[0]
w
w
-
D4
-
-
-
R_NVR1V61[5]
R_NVR1V62[5]
-
-
R_NVR1V62[4]
R_NVR1V62[3]
R_NVR1V62[2]
R_NVR1V62[1]
R_NVR1V62[0]
-
-
-
-
R_NVR1V63[4]
R_NVR1V63[3]
R_NVR1V63[2]
R_NVR1V63[1]
R_NVR1V63[0]
-
-
-
-
R_NVR2V13[4]
R_NVR2V13[3]
R_NVR2V13[2]
R_NVR2V13[1]
R_NVR2V13[0]
-
-
-
-
R_NVR2V50[4]
R_NVR2V50[3]
R_NVR2V50[2]
R_NVR2V50[1]
R_NVR2V50[0]
1
-
-
-
-
-
R_NVR3V4[3]
R_NVR3V4[2]
R_NVR3V4[1]
R_NVR3V4[0]
↑
1
-
-
-
-
-
R_NVR3V8[3]
R_NVR3V8[2]
R_NVR3V8[1]
R_NVR3V8[0]
1
↑
1
-
-
-
-
-
R_NVR3V20[3]
R_NVR3V20[2]
R_NVR3V20[1]
R_NVR3V20[0]
1
↑
1
-
-
-
-
-
R_NVR3V27[3]
R_NVR3V27[2]
R_NVR3V27[1]
R_NVR3V27[0]
1
↑
1
-
-
-
-
-
R_NVR3V36[3]
R_NVR3V36[2]
R_NVR3V36[1]
R_NVR3V36[0]
1
↑
1
-
-
-
-
-
R_NVR3V43[3]
R_NVR3V43[2]
R_NVR3V43[1]
R_NVR3V43[0]
1
↑
1
-
-
-
-
-
R_NVR3V55[3]
R_NVR3V55[2]
R_NVR3V55[1]
R_NVR3V55[0]
1
↑
1
-
-
-
-
-
R_NVR3V59[3]
R_NVR3V59[2]
R_NVR3V59[1]
R_NVR3V59[0]
w
R+ Gamma
(E0h) adjustment
re
D5
.m
0
bt
Table 6.1.2 Panel Function Command List (5)
Instruction D/CX WRX RDX D17-8 D7 D6
m
R_PVR1V62[4]
-
“-“: Don’t care, can be set to VDDI or DGND level
GAMCTRN1
(Hex) Function
↑
nd
.co
GAMCTRP1
D5
0
R- Gamma
(E1h) adjustment
“-“: Don’t care, can be set to VDDI or DGND level
© ORISE Technology Co., Ltd.
Proprietary & Confidential
20
Apr. 25, 2006
Preliminary Version: 0.1
Evaluation Only. Created with Aspose.Pdf.Kit. Copyright 2002-2005 Aspose Pty Ltd
Preliminary
SPFD54126B
Table 6.1.2 Panel Function Command List (6)
D4
D3
D2
D1
D0
1
0
0
0
0
0
-
-
G_PVR1V0[4]
G_PVR1V0[3]
G_PVR1V0[2]
G_PVR1V0[1]
G_PVR1V0[0]
-
G_PVR1V1[5]
G_PVR1V1[4]
G_PVR1V1[3]
G_PVR1V1[2]
G_PVR1V1[1]
G_PVR1V1[0]
-
-
G_PVR1V2[5]
G_PVR1V2[4]
G_PVR1V2[3]
G_PVR1V2[2]
G_PVR1V2[1]
G_PVR1V2[0]
-
-
-
G_PVR1V61[5]
G_PVR1V61[4]
G_PVR1V61[3]
G_PVR1V61[2]
G_PVR1V61[1]
G_PVR1V61[0]
1
-
-
-
G_PVR1V62[5]
G_PVR1V62[4]
G_PVR1V62[3]
G_PVR1V62[2]
G_PVR1V62[1]
G_PVR1V62[0]
1
-
-
-
-
G_PVR1V63[4]
G_PVR1V63[3]
G_PVR1V63[2]
G_PVR1V63[1]
G_PVR1V63[0]
↑
1
-
-
-
-
G_PVR2V13[4]
G_PVR2V13[3]
G_PVR2V13[2]
G_PVR2V13[1]
G_PVR2V13[0]
↑
1
-
-
-
-
G_PVR2V50[4]
G_PVR2V50[3]
G_PVR2V50[2]
G_PVR2V50[1]
G_PVR2V50[0]
1
↑
1
-
-
-
-
-
G_PVR3V4[3]
G_PVR3V4[2]
G_PVR3V4[1]
G_PVR3V4[0]
1
↑
1
-
-
-
-
-
G_PVR3V8[3]
G_PVR3V8[2]
G_PVR3V8[1]
G_PVR3V8[0]
1
↑
1
-
-
-
-
-
G_PVR3V20[3]
G_PVR3V20[2]
G_PVR3V20[1]
G_PVR3V20[0]
1
↑
1
-
-
-
-
-
G_PVR3V27[3]
G_PVR3V27[2]
G_PVR3V27[1]
G_PVR3V27[0]
1
↑
1
-
-
-
-
-
G_PVR3V36[3]
G_PVR3V36[2]
G_PVR3V36[1]
G_PVR3V36[0]
1
↑
1
-
-
-
-
-
G_PVR3V43[3]
G_PVR3V43[2]
G_PVR3V43[1]
G_PVR3V43[0]
1
↑
1
-
-
-
-
-
G_PVR3V55[3]
G_PVR3V55[2]
G_PVR3V55[1]
G_PVR3V55[0]
1
↑
1
-
-
-
-
-
G_PVR3V59[3]
G_PVR3V59[2]
G_PVR3V59[1]
G_PVR3V59[0]
↑
1
-
1
1
1
↑
1
-
-
1
↑
1
-
-
1
↑
1
-
1
↑
1
1
↑
1
↑
1
1
GAMCTRN1
D4
D3
D2
D1
D0
0
0
0
0
1
G_NVR1V0[4]
G_NVR1V0[3]
G_NVR1V0[2]
G_NVR1V0[1]
G_NVR1V0[0]
G_NVR1V1[4]
G_NVR1V1[3]
G_NVR1V1[2]
G_NVR1V1[1]
G_NVR1V1[0]
G_NVR1V2[4]
G_NVR1V2[3]
G_NVR1V2[2]
G_NVR1V2[1]
G_NVR1V2[0]
G_NVR1V61[2]
G_NVR1V61[1]
G_NVR1V61[0]
.m
D5
bt
Table 6.1.2 Panel Function Command List (7)
0
↑
1
-
1
1
↑
1
-
-
-
-
1
↑
1
-
-
-
G_NVR1V1[5]
1
↑
1
-
-
-
G_NVR1V2[5]
1
↑
1
-
1
↑
1
-
1
↑
1
1
↑
1
1
↑
1
1
1
w
w
1
(Hex) Function
-
-
G_NVR1V61[5]
G_NVR1V61[4]
G_NVR1V61[3]
-
-
G_NVR1V62[5]
(Hex) Function
G_NVR1V62[4]
G_NVR1V62[3]
G_NVR1V62[2]
G_NVR1V62[1]
G_NVR1V62[0]
-
-
-
-
G_NVR1V63[4]
G_NVR1V63[3]
G_NVR1V63[2]
G_NVR1V63[1]
G_NVR1V63[0]
-
-
-
-
G_NVR2V13[4]
G_NVR2V13[3]
G_NVR2V13[2]
G_NVR2V13[1]
G_NVR2V13[0]
1
-
-
-
-
G_NVR2V50[4]
G_NVR2V50[3]
G_NVR2V50[2]
G_NVR2V50[1]
G_NVR2V50[0]
↑
1
-
-
-
-
-
G_NVR3V4[3]
G_NVR3V4[2]
G_NVR3V4[1]
G_NVR3V4[0]
↑
1
-
-
-
-
-
G_NVR3V8[3]
G_NVR3V8[2]
G_NVR3V8[1]
G_NVR3V8[0]
1
↑
1
-
-
-
-
-
G_NVR3V20[3]
G_NVR3V20[2]
G_NVR3V20[1]
G_NVR3V20[0]
1
↑
1
-
-
-
-
-
G_NVR3V27[3]
G_NVR3V27[2]
G_NVR3V27[1]
G_NVR3V27[0]
1
↑
1
-
-
-
-
-
G_NVR3V36[3]
G_NVR3V36[2]
G_NVR3V36[1]
G_NVR3V36[0]
1
↑
1
-
-
-
-
-
G_NVR3V43[3]
G_NVR3V43[2]
G_NVR3V43[1]
G_NVR3V43[0]
1
↑
1
-
-
-
-
-
G_NVR3V55[3]
G_NVR3V55[2]
G_NVR3V55[1]
G_NVR3V55[0]
1
↑
1
-
-
-
-
-
G_NVR3V59[3]
G_NVR3V59[2]
G_NVR3V59[1]
G_NVR3V59[0]
w
G+ Gamma
(E2h) adjustment
re
“-“: Don’t care, can be set to VDDI or DGND level
Instruction D/CX WRX RDX D17-8 D7 D6
m
GAMCTRP1
D5
0
nd
.co
Instruction D/CX WRX RDX D17-8 D7 D6
G- Gamma
(E3h) adjustment
“-“: Don’t care, can be set to VDDI or DGND level
© ORISE Technology Co., Ltd.
Proprietary & Confidential
21
Apr. 25, 2006
Preliminary Version: 0.1
Evaluation Only. Created with Aspose.Pdf.Kit. Copyright 2002-2005 Aspose Pty Ltd
Preliminary
SPFD54126B
Table 6.1.2 Panel Function Command List (8)
Instruction D/CX WRX RDX D17-8 D7 D6
D4
D3
D2
D1
D0
1
0
0
0
0
0
-
1
1
1
↑
1
-
-
-
-
B_PVR1V0[4]
B_PVR1V0[3]
B_PVR1V0[2]
B_PVR1V0[1]
B_PVR1V0[0]
1
↑
1
-
-
-
B_PVR1V1[5]
B_PVR1V1[4]
B_PVR1V1[3]
B_PVR1V1[2]
B_PVR1V1[1]
B_PVR1V1[0]
1
↑
1
-
-
-
B_PVR1V2[5]
B_PVR1V2[4]
B_PVR1V2[3]
B_PVR1V2[2]
B_PVR1V2[1]
B_PVR1V2[0]
1
↑
1
-
-
-
B_PVR1V61[5]
B_PVR1V61[4]
B_PVR1V61[3]
B_PVR1V61[2]
B_PVR1V61[1]
B_PVR1V61[0]
1
↑
1
-
-
-
B_PVR1V62[5]
B_PVR1V62[4]
B_PVR1V62[3]
B_PVR1V62[2]
B_PVR1V62[1]
B_PVR1V62[0]
1
↑
1
-
-
-
-
B_PVR1V63[4]
B_PVR1V63[3]
B_PVR1V63[2]
B_PVR1V63[1]
B_PVR1V63[0]
1
↑
1
-
-
-
-
B_PVR2V13[4]
B_PVR2V13[3]
B_PVR2V13[2]
B_PVR2V13[1]
B_PVR2V13[0]
1
↑
1
-
-
-
-
B_PVR2V50[4]
B_PVR2V50[3]
B_PVR2V50[2]
B_PVR2V50[1]
B_PVR2V50[0]
1
↑
1
-
-
-
-
-
B_PVR3V4[3]
B_PVR3V4[2]
B_PVR3V4[1]
B_PVR3V4[0]
1
↑
1
-
-
-
-
-
B_PVR3V8[3]
B_PVR3V8[2]
B_PVR3V8[1]
B_PVR3V8[0]
1
↑
1
-
-
-
-
-
B_PVR3V20[3]
B_PVR3V20[2]
B_PVR3V20[1]
B_PVR3V20[0]
1
↑
1
-
-
-
-
-
B_PVR3V27[3]
B_PVR3V27[2]
B_PVR3V27[1]
B_PVR3V27[0]
1
↑
1
-
-
-
-
-
B_PVR3V36[3]
B_PVR3V36[2]
B_PVR3V36[1]
B_PVR3V36[0]
1
↑
1
-
-
-
-
-
B_PVR3V43[3]
B_PVR3V43[2]
B_PVR3V43[1]
B_PVR3V43[0]
1
↑
1
-
-
-
-
-
B_PVR3V55[3]
B_PVR3V55[2]
B_PVR3V55[1]
B_PVR3V55[0]
1
↑
1
-
-
-
-
-
B_PVR3V59[3]
B_PVR3V59[2]
B_PVR3V59[1]
B_PVR3V59[0]
1
-
1
1
1
↑
1
-
-
-
1
↑
1
-
-
-
1
↑
1
-
-
-
1
↑
1
-
1
↑
1
-
1
↑
1
1
↑
1
1
↑
1
1
↑
1
↑
1
1
D4
D3
D2
D1
D0
1
0
0
0
0
1
-
B_NVR1V0[4]
B_NVR1V0[3]
B_NVR1V0[2]
B_NVR1V0[1]
B_NVR1V0[0]
B_NVR1V1[5]
B_NVR1V1[4]
B_NVR1V1[3]
B_NVR1V1[2]
B_NVR1V1[1]
B_NVR1V1[0]
B_NVR1V2[5]
B_NVR1V2[4]
B_NVR1V2[3]
B_NVR1V2[2]
B_NVR1V2[1]
B_NVR1V2[0]
B_NVR1V61[4]
B_NVR1V61[3]
B_NVR1V61[2]
B_NVR1V61[1]
B_NVR1V61[0]
w
-
-
B_NVR1V61[5]
-
-
B_NVR1V62[5]
(Hex) Function
B_NVR1V62[4]
B_NVR1V62[3]
B_NVR1V62[2]
B_NVR1V62[1]
B_NVR1V62[0]
-
-
-
-
B_NVR1V63[4]
B_NVR1V63[3]
B_NVR1V63[2]
B_NVR1V63[1]
B_NVR1V63[0]
-
-
-
-
B_NVR2V13[4]
B_NVR2V13[3]
B_NVR2V13[2]
B_NVR2V13[1]
B_NVR2V13[0]
-
-
-
-
B_NVR2V50[4]
B_NVR2V50[3]
B_NVR2V50[2]
B_NVR2V50[1]
B_NVR2V50[0]
1
-
-
-
-
-
B_NVR3V4[3]
B_NVR3V4[2]
B_NVR3V4[1]
B_NVR3V4[0]
1
-
-
-
-
-
B_NVR3V8[3]
B_NVR3V8[2]
B_NVR3V8[1]
B_NVR3V8[0]
↑
1
-
-
-
-
-
B_NVR3V20[3]
B_NVR3V20[2]
B_NVR3V20[1]
B_NVR3V20[0]
↑
1
-
-
-
-
-
B_NVR3V27[3]
B_NVR3V27[2]
B_NVR3V27[1]
B_NVR3V27[0]
1
↑
1
-
-
-
-
-
B_NVR3V36[3]
B_NVR3V36[2]
B_NVR3V36[1]
B_NVR3V36[0]
1
↑
1
-
-
-
-
-
B_NVR3V43[3]
B_NVR3V43[2]
B_NVR3V43[1]
B_NVR3V43[0]
1
↑
1
-
-
-
-
-
B_NVR3V55[3]
B_NVR3V55[2]
B_NVR3V55[1]
B_NVR3V55[0]
1
↑
1
-
-
-
-
-
B_NVR3V59[3]
B_NVR3V59[2]
B_NVR3V59[1]
B_NVR3V59[0]
w
B+ Gamma
(E4h) adjustment
re
D5
.m
↑
w
0
bt
Table 6.1.2 Panel Function Command List (9)
Instruction D/CX WRX RDX D17-8 D7 D6
m
1
“-“: Don’t care, can be set to VDDI or DGND level
GAMCTRN1
(Hex) Function
↑
nd
.co
GAMCTRP1
D5
0
B- Gamma
(E5h) adjustment
“-“: Don’t care, can be set to VDDI or DGND level
© ORISE Technology Co., Ltd.
Proprietary & Confidential
22
Apr. 25, 2006
Preliminary Version: 0.1
Evaluation Only. Created with Aspose.Pdf.Kit. Copyright 2002-2005 Aspose Pty Ltd
Preliminary
SPFD54126B
6.2. System Command Description
6.2.1. NOP (00h)
00H
NOP (No Operation)
Inst / Para
D/CX
WRX
RDX
D17-8
D7
D6
D5
D4
D3
D2
D1
D0
(Code)
NOP
0
↑
1
-
0
0
0
0
0
0
0
0
(00H)
Parameter
NOTE: “-” Don’t care, can be set to VDDI or DGND level
No Parameter
-
-This command is empty command. It does not have effect on the display module.
Default
Status
Power On Sequence
S/W Reset
H/W Reset
Availability
Yes
Yes
Yes
Yes
Yes
.m
bt
re
Register
Availability
Status
Normal Mode On, Idle Mode Off, Sleep Out
Normal Mode On, Idle Mode On, Sleep Out
Partial Mode On, Idle Mode Off, Sleep Out
Partial Mode On, Idle Mode On, Sleep Out
Sleep In
m
Restriction
-However it can be used to terminate RAM data write or read as described in RAMWR (Memory Write), RAMHD
(Memory Read) and parameter write commands.
-
nd
.co
Description
-
w
w
w
Flow Chart
Default Value
N/A
N/A
N/A
© ORISE Technology Co., Ltd.
Proprietary & Confidential
23
Apr. 25, 2006
Preliminary Version: 0.1
Evaluation Only. Created with Aspose.Pdf.Kit. Copyright 2002-2005 Aspose Pty Ltd
Preliminary
SPFD54126B
6.2.2. SWRESET (01h): Software Reset
01H
SWRESET (Software Reset)
Inst / Para
D/CX
WRX
RDX
D17-8
D7
D6
D5
D4
D3
D2
D1
D0
(Code)
SWRESET
0
↑
1
-
0
0
0
0
0
0
0
1
(01H)
Parameter
NOTE: “-” Don’t care, can be set to VDDI or DGND level
Description
No Parameter
-
-When the Software Reset command is written, it causes a software reset. It resets the commands and parameters to
their S/W Reset default values and all source & gate outputs are set to VSS (display off). (See default tables in each
command description)
Note: The Frame Memory contents are not affected by this command.
-It will be necessary to wait 5msec before sending new command following software reset.
m
-The display module loads all display supplier’s factory default values to the registers during 5msec.
-If Software Reset is applied during Sleep Out mode, it will be necessary to wait 120msec before sending Sleep Out
command.
nd
.co
Restriction
.m
bt
Register
Availability
Status
Normal Mode On, Idle Mode Off, Sleep Out
Normal Mode On, Idle Mode On, Sleep Out
Partial Mode On, Idle Mode Off, Sleep Out
Partial Mode On, Idle Mode On, Sleep Out
Sleep In
re
-Software Reset command cannot be sent during Sleep Out sequence.
w
Default Value
N/A
N/A
N/A
w
w
Default
Status
Power On Sequence
S/W Reset
H/W Reset
Availability
Yes
Yes
Yes
Yes
Yes
SWRESET (01H)
Legend
Command
Display whole blank
screen
Parameter
Display
Flow Chart
Action
Set Commands
to S/W Default
Value
Mode
Sequential
transfer
Sleep In Mode
© ORISE Technology Co., Ltd.
Proprietary & Confidential
24
Apr. 25, 2006
Preliminary Version: 0.1
Evaluation Only. Created with Aspose.Pdf.Kit. Copyright 2002-2005 Aspose Pty Ltd
Preliminary
SPFD54126B
6.2.3. RDDID (04H): Read Display ID
04H
RDDID (Read Display ID)
Inst / Para
D/CX
WRX
RDX
D17-8
D7
D6
D5
D4
D3
D2
D1
D0
(Code)
RDDID
0
↑
1
-
0
0
0
0
0
1
0
0
(04H)
1 Parameter
st
1
1
↑
-
-
-
-
-
-
-
-
-
-
nd
1
1
↑
-
ID17
ID16
ID15
ID14
ID13
ID12
ID11
ID10
38h
rd
1
1
↑
-
ID27
ID26
ID25
ID24
ID23
ID22
ID21
ID20
80h
th
1
1
↑
-
ID37
ID36
ID35
ID34
ID33
ID32
ID31
ID30
62h
2 Parameter
3 Parameter
4 Parameter
NOTE: “-” Don’t care, can be set to VDDI or DGND level
-This read byte returns 18-bits display identification information.
nd
-The 2 parameter (ID17 to ID10): LCD module’s manufacturer ID.
rd
-The 3 parameter (ID27 to ID20): LCD module/driver version ID
nd
.co
Description
th
re
Status
Normal Mode On, Idle Mode Off, Sleep Out
Normal Mode On, Idle Mode On, Sleep Out
Partial Mode On, Idle Mode Off, Sleep Out
Partial Mode On, Idle Mode On, Sleep Out
Sleep In
Power On Sequence
S/W Reset
H/W Reset
w
Default
w
Status
w
.m
Register
Availability
-The 4 parameter (ID37 to UD30): LCD module/driver ID.
NOTE: Commands RDID1/2/3 (DAH, DBH, DCH) read data correspond to the parameters 2,3,4 of the command 04H,
respectively.
-
bt
Restriction
m
st
-The 1 parameter is dummy data
ID1
38h
80h
62h
Serial I/F Mode
Parallel I/F M
RDDID (04H)
RDDID (04H)
Availability
Yes
Yes
Yes
Yes
Yes
Default Value
ID2
38h
80h
62h
Legend
Host
Driver
Dummy Clock
Dummy Read
ID3
38h
80h
62h
Command
Parameter
Display
Flow Chart
Send ID1[7:0]
Send ID1[7:0]
Send ID2[7:0]
Send ID2[7:0]
Action
Mode
Sequential
transfer
Send ID3[7:0]
© ORISE Technology Co., Ltd.
Proprietary & Confidential
Send ID3[7:0]
25
Apr. 25, 2006
Preliminary Version: 0.1
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Preliminary
SPFD54126B
6.2.4. RDDST (09H): Read Display Status
09H
RDDST (Read Display Status)
Inst / Para
D/CX
WRX
RDX
D17-8
D7
D6
D5
D4
D3
D2
D1
D0
(Code)
RDDST
0
↑
1
-
0
0
0
0
1
0
0
1
(09H)
1 Parameter
st
1
1
↑
-
-
-
-
-
-
-
-
-
nd
1
1
↑
-
BSTON
MY
MX
MV
rd
1
1
↑
-
ST23
PF2
PF1
PF0
2 Parameter
3 Parameter
th
1
1
VSSON ST14 INVON ST12
↑
th
5 Parameter
1
1
GCS1 GCS0 TELOM HSON
↑
NOTE: “-” Don’t care, can be set to VDDI or DGND level
4 Parameter
-
ST24
NORO
IDMON PTLON SLOUT
N
ST11 DISON TEON GCS2
ML
RGB
ST25
VSON PCKON DEON
ST0
00h
61h
00h
00h
This command indicates the current status of the display as described in the table below:
m
MX
Column Address Order (MX)
MV
Row/Column Exchange (MV)
ML
Vertical Refresh Order (ML)
RGB
RGB/ BGR Order (RGB)
ST25
ST24
For Future Use
For Future Use
ST23
PF2
PF1
PF0
IDMON
PTLON
SLPOUT
For Future Use
Idle Mode On/Off
Partial Mode On/Off
Sleep In/Out
NORON
Display Normal Mode On/Off
VSSON
ST14
INVON
ST12
ST11
DISON
TEON
GCSEL2
Vertical Scrolling Status
For Future Use
Inversion Status
For Future Use
For Future Use
Display On/Off
Tearing effect line on/off
GCSEL1
Gamma Curve Selection
nd
.co
Row Address Order (MY)
.m
w
w
Color Pixel Format Definition
GCSEL0
TELOM
HSON
VSON
PCLKON
DEON
ST0
Value
‘1’ =Booster on,
‘0’ =Booster off
‘1’ =Decrement, (Bottom to Top, when MADCTL (36H) D7=’1’)
‘0’ =Increment, (Top to Bottom, when MADCTL (36H) D7=’0’)
‘1’ =Decrement, (Right to Left, when MADCTL (36H) D6=’1’)
‘0’ =Increment, (Left to Right, when MADCTL (36H) D6=’0’)
‘1’ = Row/column exchange, (when MADCTL (36H) D5=’1’)
‘0’ = Normal, (when MADCTL (36H) D5=’0’)
‘1’ =Decrement, (LCD refresh Bottom to Top, when MADCTL (36H)
D4=’1’)
“0”=Increment, (LCD refresh Top to Bottom, when MADCTL (36H)
D4=’0’)
‘1’ =BGR, (When MADCTL (36H) D3=’1’)
‘0’ =RGB, (When MADCTL (36H) D3=’0’)
‘0’
‘0’
bt
MY
w
Description
Description
Booster Voltage Status
re
Bit
BSTON
Tearing effect line mode
Horizontal Sync. (HS)
Vertical Sync, (VS, RGB I/F)
Pixel Clock (PCLK, RGB I/F)
Data Enable (DE, RGB I/F)
For Future Use
‘0’
“011” = 12-bits / pixel,
“101” = 16-bits / pixel,
“110” = 18-bits / pixel, others are no define
‘1’ = On, “0” = Off
‘1’ = On, “0” = Off
‘1’ = Out, “0” = In
‘1’ = Normal Display,
‘0’ = Partial Display
‘1’ = Scroll on,“0” = Scroll off
‘0’
‘1’ = On, “0” = Off
‘0’
‘0’
‘1’ = On, “0” = Off
‘1’ = On, “0” = Off
“000” = GC0
“001” = GC1
“010” = GC2
“011” = GC3, ”100” to “111” = Not defined
‘0’ = mode1, ‘1’ = mode2
‘1’ = On, ‘0’ = Off
‘1’ = On, ‘0’ = Off
‘1’ = On, ‘0’ = Off
‘1’ = On, ‘0’ = Off
‘0’
Note: ST0, ST11-ST12, ST14, ST23, ST24 are set to ‘0’
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Preliminary Version: 0.1
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Preliminary
SPFD54126B
Restriction
Status
Normal Mode On, Idle Mode Off, Sleep Out
Normal Mode On, Idle Mode On, Sleep Out
Partial Mode On, Idle Mode Off, Sleep Out
Partial Mode On, Idle Mode On, Sleep Out
Sleep In
Availability
Yes
Yes
Yes
Yes
Yes
Status
Default
ST[31-24]
0000-0000
0xxx-xx00
0000-0000
Power On Sequence
S/W Reset
H/W Reset
Parallel I/F Mode
RDDST (09H)
RDDST (09H)
nd
.co
Serial I/F Mode
Default Value (ST31 to ST0)
ST[23-16]
ST[15-8]
ST[7-0]
0110-0001 0000-0000 0000-0000
0xxx-0001 0000-0000 0000-0000
0110-0001 0000-0000 0000-0000
m
Register
Availability
-
Host
Driver
Dummy Clock
re
bt
w
Send ST[23:16]
Send ST[31:24]
.m
Send ST[31:24]
w
Flow Chart
Dummy Read
Send ST[7:0]
© ORISE Technology Co., Ltd.
Proprietary & Confidential
Command
Parameter
Display
Send ST[23:16]
Action
Mode
Send ST[15:8]
Sequential
transfer
w
Send ST[15:8]
Legend
Send ST[7:0]
27
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Preliminary Version: 0.1
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Preliminary
SPFD54126B
6.2.5. RDDPM (0AH): Read Display Power Mode
0AH
RDDPM (Read Display Power Mode)
Inst / Para
D/CX
WRX
RDX
D17-8
D7
D6
D5
D4
D3
D2
D1
D0
(Code)
RDDPM
0
↑
1
-
0
0
0
0
1
0
1
0
(0AH)
1 Parameter
1
1
↑
-
-
-
-
-
-
-
D1
D0
08h-
st
SLPOU NORO
nd
2 Parameter
1
1
BSTON IDMON PTLON
DISON
↑
T
N
NOTE: “-” Don’t care, can be set to VDDI or DGND level
bt
re
Description
nd
.co
m
-This command indicates the current status of the display as described in the table below:
Bit
Description
Value
“1”=Booster on,
BSTON
Booster Voltage Status
“0”=Booster off
“1” = Idle Mode On,
IDMON
Idle Mode On/Off
“0” = Idle Mode Off
“1” = Partial Mode On,
PTLON
Partial Mode On/Off
“0” = Partial Mode Off
“1” = Sleep Out,
SLPON
Sleep In/Out
“0” = Sleep In
“1” = Normal Display,
NORON
Display Normal Mode On/Off
“0” = Partial Display
“1” = Display On,
DISON
Display On/Off
“0” = Display Off
D1
Not Used
“0”
D0
Not Used
“0”
Availability
Yes
Yes
Yes
Yes
Yes
Status
Power On Sequence
S/W Reset
H/W Reset
Default Value (D7 to D0)
0000_1000 (08h)
0000_1000 (08h)
0000_1000 (08h)
w
w
Status
Normal Mode On, Idle Mode Off, Sleep Out
Normal Mode On, Idle Mode On, Sleep Out
Partial Mode On, Idle Mode Off, Sleep Out
Partial Mode On, Idle Mode On, Sleep Out
Sleep In
w
Register
Availability
.m
Restriction
Default
Legend
Serial I/F Mode
Parallel I/F Mode
RDDPM (0AH)
RDDPM (0AH)
Command
Host
Driver
Flow Chart
Send D[7:0]
Dummy Read
Parameter
Display
Action
Mode
Send D[7:0]
Sequential
transfer
© ORISE Technology Co., Ltd.
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Preliminary Version: 0.1
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Preliminary
SPFD54126B
6.2.6. RDDMADCTR (0BH): Read Display MADCTR
0BH
RDDMADCTR (Read Display MADCTR)
Inst / Para
D/CX
WRX
RDX
D17-8
D7
D6
D5
D4
D3
D2
D1
D0
(Code)
RDDMADCTR
0
↑
1
-
0
0
0
0
1
0
1
1
(0BH)
1
1
↑
-
-
-
-
-
-
-
-
-
-
MY
MV
ML
RGB
D2
D1
D0
00h
st
1 Parameter
nd
MX
2 Parameter
1
1
↑
NOTE: “-” Don’t care, can be set to VDDI or DGND level
m
re
nd
.co
Description
-This command indicates the current status of the display as described in the table below:
Bit
Description
Value
MX
Row Address Order
‘1’ =Decrement, “0”=Increment
MY
Column Address Order
‘1’ =Decrement, “0”=Increment
‘1’ = Row/column exchange (MV=1)
MV
Row/Column Order (MV)
‘0’ = Normal (MV=0)
‘1’ =LCD Refresh Top to Bottom
ML
Vertical Refresh Order
‘0’ =LCD Refresh Bottom to Top
RGB
RGB/BGR Order
‘1’ =BGR, “0”=RGB
D2
Not Used
‘0’
D1
Not Used
‘0’
D0
Not Used
‘0’
bt
Restriction
Default
Status
Power On Sequence
S/W Reset
H/W Reset
w
w
.m
Register
Availability
Status
Normal Mode On, Idle Mode Off, Sleep Out
Normal Mode On, Idle Mode On, Sleep Out
Partial Mode On, Idle Mode Off, Sleep Out
Partial Mode On, Idle Mode On, Sleep Out
Sleep In
Availability
Yes
Yes
Yes
Yes
Yes
w
Default Value (D7 to D0)
0000_0000 (00h)
No change
0000_0000 (00h)
Serial I/F Mode
Parallel I/F Mode
RDDMADCTR (0BH)
RDDMADCTR (0BH)
Legend
Command
Host
Driver
Flow Chart
Send D[7:0]
Dummy Read
Parameter
Display
Action
Mode
Send D[7:0]
Sequential
transfer
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Preliminary Version: 0.1
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Preliminary
SPFD54126B
6.2.7. RDDCOLMOD (0CH): Read Display Pixel Format
0CH
RDDCOLMOD (Read Display Pixel Format)
Inst / Para
D/CX
WRX
RDX
D17-8
D7
D6
D5
D4
D3
D2
D1
D0
(Code)
RDDCOLMOD
0
↑
1
-
0
0
0
0
1
1
0
0
(0CH)
1
1
↑
-
-
-
-
-
-
-
-
-
-
VIPF2
VIPF1
VIPF0
D3
IFPF2
IFPF1
IFPF0
66h
st
1 Parameter
nd
2 Parameter
1
1
VIPF3
↑
NOTE: “-” Don’t care, can be set to VDDI or DGND level
Restriction
nd
.co
Availability
Yes
Yes
Yes
Yes
Yes
w
.m
Status
Normal Mode On, Idle Mode Off, Sleep Out
Normal Mode On, Idle Mode On, Sleep Out
Partial Mode On, Idle Mode Off, Sleep Out
Partial Mode On, Idle Mode On, Sleep Out
Sleep In
w
w
Register
Availability
RGB Interface Color Format
16-bits/pixel (1-times data transfer)
18-bits/pixel (1-times data transfer)
Reserved
18-bits/pixel (3-times data transfer)
re
VIPF[3:0]
0101
5
0110
6
0111
7
1110
14
Others are no define and invalid
bt
Description
m
-This command indicates the current status of the display as described in the table below:
IFPF[2:0]
MCU Interface Color Format
011
3
12-bits/pixel
101
5
16-bits/pixel
110
6
18-bits/pixel
111
7
Reserved
Others are no define and invalid
Status
Default
Default Value
IFPF[2:0]
VIPF[3:0]
0101 (16-bits/pixel)
0110 (18-bits/pixel)
No Change
No Change
0101 (16-bits/pixel)
0110 (18-bits/pixel)
Power On Sequence
S/W Reset
H/W Reset
Serial I/F Mode
Parallel I/F Mode
RDDCOLMOD (0CH)
RDDCOLMOD (0CH)
Legend
Command
Host
Driver
Flow Chart
Send D[7:0]
Dummy Read
Parameter
Display
Action
Mode
Send D[7:0]
Sequential
transfer
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Preliminary Version: 0.1
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Preliminary
SPFD54126B
6.2.8. RDDIM (0DH): Read Display Image Mode
0DH
RDDIM (Read Display Image Mode
Inst / Para
D/CX
WRX
RDX
D17-8
D7
D6
D5
D4
D3
D2
D1
D0
(Code)
RDDIM
0
↑
1
-
0
0
0
0
1
1
0
1
(0DH)
1 Parameter
1
1
↑
-
-
-
-
-
-
-
-
-
-
D6
INVON
D4
D3
GCS2
GCS1
GCS0
00h
st
nd
2 Parameter
1
1
VSSON
↑
NOTE: “-” Don’t care, can be set to VDDI or DGND level
m
nd
.co
re
Description
-This command indicates the current status of the display as described in the table below:
Bit
Description
Value
“1” = Vertical scrolling is On,
VSSON Vertical Scrolling On/Off
“0” = Vertical scrolling is Off
D6
For Future Use
“0” (Not used)
“1” = Inversion is On,
INVON Inversion On/Off
“0” = Inversion is Off
D4
For Future Use
“0” (Not used)
D3
For Future Use
“0” (Not used)
GCS2
“000” = GC0,
“001” = GC1,
GCS1
Gamma Curve Selection
“010” = GC2,
GCS0
“011” = GC3, ”100” to “111” = Not defined
-
bt
Restriction
Default
Status
Power On Sequence
S/W Reset
H/W Reset
w
w
.m
Register
Availability
Status
Normal Mode On, Idle Mode Off, Sleep Out
Normal Mode On, Idle Mode On, Sleep Out
Partial Mode On, Idle Mode Off, Sleep Out
Partial Mode On, Idle Mode On, Sleep Out
Sleep In
Availability
Yes
Yes
Yes
Yes
Yes
w
Default Value (D7 to D0)
0000_0000 (00h)
0000_0000 (00h)
0000_0000 (00h)
Serial I/F Mode
Parallel I/F Mode
RDDIM (0DH)
RDDIM (0DH)
Legend
Command
Host
Driver
Flow Chart
Send D[7:0]
Dummy Read
Parameter
Display
Action
Mode
Send D[7:0]
Sequential
transfer
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Preliminary
SPFD54126B
6.2.9. RDDSM (0EH): Read Display Signal Mode
RDDSM (Read Display Signal Mode)
0EH
Inst / Para
D/CX
WRX
RDX
D17-8
D7
D6
D5
D4
D3
D2
D1
D0
(Code)
RDDSM
0
↑
1
-
0
0
0
0
1
1
1
0
(0EH)
1 Parameter
1
1
↑
-
-
-
-
-
-
-
-
-
-
D1
D0
00h
st
nd
2 Parameter
1
1
TEON TELOM HSON
↑
NOTE: “-” Don’t care, can be set to VDDI or DGND level
VSON PCKON DEON
-This command indicates the current status of the display as described in the table below:
Value
TELOM
Tearing effect line mode
HSON
VSON
PCKON
DEON
D1
D0
Horizontal Sync. (RGB I/F) On/Off
Vertical Sync. (RGB I/F) On/Off
Pixel Clock (PCLK, RGB I/F) On/Off
Data Enable (DE, RGB I/F) On/Off
Not Used
Not Used
re
Restriction
“1” = On, “0” = Off
“0” = mode1,
“1” = mode2
“1” = On, “0” = Off
“1” = On, “0” = Off
“1” = On, “0” = Off
“1” = On, “0” = Off
“1” = On, “0” = Off
“1” = On, “0” = Off
m
Description
Description
Tearing Effect Line On/Off
nd
.co
Bit
TEON
Default
Status
Power On Sequence
S/W Reset
H/W Reset
w
w
.m
bt
Register
Availability
Status
Normal Mode On, Idle Mode Off, Sleep Out
Normal Mode On, Idle Mode On, Sleep Out
Partial Mode On, Idle Mode Off, Sleep Out
Partial Mode On, Idle Mode On, Sleep Out
Sleep In
Availability
Yes
Yes
Yes
Yes
Yes
w
Default Value (D7 to D0)
0000_0000 (00h)
0000_0000 (00h)
0000_0000 (00h)
Serial I/F Mode
Parallel I/F Mode
RDDSM (0EH)
RDDSM (0EH)
Legend
Command
Host
Driver
Flow Chart
Send D[7:0]
Dummy Read
Parameter
Display
Action
Mode
Send D[7:0]
Sequential
transfer
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Preliminary
SPFD54126B
6.2.10. RDDSDR (0FH): Read Display Self-Diagnostic Result
0FH
RDDSDR (Read Display Self-Diagnostic Result)
Inst / Para
D/CX
WRX
RDX
D17-8
D7
D6
D5
D4
D3
D2
D1
D0
(Code)
RDDSDR
0
↑
1
-
0
0
0
0
1
1
1
1
(0FH)
1
1
↑
-
-
-
-
-
-
-
-
-
-
FUND
ATTD
BRD
D3
D2
D1
D0
00h
st
1 Parameter
nd
2 Parameter
1
1
RELD
↑
NOTE: “-” Don’t care, can be set to VDDI or DGND level
-This command indicates the current status of the display as described in the table below:
Value
See section 6.15.1
See section 6.15.1
See section 6.15.3
See section 6.15.4
“0”
“0”
“0”
“0”
m
Description
Register Loading Detection
Functionality Detection
Chip Attachment Detection
Display Glass Break Detection
Not Used
Not Used
Not Used
Not Used
nd
.co
Description
Bit
RELD
FUND
ATTD
BRD
D3
D2
D1
D0
Default
Status
Power On Sequence
S/W Reset
H/W Reset
w
.m
bt
Register
Availability
Status
Normal Mode On, Idle Mode Off, Sleep Out
Normal Mode On, Idle Mode On, Sleep Out
Partial Mode On, Idle Mode Off, Sleep Out
Partial Mode On, Idle Mode On, Sleep Out
Sleep In
re
Restriction
Availability
Yes
Yes
Yes
Yes
Yes
w
w
Default Value (D7 to D0)
0000_0000 (00h)
0000_0000 (00h)
0000_0000 (00h)
Serial I/F Mode
Parallel I/F Mode
RDDSDR (0FH)
RDDSTR (0FH)
Legend
Command
Host
Driver
Flow Chart
Send D[7:0]
Dummy Read
Parameter
Display
Action
Mode
Send D[7:0]
Sequential
transfer
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Preliminary
SPFD54126B
6.2.11. SLPIN (10H): Sleep In
10H
SLPIN (Sleep In)
Inst / Para
D/CX
WRX
RDX
D17-8
D7
D6
D5
D4
D3
D2
D1
D0
(Code)
SLPIN
0
↑
1
-
0
0
0
1
0
0
0
0
(10H)
st
1 Parameter
NOTE: “-” Don’t care, can be set to VDDI or DGND level
No parameter
-
-This command causes the LCD module to enter the minimum power consumption mode.
-In this mode the DC/DC converter is stopped, Internal display oscillator is stopped, and panel scanning is stopped.
Sleep In
1.6V-3.6V
m
VDDI
nd
.co
VDD
Gate Output
Description
Source Output
0V
VCOM Output
0V
VGH
STOP
0V or VDD
0V or VDD
0V
0V or VDD
w
AVDD
DISCHARGE
w
VGL
0V
STOP
.m
DC charge in capacitors
bt
Internal Oscillator
STOP
Blanking display (over 1frame display) *
re
Internal counter
2.6V-3.5V
IC Internal reset
w
0V
* Note: complete 1 frame display (ex: continue 2-falling edges of VS)
-MCU interface and memory are still working and the memory keeps its contents
-This command has no effect when module is already in sleep in mode. Sleep In Mode can only be exit by the Sleep Out
Command (11H).
Restriction
-It will be necessary to wait 5msec before sending next command, this is to allow time for the supply voltages and clock
circuits to stabilize.
-It will be necessary to wait 120msec after sending Sleep Out command (when in Sleep In Mode) before Sleep In
command can be sent.
Register
Availability
Status
Normal Mode On, Idle Mode Off, Sleep Out
Normal Mode On, Idle Mode On, Sleep Out
Partial Mode On, Idle Mode Off, Sleep Out
Partial Mode On, Idle Mode On, Sleep Out
Sleep In
Availability
Yes
Yes
Yes
Yes
Yes
Status
Power On Sequence
S/W Reset
H/W Reset
Default Value
Sleep In mode
Sleep In mode
Sleep In mode
Default
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Preliminary
SPFD54126B
-It takes about 120msec to get into Sleep In mode (booster off state) after SLPIN command issued.
-The results of booster off can be check by RDDST (09H) command Bit31.
Legend
SPLIN (10H)
Display whole blank
screen (Automatic No
effect to DISP
ON/OFF Command)
Parameter
Display
Stop
Internal
Oscillator
Drain charge
from LCD
panel
Mode
Sequential
transfer
w
w
w
.m
bt
re
nd
.co
Sleep In
Action
m
Flow Chart
Command
Stop
DC/DC
Converte
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Preliminary
SPFD54126B
6.2.12. SLPOUT (11H): Sleep Out
11H
SLPOUT (Sleep Out)
Inst / Para
D/CX
WRX
RDX
D17-8
D7
D6
D5
D4
D3
D2
D1
D0
(Code)
SLPOUT
0
↑
1
-
0
0
0
1
0
0
0
1
(11H)
st
1 Parameter
NOTE: “-” Don’t care, can be set to VDDI or DGND level
No Parameter
-
-This command turns off sleep mode.
-In this mode the DC/DC converter is enabled, Internal display oscillator is started, and panel scanning is started.
Sleep Out
1.6V-3.6V
m
VDDI
0V or VDD
VGL
0V
VGH
0V or VDD
Internal counter
STOP
IC Internal reset
0V
Gate Output
Description
0V
0V
Memory Contents
0V
0V
Memory Contents
w
w
Start
STOP
STOP
Source Output
VCOM Output
nd
.co
AVDD
Start
re
STOP
2.6V-3.5V
bt
Internal Oscillator
.m
VDD
If DISPON 29H is set
w
Blanking display (over 1frame display) *
* Note: complete 1 frame display (ex: continue 2-falling edges of VS)
-This command has no effect when module is already in sleep out mode. Sleep Out Mode can only be exit by the Sleep
In Command (10H).
-It will be necessary to wait 5msec before sending next command, this is to allow time for the supply voltages and clock
circuits to stabilize.
Restriction
-DRIVER loads all default values of extended and test command to the registers during this 5msec and there cannot be
any abnormal visual effect on the display image if those default and register values are same when this load is done
and when the DRIVER is already Sleep Out mode.
-DRIVER is doing self-diagnostic functions during this 5msec. See also section 8.19.
-It will be necessary to wait 120msec after sending Sleep In command (when in Sleep Out mode) before Sleep Out
command can be sent
Register
Availability
Status
Normal Mode On, Idle Mode Off, Sleep Out
Normal Mode On, Idle Mode On, Sleep Out
Partial Mode On, Idle Mode Off, Sleep Out
Partial Mode On, Idle Mode On, Sleep Out
Sleep In
Availability
Yes
Yes
Yes
Yes
Yes
Default
Status
Power On Sequence
S/W Reset
H/W Reset
Default Value
Sleep In mode
Sleep In mode
Sleep In mode
© ORISE Technology Co., Ltd.
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Preliminary
SPFD54126B
-It takes 120msec to become Sleep Out mode (booster on mode) after SLPOUT command issued.
-The results of booster on can be checked by RDDST (09H) command Bit31.
SLPOUT (11H)
Legend
Start Internal
Oscillator
Start
DC-DC
Converter
Display Memory
contents in accordance
with the current command
Charge Offset
voltage for
LCD Panel
nd
.co
table settings
m
Flow Chart
Display whole blank
screen for 2 frames
(Automatic No effect to
DISP ON/OFF
Command
Parameter
Display
Action
Mode
Sequential
transfer
w
w
w
.m
bt
re
Sleep Out
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Preliminary
SPFD54126B
6.2.13. PTLON (12H): Partial Display Mode On
12H
PTLON (Partial Display Mode On)
Inst / Para
D/CX
WRX
RDX
D17-8
D7
D6
D5
D4
D3
D2
D1
D0
(Code)
PTLON
0
↑
1
-
0
0
0
1
0
0
1
0
(12H)
st
1 Parameter
NOTE: “-” Don’t care, can be set to VDDI or DGND level
No Parameter
-
-This command turns on Partial mode. The partial mode window is described by the Partial Area command (30H)
Description
-To leave Partial mode, the Normal Display Mode On command (13H) should be written.
Restriction
This command has no effect when Partial mode is active.
-There is no abnormal visual effect during mode change between Normal mode On <-> Partial mode On.
m
bt
.m
See Partial Area (30H)
Default Value
Normal Mode On
Normal Mode On
Normal Mode On
w
w
w
Flow Chart
nd
.co
Default
Status
Power On Sequence
S/W Reset
H/W Reset
Availability
Yes
Yes
Yes
Yes
Yes
re
Register
Availability
Status
Normal Mode On, Idle Mode Off, Sleep Out
Normal Mode On, Idle Mode On, Sleep Out
Partial Mode On, Idle Mode Off, Sleep Out
Partial Mode On, Idle Mode On, Sleep Out
Sleep In
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6.2.14. NORON (13H): Normal Display Mode On
13H
NORON (Normal Display Mode On)
Inst / Para
D/CX
WRX
RDX
D17-8
D7
D6
D5
D4
D3
D2
D1
D0
(Code)
NORON
0
↑
1
-
0
0
0
1
0
0
1
1
(13H)
st
1 Parameter
NOTE: “-” Don’t care, can be set to VDDI or DGND level
No Parameter
-
-This command returns the display to normal mode.
Description
-Normal display mode on means Partial mode off, Scroll mode Off.
-Exit from NORON by the Partial mode On command (12H)
-There is no abnormal visual effect during mode change from Normal mode On to Partial mode On.
Default
Status
Power On Sequence
S/W Reset
H/W Reset
bt
.m
Default Value
Normal Mode On
Normal Mode On
Normal Mode On
-See Partial Area and Vertical Scrolling Definition Descriptions for details of when to use this command
w
w
w
Flow Chart
Availability
Yes
Yes
Yes
Yes
Yes
re
Register
Availability
Status
Normal Mode On, Idle Mode Off, Sleep Out
Normal Mode On, Idle Mode On, Sleep Out
Partial Mode On, Idle Mode Off, Sleep Out
Partial Mode On, Idle Mode On, Sleep Out
Sleep In
m
-This command has no effect when Normal Display mode is active.
nd
.co
Restriction
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6.2.15. INVOFF (20H): Display Inversion Off
20H
INVOFF (Display Inversion Off)
Inst / Para
D/CX
WRX
RDX
D17-8
D7
D6
D5
D4
D3
D2
D1
D0
(Code)
INVOFF
0
↑
1
-
0
0
1
0
0
0
0
0
(20H)
st
1 Parameter
NOTE: “-” Don’t care, can be set to VDDI or DGND level
No Parameter
-
-This command is used to recover from display inversion mode.
-This command makes no change of contents of frame memory.
Top-Left (0,0)
Display
-This command has no effect when module is already inversion off mode.
.m
Restriction
bt
re
nd
.co
Description
(Example)
Memory
m
-This command does not change any other status.
Default
Status
Power On Sequence
S/W Reset
H/W Reset
Availability
Yes
Yes
Yes
Yes
Yes
w
w
w
Register
Availability
Status
Normal Mode On, Idle Mode Off, Sleep Out
Normal Mode On, Idle Mode On, Sleep Out
Partial Mode On, Idle Mode Off, Sleep Out
Partial Mode On, Idle Mode On, Sleep Out
Sleep In
Default Value
Display Inversion off
Display Inversion off
Display Inversion off
Legend
Display Inversion On
Mode
Flow Chart
Command
Parameter
Display
INVOFF (20H)
Action
Mode
Display Inversion OFF
Mode
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6.2.16. INVON (21H): Display Inversion On
21H
INVON (Display Inversion On)
Inst / Para
D/CX
WRX
RDX
D17-8
D7
D6
D5
D4
D3
D2
D1
D0
(Code)
INVON
0
↑
1
-
0
0
1
0
0
0
0
1
(21H)
st
1 Parameter
NOTE: “-” Don’t care, can be set to VDDI or DGND level
No Parameter
-
-This command is used to enter into display inversion mode
-This command makes no change of contents of frame memory.
-This command does not change any other status.
(Example)
Memory
Display
-This command has no effect when module is already Inversion On mode.
.m
Restriction
bt
re
Top-Left (0,0)
nd
.co
Description
m
-To exit from Display Inversion On, the Display Inversion Off command (20H) should be written.
Default
Status
Power On Sequence
S/W Reset
H/W Reset
Availability
Yes
Yes
Yes
Yes
Yes
w
w
w
Register
Availability
Status
Normal Mode On, Idle Mode Off, Sleep Out
Normal Mode On, Idle Mode On, Sleep Out
Partial Mode On, Idle Mode Off, Sleep Out
Partial Mode On, Idle Mode On, Sleep Out
Sleep In
Default Value
Display Inversion off
Display Inversion off
Display Inversion off
Legend
Display Inversion OFF
Mode
Flow Chart
Command
Parameter
Display
INVON (21H)
Action
Mode
Display Inversion ON
Mode
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6.2.17. GAMSET (26H): Gamma Set
26H
GAMSET (Gamma Set)
Inst / Para
D/CX
WRX
RDX
D17-8
D7
D6
D5
D4
D3
D2
D1
D0
(Code)
GAMSET
0
↑
1
-
0
0
1
0
0
1
1
0
(26H)
GC6
GC5
GC4
GC3
GC2
GC1
GC0
01h
st
1 Parameter
1
GC7
1
↑
NOTE: “-” Don’t care, can be set to VDDI or DGND level
-This command is used to select the desired Gamma curve for the current display. A maximum of 4 curves can be
selected. The curves are defined in section 6.12. The curve is selected by setting the appropriate bit in the parameter as
described in the Table.
Parameter
Curve Selected
01h
GC0
Gamma Curve 1 (G2.2)
02h
GC1
Gamma Curve 2 (G1.8)
04h
GC2
Gamma Curve 3 (G2.5)
08h
GC3
Note: All other values are undefined.
Gamma Curve 4 (G1.0)
-Values of GC [7:0] not shown in table above are invalid and will not change the current selected Gamma curve until valid
is received.
Default
Status
Power On Sequence
S/W Reset
H/W Reset
w
.m
bt
Register
Availability
Status
Normal Mode On, Idle Mode Off, Sleep Out
Normal Mode On, Idle Mode On, Sleep Out
Partial Mode On, Idle Mode Off, Sleep Out
Partial Mode On, Idle Mode On, Sleep Out
Sleep In
re
Restriction
nd
.co
Description
m
GC [7:0]
Availability
Yes
Yes
Yes
Yes
Yes
w
w
Default Value
01h
01h
01h
Legend
----------------
Command
GAMSET (26H)
Parameter
Display
st
Flow Chart
1 Parameter: GC[7:0]
Action
Mode
Sequential
transfer
New Gamma
Curve Loaded
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6.2.18. DISPOFF (28H): Display Off
28H
DISPOFF (Display Off)
Inst / Para
D/CX
WRX
RDX
D17-8
D7
D6
D5
D4
D3
D2
D1
D0
(Code)
DISPOFF
0
↑
1
-
0
0
1
0
1
0
0
0
(28H)
st
1 Parameter
NOTE: “-” Don’t care, can be set to VDDI or DGND level
No Parameter
-
-This command is used to enter into DISPLAY OFF mode. In this mode, the output from Frame Memory is disables and
blank page inserted.
-This command makes no change of contents of frame memory.
-This command does not change any other status.
-There will be no abnormal visible effect on the display.
m
-Exit from this command by Display On (29H)
nd
.co
(Example)
Top-Left (0,0)
Display
VDDI
Description
1.6V-3.6V
.m
Display OFF
bt
re
Memory
w
Gate Output
2.6V-3.5V
w
VDD
0V
VCOM Output
0V
w
Source Output
STOP
Blanking display (over 1 frame display) *
0V
Internal counter
STOP
Internal Oscillator
VGH
VGL
AVDD
IC Internal reset
* Note: complete 1 frame display (ex: continue 2-falling edges of VS)
Restriction
Register
Availability
-This command has no effect when module is already in Display Off mode.
Status
Normal Mode On, Idle Mode Off, Sleep Out
Normal Mode On, Idle Mode On, Sleep Out
Partial Mode On, Idle Mode Off, Sleep Out
Partial Mode On, Idle Mode On, Sleep Out
Sleep In
Availability
Yes
Yes
Yes
Yes
Yes
Status
Power On Sequence
S/W Reset
H/W Reset
Default Value
Display off
Display off
Display off
Default
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Legend
Display On Mode
Command
Parameter
Flow Chart
Display
DISPOFF (28H)
Action
Mode
Display OFF Mode
w
w
w
.m
bt
re
nd
.co
m
Sequential
transfer
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6.2.19. DISPON (29H): Display On
29H
DISPON (Display On)
Inst / Para
D/CX
WRX
RDX
D17-8
D7
D6
D5
D4
D3
D2
D1
D0
(Code)
DISPON
0
↑
1
-
0
0
1
0
1
0
0
1
(29H)
st
1 Parameter
NOTE: “-” Don’t care, can be set to VDDI or DGND level
No Parameter
-
-This command is used to recover from DISPLAY OFF mode. Output from the Frame Memory is enabled.
-This command makes no change of contents of frame memory.
-This command does not change any other status.
Display
re
nd
.co
Memory
m
(Example)
Top-Left (0,0)
VDD
1.6V-3.6V
2.6V-3.5V
Blanking display (over 1 frame display) *
.m
Description
Display ON
bt
VDDI
Gate Output
w
VCOM Output
STOP
Memory Contents
0V
Memory Contents
Start
STOP
w
Internal counter
0V
w
Source Output
Internal Oscillator
VGH
VGL
AVDD
IC Internal reset
* Note: complete 1 frame display (ex: continue 2-falling edges of VS)
Restriction
-This command has no effect when module is already in Display On mode.
Register
Availability
Status
Normal Mode On, Idle Mode Off, Sleep Out
Normal Mode On, Idle Mode On, Sleep Out
Partial Mode On, Idle Mode Off, Sleep Out
Partial Mode On, Idle Mode On, Sleep Out
Sleep In
Availability
Yes
Yes
Yes
Yes
Yes
Default
Status
Power On Sequence
S/W Reset
H/W Reset
Default Value
Display off
Display off
Display off
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Legend
Display OFF Mode
Command
Parameter
Flow Chart
Display
DISPON (29H)
Action
Mode
Display ON Mode
w
w
w
.m
bt
re
nd
.co
m
Sequential
transfer
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6.2.20. CASET (2AH): Column Address Set
CASET (Column Address Set)
2AH
Inst / Para
D/CX
WRX
RDX
D17-8
D7
D6
D5
D4
D3
D2
D1
D0
(Code)
CASET
0
↑
1
-
0
0
1
0
1
0
1
0
(2AH)
1 Parameter
st
1
↑
1
-
XS15
XS14
XS13
XS12
XS11
XS10
XS9
XS8
00h
nd
1
↑
1
-
XS7
XS6
XS5
XS4
XS3
XS2
XS1
XS0
00h
rd
1
↑
1
-
XE15
XE14
XE13
XE12
XE11
XE10
XE9
XE8
4 Parameter
1
1
XE7
↑
NOTE: “-” Don’t care, can be set to VDDI or DGND level
XE6
XE5
XE4
XE3
XE2
XE1
XE0
2 Parameter
3 Parameter
th
-This command is used to define area of frame memory where MCU can access.
-This command makes no change on the other driver status.
m
-The value of XS [15:0] and XE [15:0] are referred when RAMWR command comes.
nd
.co
-Each value represents one column line in the Frame Memory.
(Example)
XS[15:0]
XE[15:0]
w
.m
bt
re
Description
XS [15:0] always must be equal to or less than XE [15:0]
w
When XS [15:0] or XE [15:0] is greater than maximum address like below, data of out of range will be ignored.
w
1. 176x220 memory base (GM1, GM0 = “00”)
(Parameter range: 0 ≤ XS [15:0] ≤ XE [15:0] ≤ 175 (00AFh)): MV=”0”
If the “XS” or “XE” are large then 175d, it become 175d
(Parameter range: 0 ≤ XS [15:0] ≤ XE [15:0] ≤ 219d (00DBh)): MV=”1”
If the “XS” or “XE” are large then 219d, it become 219d
2. 176x176 memory base (GM1, GM0 = “01”)
Restriction
(Parameter range: 0 ≤ XS [15:0] ≤ XE [15:0] ≤ 175 (00AFh)): MV=”0”
If the “XS” or “XE” are large then 175d, it become 175d
(Parameter range: 0 ≤ XS [15:0] ≤ XE [15:0] ≤ 175 (00AFh)): MV=”1”
If the “XS” or “XE” are large then 175d, it become 175d
1. 176x132 memory base (GM1, GM0 = “11”)
(Parameter range: 0 ≤ XS [15:0] ≤ XE [15:0] ≤ 175 (00AFh)): MV=”0”
If the “XS” or “XE” are large then 175d, it become 175d
(Parameter range: 0 ≤ XS [15:0] ≤ XE [15:0] ≤ 131d (0083h)): MV=”1”
If the “XS” or “XE” are large then 131d, it become 131d
Register
Availability
Status
Normal Mode On, Idle Mode Off, Sleep Out
Normal Mode On, Idle Mode On, Sleep Out
Partial Mode On, Idle Mode Off, Sleep Out
Partial Mode On, Idle Mode On, Sleep Out
Sleep In
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Yes
Yes
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Yes
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1. 176x220 memory base (GM1, GM0 = “00”)
Status
Default Value
XE [15:0] (MV=’0’)
XE [15:0] (MV=’1’)
00AFh (175d)
00AFh (175d)
00DBh (219d)
00AFh (175d)
XS [15:0]
Power On Sequence
S/W Reset
H/W Reset
0000h
2. 176x176 memory base (GM1, GM0 = “01”)
Status
Default
Default Value
XE [15:0] (MV=’0’)
XS [15:0]
Power On Sequence
S/W Reset
H/W Reset
0000h
XE [15:0] (MV=’1’)
00AFh (175d)
3. 176x132 memory base (GM1, GM0 = “11”)
Default Value
XE [15:0] (MV=’0’)
XE [15:0] (MV=’1’)
00AFh (175d)
00AFh (175d)
0083h (132d)
00AFh (175d)
m
Status
Power On Sequence
S/W Reset
H/W Reset
nd
.co
XS [15:0]
re
0000h
.m
CASET (2AH)
bt
Partial Mode
w
w
th
w
rd
1st & 2nd Parameter:
XS[15:0]
RASET (2BH)
Flow Chart
rd
st
nd
1 & 2 Parameter:
YS[15:0]
th
If Needed
RAMWR (2CH)
Image Data
D1[B:0],D2[B:0]……Dn[B:0]
Legend
Command
Parameter
Display
Action
Mode
Note: B=17
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6.2.21. RASET (2BH): Row Address Set
2BH
RASET (Row Address Set)
Inst / Para
D/CX
WRX
RDX
D17-8
D7
D6
D5
D4
D3
D2
D1
D0
(Code)
RASET
0
↑
1
-
0
0
1
0
1
0
1
1
(2BH)
1 Parameter
st
1
↑
1
-
YS15
YS14
YS13
YS12
YS11
YS10
YS9
YS8
00h
nd
1
↑
1
-
YS7
YS6
YS5
YS4
YS3
YS2
YS1
YS0
00h
rd
1
↑
1
-
YE15
YE14
YE13
YE12
YE11
YE10
YE9
YE8
4 Parameter
1
1
YE7
↑
NOTE: “-” Don’t care, can be set to VDDI or DGND level
YE6
YE5
YE4
YE3
YE2
YE1
YE0
2 Parameter
3 Parameter
th
-This command is used to define area of frame memory where MCU can access.
-This command makes no change on the other driver status.
nd
.co
-Each value represents one column line in the Frame Memory.
m
-The value of YS [15:0] and YE [15:0] are referred when RAMWR command comes.
(Example)
Description
bt
re
YS[15:0]
.m
YE[15:0]
w
YS [15:0] always must be equal to or less than YE [15:0]
When YS [15:0] or YE [15:0] are greater than maximum row address like below, data of out of range will be ignored.
w
1. 176x220 memory base (GM1, GM0 = “00”)
w
(Parameter range: 0 ≤ YS [15:0] ≤ YE [15:0] ≤ 219 (0DBh)): MV=”0”
If the “XS” or “XE” are large then 219d, it become 219d
(Parameter range: 0 ≤ YS [15:0] ≤ YE [15:0] ≤ 175 (00AFh)): MV=”1”
If the “XS” or “XE” are large then 175d, it become 175d
2. 176x176 memory base (GM1, GM0 = “01”)
Restriction
(Parameter range: 0 ≤ YS [15:0] ≤ YE [15:0] ≤ 175 (00AFh)): MV=”0”
If the “XS” or “XE” are large then 175d, it become 175d
(Parameter range: 0 ≤ YS [15:0] ≤ YE [15:0] ≤ 175 (00AFh)): MV=”1”
If the “XS” or “XE” are large then 175d, it become 175d
3. 176x132 memory base (GM1, GM0 = “11”)
(Parameter range: 0 ≤ YS [15:0] ≤ YE [15:0] ≤ 131 (0083h)): MV=”0”
If the “XS” or “XE” are large then 131d, it become 131d
(Parameter range: 0 ≤ YS [15:0] ≤ YE [15:0] ≤ 175 (00AFh)): MV=”1”
If the “XS” or “XE” are large then 175d, it become 175d
Register
Availability
Status
Normal Mode On, Idle Mode Off, Sleep Out
Normal Mode On, Idle Mode On, Sleep Out
Partial Mode On, Idle Mode Off, Sleep Out
Partial Mode On, Idle Mode On, Sleep Out
Sleep In
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Yes
Yes
Yes
Yes
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1. 176x220 memory base (GM1, GM0 = “00”)
Status
Default Value
YE [15:0] (MV=’0’)
YE [15:0] (MV=’1’)
0DBh (219d)
0DBh (219d)
00AFh (175d)
0DBh (219d)
YS [15:0]
Power On Sequence
S/W Reset
H/W Reset
0000h
2. 176x176 memory base (GM1, GM0 = “01”)
Status
Default
Default Value
YE [15:0] (MV=’0’)
YS [15:0]
Power On Sequence
S/W Reset
H/W Reset
0000h
YE [15:0] (MV=’1’)
00AFh (175d)
3. 176x132 memory base (GM1, GM0 = “11”)
Default Value
YE [15:0] (MV=’0’)
YE [15:0] (MV=’1’)
0083h (131d)
0083h (131d)
00AFh (175d)
0083h (131d)
m
Status
Power On Sequence
S/W Reset
H/W Reset
nd
.co
YS [15:0]
re
0000h
.m
w
w
th
w
rd
st
nd
1 & 2 Parameter:
XS[15:0]
If Needed
CASET (2AH)
bt
Partial Mode
RASET (2BH)
Flow Chart
rd
st
nd
1 & 2 Parameter:
YS[15:0]
th
Legend
RAMWR (2CH)
Command
Parameter
If Needed
Image Data
D1[B:0],D2[B:0]……Dn[B:0]
Display
Action
Mode
Any Command
Sequential
transfer
Note: B=17
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6.2.22. RAMWR (2CH): Memory Write
2CH
RAMWR (Memory Write)
Inst / Para
D/CX
WRX
RDX
D17-8
D7
D6
D5
D4
D3
D2
D1
D0
(Code)
RAMWR
0
↑
1
-
0
0
1
0
1
1
0
0
(2CH)
1 Parameter
∣
1
↑
1
1
↑
1
D17-8
∣
D7
∣
D6
∣
D5
∣
D4
∣
D3
∣
D2
∣
D1
∣
D0
∣
∣
N Parameter
1
1
D17-8
D7
↑
NOTE: “-” Don’t care, can be set to VDDI or DGND level
D6
D5
D4
D3
D2
D1
D0
-
st
th
-This command is used to transfer data from MCU to frame memory.
-This command makes no change to the other driver status.
m
-The Start Column/Start Row positions are different in accordance with MADCTR setting. (See section 6.6)
nd
.co
Description
-When this command is accepted, the column register and the row register are reset to the Start Column/Start Row
positions.
-Then D[B:0] is stored in frame memory and the column register and the row register incremented as section 6.5.2.
-Sending any other command can stop Frame Write.
In all color modes, there is no restriction on length of parameters.
2. 176x176 memory base (GM1, GM0 = “01”)
176x220x18-bits memory can be written by this command
Memory range: (0000h,0000h) -> (00AFh, 00AFh)
.m
Restriction
bt
re
1. 176x220 memory base (GM1, GM0 = “00”)
176x220x18-bits memory can be written by this command
Memory range: (0000h,0000h) -> (00AFh, 00DBh)
w
w
w
3. 176x132 memory base (GM1, GM0 = “11”)
176x220x18-bits memory can be written by this command
Memory range: (0000h,0000h) -> (00AFh, 0083h)
Register
Availability
Status
Normal Mode On, Idle Mode Off, Sleep Out
Normal Mode On, Idle Mode On, Sleep Out
Partial Mode On, Idle Mode Off, Sleep Out
Partial Mode On, Idle Mode On, Sleep Out
Sleep In
Availability
Yes
Yes
Yes
Yes
Yes
Default
Status
Power On Sequence
S/W Reset
H/W Reset
Default Value
Contents of memory is set randomly
Contents of memory is not cleared
Contents of memory is not cleared
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Legend
RAMWR (2CH)
Command
Parameter
Image Data
D1[B:0],D2[B:0]……Dn[B:0]
Flow Chart
Display
Action
Mode
Any Command
m
Sequential
transfer
w
w
w
.m
bt
re
nd
.co
Note: B=17
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6.2.23. RGBSET (2DH): Colour Setting
2DH
RGBSET (Colour Setting)
Inst / Para
D/CX
WRX
RDX
D17-8
D7
D6
D5
D4
D3
D2
D1
D0
(Code)
RGBSET
0
↑
1
-
0
0
1
0
1
1
0
1
(2DH)
1 Parameter
∣
1
↑
1
-
R007
R006
R005
R004
R003
R002
R001
R000
-
1
↑
1
-
:
:
:
:
:
:
:
:
-
∣
1
↑
1
-
Raa7
Raa6
Raa5
Raa4
Raa3
Raa2
Raa1
Raa0
-
∣
1
↑
1
-
G007
G006
005
G004
G003
G002
G001
G000
-
∣
1
↑
1
-
:
:
:
:
:
:
:
:
-
∣
1
↑
1
-
Gbb7
Gbb6
Gbb5
Gbb4
Gbb3
Gbb2
Gbb1
Gbb0
-
∣
1
↑
1
-
B007
B006
B005
B004
B003
B002
B001
B000
-
∣
1
↑
1
-
:
nd
:
:
:
:
:
:
:
-
Bcc6
Bcc5
Bcc4
Bcc3
Bcc2
Bcc1
Bcc0
-
nd
.co
n Parameter
1
1
Bcc7
↑
NOTE: “-” Don’t care, can be set to VDDI or DGND level
m
st
-This command is used to define the LUT for 12-bits-to-18-bits / 16bits-to-18-bits colors depth conversations.
re
Description
-262K-colors used.
-LUT has total trough 128 parameters.
-In this condition, 4K-color (4-4-4) and 65K-color(5-6-5) data input are transferred 6(R)-6(G)-6(B) through RGB LUT
table. (aa=31, bb=63, cc=31)
-This command has no effect on other commands/parameters and Contents of frame memory.
bt
-Visible change takes effect next time the Frame Memory is written .
Do not send any command before the last data is sent or LUT is not defined correctly.
.m
Restriction
Default
Status
Power On Sequence
S/W Reset
H/W Reset
Availability
Yes
Yes
Yes
Yes
Yes
w
w
w
Register
Availability
Status
Normal Mode On, Idle Mode Off, Sleep Out
Normal Mode On, Idle Mode On, Sleep Out
Partial Mode On, Idle Mode Off, Sleep Out
Partial Mode On, Idle Mode On, Sleep Out
Sleep In
Default Value
LUT default value
Contents of the look-up table protected
LUT default value
Legend
RGBSET (2DH)
Command
Parameter
st
1 Parameter:
Display
∣
∣
Action
Flow Chart
th
n arameter:
Mode
Sequential
transfer
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6.2.24. RAMHD (2EH): Memory Read
2EH
RAMHD (Memory Read)
Inst / Para
D/CX
WRX
RDX
D17-8
D7
D6
D5
D4
D3
D2
D1
D0
(Code)
RAMHD
0
↑
1
-
0
0
1
0
1
1
1
0
(2EH)
1 Parameter
st
1
1
↑
-
-
-
-
-
-
-
-
-
-
2 Parameter
nd
1
1
↑
D17-8
D7
D6
D5
D4
D3
D2
D1
D0
-
∣
1
1
↑
∣
∣
∣
∣
∣
∣
∣
∣
∣
∣
(N+1) Parameter
1
1
D17-8
D7
↑
NOTE: “-” Don’t care, can be set to VDDI or DGND level
D6
D5
D4
D3
D2
D1
D0
-
th
-This command is used to transfer data from frame memory to MCU.
-This command makes no change to the other driver status.
m
-When this command is accepted, the column register and the row register are reset to the Start Column/Start Row
positions.
-The Start Column/Start Row positions are different in accordance with MADCTR setting. (See section 6.7)
nd
.co
Description
-Then D[B:0] is read back from the frame memory and the column register and the row register incremented as section
6.5.2.
-Frame Read can be canceled by sending any other command.
bt
.m
-Memory read is only possible via the SPI and parallel interface.
Status
Normal Mode On, Idle Mode Off, Sleep Out
Normal Mode On, Idle Mode On, Sleep Out
Partial Mode On, Idle Mode Off, Sleep Out
Partial Mode On, Idle Mode On, Sleep Out
Sleep In
Availability
Yes
Yes
Yes
Yes
Yes
w
w
Register
Availability
-In all color modes, the Frame Read is always 18-bits and there is no restriction on length of parameters.
w
Restriction
re
-See section 6.4 “Data color coding” for color coding (18-bits cases), when there is used 12, 16, and 18-bits data lines for
image data.
Status
Power On Sequence
S/W Reset
H/W Reset
Default
Default Value
Contents of memory is set randomly
Contents of memory is not cleared
Contents of memory is not cleared
Note: B=17
RAMRD (2EH)
Legend
Command
Dummy Read
Parameter
Flow Chart
Display
Image Data
D1[B:0],D2[B:0]……Dn[B:0]
Action
Mode
Sequential
transfer
Any Command
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6.2.25. PTLAR (30H): Partial Area
30H
PTLAR (Partial Area)
Inst / Para
D/CX
WRX
RDX
D17-8
D7
D6
D5
D4
D3
D2
D1
D0
(Code)
PTLAR
0
↑
1
-
0
0
1
1
0
0
0
0
(30H)
1 Parameter
st
1
↑
1
-
PSL15
PSL14
PSL13
PSL12
PSL11
PSL10
PSL9
PSL8
00h
nd
1
↑
1
-
PSL7
PSL6
PSL5
PSL4
PSL3
PSL2
PSL1
PSL0
00h
rd
1
↑
1
-
PEL15
PEL14
PEL13
PEL12
PEL11
PEL10
PEL9
PEL8
4 Parameter
1
1
PEL7
↑
NOTE: “-” Don’t care, can be set to VDDI or DGND level
PEL6
PEL5
PEL4
PEL3
PEL2
PEL1
PEL0
2 Parameter
3 Parameter
th
-This command defines the partial mode’s display area.
Start Row
PSL [15:0]
nd
.co
-If End Row > Start Row, when MADCTL ML=’0’
m
-There are 4 parameters associated with this command, the first defines the Start Row (PSL) and the second the End
Row (PEL), as illustrated in the figures below. PSL and PEL refer to the Frame Memory row address counter.
Non-displaying Area
Non-displaying Area
bt
PEL [15:0]
End Row
re
Partial Display Area
.m
-If End Row > Start Row, when MADCTL ML=’1’
End Row
Non-displaying Area
w
PEL [15:0]
Partial Display Area
w
w
Description
PSL [15:0]
Start Row
Non-displaying Area
-If End Row < Start Row, when MADCTL ML=’0’
End Row
Partial Display Area
PEL [15:0]
Non-displaying Area
PSL [15:0]
Partial Display Area
Start Row
-If End Row = Start Row then the Partial Area will be one row deep.
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-PEL [15:0] always must be equal to or less than PSL [15:0]
-When PEL [15:0] or PSL [15:0] are greater than maximum row address like below, data of out of range will be ignored.
1. 176x220 memory base (GM1, GM0 = “00”)
(Parameter range: 0 ≤ PSL [15:0] ≤ PEL [15:0] ≤ 219 (0DBh))
If the “PSL” or “PEL” are large then 219d, it become 219d
Restriction
2. 176x176 memory base (GM1, GM0 = “01”)
(Parameter range: 0 ≤ PSL [15:0] ≤ PEL [15:0] ≤ 176 (00AFh))
If the “PSL” or “PEL” are large then 176d, it become 176d
3. 176x132 memory base (GM1, GM0 = “11”)
(Parameter range: 0 ≤ PSL [15:0] ≤ PEL [15:0] ≤ 131 (0083h))
If the “PSL” or “PEL” are large then 131d, it become 131d
m
Availability
Yes
Yes
Yes
Yes
Yes
nd
.co
Register
Availability
Status
Normal Mode On, Idle Mode Off, Sleep Out
Normal Mode On, Idle Mode On, Sleep Out
Partial Mode On, Idle Mode Off, Sleep Out
Partial Mode On, Idle Mode On, Sleep Out
Sleep In
1. 176x220 memory base (GM1, GM0 = “00”)
bt
.m
Power On Sequence
S/W Reset
H/W Reset
Default Value
re
Status
PSL [15:0]
PEL [15:0]
0000h
00DBh
2. 176x176 memory base (GM1, GM0 = “01”)
Default Value
w
Status
Power On Sequence
S/W Reset
H/W Reset
w
Default
PSL [15:0]
PEL [15:0]
0000h
00AFh
w
3. 176x132 memory base (GM1, GM0 = “11”)
Default Value
Status
Power On Sequence
S/W Reset
H/W Reset
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PSL [15:0]
PEL [15:0]
0000h
0083h
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1. To Enter Partial Mode
2. To Exit Partial Mode
PTLAR (30H)
Partial Mode
st
nd
rd
th
DISPOFF (28H)
1 & 2 Parameter:
PSL[15:0]
NORON (13H)
3 & 4 Parameter:
PEL[15:0]
Partial Mode OFF
PTLON (12H)
Flow Chart
Optional to
prevent tearing
effect image
display
Legend
Command
Parameter
m
RAMRW (2CH)
Partial Mode
nd
.co
Image Data
D1[B:0],D2[B:0]…
…Dn[B:0]
DISON (29H)
Action
Mode
Sequential
transfer
w
w
w
.m
bt
re
Note: B=17
Display
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6.2.26. SCRLAR (33H): Scroll Area
33H
SCRLAR (Scroll Area)
D/CX
WRX
RDX
D17-8
D7
D6
D5
D4
D3
D2
D1
D0
(Code)
SCRLAR
0
↑
1
-
0
0
1
1
0
0
1
1
(33H)
st
1
↑
1
-
TFA15
TFA14
TFA13
TFA12
TFA11
TFA10
TFA9
TFA8
00h
nd
1
↑
1
-
TFA7
TFA6
TFA5
TFA4
TFA3
TFA2
TFA1
TFA0
00h
rd
1
↑
1
-
VSA15 VSA14 VSA13 VSA12 VSA11 VSA10
VSA9
VSA8
th
1
↑
1
-
VSA7
VSA6
VSA5
VSA4
VSA3
VSA2
VSA1
VSA0
th
1
↑
1
-
BFA15
BFA14
BFA13
BFA12
BFA11
BFA10
BFA9
BFA8
00h
6 Parameter
1
1
BFA7
↑
NOTE: “-” Don’t care, can be set to VDDI or DGND level
BFA6
BFA5
BFA4
BFA3
BFA2
BFA1
BFA0
00h
1 Parameter
2 Parameter
3 Parameter
4 Parameter
5 Parameter
th
-This command defines the Vertical Scrolling Area of the display.
-When MADCTR ML=0
st
nd
m
Inst / Para
th
nd
.co
－The 1 & 2 parameter TFA [15:0] describes the Top Fixed Area (in No. of lines from Top of the Frame Memory and
Display).
rd
th
－The 3 & 4 parameter VSA [15:0] describes the height of the Vertical Scrolling Area (in No. of lines of the Frame
Memory [not the display] from the Vertical Scrolling Start Address)
－The first line appears immediately after the bottom most line of the Top Fixed Area.
th
bt
re
－The 5 & 6 parameter BFA [15:0] describes the Bottom Fixed Area (in No. of lines from Bottom of the Frame
Memory and Display).
－TFA, VSA and BFA refer to the Frame Memory row address.
.m
Top-Left (0,0)
Top Fixed Area
TFA [15:0]
w
First line read from
frame memory
Scroll Fixed Area
w
VSFA [15:0]
w
Bottom Fixed Area
BFA [15:0]
Description
-When MADCTR ML=1
st
nd
th
th
－The 1 & 2 parameter TFA [15:0] describes the Top Fixed Area (in No. of lines from Bottom of the Frame Memory
and Display).
rd
th
－The 3 & 4 parameter VSA [15:0] describes the height of the Vertical Scrolling Area (in No. of lines of the Frame
Memory [not the display] from the Vertical Scrolling Start Address)
－The first line appears immediately after the top most line of the Top Fixed Area.
－The 5 & 6 parameter BFA [15:0] describes the Bottom Fixed Area (in No. of lines from Top of the Frame Memory
and Display).
Top-Left (0,0)
Bottom Fixed Area
BFA [15:0]
Scroll Fixed Area
VSFA [15:0]
First line read from
frame memory
Top Fixed Area
TFA [15:0]
-See Section 6.5.4 for details of the Memory to Display Mapping.
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1. 176x220 memory base (GM1, GM0 = “00”)
-The condition is 0 ≤ (TFA+VSA+BFA) ≤ 220, otherwise Scrolling mode is undefined.
2. 176x176 memory base (GM1, GM0 = “01”)
Restriction
-The condition is 0 ≤ (TFA+VSA+BFA) ≤ 176, otherwise Scrolling mode is undefined.
3. 176x132 memory base (GM1, GM0 = “11”)
-The condition is 0 ≤ (TFA+VSA+BFA) ≤ 132, otherwise Scrolling mode is undefined.
-In Vertical Scroll Mode, MADCTR parameter MV should be set to ‘0’-this only affects the Frame Memory Write.
Availability
Yes
Yes
Yes
Yes
Yes
m
Register
Availability
Status
Normal Mode On, Idle Mode Off, Sleep Out
Normal Mode On, Idle Mode On, Sleep Out
Partial Mode On, Idle Mode Off, Sleep Out
Partial Mode On, Idle Mode On, Sleep Out
Sleep In
1. 176x220 memory base (GM1, GM0 = “00”)
TFA [15:0]
Power On Sequence
S/W Reset
H/W Reset
0000h
re
2. 176x176 memory base (GM1, GM0 = “01”)
Status
0000h
.m
bt
TFA [15:0]
Power On Sequence
S/W Reset
H/W Reset
Default
Default Value
VSA [15:0]
nd
.co
Status
00DCh
Default Value
VSA [15:0]
00B0h
BFA [15:0]
0000h
BFA [15:0]
0000h
3. 176x132 memory base (GM1, GM0 = “11”)
w
Status
TFA [15:0]
w
Power On Sequence
S/W Reset
H/W Reset
0084h
BFA [15:0]
0000h
w
0000h
Default Value
VSA [15:0]
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1. To Enter Vertical Scroll Mode
Legend
Normal Mode
Command
Parameter
SCRLAR (33H)
Display
Action
3rd & 4th Parameter VSA[15:0]
Mode
5th & 6th Parameter BFA[15:0]
Sequential
transfer
CASET (2AH)
nd
.co
1st & 2nd Parameter XS[15:0]
m
1st & 2nd Parameter: TFA[15:0]
3rd & 4th Parameter XE[15:0]
re
RASET (2BH)
Redefines the Frame
Memory Window that
the scroll data will be
written to.
See NOTE
1st & 2nd Parameter YS[15:0]
bt
Only required
for non-rolling
scrolling
3rd & 4th Parameter YE[15:0]
.m
Flow Chart
w
MADCTR (36H)
w
w
Parameter: MY,MX,MV,ML,RGB
Optional –
It may be necessary
to redefine the Frame
Memory Write
Direction.
RAMRW (2CH)
Scroll Image
Data
VSCSAD (37H)
1st & 2nd Parameter SSA[15:0]
Scroll Mode
NOTE: The Frame Memory Window size must be defined correctly otherwise undesirable image will be displayed.
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2. Continuous Scroll
Legend
Normal Mode
Command
Parameter
CASET (2AH)
st
&2
Display
Parameter XS[15:0]
Action
3rd & 4th Parameter XE[15:0]
Mode
RASET (2BH)
Sequential
transfer
1st & 2nd Parameter YS[15:0]
nd
.co
3rd & 4th Parameter YE[15:0]
m
1
nd
RAMRW (2CH)
Only required
for non-rolling
scrolling
bt
re
Scroll Image
Data
.m
VSCSAD (37H)
1st & 2nd Parameter SSA[15:0]
w
w
w
Flow Chart
3. To Exit Vertical Scroll Mode
Scroll Mode
DISOFF (28H)
NORON (13H) / PTLON (12H)
OptionTo prevent
Tearing Effect
Image Display
Scroll Mode OFF
RAMRW (2CH)
Image Data
D1[B:0],D2[B:0]…
…Dn[B:0]
DISON (29H)
Note: B=17
Note: Scroll Mode can be exit by both the Normal Display Mode On (13H) and Partial Mode On (12H) commands.
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6.2.27. TEOFF (34H): Tearing Effect Line OFF
TEOFF (Tearing Effect Line OFF)
34H
Inst / Para
D/CX
WRX
RDX
D17-8
D7
D6
D5
D4
D3
D2
D1
D0
(Code)
TEOFF
0
↑
1
-
0
0
1
1
0
1
0
0
(34H)
st
1 Parameter
NOTE: “-” Don’t care, can be set to VDDI or DGND level
No Parameter
-
Description
-This command is used to turn OFF (Active Low) the Tearing Effect output signal from the TE signal line.
Restriction
-This command has no effect when Tearing Effect output is already OFF.
m
ON
w
Legend
Command
TE Line Output ON
w
Parameter
Display
w
Flow Chart
OFF
bt
Power On Sequence
S/W Reset
H/W Reset
.m
Default
Availability
Yes
Yes
Yes
Yes
Yes
Default Value
RCM1, RCM0 = “00”, “1x”
RCM1, RCM0 = “01”
re
Status
nd
.co
Register
Availability
Status
Normal Mode On, Idle Mode Off, Sleep Out
Normal Mode On, Idle Mode On, Sleep Out
Partial Mode On, Idle Mode Off, Sleep Out
Partial Mode On, Idle Mode On, Sleep Out
Sleep In
TEOFF (34H)
Action
Mode
TE Line Output OFF
Sequential
transfer
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6.2.28. TEON (35H): Tearing Effect Line ON
35H
TEON (Tearing Effect Line ON)
Inst / Para
D/CX
WRX
RDX
D17-8
D7
D6
D5
D4
D3
D2
D1
D0
(Code)
TEON
0
↑
1
-
0
0
1
1
0
1
0
1
(35H)
0
0
0
0
0
0
0
TELOM
00h
st
1 Parameter
1
1
↑
NOTE: “-” Don’t care, can be set to VDDI or DGND level
-This command is used to turn ON the Tearing Effect output signal from the TE signal line.
-This output is not affected by changing MADCTR bit ML.
-The Tearing Effect Line On has one parameter, which describes the mode of the Tearing Effect Output Line.
(“-“=Don’t Care).
－When M=’0’:
nd
.co
tvdl
Vertical
time scale
Description
m
The Tearing Effect Output line consists of V-Blanking information only.
－When M=’1’:
tvdh
tvdl
tvdh
bt
re
The Tearing Effect Output line consists of both V-Blanking and H-Blinking information.
.m
Vertical
time scale
Note: During Sleep In Mode with Tearing Effect Line On, Tearing Effect Output pin will be active Low.
w
-This command has no effect when Tearing Effect output is already OFF.
w
Restriction
Status
Default
Availability
Yes
Yes
Yes
Yes
Yes
w
Register
Availability
Status
Normal Mode On, Idle Mode Off, Sleep Out
Normal Mode On, Idle Mode On, Sleep Out
Partial Mode On, Idle Mode Off, Sleep Out
Partial Mode On, Idle Mode On, Sleep Out
Sleep In
Default Value
RCM1, RCM0 = “00”, “1x”
RCM1, RCM0 = “01”
Power On Sequence
S/W Reset
H/W Reset
OFF &
TELOM=0
ON &
TELOM=0
Legend
Command
TE Line Output OFF
Parameter
Flow Chart
Display
TEON (35H)
Action
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Mode
TE Line Output ON
Sequential
transfer
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6.2.29. MADCTR (36H): Memory Data Access Control
36H
MADCTR (Memory Data Access Control)
Inst / Para
D/CX
WRX
RDX
D17-8
D7
D6
D5
D4
D3
D2
D1
D0
(Code)
MADCTR
0
↑
1
-
0
0
1
1
0
1
1
0
(36H)
MX
MV
ML
RGB
MH
0
0
00h
st
1 Parameter
1
1
MY
↑
NOTE: “-” Don’t care, can be set to VDDI or DGND level
-This command defines read/ write scanning direction of frame memory.
-This command makes no change on the other driver status.
NAME
DESCRIPTION
MY
MX
MV
Row Address Order
Column Address Order
Row/Column Exchange
These 3bits controls MCU to memory write/read
direction. (See Section 8.11)
ML
Vertical Refresh Order
RGB
RGB-BGR ORDER
m
-Bit Assignment
Bit
re
nd
.co
LCD vertical refresh direction control
‘0’ = LCD vertical refresh Top to Bottom
‘1’ = LCD vertical refresh Bottom to Top
Color selector switch control
‘0’ =RGB color filter panel,
‘1’ =BGR color filter panel)
Memory
Display
Sent First
Sent 2nd
Sent 3rd
w
.m
ML=’0’
bt
ML: Vertical Refresh Order
Top-Left (0,0)
w
Sent Last
w
Description
Top-Left (0,0)
Memory
Display
Sent Last
ML=’1’
Sent 3rd
Sent 2nd
Sent First
RGB: RGB-BGR Order
RGB=”0”
Driver IC
RGB=”1”
Driver IC
RGB
RGB
RGB
RGB
RGB
RGB
RGB
RGB
RGB
BGR
BGR
BGR
RGB
RGB
RGB
BGR
BGR
BGR
LCD Panel
Restriction
LCD Panel
st
D1 and D0 of the 1 parameter are set to “00” internally.
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Register
Availability
Status
Normal Mode On, Idle Mode Off, Sleep Out
Normal Mode On, Idle Mode On, Sleep Out
Partial Mode On, Idle Mode Off, Sleep Out
Partial Mode On, Idle Mode On, Sleep Out
Sleep In
Availability
Yes
Yes
Yes
Yes
Yes
Status
Power On Sequence
S/W Reset
H/W Reset
Default Value
MY=0,MX=0,MV=0,ML=0,RGB=0,
No Change
MY=0,MX=0,MV=0,ML=0,RGB=0,
nd
.co
m
Default
MADCTR (36H)
st
re
1 Parameter:
MY, MX, ML, RGB
Command
Parameter
Display
Action
Mode
Sequential
transfer
w
w
w
.m
bt
Flow Chart
Legend
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SPFD54126B
6.2.30. VSCSAD (37H): Vertical Scroll Start Address of RAM
37H
VSCSAD (Vertical Scroll Start Address of RAM)
Inst / Para
D/CX
WRX
RDX
D17-8
D7
D6
D5
D4
D3
D2
D1
D0
(Code)
VSCSAD
0
↑
1
-
0
0
1
1
0
1
1
1
(37h)
1
↑
1
-
SSA9
SSA8
SSA1
SSA0
st
1 Parameter
SSA15 SSA14 SSA13 SSA12 SSA11 SSA10
nd
2 Parameter
1
1
SSA7
↑
NOTE: “-” Don’t care, can be set to VDDI or DGND level
SSA6
SSA5
SSA4
SSA3
SSA2
-This command is used together with Vertical Scrolling Definition (33h). These two commands describe the scrolling area
and the scrolling mode.
-The Vertical Scrolling Start Address command has one parameter which describes which line in the Frame Memory will
be written as the first line after the last line of the Top Fixed Area on the display as illustrated below:
m
-This command Start the scrolling.
-Exit from V-scrolling mode by commands Partial mode On (12h) or Normal mode On (13h).
nd
.co
When MADCTR ML= ‘0’
Example:
－When Top Fixed Area=Bottom Fixed Area=00, Vertical Scrolling Area=220 and Vertical Scrolling Pointer SSA= ’3’.
(Example)
re
0
1
2
3
∣
∣
158
159
Display
G1
G2
G3
G4
|
|
G159
G160
w
w
.m
SSA[15:0]
Scroll start address
Description
Scan address
Memory
bt
Top-Left (0,0)
w
When MADCTR ML = ‘1’
Example:
－When Top Fixed Area= Bottom Fixed Area=00, Vertical Scrolling Area=220 and SSA= ’3’
(Example)
Top-Left (0,0)
Scan address
Memory
Display
159
158
∣
∣
3
2
1
0
SSA[15:0]
Scroll start address
G1
G2
G3
G4
|
|
G159
G160
NOTE: -When new Pointer position and Picture Data are sent, the result on the display will happen at the next Panel
Scan to avoid tearing effect.
-SSA refers to the Frame Memory scan address.
-Since the value of the Vertical Scrolling Start Address is absolute (with reference to the Frame Memory), it must not enter
the fixed area (defined by Vertical Scrolling Definition (33h)-otherwise undesirable image will be displayed on the Panel.
Restriction
SSA[15:0] is based on 1-line unit.
-SSA[15:0] = 0000h, 0001h, 0002h, 0003h, … , 00A1h
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Register
Availability
Status
Normal Mode On, Idle Mode Off, Sleep Out
Normal Mode On, Idle Mode On, Sleep Out
Partial Mode On, Idle Mode Off, Sleep Out
Partial Mode On, Idle Mode On, Sleep Out
Sleep In
Availability
Yes
Yes
No
No
Yes
Default
Status
Power On Sequence
S/W Reset
H/W Reset
Default Value
0000h
0000h
0000h
See Vertical Scrolling Definition (33h) description.
w
w
w
.m
bt
re
nd
.co
m
Flow Chart
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SPFD54126B
6.2.31. IDMOFF (38H): Idle Mode Off
38H
IDMOFF (Idle Mode Off)
Inst / Para
D/CX
WRX
RDX
D17-8
D7
D6
D5
D4
D3
D2
D1
D0
(Code)
IDMOFF
0
↑
1
-
0
0
1
1
1
0
0
0
(38H)
st
1 Parameter
NOTE: “-” Don’t care, can be set to VDDI or DGND level
No Parameter
-
-This command is used to recover from Idle mode on.
-In the idle off mode,
1. LCD can display 4k, 65k and 262k -colors.
2. Normal frame frequency is applied.
Restriction
-This command has no effect when module is already in idle off mode.
nd
.co
Default
Status
Power On Sequence
S/W Reset
H/W Reset
Availability
Yes
Yes
Yes
Yes
Yes
w
.m
bt
re
Register
Availability
Status
Normal Mode On, Idle Mode Off, Sleep Out
Normal Mode On, Idle Mode On, Sleep Out
Partial Mode On, Idle Mode Off, Sleep Out
Partial Mode On, Idle Mode On, Sleep Out
Sleep In
Default Value
Idle Mode Off
Idle Mode Off
Idle Mode Off
Legend
Idle mode ON
w
Command
Parameter
w
Flow Chart
m
-There will be no abnormal visible effect on the display mode change transition.
Description
Display
IDMOFF (38)
Action
Mode
Idle mode OFF
Sequential
transfer
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6.2.32. IDMON (39H): Idle Mode On
39H
IDMON (Idle Mode On)
Inst / Para
D/CX
WRX
RDX
D17-8
D7
D6
D5
D4
D3
D2
D1
D0
(Code)
IDMON
0
↑
1
-
0
0
1
1
1
0
0
1
(39H)
st
1 Parameter
NOTE: “-” Don’t care, can be set to VDDI or DGND level
No Parameter
-
-This command is used to enter into Idle mode on.
-There will be no abnormal visible effect on the display mode change transition.
nd
.co
(Example)
Top-Left (0,0)
Memory
Display
w
w
.m
R5 R4 R3 R2 R1 R0
0xxxxx
0xxxxx
1xxxxx
1xxxxx
0xxxxx
0xxxxx
1xxxxx
1xxxxx
w
Color
Black
Blue
Red
Magenta
Green
Cyan
Yellow
White
bt
re
Description
Restriction
m
-In the idle on mode,
1. Color expression is reduced. The primary and the secondary colors using MSB of each
R,G and B in the Frame Memory, 8 color depth data is displayed.
2. 8-Color mode frame frequency is applied.
3. Exit from IDMON by Idle Mode Off (38H) command
G5 G4 G3 G2 G1 G0
0xxxxx
0xxxxx
0xxxxx
0xxxxx
1xxxxx
1xxxxx
1xxxxx
1xxxxx
“x“ Don’t care
B5 B4 B3 B4 B1 B0
0xxxxx
1xxxxx
0xxxxx
1xxxxx
0xxxxx
1xxxxx
0xxxxx
1xxxxx
This command has no effect when module is already in idle on mode.
Register
Availability
Status
Normal Mode On, Idle Mode Off, Sleep Out
Normal Mode On, Idle Mode On, Sleep Out
Partial Mode On, Idle Mode Off, Sleep Out
Partial Mode On, Idle Mode On, Sleep Out
Sleep In
Availability
Yes
Yes
Yes
Yes
Yes
Default
Status
Power On Sequence
S/W Reset
H/W Reset
Default Value
Idle Mode Off
Idle Mode Off
Idle Mode Off
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SPFD54126B
Legend
Command
Idle mode OFF
Parameter
Display
Flow Chart
IDMOFF (39)
Action
Mode
Idle mode ON
w
w
w
.m
bt
re
nd
.co
m
Sequential
transfer
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SPFD54126B
6.2.33. COLMOD (3AH): Interface Pixel Format
3AH
COLMOD (Interface Pixel Format)
Inst / Para
D/CX
WRX
RDX
D17-8
D7
D6
D5
D4
D3
D2
D1
D0
(Code)
COLMOD
0
↑
1
-
0
0
1
1
1
0
1
0
(3AH)
VIPF2
VIPF1
VIPF0
D3
IFPF2
IFPF1
IFPF0
66h
st
1 Parameter
1
1
VIPF3
↑
NOTE: “-” Don’t care, can be set to VDDI or DGND level
This command is used to define the format of RGB picture data, which is to be transferred via the MCU interface and
RGB interface. The formats are shown in the table:
IFPF[2:0]
MCU Interface Color Format
011
3
12-bits/pixel
101
5
16-bits/pixel
110
6
18-bits/pixel
111
7
Reserved
Others are no define and invalid
nd
.co
m
Description
RGB Interface Color Format
16-bits/pixel (1-times data transfer)
18-bits/pixel (1-times data transfer)
Reserved
18-bits/pixel (3-times data transfer)
Others are no define and invalid
Note1: In 12-bits/Pixel, 16-bits/Pixel or 18-bits/Pixel mode, the LUT is applied to transfer data into the Frame Memory.
Note2: When RGB I/F the 12-bit/pixel don’t care
Note 3: When VIPF[3:0]=”1110”,6-bits data width of 3-times transfer is used to transmit 1 pixel data with the 18-bits color
depth information.
.m
Availability
Yes
Yes
Yes
Yes
Yes
Status
Default Value
IFPF[2:0]
VIPF[3:0]
0101 (16-bits/pixel)
0110 (18-bits/pixel)
No Change
No Change
0101 (16-bits/pixel)
0110 (18-bits/pixel)
w
Status
Normal Mode On, Idle Mode Off, Sleep Out
Normal Mode On, Idle Mode On, Sleep Out
Partial Mode On, Idle Mode Off, Sleep Out
Partial Mode On, Idle Mode On, Sleep Out
Sleep In
w
Register
Availability
There is no visible effect until the Frame Memory is written to.
w
Restriction
bt
re
VIPF[3:0]
0101
5
0110
6
0111
7
1110
14
Default
Power On Sequence
S/W Reset
H/W Reset
Example:
Legend
16-bits/Pixel Mode
Command
Parameter
COLMOD (3AH)
Display
Flow Chart
Action
st
1 Parameter
Mode
Sequential
transfer
18-bits/Pixel Mode
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6.2.34. RDID1 (DAH): Read ID1 Value
DAH
RDID1 (Read ID1 Value)
Inst / Para
D/CX
WRX
RDX
D17-8
D7
D6
D5
D4
D3
D2
D1
D0
(Code)
RDID1
0
↑
1
-
1
1
0
1
1
0
1
0
(DAH)
1 Parameter
1
1
↑
-
-
-
-
-
-
-
-
-
-
ID16
ID15
ID14
ID13
ID12
ID11
ID10
38h
st
nd
2 Parameter
1
1
ID17
↑
NOTE: “-” Don’t care, can be set to VDDI or DGND level
-This read byte returns 8-bits LCD module’s manufacturer ID
Description
st
-The 1 parameter is dummy data
nd
-The 2 parameter (ID17 to ID10): LCD module’s manufacturer ID.
nd
NOTE: See command RDDID (04H), 2 parameter.
nd
.co
Default
Status
Power On Sequence
S/W Reset
H/W Reset
Availability
Yes
Yes
Yes
Yes
Yes
w
.m
bt
re
Register
Availability
Status
Normal Mode On, Idle Mode Off, Sleep Out
Normal Mode On, Idle Mode On, Sleep Out
Partial Mode On, Idle Mode Off, Sleep Out
Partial Mode On, Idle Mode On, Sleep Out
Sleep In
m
Restriction
Partial I/F Mode
RDID1 (DAH)
RDID1 (DAH)
w
w
Serial I/F Mode
Send 2 parameter:
ID1[7:0]
Legend
Command
Host
Driver
nd
Flow Chart
Default Value
38h
38h
38h
Dummy Read
Parameter
Display
Action
Mode
nd
Send 2 parameter:
ID1[7:0]
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6.2.35. RDID2 (DBH): Read ID2 Value
DBH
RDID2 (Read ID2 Value)
Inst / Para
D/CX
WRX
RDX
D17-8
D7
D6
D5
D4
D3
D2
D1
D0
(Code)
RDID2
0
↑
1
-
1
1
0
1
1
0
1
1
(DBH)
1 Parameter
1
1
↑
-
-
-
-
-
-
-
-
-
-
ID26
ID25
ID24
ID23
ID22
ID21
ID20
80h
st
nd
2 Parameter
1
1
ID27
↑
NOTE: “-” Don’t care, can be set to VDDI or DGND level
-This read byte returns 8-bits LCD module/driver version ID
Description
st
-The 1 parameter is dummy data
nd
-The 2 parameter (ID26 to ID20): LCD module/driver version ID
rd
NOTE: See command RDDID (04H), 3 parameter.
Status
Power On Sequence
S/W Reset
H/W Reset
nd
.co
Default
Availability
Yes
Yes
Yes
Yes
Yes
w
.m
bt
re
Register
Availability
Status
Normal Mode On, Idle Mode Off, Sleep Out
Normal Mode On, Idle Mode On, Sleep Out
Partial Mode On, Idle Mode Off, Sleep Out
Partial Mode On, Idle Mode On, Sleep Out
Sleep In
m
Restriction
w
Serial I/F Mode
Flow Chart
nd
Send 2 parameter:
ID2[7:0]
Legend
Partial I/F Mode
Command
RDID2 (DBH)
w
RDID2 (DBH)
Default Value
80h
80h
80h
Host
Driver
Dummy Read
Parameter
Display
Action
Mode
nd
Send 2 parameter:
ID2[7:0]
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6.2.36. RDID3 (DCH): Read ID3 Value
DCH
RDID3 (Read ID2 Value)
Inst / Para
D/CX
WRX
RDX
D17-8
D7
D6
D5
D4
D3
D2
D1
D0
(Code)
RDID3
0
↑
1
-
1
1
0
1
1
1
0
0
(DCH)
1 Parameter
1
1
↑
-
-
-
-
-
-
-
-
-
-
ID36
ID35
ID34
ID33
ID32
ID31
ID30
62h
st
nd
2 Parameter
1
1
ID37
↑
NOTE: “-” Don’t care, can be set to VDDI or DGND level
-This read byte returns 8-bits LCD module/driver ID.
Description
st
-The 1 parameter is dummy data
nd
-The 2 parameter (ID37 to ID30): LCD module/driver ID.
th
NOTE: See command RDDID (04H), 4 parameter.
Default
Status
Power On Sequence
S/W Reset
H/W Reset
Availability
Yes
Yes
Yes
Yes
Yes
w
.m
bt
re
Register
Availability
Status
Normal Mode On, Idle Mode Off, Sleep Out
Normal Mode On, Idle Mode On, Sleep Out
Partial Mode On, Idle Mode Off, Sleep Out
Partial Mode On, Idle Mode On, Sleep Out
Sleep In
m
-
nd
.co
Restriction
w
w
Serial I/F Mode
RDID3 (DCH)
Flow Chart
Legend
Partial I/F Mode
Command
RDID3 (DCH)
Host
Driver
nd
Send 2 parameter:
ID3[7:0]
Default Value
62h
62h
62h
Dummy Read
Parameter
Display
Action
Mode
nd
Send 2 parameter:
ID3[7:0]
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6.2.37. SRGBOFF (AAH): Separate RGB Gamma OFF
AAH
SRGBOFF (Separate RGB Gamma OFF)
Inst / Para
D/CX
WRX
RDX
D17-8
D7
D6
D5
D4
D3
D2
D1
D0
(Code)
SRGBOFF
0
↑
1
-
1
0
1
0
1
0
1
0
(AAH)
st
1 Parameter
NOTE: “-” Don’t care, can be set to VDDI or DGND level
No Parameter
-
-This command is used to turn OFF the separate RGB gamma function.
Restriction
-This command has no effect when separate RGB gamma function OFF.
ON
Legend
Separate RGB gamma
ON
w
Command
w
Parameter
Display
w
SRGBOFF (AAH)
Flow Chart
OFF
bt
Power On Sequence
S/W Reset
H/W Reset
.m
Default
Availability
Yes
Yes
Yes
Yes
Yes
Default Value
RCM1, RCM0 = “00”, “1x”
RCM1, RCM0 = “01”
re
Status
nd
.co
Register
Availability
Status
Normal Mode On, Idle Mode Off, Sleep Out
Normal Mode On, Idle Mode On, Sleep Out
Partial Mode On, Idle Mode Off, Sleep Out
Partial Mode On, Idle Mode On, Sleep Out
Sleep In
m
Description
Action
Mode
Separate RGB gamma
OFF
Sequential
transfer
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6.2.38. SRGBOFF (ABH): Separate RGB Gamma ON
ABH
SRGBOFF (Separate RGB Gamma ON)
Inst / Para
D/CX
WRX
RDX
D17-8
D7
D6
D5
D4
D3
D2
D1
D0
(Code)
SRGBON
0
↑
1
-
1
0
1
0
1
0
1
1
(ABH)
st
1 Parameter
NOTE: “-” Don’t care, can be set to VDDI or DGND level
-This command is used to turn On the separate RGB gamma function.
-In this mode, It only the gamma curve 2.2 (GC0) can be separated to R, G, and B gamma curve
-This command has no effect when separate RGB gamma function ON.
Register
Availability
Status
Normal Mode On, Idle Mode Off, Sleep Out
Normal Mode On, Idle Mode On, Sleep Out
Partial Mode On, Idle Mode Off, Sleep Out
Partial Mode On, Idle Mode On, Sleep Out
Sleep In
bt
Power On Sequence
S/W Reset
H/W Reset
.m
Default
Default Value
RCM1, RCM0 = “00”, “1x”
RCM1, RCM0 = “01”
re
Status
Availability
Yes
Yes
Yes
Yes
Yes
m
Restriction
-
nd
.co
Description
No Parameter
OFF
ON
w
Legend
Separate RGB gamma
OFF
w
Command
w
Parameter
Display
SRGBON (ABH)
Flow Chart
Action
Mode
Separate RGB gamma
ON
Sequential
transfer
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SPFD54126B
6.2.39. VSYNCOFF (ACH): VSYNC Interface OFF
ACH
VSYNCOFF (VSYNC Interface OFF)
Inst / Para
D/CX
WRX
RDX
D17-8
D7
D6
D5
D4
D3
D2
D1
D0
(Code)
VSYNCOFF
0
↑
1
-
1
0
1
0
1
1
0
0
(ACH)
st
1 Parameter
NOTE: “-” Don’t care, can be set to VDDI or DGND level
-This command is used to turn OFF the VSYNC interface function.
-This command has no effect when VSYNC interface OFF.
-Input Vs signal for more than 1 frame period after turn OFF the VSYNC I/F
Status
Normal Mode On, Idle Mode Off, Sleep Out
Normal Mode On, Idle Mode On, Sleep Out
Partial Mode On, Idle Mode Off, Sleep Out
Partial Mode On, Idle Mode On, Sleep Out
Sleep In
Register
Availability
bt
Power On Sequence
S/W Reset
H/W Reset
OFF
.m
Default
Default Value
RCM1, RCM0 = “00”, “1x”
RCM1, RCM0 = “01”
re
Status
Availability
Yes
Yes
Yes
Yes
Yes
m
Restriction
--
nd
.co
Description
No Parameter
w
Legend
VSYNC Interface function ON
w
Command
Parameter
w
VSYNCOFF (ACH)
Display
Wait more than
1 frame
Flow Chart
ON
Action
Mode
VSYNC Interface function OFF
Sequential
transfer
Input Vs signal foe more than 1 frame period after turn OFF the VSYNC I/F
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Preliminary
SPFD54126B
6.2.40. VSYNCON (ADH): VSYNC Interface ON
ADH
VSYNCOFF (VSYNC Interface ON)
Inst / Para
D/CX
WRX
RDX
D17-8
D7
D6
D5
D4
D3
D2
D1
D0
(Code)
VSYNCON
0
↑
1
-
1
0
1
0
1
1
0
1
(ADH)
st
1 Parameter
NOTE: “-” Don’t care, can be set to VDDI or DGND level
-This command is used to turn ON the VSYNC interface function.
-This command has no effect when VSYNC interface ON.
-Input VS signal before turn On the VSYNC I/F
Status
Normal Mode On, Idle Mode Off, Sleep Out
Normal Mode On, Idle Mode On, Sleep Out
Partial Mode On, Idle Mode Off, Sleep Out
Partial Mode On, Idle Mode On, Sleep Out
Sleep In
Register
Availability
bt
Power On Sequence
S/W Reset
H/W Reset
.m
Default
Default Value
RCM1, RCM0 = “00”, “1x”
RCM1, RCM0 = “01”
re
Status
OFF
ON
w
Legend
VSYNC Interface function OFF
w
Command
Parameter
w
VSYNCON (ADH)
Display
Wait more than
1 frame
Flow Chart
Availability
Yes
Yes
Yes
Yes
Yes
m
Restriction
--
nd
.co
Description
No Parameter
Action
Mode
VSYNC Interface function ON
Sequential
transfer
Note: Input VS signal before turn On the VSYNC I/F
© ORISE Technology Co., Ltd.
Proprietary & Confidential
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Preliminary Version: 0.1
Evaluation Only. Created with Aspose.Pdf.Kit. Copyright 2002-2005 Aspose Pty Ltd
Preliminary
SPFD54126B
6.2.41. VSCTR1 (AEH): VSYNC Interface function control 1
AEH
VSYNCTR1 (VSYNC Interface function control 1)
Inst / Para
D/CX
WRX
RDX
D17-8
D7
D6
D5
D4
D3
D2
D1
D0
(Code)
VSCTR1
0
↑
1
-
1
0
1
0
1
1
0
1
(AEH)
st
1 Parameter
1
VSFP3 VSFP2 VSFP1 VSFP0 VSBP3 VSBP2 VSBP1 VSBP0
1
↑
NOTE: “-” Don’t care, can be set to VDDI or DGND level
2Eh
-Set the back porch and front porch on the VSYNC interface. The setting becomes effective as soon as the command is
received.
-VSFP: Front porch set on VSYNC I/F
Register
Availability
m
Back porch period (Line)
nd
.co
Setting inhibited
Setting inhibited
2-lines
3-lines
4-lines
5-lines
6-lines
7-lines
8-lines
9-lines
10-lines
11-lines
12-lines
13-lines
14-lines
Setting inhibited
w
-The command is enabled by VSYNCON (ADH)
Status
Normal Mode On, Idle Mode Off, Sleep Out
Normal Mode On, Idle Mode On, Sleep Out
Partial Mode On, Idle Mode Off, Sleep Out
Partial Mode On, Idle Mode On, Sleep Out
Sleep In
Availability
Yes
Yes
Yes
Yes
Yes
w
Restriction
w
.m
bt
re
Description
-VSBP: Back porch set on VSYNC I/F
VSBP[3:0]
Front porch period (Line)
VSFP[3:0]
0000
0
Setting inhibited
0001
1
Setting inhibited
0010
2
2-lines
0011
3
3-lines
0100
4
4-lines
0101
5
5-lines
0110
6
6-lines
0111
7
7-lines
1000
8
8-lines
1001
9
9-lines
1010
10
10-lines
1011
11
11-lines
1100
12
12-lines
1101
13
13-lines
1110
14
14-lines
1111
15
Setting inhibited
Status
Default
Default Value
Power On Sequence
S/W Reset
H/W Reset
VSFP[3:0]
2d
No Change
2d
VSBP[3:0]
14d
No Change
14d
Legend
------------------
Command
VSCTR1 (AEH)
Parameter
Display
Flow Chart
Action
1st Parameter:
VSFP[3:0], VSBP[3:0]
Mode
Sequential
transfer
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Preliminary
SPFD54126B
6.3. Panel Command Description
6.3.1. RGBCTR (B0H): RGB signal control
B0H
RGBCTR (RGB signal control)
Inst / Para
D/CX
WRX
RDX
D17-8
D7
D6
D5
D4
D3
D2
D1
D0
(Code)
RGBCTR
0
↑
1
-
1
0
1
1
0
0
0
0
(B0H)
0
0
0
ICM
DP
EP
HSP
VSP
00h
st
1 Parameter
1
1
↑
NOTE: “-” Don’t care, can be set to VDDI or DGND level
-Set the operation status on the RGB interface. The setting becomes effective as soon as the command is received.
PCLK polarity set
EP
Enable polarity set
HSP
Hsync polarity set
VSP
Vsync polarity set
Clock polarity set for RGB Interface
‘1’ = data fetched at the falling edge
‘0’ = data fetched at the rising edge
‘1’ = Low enable for RGB interface
‘0’ = High enable for RGB interface
‘1’ = High level sync clock
‘0’ = Low level sync clock
‘1’ = High level sync clock
‘0’ = Low level sync clock
re
Name
DP
bt
Symbol
.m
Description
nd
.co
m
-ICM: GRAM Write/Read frequency and data input select on the RGB interface
ICM
Write/ Read frequency and input data select
Write cycle
Read cycle
Data input
0
PCLK
PCLK
D[B:0]
1
SCL
Internal oscillator
SDA
B=17
-If this register not using the register need be reserved.
Register
Availability
Status
Normal Mode On, Idle Mode Off, Sleep Out
Normal Mode On, Idle Mode On, Sleep Out
Partial Mode On, Idle Mode Off, Sleep Out
Partial Mode On, Idle Mode On, Sleep Out
Sleep In
w
w
Restriction
w
Availability
Yes
Yes
Yes
Yes
Yes
Status
Default
Default Value
ICM
0d
0d
0d
Power On Sequence
S/W Reset
H/W Reset
DP/EP/HSP/VSP
0d/0d/0d/0d
0d/0d/0d/0d
0d/0d/0d/0d
------------------
Legend
RGBCTR (B0H)
Command
Parameter
Display
Flow Chart
Action
1st Parameter:
ICM, DP,
EP, HSP, VSP
Mode
Sequential
transfer
© ORISE Technology Co., Ltd.
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Preliminary
SPFD54126B
6.3.2.
FRMCTR1 (B1h): Frame Rate Control (In normal mode/ Full colors)
B1H
FRMCTR1 (Frame Rate Control)
Inst / Para
D/CX
WRX
RDX
D17-8
D7
D6
D5
D4
D3
D2
D1
D0
(Code)
FRMCTR1
0
↑
1
-
1
0
1
1
0
0
0
1
(B1h)
st
1
↑
1
-
0
0
0
0
FP0[3]
FP0[2]
FP0[1]
FP0[0]
-
nd
1
↑
1
-
0
0
0
0
1
↑
1
-
0
0
0
0
BP0[2]
RTN0
[2]
BP0[1]
RTN0
[1]
BP0[0]
RTN0
[0]
-
rd
BP0[3]
RTN0
[3]
1 Parameter
2 Parameter
3 Parameter
-
NOTE: “-“ Don’t care
-Set the frame frequency of the full colors normal mode in MPU interface.
re
bt
w
w
.m
Amount of Back Porch
0
1
2
3
4
…
13
14
15
w
Description
BP0[3:0]
0
1
2
3
4
…
D
E
F
Amount of Front Porch
0
1
2
3
4
…
13
14
15
nd
.co
FP0[3:0]
0
1
2
3
4
…
D
E
F
RTN0[3:0]
0
1
2
3
4
…
D
E
F
No. of clock in one line
16
17
18
19
20
…
29
30
31
Restriction
-If this register not using the register need be reserved.
Register
Availability
Status
Normal Mode On, Idle Mode Off, Sleep Out
Normal Mode On, Idle Mode On, Sleep Out
Partial Mode On, Idle Mode Off, Sleep Out
Partial Mode On, Idle Mode On, Sleep Out
Sleep In
Availability
Yes
Yes
Yes
Yes
Yes
Status
Default
Power On Sequence
S/W Reset
H/W Reset
© ORISE Technology Co., Ltd.
Proprietary & Confidential
m
--The default vaule of BP0, FP0, and RTN0 can fit the frame frequency to be 65Hz ±5%.
Default Value
BP0
14d
14d
14d
FP0
2d
2d
2d
81
RTN0
0d
0d
0d
Apr. 25, 2006
Preliminary Version: 0.1
Evaluation Only. Created with Aspose.Pdf.Kit. Copyright 2002-2005 Aspose Pty Ltd
Preliminary
SPFD54126B
-------------
Legend
FRMCTR1 (B1h)
Command
Parameter
Display
st
1 Parameter:
FP0 [3:0]
nd
2 Parameter:
BP0 [3:0]
3rd Parameter:
RTN0 [3:0]
Action
Mode
Sequential
transfer
w
w
w
.m
bt
re
nd
.co
m
Flow Chart
© ORISE Technology Co., Ltd.
Proprietary & Confidential
82
Apr. 25, 2006
Preliminary Version: 0.1
Evaluation Only. Created with Aspose.Pdf.Kit. Copyright 2002-2005 Aspose Pty Ltd
Preliminary
SPFD54126B
6.3.3.
FRMCTR2 (B2h): Frame Rate Control (In Idle mode/ 8-colors)
B2H
FRMCTR2 (Frame Rate Control)
Inst / Para
D/CX
WRX
RDX
D17-8
D7
D6
D5
D4
D3
D2
D1
D0
(Code)
FRMCTR2
0
↑
1
-
1
0
1
1
0
0
1
0
(B2h)
st
1
↑
1
-
0
0
0
0
FP1[3]
FP1[2]
FP1[1]
FP1[0]
-
nd
1
↑
1
-
0
0
0
0
1
↑
1
-
0
0
0
0
BP1[2]
RTN1
[2]
BP1[1]
RTN1
[1]
BP1[0]
RTN1
[0]
-
rd
BP1[3]
RTN1
[3]
1 Parameter
2 Parameter
3 Paramete
-
NOTE: “-“ Don’t care
-Set the frame frequency of the Idle mode in MPU interface.
re
bt
w
w
.m
Amount of Back Porch
0
1
2
3
4
…
13
14
15
w
Description
BP1[3:0]
0
1
2
3
4
…
D
E
F
Amount of Front Porch
0
1
2
3
4
…
13
14
15
nd
.co
FP1[3:0]
0
1
2
3
4
…
D
E
F
RTN1[3:0]
0
1
2
3
4
…
D
E
F
No. of clock in one line
16
17
18
19
20
…
29
30
31
Restriction
-If this register not using the register need be reserved.
Register
Availability
Status
Normal Mode On, Idle Mode Off, Sleep Out
Normal Mode On, Idle Mode On, Sleep Out
Partial Mode On, Idle Mode Off, Sleep Out
Partial Mode On, Idle Mode On, Sleep Out
Sleep In
Availability
Yes
Yes
Yes
Yes
Yes
Status
Default
Power On Sequence
S/W Reset
H/W Reset
© ORISE Technology Co., Ltd.
Proprietary & Confidential
m
-The default vaule of BP1, FP1, and RTN1 can fit the frame frequency to be 70Hz ±5%.
Default Value
BP1
14d
14d
14d
FP1
2d
2d
2d
83
RTN1
0d
0d
0d
Apr. 25, 2006
Preliminary Version: 0.1
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Preliminary
SPFD54126B
-------------
Legend
FRMCTR2 (B2h)
Command
Parameter
Display
st
1 Parameter:
FP1 [3:0]
nd
2 Parameter:
BP1 [3:0]
3rd Parameter:
RTN1 [3:0]
Action
Mode
Sequential
transfer
w
w
w
.m
bt
re
nd
.co
m
Flow Chart
© ORISE Technology Co., Ltd.
Proprietary & Confidential
84
Apr. 25, 2006
Preliminary Version: 0.1
Evaluation Only. Created with Aspose.Pdf.Kit. Copyright 2002-2005 Aspose Pty Ltd
Preliminary
SPFD54126B
6.3.4.
FRMCTR3 (B3h): Frame Rate Control (In Partial mode/ full colors)
B3H
FRMCTR3 (Frame Rate Control)
Inst / Para
D/CX
WRX
RDX
D17-8
D7
D6
D5
D4
D3
D2
D1
D0
(Code)
FRMCTR3
0
↑
1
-
1
0
1
1
0
0
1
1
(B3h)
st
1
↑
1
-
0
0
0
0
FP2[3]
FP2[2]
FP2[1]
FP2[0]
-
nd
1
↑
1
-
0
0
0
0
1
↑
1
-
0
0
0
0
BP2[2]
RTN2
[2]
BP2[1]
RTN2
[1]
BP2[0]
RTN2
[0]
-
rd
BP2[3]
RTN2
[3]
1 Parameter
2 Parameter
3 Parameter
-
NOTE: “-“ Don’t care
-Set the frame frequency of the Partial mode/ full colors in MPU interface.
and
65Hz ±5% with line inversion in this mode
re
bt
.m
w
Amount of Back Porch
0
1
2
3
4
…
13
14
15
w
BP2[3:0]
0
1
2
3
4
…
D
E
F
w
Description
Amount of Front Porch
0
1
2
3
4
…
13
14
15
nd
.co
FP2[3:0]
0
1
2
3
4
…
D
E
F
RTN2[3:0]
0
1
2
3
4
…
D
E
F
No. of clock in one line
16
17
18
19
20
…
29
30
31
Restriction
-If this register not using the register need be reserved.
Register
Availability
Status
Normal Mode On, Idle Mode Off, Sleep Out
Normal Mode On, Idle Mode On, Sleep Out
Partial Mode On, Idle Mode Off, Sleep Out
Partial Mode On, Idle Mode On, Sleep Out
Sleep In
Availability
Yes
Yes
Yes
Yes
Yes
Status
Default
Power On Sequence
S/W Reset
H/W Reset
© ORISE Technology Co., Ltd.
Proprietary & Confidential
m
-The default vaule of BP2, FP2, and RTN2 can fit the frame frequency to be 70Hz ±5% with frame inversion
Default Value
BP2
14d
14d
14d
FP2
2d
2d
2d
85
RTN2
0d
0d
0d
Apr. 25, 2006
Preliminary Version: 0.1
Evaluation Only. Created with Aspose.Pdf.Kit. Copyright 2002-2005 Aspose Pty Ltd
Preliminary
SPFD54126B
-------------
Legend
FRMCTR3 (B3h)
Command
Parameter
Display
st
1 Parameter:
FP2 [3:0]
nd
2 Parameter:
BP2 [3:0]
3rd Parameter:
RTN2 [3:0]
Action
Mode
Sequential
transfer
w
w
w
.m
bt
re
nd
.co
m
Flow Chart
© ORISE Technology Co., Ltd.
Proprietary & Confidential
86
Apr. 25, 2006
Preliminary Version: 0.1
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Preliminary
SPFD54126B
6.3.5.
INVCTR (B4h): Display Inversion Control
B4H
INVCTR (Display Inversion Control)
Inst / Para
D/CX
WRX
RDX
D17-8
D7
D6
D5
D4
D3
D2
D1
D0
(Code)
INVCTR
0
↑
1
-
1
0
1
1
0
1
0
0
(B4h)
0
0
0
0
0
NLA
NLB
NLC
st
1 Parameter
1
1
↑
NOTE: “-” Don’t care, can be set to VDDI or DGND level
-Display Inversion mode control
m
-NLA: Inversion setting in full colors normal mode (Normal mode on)
NLA
Inversion setting in full colours normal mode
0
Line Inversion
1
Frame Inversion
-NLB: Inversion setting in Idle mode (Idle mode on)
NLB
Inversion setting in Idle mode
0
Line Inversion
1
Frame Inversion
nd
.co
Description
.m
bt
re
-NLC: Inversion setting in full colors partial mode (Partial mode on / Idle mode off)
NLC
Inversion setting in full colours partial mode
0
Line Inversion
1
Frame Inversion
Restriction
-If this register not using the register need be reserved.
Register
Availability
Status
Normal Mode On, Idle Mode Off, Sleep Out
Normal Mode On, Idle Mode On, Sleep Out
Partial Mode On, Idle Mode Off, Sleep Out
Partial Mode On, Idle Mode On, Sleep Out
Sleep In
w
w
w
Availability
Yes
Yes
Yes
Yes
Yes
Status
Default
Default Value
NLA
0d
0d
0d
Power On Sequence
S/W Reset
H/W Reset
NLB
1d
1d
1d
NLC
0d
0d
0d
B4h
02h
02h
02h
-------------
Legend
INVCTR (B4h)
Command
Parameter
Display
Flow Chart
Action
st
1 Parameter:
NLA, NLB, NLC
Mode
Sequential
transfer
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Preliminary
SPFD54126B
6.3.6.
RGBBPCTR (B5h): RGB Interface Blanking Porch setting
B5H
RGBPSET (RGB Interface Blanking Porch setting)
Inst / Para
D/CX
WRX
RDX
D17-8
D7
D6
D5
D4
D3
D2
D1
D0
(Code)
RGBBPCTR
0
↑
1
-
1
0
1
1
0
1
0
1
(B5h)
1
↑
1
-
st
1 Parameter
NOTE: “-“ Don’t care
VBP[3] VBP[2] VBP[1] VBP[0]
-
-Set the blanking porch in the RGB interface
m
Amount of Back Porch in RGB interface
0
1
2
3
4
…
13
14
15
-If this register not using the register need be reserved.
Register
Availability
Status
Normal Mode On, Idle Mode Off, Sleep Out
Normal Mode On, Idle Mode On, Sleep Out
Partial Mode On, Idle Mode Off, Sleep Out
Partial Mode On, Idle Mode On, Sleep Out
Sleep In
Status
w
Power On Sequence
S/W Reset
H/W Reset
Availability
Yes
Yes
Yes
Yes
Yes
Default Value
VBP
3d
3d
3d
w
Default
w
.m
bt
re
Restriction
nd
.co
Description
VBP[3:0]
0
1
2
3
4
…
D
E
F
----------------
Legend
RGBBPCTR (B3h)
Command
Parameter
Display
Flow Chart
Action
st
1 Parameter:
VBP [3:0]
Mode
Sequential
transfer
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Proprietary & Confidential
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Preliminary
SPFD54126B
6.3.7.
DISSET5 (B6h): Display Function set 5
B4H
DISSET (Display Function set 5)
Inst / Para
D/CX
WRX
RDX
D17-8
D7
D6
D5
D4
D3
D2
D1
D0
(Code)
DISSET5
0
↑
1
-
1
0
1
1
0
1
1
0
(B6h)
1
1
↑
↑
1
1
-
0
0
0
0
NO1
0
NO0
0
SDT1
PTG1
STD0
PTG0
EQ1
PT1
EQ0
PT0
st
1 Parameter
nd
2 Parameter
NOTE: “-“ Don’t care
st
-1 parameter: Set output waveform relation.
nd
.co
m
-NO[1:0]: Set the amount of non-overlap of the gate output
NO[1:0]
Amount of non-overlap of the gate output
Refer the Internal oscillator
Refer the PCLK
00
0
1 clock cycle
4 clock cycle
01
1
4 clock cycle
16 clock cycle
10
2
6 clock cycle
24 clock cycle
11
3
8 clock cycle
32 clock cycle
bt
re
-SDT[1:0]: Set delay amount from gate signal falling edge of the source output.
SDT[1:0]
Amount of non-overlap of the source output
Refer the Internal oscillator
Refer the PCLK
00
0
1 clock cycle
4 clock cycle
01
1
2 clock cycle
8 clock cycle
10
2
3 clock cycle
12 clock cycle
11
3
4 clock cycle
16 clock cycle
Gn
Description
w
w
w
.m
-EQ[1:0]: Set the Equalizing period
EQ[1:0]
EQ period
Refer the Internal oscillator
00
0
No EQ
01
1
2 clock cycle
10
2
4 clock cycle
11
3
6 clock cycle
Refer the PCLK
No EQ
4 clock cycle
16 clock cycle
24 clock cycle
Gate Non-overlap period
Gn+1
Sn
VCOM
Delay time for source output EQ period
nd
-2 parameter: Set the output waveform in non-display area.
-PTG[1:0]: Determine gate output in a non-display area in the partial mode
PTG[1:0]
Gate output in a non-display area
00
0
Normal scan
01
1
Fix on VGL
10
2
Fix on VGL
11
3
Fix on VGL
-PT[1:0]: Determine Source /VCOM output in a non-display area in the partial mode
Source output on non-display
VCOM output on non-display
PT[1:0]
area
area
Positive
Negative
Positive
Negative
00
0
V63
V0
VCOML
VCOMH
01
1
V0
V63
VCOML
VCOMH
10
2
AGND
AGND
AGND
AGND
11
3
Hi-z
Hi-z
AGND
AGND
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Preliminary
SPFD54126B
Restriction
-If this register not using the register need be reserved.
Register
Availability
Status
Normal Mode On, Idle Mode Off, Sleep Out
Normal Mode On, Idle Mode On, Sleep Out
Partial Mode On, Idle Mode Off, Sleep Out
Partial Mode On, Idle Mode On, Sleep Out
Sleep In
Availability
Yes
Yes
Yes
Yes
Yes
Status
Power On Sequence
S/W Reset
H/W Reset
STD[1:0]
1d
1d
1d
nd
.co
-----------------DISSET5 (B6h)
st
re
1 Parameter:
NO[1:0], STD[1:0], EQ[1:0]
nd
2 Parameter:
PTG[1:0], PT[1:0]
PTG[1:0]
0d
0d
0d
PT[1:0]
2d
2d
2d
Legend
Command
Parameter
Display
Action
Mode
Sequential
transfer
w
w
w
.m
bt
Flow Chart
Default Value
EQ[1:0]
2d
2d
2d
m
Default
NO[1:0]
1d
1d
1d
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Preliminary
SPFD54126B
6.3.8.
PWCTR1 (C0H): Power Control 1
C0H
PWCTR1 (Power Control 1)
Inst / Para
D/CX
WRX
RDX
D17-8
D7
D6
D5
D4
D3
D2
D1
D0
(Code)
PWCTR1
0
↑
1
-
1
1
0
0
0
0
0
0
(C0H)
1
↑
1
-
0
0
0
VRH4
VRH3
VRH2
VRH1
VRH0
05h
0
0
0
0
0
VCI2
VCI1
VCI0
05h
0
1
2
3
4
5
6
7
VCI1
2.75
2.70
2.65
2.60
2.55
2.50
2.80
2.90
st
1 Parameter
nd
2 Parameter
1
1
↑
NOTE: “-” Don’t care, can be set to VDDI or DGND level
nd
.co
.m
bt
re
VC[2:0]
000
001
010
011
100
101
110
111
w
w
GVDD
5.00
4.75
4.70
4.65
4.60
4.55
4.50
4.45
4.35
4.30
4.25
4.20
4.15
4.10
4.05
4.00
3.95
3.90
3.85
3.80
3.75
3.70
3.65
3.60
3.55
3.50
3.45
3.40
3.35
3.25
3.00
w
Description
VRH[4:0]
00000
0
00001
1
00010
2
00011
3
00100
4
00101
5
00110
6
00111
7
01001
9
01010
10
01011
11
01100
12
01101
13
01110
14
01111
15
10000
16
10001
17
10010
18
10011
19
10100
20
10101
21
10110
22
10111
23
11000
24
11001
25
11010
26
11011
27
11100
28
11101
29
11110
30
11111
31
m
-Set the GVDD and VCI1 voltage
-If this register not using the register need be reserved.
Restriction
-The deviation value of GVDD between with Measurement and Specification: Max <=50mV
-The deviation value of VCI1 between with Measurement and Specification: Max <=2% deviation
Register
Availability
Status
Normal Mode On, Idle Mode Off, Sleep Out
Normal Mode On, Idle Mode On, Sleep Out
Partial Mode On, Idle Mode Off, Sleep Out
Partial Mode On, Idle Mode On, Sleep Out
Sleep In
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Yes
Yes
Yes
Yes
Yes
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Preliminary
SPFD54126B
Status
Default Value
LCM = ‘01’
LCM = ‘11’
TM LC Type
ECB LC type
VRH[4:0]
VC[2:0]
VRH[4:0]
VC[2:0]
5d
5d
5d
5d
5d
5d
5d
5d
5d
5d
5d
5d
Default
Power On Sequence
S/W Reset
H/W Reset
--------------
Legend
PWCTR1 (C0H)
Command
1st Parameter:
VRH[4:0]
nd
Parameter:
VCI[2:0]
Display
Action
Mode
Sequential
transfer
w
w
w
.m
bt
re
2
nd
.co
Flow Chart
m
Parameter
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Preliminary
SPFD54126B
6.3.9.
PWCTR2 (C1H): Power Control 2
C1H
PWCTR2 (Power Control 2)
Inst / Para
D/CX
WRX
RDX
D17-8
D7
D6
D5
D4
D3
D2
D1
D0
(Code)
PWCTR2
0
↑
1
-
1
1
0
0
0
0
0
1
(C1H)
0
0
0
0
0
BT2
BT1
BT0
07h
st
1 Parameter
1
1
↑
NOTE: “-” Don’t care, can be set to VDDI or DGND level
-Set the AVDD, VCL, VGH and VGL supply power level
VCL
-1xVDDI
-2.45
-1xVDDI
-2.45
VGH
4*VDDI
9.80
4*VDDI
9.80
VGL
-3*VDDI
-7.35
-4*VDDI
-9.80
010
011
100
2
3
4
2xVDDI
2xVDDI
2xVDDI
4.75
4.75
4.75
-1xVDDI
-1xVDDI
-1xVDDI
-2.45
-2.45
-2.45
5*VDDI
5*VDDI
5*VDDI
12.25
12.25
12.25
-3*VDDI
-4*VDDI
-5*VDDI
-7.35
-9.80
-12.25
101
110
111
5
6
7
2xVDDI
2xVDDI
2xVDDI
4.75
4.75
4.75
-1xVDDI
-1xVDDI
-1xVDDI
-2.45
-2.45
-2.45
6*VDDI
6*VDDI
6*VDDI
14.70
14.70
14.70
-3*VDDI
-4*VDDI
-5*VDDI
-7.35
-9.80
-12.25
m
AVDD
2xVDDI
4.75
2xVDDI
4.75
nd
.co
Description
BT[2:0]
000
0
001
1
Note: When VCI1=2.5V, Set-up cycle 1 effective=95%, Set-up cycle 2 effective=98%,
-The deviation value of VGH/ VGL between with Measurement and Specification: Max: VGH-VGL<=1V
bt
Restriction
re
-If this register not using the register need be reserved.
-VGH-VGL <= 25V
w
.m
Availability
Yes
Yes
Yes
Yes
Yes
w
w
Register
Availability
Status
Normal Mode On, Idle Mode Off, Sleep Out
Normal Mode On, Idle Mode On, Sleep Out
Partial Mode On, Idle Mode Off, Sleep Out
Partial Mode On, Idle Mode On, Sleep Out
Sleep In
Status
Default
Default Value
BT[2:0]
7d
7d
7d
Power On Sequence
S/W Reset
H/W Reset
---------------
Legend
PWCTR2 (C1H)
Command
Parameter
Display
Flow Chart
Action
st
1 Parameter:
BT[2:0]
Mode
Sequential
transfer
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Preliminary
SPFD54126B
6.3.10. PWCTR3 (C2H): Power Control 3 (in Normal mode/ Full colors)
C2H
PWCTR3 (Power Control 3)
Inst / Para
D/CX
WRX
RDX
D17-8
D7
D6
D5
D4
D3
D2
D1
D0
(Code)
PWCTR3
0
↑
1
-
1
1
0
0
0
0
1
0
(C2H)
0
0
0
0
0
0
0
0
0
0
APA2
DCA2
APA1
DCA1
APA0
DCA0
01h
st
1 Parameter
1
1
↑
nd
2 Parameter
1
1
↑
NOTE: “-” Don’t care, can be set to VDDI or DGND level
-Set the amount of current in Operational amplifier in normal mode/full colors.
nd
.co
-Set the Booster circuit Step-up cycle in Normal mode/ full colors.
.m
bt
Step-up cycle in Booster circuit 1
BCLK / 1
BCLK / 1
BCLK / 1
BCLK / 2
BCLK / 2
BCLK / 4
BCLK / 4
BCLK / 4
w
0
1
2
3
4
5
6
7
w
DC[2:0]
000
001
010
011
100
101
110
111
w
Description
Amount of Current in Operational Amplifier
Operation of the operational amplifier stops
Small
Medium Low
Medium
Medium High
Large
Reserved
Reserved
0
1
2
3
4
5
6
7
re
AP[2:0]
000
001
010
011
100
101
110
111
m
-Adjust the amount of fixed current from the fixed current source in the operational amplifier for the source driver.
Step-up cycle in Booster circuit 2,3
BCLK / 1
BCLK / 2
BCLK / 4
BCLK / 2
BCLK / 4
BCLK / 4
BCLK / 8
BCLK / 16
Note: BCLK is Clock frequency for Booster circuit
Restriction
Register
Availability
-If some parameters of the register not use the register need to be reserved.
Status
Normal Mode On, Idle Mode Off, Sleep Out
Normal Mode On, Idle Mode On, Sleep Out
Partial Mode On, Idle Mode Off, Sleep Out
Partial Mode On, Idle Mode On, Sleep Out
Sleep In
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Yes
Yes
Yes
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Preliminary
SPFD54126B
1. 176x220 memory base (GM1, GM0 = “00”)
Status
DC[2:0]
1d
No Change
1d
Default Value
DC[2:0]
1d
No Change
1d
Default Value
m
DC[2:0]
1d
No Change
1d
nd
.co
Default
Default Value
AP[2:0]
Power On Sequence
4d
S/W Reset
No Change
H/W Reset
4d
2. 176x176 memory base (GM1, GM0 = “01”)
Status
AP[2:0]
Power On Sequence
4d
S/W Reset
No Change
H/W Reset
4d
3. 176x132 memory base (GM1, GM0 = “11”)
Status
AP[2:0]
Power On Sequence
3d
S/W Reset
No Change
H/W Reset
3d
---------------
1st Parameter:
APA[2:0]
nd
Command
Parameter
Display
Action
Mode
Parameter:
DCA[2:0]
w
2
.m
Flow Chart
bt
re
PWCTR3 (C2H)
Legend
w
w
Sequential
transfer
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Preliminary
SPFD54126B
6.3.11. PWCTR4 (C3H): Power Control 4 (in Idle mode/ 8-colors)
C3H
PWCTR4 (Power Control 4)
Inst / Para
D/CX
WRX
RDX
D17-8
D7
D6
D5
D4
D3
D2
D1
D0
(Code)
PWCTR4
0
↑
1
-
1
1
0
0
0
0
1
1
(C3H)
0
0
0
0
0
0
0
0
0
0
APB2
DCB2
APB1
DCB1
APB0
DCB0
04h
st
1 Parameter
1
1
↑
nd
2 Parameter
1
1
↑
NOTE: “-” Don’t care, can be set to VDDI or DGND level
-Set the amount of current in Operational amplifier in Idle mode/ 8-colors.
nd
.co
-Set the Booster circuit Step-up cycle in Idle mode/ 8-colors.
.m
bt
Step-up cycle in Booster circuit 1
BCLK / 1
BCLK / 1
BCLK / 1
BCLK / 2
BCLK / 2
BCLK / 4
BCLK / 4
BCLK / 4
w
0
1
2
3
4
5
6
7
w
DC[2:0]
000
001
010
011
100
101
110
111
w
Description
Amount of Current in Operational Amplifier
Operation of the operational amplifier stops
Small
Medium Low
Medium
Medium High
Large
Reserved
Reserved
0
1
2
3
4
5
6
7
re
AP[2:0]
000
001
010
011
100
101
110
111
m
-Adjust the amount of fixed current from the fixed current source in the operational amplifier for the source driver.
Step-up cycle in Booster circuit 2,3
BCLK / 1
BCLK / 2
BCLK / 4
BCLK / 2
BCLK / 4
BCLK / 4
BCLK / 8
BCLK / 16
Note: BCLK is Clock frequency for Booster circuit
Restriction
Register
Availability
-If some parameters of the register not use the register need to be reserved.
Status
Normal Mode On, Idle Mode Off, Sleep Out
Normal Mode On, Idle Mode On, Sleep Out
Partial Mode On, Idle Mode Off, Sleep Out
Partial Mode On, Idle Mode On, Sleep Out
Sleep In
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Yes
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Preliminary
SPFD54126B
Default Value
DC[2:0]
4d
4d
4d
Default Value
DC[2:0]
4d
4d
4d
Default Value
m
DC[2:0]
4d
4d
4d
nd
.co
Default
1. 176x220 memory base (GM1, GM0 = “00”)
Status
AP[2:0]
Power On Sequence
2d
S/W Reset
2d
H/W Reset
2d
2. 176x176 memory base (GM1, GM0 = “01”)
Status
AP[2:0]
Power On Sequence
2d
S/W Reset
2d
H/W Reset
2d
3. 176x132 memory base (GM1, GM0 = “11”)
Status
AP[2:0]
Power On Sequence
2d
S/W Reset
2d
H/W Reset
2d
---------------
1st Parameter:
APB[2:0]
nd
Command
Parameter
Display
Action
Mode
Parameter:
DCB[2:0]
w
2
.m
Flow Chart
bt
re
PWCTR4 (C3H)
Legend
w
w
Sequential
transfer
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Preliminary
SPFD54126B
6.3.12. PWCTR5 (C4H): Power Control 5 (in Partial mode/ full-colors)
C4H
PWCTR5 (Power Control 5)
Inst / Para
D/CX
WRX
RDX
D17-8
D7
D6
D5
D4
D3
D2
D1
D0
(Code)
PWCTR5
0
↑
1
-
1
1
0
0
0
1
0
0
(C4H)
0
0
0
0
0
0
0
0
0
0
APC2
DCC2
APC1
DCC1
APC0
DCC0
03h
02h
st
1 Parameter
1
1
↑
nd
2 Parameter
1
1
↑
NOTE: “-” Don’t care, can be set to VDDI or DGND level
-Set the amount of current in Operational amplifier in Partial mode/ full-colors.
nd
.co
-Set the Booster circuit Step-up cycle in Partial mode/ full-colors.
.m
bt
Step-up cycle in Booster circuit 1
BCLK / 1
BCLK / 1
BCLK / 1
BCLK / 2
BCLK / 2
BCLK / 4
BCLK / 4
BCLK / 4
w
0
1
2
3
4
5
6
7
w
DC[2:0]
000
001
010
011
100
101
110
111
w
Description
Amount of Current in Operational Amplifier
Operation of the operational amplifier stops
Small
Medium Low
Medium
Medium High
Large
Reserved
Reserved
0
1
2
3
4
5
6
7
re
AP[2:0]
000
001
010
011
100
101
110
111
m
-Adjust the amount of fixed current from the fixed current source in the operational amplifier for the source driver.
Step-up cycle in Booster circuit 2,3
BCLK / 1
BCLK / 2
BCLK / 4
BCLK / 2
BCLK / 4
BCLK / 4
BCLK / 8
BCLK / 16
Note: BCLK is Clock frequency for Booster circuit
Restriction
Register
Availability
-If some parameters of the register not use the register need to be reserved.
Status
Normal Mode On, Idle Mode Off, Sleep Out
Normal Mode On, Idle Mode On, Sleep Out
Partial Mode On, Idle Mode Off, Sleep Out
Partial Mode On, Idle Mode On, Sleep Out
Sleep In
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Yes
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Preliminary
SPFD54126B
Default Value
DCC[2:0]
2d
2d
2d
Default Value
DCC[2:0]
2d
2d
2d
Default Value
m
DCC[2:0]
2d
2d
2d
nd
.co
Default
1. 176x220 memory base (GM1, GM0 = “00”)
Status
APC[2:0]
Power On Sequence
4d
S/W Reset
4d
H/W Reset
4d
2. 176x176 memory base (GM1, GM0 = “01”)
Status
APC[2:0]
Power On Sequence
4d
S/W Reset
4d
H/W Reset
4d
3. 176x132 memory base (GM1, GM0 = “11”)
Status
APC[2:0]
Power On Sequence
3d
S/W Reset
3d
H/W Reset
3d
---------------
1st Parameter:
APC[2:0]
nd
Command
Parameter
Display
Action
Mode
Parameter:
DCC[2:0]
w
2
.m
Flow Chart
bt
re
PWCTR5 (C4H)
Legend
w
w
Sequential
transfer
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Preliminary
SPFD54126B
6.3.13. VMCTR1 (C5H): VCOM Control 1
C5H
VMCTR1 (VCOM Control 1)
Inst / Para
D/CX
WRX
RDX
D17-8
D7
D6
D5
D4
D3
D2
D1
D0
(Code)
VMCTR1
0
↑
1
-
1
1
0
0
0
1
0
1
(C5h)
VMH6
VMH5
st
1 Parameter
1
nVM *
1
↑
NOTE: “-” Don’t care, can be set to VDDI or DGND level
VMH 4 VMH 3 VMH 2 VMH 1 VMH 0
-Set VCOMH Voltage
.m
w
w
VCOMH
3.850
3.875
3.900
3.925
3.950
3.975
4.000
4.025
4.050
4.075
4.100
4.125
4.150
4.175
4.200
4.225
4.250
4.275
4.300
4.325
4.350
4.375
4.400
4.425
4.450
4.475
4.500
m
VMH[6:0]
0110110
54
0110111
55
0111000
56
0111001
57
0111010
58
0111011
59
0111100
60
0111101
61
0111110
62
0111111
63
1000000
64
1000001
65
1000010
66
1000011
67
1000100
68
1000101
69
1000110
70
1000111
71
1001000
72
1001001
73
1001010
74
1001011
75
1001100
76
1001101
77
1001110
78
1001111
79
1010000
80
nd
.co
VCOMH
3.175
3.200
3.225
3.250
3.275
3.300
3.325
3.350
3.375
3.400
3.425
3.450
3.475
3.500
3.525
3.550
3.575
3.600
3.625
3.650
3.675
3.700
3.725
3.750
3.775
3.800
3.825
re
VMH[6:0]
0011011
27
0011100
28
0011101
29
0011110
30
0011111
31
0100000
32
0100001
33
0100010
34
0100011
35
0100100
36
0100101
37
0100110
38
0100111
39
0101000
40
0101001
41
0101010
42
0101011
43
0101100
44
0101101
45
0101110
46
0101111
47
0110000
48
0110001
49
0110010
50
0110011
51
0110100
52
0110101
53
bt
VCOMH
2.500
2.525
2.550
2.575
2.600
2.625
2.650
2.675
2.700
2.725
2.750
2.775
2.800
2.825
2.850
2.875
2.900
2.925
2.950
2.975
3.000
3.025
3.050
3.075
3.100
3.125
3.150
w
Description
VMH[6:0]
0000000
0
0000001
1
0000010
2
0000011
3
0000100
4
0000101
5
0000110
6
0000111
7
0001000
8
0001001
9
0001010
10
0001011
11
0001100
12
0001101
13
0001110
14
0001111
15
0010000
16
0010001
17
0010010
18
0010011
19
0010100
20
0010101
21
0010110
22
0010111
23
0011000
24
0011001
25
0011010
26
VMH[6:0]
VCOMH
1010001 81
4.525
1010010 82
4.550
1010011 83
4.575
1010100 84
4.600
1010101 85
4.625
1010110 86
4.650
1010111
87
4.675
1011000 88
4.700
1011001 89
4.725
1011010 90
4.750
1011011
91
4.775
1011100
92
4.800
1011101
93
4.825
1011110
94
4.850
1011111
95
4.875
1100000 96
4.900
1100001 97
4.925
1100010 98
4.950
1100011
99
4.975
1100100 100
5.000
1100101 101
Not
|
Permitted
1111111 127
-Select the VCOMH value
nVM *
VCOMH value
0
VCOMH value is from NV memory
1
VCOMH value is from the VCOMH[6:0] setting
st
-The nVM need be used in 1 parameter of VMCTR1 (C5h)
- When nVM=0, the value of VMH[6:0] is from NV memory. So it must program the NV memory first.
- When nVM=1, the vaule of VMH[6:0] is from $C5 register. It can fine-tune the display performance to the best quality
by setting this register, and program this optium value to NV memory.
-If this register not using the register need be reserved.
Restriction
-The deviation value of VCOMH between with Measurement and Specification: Max <=25mV
-The deviation value of VCOMAC between with Measurement and Specification: Max <=50mV
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Preliminary
SPFD54126B
Register
Availability
Status
Normal Mode On, Idle Mode Off, Sleep Out
Normal Mode On, Idle Mode On, Sleep Out
Partial Mode On, Idle Mode Off, Sleep Out
Partial Mode On, Idle Mode On, Sleep Out
Sleep In
Availability
Yes
Yes
Yes
Yes
Yes
Status
Default Value
LCM = ‘11’
VMH[6:0]
40d
40d
40d
nVM
Power On Sequence
S/W Reset
H/W Reset
0d
0d
0d
m
Default
1st Parameter: VMH[6:0]
Legend
Command
Parameter
Display
Action
Mode
Sequential
transfer
w
w
w
.m
bt
Flow Chart
re
VMCTR1 (C5h)
nd
.co
---------------
LCM = ‘01’
VMH[6:0]
26d
26d
26d
.
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Preliminary
SPFD54126B
6.3.14. VMCTR2 (C6H): VCOM Control 2
C6H
VMCTR2 (VCOM Control 2)
Inst / Para
D/CX
WRX
RDX
D17-8
D7
D6
D5
D4
D3
D2
D1
D0
(Code)
VMCTR2
0
↑
1
-
1
1
0
0
0
1
1
0
(C6H)
0
0
VMA5
VMA4
VMA3
VMA2
VMA1
VMA0
st
1 Parameter
1
1
↑
NOTE: “-” Don’t care, can be set to VDDI or DGND level
-Set VCOMAC Voltage
VMA[5:0]
100000
100001
100010
100011
100100
100101
100110
100111
101000
101001
m
VCOMAC
4.800
4.850
4.900
4.950
5.000
5.050
5.100
5.150
5.200
5.250
5.300
5.350
5.400
5.450
5.500
5.550
nd
.co
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
re
VMA[5:0]
010000
010001
010010
010011
010100
010101
010110
010111
011000
011001
011010
011011
011100
011101
011110
011111
111111
32
33
34
35
36
37
38
39
40
41
|
63
VCOMAC
5.600
5.650
5.700
5.750
5.800
5.850
5.900
5.950
6.000
Not
Permitted
bt
VCOMAC
4.000
4.050
4.100
4.150
4.200
4.250
4.300
4.350
4.400
4.450
4.500
4.550
4.600
4.650
4.700
4.750
.m
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
Restriction
Register
Availability
w
w
w
Description
VMA[5:0]
000000
000001
000010
000011
000100
000101
000110
000111
001000
001001
001010
001011
001100
001101
001110
001111
-If this register not use the register need be reserved.
-The deviation value of VCOMAC between with Measurement and Specification: Max <=50mV
Status
Normal Mode On, Idle Mode Off, Sleep Out
Normal Mode On, Idle Mode On, Sleep Out
Partial Mode On, Idle Mode Off, Sleep Out
Partial Mode On, Idle Mode On, Sleep Out
Sleep In
Availability
Yes
Yes
Yes
Yes
Yes
Status
Default
Power On Sequence
S/W Reset
H/W Reset
© ORISE Technology Co., Ltd.
Proprietary & Confidential
Default Value
LCM = ‘01’
TM LC Type
VMA[5:0]
21d
21d
21d
102
LCM = ‘11’
ECB LC type
VMA[5:0]
21d
21d
21d
Apr. 25, 2006
Preliminary Version: 0.1
Evaluation Only. Created with Aspose.Pdf.Kit. Copyright 2002-2005 Aspose Pty Ltd
Preliminary
SPFD54126B
---------------
Legend
VMCTR2 (C6H)
Command
Parameter
Display
Flow Chart
Action
st
1 Parameter: VMA[5:0]
Mode
w
w
w
.m
bt
re
nd
.co
m
Sequential
transfer
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Preliminary
SPFD54126B
6.3.15. RDVMOF (C8H): Read the VCOM Offset Value NV memory
C8H
RDVMOF (Read the VCOM Offset Value NV memory)
Inst / Para
D/CX
WRX
RDX
D17-8
D7
D6
D5
D4
D3
D2
D1
D0
(Code)
RDVMOF
0
↑
1
-
1
1
0
0
1
0
0
0
(C8H)
st
1 Parameter
0
1
↑
nd
2 Parameter
1
1
nVM
↑
NOTE: “-” Don’t care, can be set to VDDI or DGND level
RVMF6 RVMF5 RVMF4 RVMF3 RVMF2 RVMF1 RVMF0
-
-Read the VCOM offset value from NV memory
st
-The 1 parameter is dummy data.
Description
-The 2 parameter is VMF[6:0] value from NV memory or default value.
Restriction
-If this register not use the register need be reserved.
nd
.co
re
Default
Status
Power On Sequence
S/W Reset
H/W Reset
Availability
Yes
Yes
Yes
Yes
Yes
Default Value-
w
w
.m
bt
Register
Availability
Status
Normal Mode On, Idle Mode Off, Sleep Out
Normal Mode On, Idle Mode On, Sleep Out
Partial Mode On, Idle Mode Off, Sleep Out
Partial Mode On, Idle Mode On, Sleep Out
Sleep In
m
nd
Parallel I/F Mode
RDVMOF (BEH)
RDVMOF (BEH)
w
Flow Chart
Legend
Serial I/F Mode
Command
Parameter
Host
Driver
Send VMF[5:0]
Dummy Read
Display
Action
Mode
Send VMF[5:0]
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Preliminary
SPFD54126B
6.3.16. WRID2 (D1h): Write ID2 Value
WRID2 (Write ID2 Value)
D0H
Inst / Para
D/CX
WRX
RDX
D17-8
D7
D6
D5
D4
D3
D2
D1
D0
(Code)
WRID2
0
↑
1
-
1
1
0
1
0
0
0
1
(D1h)
1
↑
1
-
1
ID26
ID25
ID24
ID23
ID22
ID21
ID20
-
st
1 Parameter
NOTE: “-“ Don’t care
-Write 7-bits data of LCD module version to save it to NV memory.
Description
st
-The 1 parameter ID2[6:0] is LCD Module version ID.
nd
.co
Default
Status
Power On Sequence
S/W Reset
H/W Reset
Availability
Yes
Yes
Yes
Yes
Yes
.m
bt
re
Register
Availability
Status
Normal Mode On, Idle Mode Off, Sleep Out
Normal Mode On, Idle Mode On, Sleep Out
Partial Mode On, Idle Mode Off, Sleep Out
Partial Mode On, Idle Mode On, Sleep Out
Sleep In
m
Restriction
---------------
w
Legend
WRID2 (D1h)
w
Command
Parameter
w
Flow Chart
Default Value
Not Fixed
Not Fixed
Not Fixed
Display
Action
1st Parameter: ID2[6:0]
Mode
Sequential
transfer
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Preliminary
SPFD54126B
6.3.17. WRID3 (D2h): Write ID3 Value
WRID3 (Write ID3 Value)
D0H
Inst / Para
D/CX
WRX
RDX
D17-8
D7
D6
D5
D4
D3
D2
D1
D0
(Code)
WRID3
0
↑
1
-
1
1
0
1
0
0
1
0
(D2h)
1
↑
1
-
ID37
ID36
ID35
ID34
ID33
ID32
ID31
ID30
st
1 Parameter
NOTE: “-“ Don’t care
-Write 8-bits data of project code module to save it to NV memory.
st
-The 1 parameter ID3[7:0] is product project ID.
m
Description
Default
Status
Power On Sequence
S/W Reset
H/W Reset
Availability
Yes
Yes
Yes
Yes
Yes
w
.m
bt
re
Register
Availability
Status
Normal Mode On, Idle Mode Off, Sleep Out
Normal Mode On, Idle Mode On, Sleep Out
Partial Mode On, Idle Mode Off, Sleep Out
Partial Mode On, Idle Mode On, Sleep Out
Sleep In
nd
.co
Restriction
---------------
Default Value
00h
00h
00h
w
Legend
WRID3 (D2h)
w
Command
Parameter
Display
Flow Chart
Action
1st Parameter: ID3[7:0]
Mode
Sequential
transfer
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Preliminary
SPFD54126B
6.3.18. RDID4 (D3h): Read the ID4 value
RDID4 (Read the ID4 value)
D4H
Inst / Para
D/CX
WRX
RDX
D17-8
D7
D6
D5
D4
D3
D2
D1
D0
(Code)
RDID4
0
↑
1
-
1
1
0
1
0
0
1
1
(D3h)
1 Parameter
st
1
1
↑
-
-
-
-
-
-
-
-
-
nd
1
1
↑
-
ID417
ID416
ID415
ID414
ID413
ID412
ID411
ID410
-
rd
1
1
1
1
1
1
↑
↑
↑
-
ID427
ID437
ID447
ID426
ID436
ID446
ID425
ID435
ID445
ID424
ID434
ID444
ID423
ID433
ID443
ID422
ID432
ID442
ID421
ID431
ID441
ID420
ID430
ID440
-
2 Parameter
3 Parameter
th
4 Parameter
th
5 Parameter
NOTE: “-“ Don’t care
-Read the Driver IC information from mask value.
st
m
-The 1 parameter is dummy data.
Description
rd
nd
.co
nd
-The 2 parameter ID41[7:0] is Driver IC ID code.
-ID41[7:0] is 06H.
-The 3 parameter ID42[7:0] is Driver IC Part number ID. It is 16H.
th
th
bt
Status
Normal Mode On, Idle Mode Off, Sleep Out
Normal Mode On, Idle Mode On, Sleep Out
Partial Mode On, Idle Mode Off, Sleep Out
Partial Mode On, Idle Mode On, Sleep Out
Sleep In
Default
w
Status
w
w
Register
Availability
-
.m
Restriction
re
-The 4 & 5 parameter ID43[7:0] & ID44[7:0] are Driver IC version ID.
Power On Sequence
S/W Reset
H/W Reset
Availability
Yes
Yes
Yes
Yes
Yes
Default ValueID42[7:0]
ID43[7:0]
14H
00H
14H
00H
14H
00H
ID41[7:0]
06H
06H
06H
Serial I/F Mode
Partial I/F Mode
RDID4 (D3h)
RDID4 (D3h)
Legend
Command
Host
Driver
Flow Chart
Dummy Clock
Dummy Read
Send ID41[7:0]
Send ID41[7:0]
ID44[7:0]
00H
00H
00H
Parameter
Display
Action
Mode
© ORISE Technology Co., Ltd.
Proprietary & Confidential
Send ID42[7:0]
Send ID42[7:0]
Send ID43[7:0]
Send ID43[7:0]
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Preliminary
SPFD54126B
6.3.19. NVFCTR1 (D9h): NV Memory Function Controller 1
NVFCTR1 (NV Memory Function Controller 1)
D9H
Inst / Para
D/CX
WRX
RDX
D17-8
D7
D6
D5
D4
D3
D2
D1
D0
(Code)
NVFCTR1
0
↑
1
-
1
1
0
1
1
0
0
1
(D9h)
st
1 Parameter
1
↑
1
WVMH WVMH WVMH WVMH WVMH WVMH WVMH WVMH
7
6
5
4
3
2
1
0
-
-
NOTE: “-“ Don’t care1
- Write WVMH[6:0] for VCOMH voltage to $D9 when the value is considered as the optimum for display quality.
- The endurence for SPFD54126B NV memory is 4 times for VCOMH, ID1, ID2 and ID3.
m
START
nd
.co
EXTC=VDDI -->
Accessing Command2 enable
EXTC=VDDI
re
SLPOUT($11)
.m
bt
RAMWR($2C)
VMCTR1($C5)
= 8'b1xxx_xxxx
DISPON($29)
Description
w
w
w
Check the display quality
No
The Optimum value for
VCOMH = 7'bnnn_nnnn
Optimum Display??
Yes
VMCTR1($C5)
= 8'b0xxx_xxxx
Prepare the data that will be
written into OTP cell
WRID1($D0)
WRID2($D1)
WRID3($D2)
NVFCTR3($DF)
8'b1nnn_nnnn
SLPIN($10)
Wait more than 50ms
Apply 7.75V at VGH pad
Wait more than 200ms
OTP programming procedure
NVFCTR1 ($D9)
Wait more than 500ms
NVFCTR2 ($DE)
Wait more than 10ms
Remove external power
from VGH pad
Wait more than 10ms
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Preliminary
SPFD54126B
Restriction
The endurence of WVMH, ID1, ID2, and ID3 is 4 times.
Register
Availability
Status
Normal Mode On, Idle Mode Off, Sleep Out
Normal Mode On, Idle Mode On, Sleep Out
Partial Mode On, Idle Mode Off, Sleep Out
Partial Mode On, Idle Mode On, Sleep Out
Sleep In
Availability
Yes
Yes
Yes
Yes
Yes
Default
Status
Power On Sequence
S/W Reset
H/W Reset
Default Value
Not Fixed
Not Fixed
Not Fixed
Legend
Command
Parameter
Display
Action
Mode
Sequential
transfer
w
w
w
.m
bt
st
1 Parameter:
nd
.co
Flow Chart
re
NVFCTR1 (D9h)
m
---------------
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Preliminary
SPFD54126B
6.3.20. NVFCTR2 (DEh): NV Memory Function Controller 2
NVFCTR2 (NV Memory Function Controller 2)
DEH
Inst / Para
D/CX
WRX
RDX
D17-8
D7
D6
D5
D4
D3
D2
D1
D0
(Code)
NVFCTR2
0
↑
1
-
1
1
0
1
1
1
1
0
(DEh)
st
1
↑
1
-
1
1 Parameter
NOTE: “-“ Don’t care
Description
-
- Please refer to $D9 for details.
nd
.co
Default
Status
Power On Sequence
S/W Reset
H/W Reset
Availability
Yes
Yes
Yes
Yes
Yes
.m
bt
re
Register
Availability
Status
Normal Mode On, Idle Mode Off, Sleep Out
Normal Mode On, Idle Mode On, Sleep Out
Partial Mode On, Idle Mode Off, Sleep Out
Partial Mode On, Idle Mode On, Sleep Out
Sleep In
m
Restriction
---------------
w
Legend
NVFCTR1 (DEh)
w
Command
Parameter
w
Flow Chart
Default Value
Not Fixed
Not Fixed
Not Fixed
Display
Action
1st Parameter:
Mode
Sequential
transfer
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Preliminary
SPFD54126B
6.3.21. NVFCTR3 (DFh): NV Memory Function Controller 3
NVFCTR3 (NV Memory Function Controller 3)
DEH
Inst / Para
D/CX
WRX
RDX
D17-8
D7
D6
D5
D4
D3
D2
D1
D0
(Code)
NVFCTR3
0
↑
1
-
1
1
0
1
1
1
1
1
(DFh)
st
1
↑
1
-
1
1 Parameter
NOTE: “-“ Don’t care
Description
-
- Please refer to $D9 for details.
nd
.co
Default
Status
Power On Sequence
S/W Reset
H/W Reset
Availability
Yes
Yes
Yes
Yes
Yes
.m
bt
re
Register
Availability
Status
Normal Mode On, Idle Mode Off, Sleep Out
Normal Mode On, Idle Mode On, Sleep Out
Partial Mode On, Idle Mode Off, Sleep Out
Partial Mode On, Idle Mode On, Sleep Out
Sleep In
m
Restriction
---------------
w
Legend
NVFCTR3 (DFh)
w
Command
Parameter
w
Flow Chart
Default Value
Not Fixed
Not Fixed
Not Fixed
Display
Action
1st Parameter:
Mode
Sequential
transfer
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Preliminary
SPFD54126B
6.3.22. GMCTRP1 (E0H): Gamma (‘+’polarity for Red color) Correction Characteristics Setting
E0H
GMCTRP1 (Gamma ‘+’polarity Correction Characteristics Setting)
D/CX
WRX
RDX
D17-8
D7
D6
D5
D4
D3
D2
D1
D0
(Code)
0
↑
1
-
1
1
1
0
0
0
0
0
(E0h)
R_PVR1
V0[4]
R_PVR1
V1[4]
R_PVR1
V2[4]
R_PVR1
V61[4]
R_PVR1
V62[4]
R_PVR1
V63[4]
R_PVR2
V13[4]
R_PVR2
V50[4]
R_PVR1
V0[3]
R_PVR1
V1[3]
R_PVR1
V2[3]
R_PVR1
V61[3]
R_PVR1
V62[3]
R_PVR1
V63[3]
R_PVR2
V13[3]
R_PVR2
V50[3]
R_PVR3
V4[3]
R_PVR3
V8[3]
R_PVR3
V20[3]
R_PVR3
V27[3]
R_PVR3
V36[3]
R_PVR3
V43[3]
R_PVR3
V55[3]
R_PVR3
V59[3]
R_PVR1
V0[2]
R_PVR1
V1[2]
R_PVR1
V2[2]
R_PVR1
V61[2]
R_PVR1
V62[2]
R_PVR1
V63[2]
R_PVR2
V13[2]
R_PVR2
V50[2]
R_PVR3
V4[2]
R_PVR3
V8[2]
R_PVR3
V20[2]
R_PVR3
V27[2]
R_PVR3
V36[2]
R_PVR3
V43[2]
R_PVR3
V55[2]
R_PVR3
V59[2]
R_PVR1
V0[1]
R_PVR1
V1[1]
R_PVR1
V2[1]
R_PVR1
V61[1]
R_PVR1
V62[1]
R_PVR1
V63[1]
R_PVR2
V13[1]
R_PVR2
V50[1]
R_PVR3
V4[1]
R_PVR3
V8[1]
R_PVR3
V20[1]
R_PVR3
V27[1]
R_PVR3
V36[1]
R_PVR3
V43[1]
R_PVR3
V55[1]
R_PVR3
V59[1]
R_PVR1
V0[0]
R_PVR1
V1[0]
R_PVR1
V2[0]
R_PVR1
V61[0]
R_PVR1
V62[0]
R_PVR1
V63[0]
R_PVR2
V13[0]
R_PVR2
V50[0]
R_PVR3
V4[0]
R_PVR3
V8[0]
R_PVR3
V20[0]
R_PVR3
V27[0]
R_PVR3
V36[0]
R_PVR3
V43[0]
R_PVR3
V55[0]
R_PVR3
V59[0]
st
1
↑
1
-
-
-
nd
1
↑
1
-
-
-
rd
1
↑
1
-
-
-
th
1
↑
1
-
-
-
th
1
↑
1
-
-
-
th
1
↑
1
-
-
-
-
th
1
↑
1
-
-
-
-
th
1
↑
1
-
-
-
-
th
-
-
-
3 Parameter
4 Parameter
5 Parameter
6 Parameter
7 Parameter
8 Parameter
↑
1
th
1
↑
1
-
-
-
th
1
↑
1
-
-
-
th
1
↑
1
-
-
-
th
1
↑
1
-
-
-
th
1
↑
1
-
-
th
1
↑
1
-
-
th
1
↑
1
-
-
10 Parameter
11 Parameter
12 Parameter
13 Parameter
14 Parameter
15 Parameter
16 Parameter
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
.m
NOTE: “-“ Don’t care
-
-
bt
9 Parameter
re
1
-
R_PVR1
V1[5]
R_PVR1
V2[5]
R_PVR1
V61[5]
R_PVR1
V62[5]
nd
.co
1 Parameter
2 Parameter
m
Inst / Para
GMCTRP1
-When turn OFF the separate RGB gamma function the command is used for gamma (‘+’ polarity) correction
characteristics setting
w
w
Description
w
-When turn ON the separate RGB gamma function the command is used for R gamma (‘+’polarity) of GC0 correction
characteristics setting
Restriction
Register
Availability
Status
Normal Mode On, Idle Mode Off, Sleep Out
Normal Mode On, Idle Mode On, Sleep Out
Partial Mode On, Idle Mode Off, Sleep Out
Partial Mode On, Idle Mode On, Sleep Out
Sleep In
Availability
Yes
Yes
Yes
Yes
Yes
Default
Status
Power On Sequence
S/W Reset
H/W Reset
Default Value
----------
© ORISE Technology Co., Ltd.
Proprietary & Confidential
112
Apr. 25, 2006
Preliminary Version: 0.1
Evaluation Only. Created with Aspose.Pdf.Kit. Copyright 2002-2005 Aspose Pty Ltd
Preliminary
SPFD54126B
---------------
Legend
GMCTRP1 (E0H)
Command
Parameter
Flow Chart
Display
1st ~ 5th Parameter:
V0RP [3:0] ~ V9 RP [3:0]
Action
Mode
w
w
w
.m
bt
re
nd
.co
m
Sequential
transfer
© ORISE Technology Co., Ltd.
Proprietary & Confidential
113
Apr. 25, 2006
Preliminary Version: 0.1
Evaluation Only. Created with Aspose.Pdf.Kit. Copyright 2002-2005 Aspose Pty Ltd
Preliminary
SPFD54126B
6.3.23. GMCTRN1 (E1H): Gamma (‘-’polarity for Red color) Correction Characteristics Setting
E1H
GMCTRP1 (Gamma ‘+’polarity Correction Characteristics Setting)
D/CX
WRX
RDX
D17-8
D7
D6
D5
D4
D3
D2
D1
D0
(Code)
0
↑
1
-
1
1
1
0
0
0
0
0
(E1h)
R_NVR1
V0[4]
R_NVR1
V1[4]
R_NVR1
V2[4]
R_NVR1
V61[4]
R_NVR1
V62[4]
R_NVR1
V63[4]
R_NVR2
V13[4]
R_NVR2
V50[4]
R_NVR1
V0[3]
R_NVR1
V1[3]
R_NVR1
V2[3]
R_NVR1
V61[3]
R_NVR1
V62[3]
R_NVR1
V63[3]
R_NVR2
V13[3]
R_NVR2
V50[3]
R_NVR3
V4[3]
R_NVR3
V8[3]
R_NVR3
V20[3]
R_NVR3
V27[3]
R_NVR3
V36[3]
R_NVR3
V43[3]
R_NVR3
V55[3]
R_NVR3
V59[3]
R_NVR1
V0[2]
R_NVR1
V1[2]
R_NVR1
V2[2]
R_NVR1
V61[2]
R_NVR1
V62[2]
R_NVR1
V63[2]
R_NVR2
V13[2]
R_NVR2
V50[2]
R_NVR3
V4[2]
R_NVR3
V8[2]
R_NVR3
V20[2]
R_NVR3
V27[2]
R_NVR3
V36[2]
R_NVR3
V43[2]
R_NVR3
V55[2]
R_NVR3
V59[2]
R_NVR1
V0[1]
R_NVR1
V1[1]
R_NVR1
V2[1]
R_NVR1
V61[1]
R_NVR1
V62[1]
R_NVR1
V63[1]
R_NVR2
V13[1]
R_NVR2
V50[1]
R_NVR3
V4[1]
R_NVR3
V8[1]
R_NVR3
V20[1]
R_NVR3
V27[1]
R_NVR3
V36[1]
R_NVR3
V43[1]
R_NVR3
V55[1]
R_NVR3
V59[1]
R_NVR1
V0[0]
R_NVR1
V1[0]
R_NVR1
V2[0]
R_NVR1
V61[0]
R_NVR1
V62[0]
R_NVR1
V63[0]
R_NVR2
V13[0]
R_NVR2
V50[0]
R_NVR3
V4[0]
R_NVR3
V8[0]
R_NVR3
V20[0]
R_NVR3
V27[0]
R_NVR3
V36[0]
R_NVR3
V43[0]
R_NVR3
V55[0]
R_NVR3
V59[0]
st
1
↑
1
-
-
-
nd
1
↑
1
-
-
-
rd
1
↑
1
-
-
-
th
1
↑
1
-
-
-
th
1
↑
1
-
-
-
th
1
↑
1
-
-
-
-
th
1
↑
1
-
-
-
-
th
1
↑
1
-
-
-
-
th
-
-
-
3 Parameter
4 Parameter
5 Parameter
6 Parameter
7 Parameter
8 Parameter
↑
1
th
1
↑
1
-
-
-
th
1
↑
1
-
-
-
th
1
↑
1
-
-
-
th
1
↑
1
-
-
-
th
1
↑
1
-
-
th
1
↑
1
-
-
th
1
↑
1
-
-
10 Parameter
11 Parameter
12 Parameter
13 Parameter
14 Parameter
15 Parameter
16 Parameter
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
.m
NOTE: “-“ Don’t care
-
-
bt
9 Parameter
re
1
-
R_NVR1
V1[5]
R_NVR1
V2[5]
R_NVR1
V61[5]
R_NVR1
V62[5]
nd
.co
1 Parameter
2 Parameter
m
Inst / Para
GMCTRP1
w
-When turn OFF the separate RGB gamma function the command is used for gamma (‘-’ polarity) correction
characteristics setting
w
Description
w
-When turn ON the separate RGB gamma function the command is used for R gamma (‘-’ polarity) of GC0 correction
characteristics setting
Restriction
Register
Availability
Status
Normal Mode On, Idle Mode Off, Sleep Out
Normal Mode On, Idle Mode On, Sleep Out
Partial Mode On, Idle Mode Off, Sleep Out
Partial Mode On, Idle Mode On, Sleep Out
Sleep In
Availability
Yes
Yes
Yes
Yes
Yes
Default
Status
Power On Sequence
S/W Reset
H/W Reset
Default Value
----------
© ORISE Technology Co., Ltd.
Proprietary & Confidential
114
Apr. 25, 2006
Preliminary Version: 0.1
Evaluation Only. Created with Aspose.Pdf.Kit. Copyright 2002-2005 Aspose Pty Ltd
Preliminary
SPFD54126B
---------------
Legend
GMCTRN1 (E1H)
Command
Parameter
Flow Chart
Display
1st ~ 5th Parameter:
V0RN [3:0] ~ V9 RN [3:0]
Action
Mode
w
w
w
.m
bt
re
nd
.co
m
Sequential
transfer
© ORISE Technology Co., Ltd.
Proprietary & Confidential
115
Apr. 25, 2006
Preliminary Version: 0.1
Evaluation Only. Created with Aspose.Pdf.Kit. Copyright 2002-2005 Aspose Pty Ltd
Preliminary
SPFD54126B
6.3.24. GMCTRP2 (E2H): Gamma (‘+’polarity) for Green color Correction Characteristics Setting
E2H
GMCTRP1 (Gamma ‘+’polarity Correction Characteristics Setting)
D/CX
WRX
RDX
D17-8
D7
D6
D5
D4
D3
D2
D1
D0
(Code)
0
↑
1
-
1
1
1
0
0
0
0
0
(E2h)
G_PVR1
V0[4]
G_PVR1
V1[4]
G_PVR1
V2[4]
G_PVR1
V61[4]
G_PVR1
V62[4]
G_PVR1
V63[4]
G_PVR2
V13[4]
G_PVR2
V50[4]
G_PVR1
V0[3]
G_PVR1
V1[3]
G_PVR1
V2[3]
G_PVR1
V61[3]
G_PVR1
V62[3]
G_PVR1
V63[3]
G_PVR2
V13[3]
G_PVR2
V50[3]
G_PVR3
V4[3]
G_PVR3
V8[3]
G_PVR3
V20[3]
G_PVR3
V27[3]
G_PVR3
V36[3]
G_PVR3
V43[3]
G_PVR3
V55[3]
G_PVR3
V59[3]
G_PVR1
V0[2]
G_PVR1
V1[2]
G_PVR1
V2[2]
G_PVR1
V61[2]
G_PVR1
V62[2]
G_PVR1
V63[2]
G_PVR2
V13[2]
G_PVR2
V50[2]
G_PVR3
V4[2]
G_PVR3
V8[2]
G_PVR3
V20[2]
G_PVR3
V27[2]
G_PVR3
V36[2]
G_PVR3
V43[2]
G_PVR3
V55[2]
G_PVR3
V59[2]
G_PVR1
V0[1]
G_PVR1
V1[1]
G_PVR1
V2[1]
G_PVR1
V61[1]
G_PVR1
V62[1]
G_PVR1
V63[1]
G_PVR2
V13[1]
G_PVR2
V50[1]
G_PVR3
V4[1]
G_PVR3
V8[1]
G_PVR3
V20[1]
G_PVR3
V27[1]
G_PVR3
V36[1]
G_PVR3
V43[1]
G_PVR3
V55[1]
G_PVR3
V59[1]
G_PVR1
V0[0]
G_PVR1
V1[0]
G_PVR1
V2[0]
G_PVR1
V61[0]
G_PVR1
V62[0]
G_PVR1
V63[0]
G_PVR2
V13[0]
G_PVR2
V50[0]
G_PVR3
V4[0]
G_PVR3
V8[0]
G_PVR3
V20[0]
G_PVR3
V27[0]
G_PVR3
V36[0]
G_PVR3
V43[0]
G_PVR3
V55[0]
G_PVR3
V59[0]
st
1 Parameter
1
↑
1
-
-
-
G_PVR1
V1[5]
G_PVR1
V2[5]
G_PVR1
V61[5]
G_PVR1
V62[5]
1
↑
1
-
-
-
rd
1
↑
1
-
-
-
th
1
↑
1
-
-
-
th
1
↑
1
-
-
-
th
1
↑
1
-
-
-
-
th
1
↑
1
-
-
-
-
th
1
↑
1
-
-
-
-
th
-
2 Parameter
3 Parameter
4 Parameter
5 Parameter
6 Parameter
7 Parameter
8 Parameter
↑
1
-
-
-
1
↑
1
-
-
-
th
1
↑
1
-
-
-
th
1
↑
1
-
-
-
th
1
↑
1
-
-
-
th
1
↑
1
-
-
th
1
↑
1
-
-
th
1
↑
1
-
-
11 Parameter
12 Parameter
13 Parameter
14 Parameter
15 Parameter
16 Parameter
-
-
-
-
-
-
-
-
-
-
-
-
-
-
w
-When turn ON the separate RGB gamma function the command is only used for G gamma (‘+’polarity) of GC0 correction
characteristics setting
-When turn OFF the separate RGB gamma function the command is not used.
w
w
Description
-
.m
NOTE: “-“ Don’t care
-
bt
10 Parameter
-
-
re
1
th
9 Parameter
nd
.co
nd
m
Inst / Para
GMCTRP1
Restriction
Register
Availability
Status
Normal Mode On, Idle Mode Off, Sleep Out
Normal Mode On, Idle Mode On, Sleep Out
Partial Mode On, Idle Mode Off, Sleep Out
Partial Mode On, Idle Mode On, Sleep Out
Sleep In
Availability
Yes
Yes
Yes
Yes
Yes
Default
Status
Power On Sequence
S/W Reset
H/W Reset
Default Value
----------
© ORISE Technology Co., Ltd.
Proprietary & Confidential
116
Apr. 25, 2006
Preliminary Version: 0.1
Evaluation Only. Created with Aspose.Pdf.Kit. Copyright 2002-2005 Aspose Pty Ltd
Preliminary
SPFD54126B
---------------
Legend
GMCTRP2 (E2H)
Command
Parameter
Flow Chart
Display
1st ~ 5th Parameter:
V0GP [3:0] ~ V9 GP [3:0]
Action
Mode
w
w
w
.m
bt
re
nd
.co
m
Sequential
transfer
© ORISE Technology Co., Ltd.
Proprietary & Confidential
117
Apr. 25, 2006
Preliminary Version: 0.1
Evaluation Only. Created with Aspose.Pdf.Kit. Copyright 2002-2005 Aspose Pty Ltd
Preliminary
SPFD54126B
6.3.25. GMCTRN2 (E3H): Gamma (‘-’polarity) for Green color Correction Characteristics Setting
E3H
GMCTRP1 (Gamma ‘+’polarity Correction Characteristics Setting)
D/CX
WRX
RDX
D17-8
D7
D6
D5
D4
D3
D2
D1
D0
(Code)
0
↑
1
-
1
1
1
0
0
0
0
0
(E3h)
G_NVR1
V0[4]
G_NVR1
V1[4]
G_NVR1
V2[4]
G_NVR1
V61[4]
G_NVR1
V62[4]
G_NVR1
V63[4]
G_NVR2
V13[4]
G_NVR2
V50[4]
G_NVR1
V0[3]
G_NVR1
V1[3]
G_NVR1
V2[3]
G_NVR1
V61[3]
G_NVR1
V62[3]
G_NVR1
V63[3]
G_NVR2
V13[3]
G_NVR2
V50[3]
G_NVR3
V4[3]
G_NVR3
V8[3]
G_NVR3
V20[3]
G_NVR3
V27[3]
G_NVR3
V36[3]
G_NVR3
V43[3]
G_NVR3
V55[3]
G_NVR3
V59[3]
G_NVR1
V0[2]
G_NVR1
V1[2]
G_NVR1
V2[2]
G_NVR1
V61[2]
G_NVR1
V62[2]
G_NVR1
V63[2]
G_NVR2
V13[2]
G_NVR2
V50[2]
G_NVR3
V4[2]
G_NVR3
V8[2]
G_NVR3
V20[2]
G_NVR3
V27[2]
G_NVR3
V36[2]
G_NVR3
V43[2]
G_NVR3
V55[2]
G_NVR3
V59[2]
G_NVR1
V0[1]
G_NVR1
V1[1]
G_NVR1
V2[1]
G_NVR1
V61[1]
G_NVR1
V62[1]
G_NVR1
V63[1]
G_NVR2
V13[1]
G_NVR2
V50[1]
G_NVR3
V4[1]
G_NVR3
V8[1]
G_NVR3
V20[1]
G_NVR3
V27[1]
G_NVR3
V36[1]
G_NVR3
V43[1]
G_NVR3
V55[1]
G_NVR3
V59[1]
G_NVR1
V0[0]
G_NVR1
V1[0]
G_NVR1
V2[0]
G_NVR1
V61[0]
G_NVR1
V62[0]
G_NVR1
V63[0]
G_NVR2
V13[0]
G_NVR2
V50[0]
G_NVR3
V4[0]
G_NVR3
V8[0]
G_NVR3
V20[0]
G_NVR3
V27[0]
G_NVR3
V36[0]
G_NVR3
V43[0]
G_NVR3
V55[0]
G_NVR3
V59[0]
st
1
↑
1
-
-
-
nd
1
↑
1
-
-
-
rd
1
↑
1
-
-
-
th
1
↑
1
-
-
-
th
1
↑
1
-
-
-
th
1
↑
1
-
-
-
-
th
1
↑
1
-
-
-
-
th
1
↑
1
-
-
-
-
th
-
-
-
3 Parameter
4 Parameter
5 Parameter
6 Parameter
7 Parameter
8 Parameter
↑
1
th
1
↑
1
-
-
-
th
1
↑
1
-
-
-
th
1
↑
1
-
-
-
th
1
↑
1
-
-
-
th
1
↑
1
-
-
th
1
↑
1
-
-
th
1
↑
1
-
-
10 Parameter
11 Parameter
12 Parameter
13 Parameter
14 Parameter
15 Parameter
16 Parameter
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
w
w
-When turn ON the separate RGB gamma function the command is only used for G gamma (‘-’ polarity) of GC0 correction
characteristics setting
-When turn OFF the separate RGB gamma function the command is not used.
w
Description
-
.m
NOTE: “-“ Don’t care
-
-
bt
9 Parameter
re
1
-
G_NVR1
V1[5]
G_NVR1
V2[5]
G_NVR1
V61[5]
G_NVR1
V62[5]
nd
.co
1 Parameter
2 Parameter
m
Inst / Para
GMCTRP1
Restriction
Register
Availability
Status
Normal Mode On, Idle Mode Off, Sleep Out
Normal Mode On, Idle Mode On, Sleep Out
Partial Mode On, Idle Mode Off, Sleep Out
Partial Mode On, Idle Mode On, Sleep Out
Sleep In
Availability
Yes
Yes
Yes
Yes
Yes
Default
Status
Power On Sequence
S/W Reset
H/W Reset
Default Value
----------
© ORISE Technology Co., Ltd.
Proprietary & Confidential
118
Apr. 25, 2006
Preliminary Version: 0.1
Evaluation Only. Created with Aspose.Pdf.Kit. Copyright 2002-2005 Aspose Pty Ltd
Preliminary
SPFD54126B
---------------
Legend
GMCTRN2 (E3H)
Command
Parameter
Flow Chart
Display
1st ~ 5th Parameter:
V0GN [3:0] ~ V9 GN [3:0]
Action
Mode
w
w
w
.m
bt
re
nd
.co
m
Sequential
transfer
© ORISE Technology Co., Ltd.
Proprietary & Confidential
119
Apr. 25, 2006
Preliminary Version: 0.1
Evaluation Only. Created with Aspose.Pdf.Kit. Copyright 2002-2005 Aspose Pty Ltd
Preliminary
SPFD54126B
6.3.26. GMCTRP3 (E4H): Gamma (‘+’polarity) for Blue color correction Characteristics Setting
E4H
GMCTRP1 (Gamma ‘+’polarity Correction Characteristics Setting)
D/CX
WRX
RDX
D17-8
D7
D6
D5
D4
D3
D2
D1
D0
(Code)
0
↑
1
-
1
1
1
0
0
0
0
0
(E4h)
B_PVR1
V0[4]
B_PVR1
V1[4]
B_PVR1
V2[4]
B_PVR1
V61[4]
B_PVR1
V62[4]
B_PVR1
V63[4]
B_PVR2
V13[4]
B_PVR2
V50[4]
B_PVR1
V0[3]
B_PVR1
V1[3]
B_PVR1
V2[3]
B_PVR1
V61[3]
B_PVR1
V62[3]
B_PVR1
V63[3]
B_PVR2
V13[3]
B_PVR2
V50[3]
B_PVR3
V4[3]
B_PVR3
V8[3]
B_PVR3
V20[3]
B_PVR3
V27[3]
B_PVR3
V36[3]
B_PVR3
V43[3]
B_PVR3
V55[3]
B_PVR3
V59[3]
B_PVR1
V0[2]
B_PVR1
V1[2]
B_PVR1
V2[2]
B_PVR1
V61[2]
B_PVR1
V62[2]
B_PVR1
V63[2]
B_PVR2
V13[2]
B_PVR2
V50[2]
B_PVR3
V4[2]
B_PVR3
V8[2]
B_PVR3
V20[2]
B_PVR3
V27[2]
B_PVR3
V36[2]
B_PVR3
V43[2]
B_PVR3
V55[2]
B_PVR3
V59[2]
B_PVR1
V0[1]
B_PVR1
V1[1]
B_PVR1
V2[1]
B_PVR1
V61[1]
B_PVR1
V62[1]
B_PVR1
V63[1]
B_PVR2
V13[1]
B_PVR2
V50[1]
B_PVR3
V4[1]
B_PVR3
V8[1]
B_PVR3
V20[1]
B_PVR3
V27[1]
B_PVR3
V36[1]
B_PVR3
V43[1]
B_PVR3
V55[1]
B_PVR3
V59[1]
B_PVR1
V0[0]
B_PVR1
V1[0]
B_PVR1
V2[0]
B_PVR1
V61[0]
B_PVR1
V62[0]
B_PVR1
V63[0]
B_PVR2
V13[0]
B_PVR2
V50[0]
B_PVR3
V4[0]
B_PVR3
V8[0]
B_PVR3
V20[0]
B_PVR3
V27[0]
B_PVR3
V36[0]
B_PVR3
V43[0]
B_PVR3
V55[0]
B_PVR3
V59[0]
st
1
↑
1
-
-
-
nd
1
↑
1
-
-
-
rd
1
↑
1
-
-
-
th
1
↑
1
-
-
-
th
1
↑
1
-
-
-
th
1
↑
1
-
-
-
-
th
1
↑
1
-
-
-
-
th
1
↑
1
-
-
-
-
th
-
-
-
3 Parameter
4 Parameter
5 Parameter
6 Parameter
7 Parameter
8 Parameter
↑
1
th
1
↑
1
-
-
-
th
1
↑
1
-
-
-
th
1
↑
1
-
-
-
th
1
↑
1
-
-
-
th
1
↑
1
-
-
th
1
↑
1
-
-
th
1
↑
1
-
-
10 Parameter
11 Parameter
12 Parameter
13 Parameter
14 Parameter
15 Parameter
16 Parameter
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
w
.m
NOTE: “-“ Don’t care
-
-
bt
9 Parameter
re
1
-
B_PVR1
V1[5]
B_PVR1
V2[5]
B_PVR1
V61[5]
B_PVR1
V62[5]
nd
.co
1 Parameter
2 Parameter
m
Inst / Para
GMCTRP1
w
-When turn OFF the separate RGB gamma function the command is not used.
w
Description
-When turn ON the separate RGB gamma function the command is only used for B gamma (‘+’polarity) of GC0 correction
characteristics setting
Restriction
Register
Availability
Status
Normal Mode On, Idle Mode Off, Sleep Out
Normal Mode On, Idle Mode On, Sleep Out
Partial Mode On, Idle Mode Off, Sleep Out
Partial Mode On, Idle Mode On, Sleep Out
Sleep In
Availability
Yes
Yes
Yes
Yes
Yes
Default
Status
Power On Sequence
S/W Reset
H/W Reset
Default Value
----------
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Preliminary
SPFD54126B
---------------
Legend
GMCTRP3 (E4H)
Command
Parameter
Flow Chart
Display
1st ~ 5th Parameter:
V0BP [3:0] ~ V9 BP [3:0]
Action
Mode
w
w
w
.m
bt
re
nd
.co
m
Sequential
transfer
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Preliminary
SPFD54126B
6.3.27. GMCTRN3 (E5H): Gamma (‘-’polarity) for Blue color Correction Characteristics Setting
E5H
GMCTRP1 (Gamma ‘+’polarity Correction Characteristics Setting)
D/CX
WRX
RDX
D17-8
D7
D6
D5
D4
D3
D2
D1
D0
(Code)
0
↑
1
-
1
1
1
0
0
0
0
0
(E5h)
B_NVR1
V0[4]
B_NVR1
V1[4]
B_NVR1
V2[4]
B_NVR1
V61[4]
B_NVR1
V62[4]
B_NVR1
V63[4]
B_NVR2
V13[4]
B_NVR2
V50[4]
B_NVR1
V0[3]
B_NVR1
V1[3]
B_NVR1
V2[3]
B_NVR1
V61[3]
B_NVR1
V62[3]
B_NVR1
V63[3]
B_NVR2
V13[3]
B_NVR2
V50[3]
B_NVR3
V4[3]
B_NVR3
V8[3]
B_NVR3
V20[3]
B_NVR3
V27[3]
B_NVR3
V36[3]
B_NVR3
V43[3]
B_NVR3
V55[3]
B_NVR3
V59[3]
B_NVR1
V0[2]
B_NVR1
V1[2]
B_NVR1
V2[2]
B_NVR1
V61[2]
B_NVR1
V62[2]
B_NVR1
V63[2]
B_NVR2
V13[2]
B_NVR2
V50[2]
B_NVR3
V4[2]
B_NVR3
V8[2]
B_NVR3
V20[2]
B_NVR3
V27[2]
B_NVR3
V36[2]
B_NVR3
V43[2]
B_NVR3
V55[2]
B_NVR3
V59[2]
B_NVR1
V0[1]
B_NVR1
V1[1]
B_NVR1
V2[1]
B_NVR1
V61[1]
B_NVR1
V62[1]
B_NVR1
V63[1]
B_NVR2
V13[1]
B_NVR2
V50[1]
B_NVR3
V4[1]
B_NVR3
V8[1]
B_NVR3
V20[1]
B_NVR3
V27[1]
B_NVR3
V36[1]
B_NVR3
V43[1]
B_NVR3
V55[1]
B_NVR3
V59[1]
B_NVR1
V0[0]
B_NVR1
V1[0]
B_NVR1
V2[0]
B_NVR1
V61[0]
B_NVR1
V62[0]
B_NVR1
V63[0]
B_NVR2
V13[0]
B_NVR2
V50[0]
B_NVR3
V4[0]
B_NVR3
V8[0]
B_NVR3
V20[0]
B_NVR3
V27[0]
B_NVR3
V36[0]
B_NVR3
V43[0]
B_NVR3
V55[0]
B_NVR3
V59[0]
st
1
↑
1
-
-
-
nd
1
↑
1
-
-
-
rd
1
↑
1
-
-
-
th
1
↑
1
-
-
-
th
1
↑
1
-
-
-
th
1
↑
1
-
-
-
-
th
1
↑
1
-
-
-
-
th
1
↑
1
-
-
-
-
th
-
-
-
3 Parameter
4 Parameter
5 Parameter
6 Parameter
7 Parameter
8 Parameter
↑
1
th
1
↑
1
-
-
-
th
1
↑
1
-
-
-
th
1
↑
1
-
-
-
th
1
↑
1
-
-
-
th
1
↑
1
-
-
th
1
↑
1
-
-
th
1
↑
1
-
-
10 Parameter
11 Parameter
12 Parameter
13 Parameter
14 Parameter
15 Parameter
16 Parameter
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
w
.m
NOTE: “-“ Don’t care
-
-
bt
9 Parameter
re
1
-
B_NVR1
V1[5]
B_NVR1
V2[5]
B_NVR1
V61[5]
B_NVR1
V62[5]
nd
.co
1 Parameter
2 Parameter
m
Inst / Para
GMCTRP1
w
-When turn OFF the separate RGB gamma function the command is not used.
w
Description
-When turn ON the separate RGB gamma function the command is only used for B gamma (‘-’ polarity) of GC0 correction
characteristics setting
Restriction
Register
Availability
Status
Normal Mode On, Idle Mode Off, Sleep Out
Normal Mode On, Idle Mode On, Sleep Out
Partial Mode On, Idle Mode Off, Sleep Out
Partial Mode On, Idle Mode On, Sleep Out
Sleep In
Availability
Yes
Yes
Yes
Yes
Yes
Default
Status
Power On Sequence
S/W Reset
H/W Reset
Default Value
----------
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Preliminary
SPFD54126B
---------------
Legend
GMCTRN3 (E5H)
Command
Parameter
Flow Chart
Display
1st ~ 5th Parameter:
V0BN [3:0] ~ V9 BN [3:0]
Action
Mode
w
w
w
.m
bt
re
nd
.co
m
Sequential
transfer
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Preliminary
SPFD54126B
7. FUNCTION DESCRIPTION
7.1. MCU & RGB Interface
The SPFD54126B features System interfaces and RGB interface to satisfy various needs of small or medium size’s LCD panel. Based on
the application requirements, there are two display modes mostly used in the LCD end product.
1. Still picture display mode
2.
Moving picture display mode.
System interface is suitable for still picture display while RGB interface are suitable for moving picture display. Table 6.1 summarizes
different interfaces for various display requirements.
Table 7.1 MCU & RGB Interface Comparisons table
Function
RCM1, RCM0
RCM1, RCM0
“01”
"10"
m
"00"
Mode selection 1
MCU Mode 2
"11"
RGB I/F + SPI I/F
RGB Mode 1
IM2=’0’
IM2=’1’
IM2=’0’
SPI I/F
8080/ 6800 IF
SPI I/F
Motion /Still
selection
Motion or Still
Still
Motion or Still
Still
Motion or Still
Still
Motion or Stil
Still
Input data
D[B:0]
D0 = SDA
D[B:0]
SDA H/W pin
D[B:0]
SDA H/W pin
D[B:0]
SDA H/W pin
CSX
D/CX = SCL
CSX
SCL H/W pin
PCLK
D/CX = SCL
PCLK
D/CX = SCL
Input signal
WRX (R/WX),
RDX (E)
CSX
WRX (R/WX),
RDX (E)
SPI_CSX
VS, HS, DE
CSX
VS, HS, DE
CSX
GRAM Write cycle
Refer WRX
Refer SCL
Refer WRX
Refer SCL
Refer PCLK
D[7:0]
D0 = SDA
.m
w
Command setting
ICM='1'
RGB-1 I/F + SPI I/F
ICM='0'
ICM='1'
RGB-2 I/F + SPI I/F
Refer SCL
Refer PCLK
Refer SCL
Refer
Refer
Refer
Refer PCLK
Internal
Refer PCLK
Internal
Internal Oscillator
Oscillator
Oscillator
D[7:0]
SDA H/W pin
SDA
SDA H/W pin
SDA
SDA H/W pin
w
Refer
Internal Oscillator
GRAM Read Cycle
bt
IM2=’1’
8080/ 6800 IF
Mode selection 2
ICM='0'
RGB Mode 2
re
MCU Mode 1
nd
.co
8080/ 6800 IF + SPI I/F
VSYNC I/F
TE Function
Normal /
Partial mode
w
SMX, SMY, SRGB -When Power On or H/W reset, those function follow H/W pins setting first.
-By command setting
-Default is OFF
-By command setting
-Default is ON
-By command setting
-No support this function in these modes
-By command setting
-By command setting
Idle Mode
(IDM H/W pin)
Display On/ Off -By command setting
(SHUT H/W pin) -Don’t care in this mode, but should be set to VDDI or DGND.
Data inverter
(REV H/W pin)
DE H/W pin
-Don’t care in this mode, but should be set to VDDI or
DGND
RL H/W pin
TB H/W pin
Blanking porch
-Don’t care in this mode
Colors Format
-Control by IFPF[2:0] of COLMOD(3AH)
-By IDM H/W pin
-IDM On/OFF (39H/28H) are
disable
-By SHUT H/W pin
-SLPIN(10H),
SLPOUT(11H), Display
On/OFF (29h/28H) are
disable
-By REV H/W pin
-INVON/OFF (21H/20H) are
disable
-The data latched by rising
edge of PCLK when DE=’1’
-When DE='0' area, output is
-When display data coming
blanking display
the DE signal should be
VDDI level
-Don’t care in this mode, but
-By H/W pin
should be set to VDDI or
-No commands conflict
DGND
-Control by RGBBPCTR
-Control by DE signal
(D5)
-Control by VIPF[3:0] of COLMOD (3AH)
Note 1: RCM1 and RCM0 are H/W setting pins.
Note 2: In RGB + SPI I/F (RCM="1x"), VS, HS, DE, PCLK and D[17:0] are Hi-Z by Driver and can be stop for Host, when ICM='1'.
Note 3: In RGB + SPI I/F (RCM="1x"), the data deliver via GRAM
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Preliminary
SPFD54126B
Note 4: When Power on Driver IC should be detect SMX, SMY, SRGB H/W setting
Note 5: When Power on Driver IC should be detect RCM1, RCM0 H/W setting and get into the I/F mode.
Note 6: When Power on Driver IC should be detect LCM1, LCM0 H/W setting and get into the setting mode.
w
w
w
.m
bt
re
nd
.co
m
Note 7: When Power on Driver IC should be detect GM1, GM0 H/W setting and get into the setting mode.
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Preliminary
SPFD54126B
7.2. MPU Interface
7.2.1. Interface Type Selection
The MPU interfaces of SPFD54126B support 8-bit, 9-bit, 16-bit, and 18-bit’s 80- or 68-system Interface and Serial Peripheral Interface (SPI),
which can be set by the P68 and IM2/1/0 pins. The MPU interface can set instructions and access RAM. Table 6.2.1 depicts the interface
corresponding to P68and IM2/1/0 settings.
IM0
0
1
0
1
0
1
0
1
Interface
3-Pin Serial interface
8080 MCU 8-bits Parallel
8080 MCU 16-bits Parallel
8080 MCU 9-bits Parallel
8080 MCU 18-bits Parallel
3-Pin Serial interface
6800 MCU 8-bits Parallel
6800 MCU 16-bits Parallel
6800 MCU 9-bits Parallel
6800 MCU 18-bits Parallel
Read back selection
Via the read instruction (8-bits, 24-bits and 32-bits read parameter
RDX strobe (8-bits read data and 8-bits read parameter)
RDX strobe (16-bits read data and 8-bits read parameter)
RDX strobe (9-bits read data and 8-bits read parameter)
RDX strobe (18-bits read data and 8-bits read parameter)
Via the read instruction (8-bits, 24-bits and 32-bits read parameter
E strobe (8-bits read data and 8-bits read parameter)
E strobe (16-bits read data and 8-bits read parameter)
E strobe (9-bits read data and 8-bits read parameter)
E strobe (18-bits read data and 8-bits read parameter)
m
IM1
0
0
1
1
0
0
1
1
nd
.co
Table 7.2.1
P68 IM2
0
0
0
1
0
1
0
1
0
1
1
0
1
1
1
1
1
1
1
1
re
7.2.2. 8080-Series Parallel interface(P68=’0’)
bt
The MCU uses a 11-wires 8-data parallel interface or 19-wires 16-data parallel interface or 12-wires 9-data parallel interface or 21-wires
18-data parallel interface. The chip-select CSX(active low) enables and disables the parallel interface. RESX (active low) is an external
reset signal. WRX is the parallel data write, RDX is the parallel data read and D[17:0] is parallel data.
.m
The Graphics Controller Chip reads the data at the rising edge of WRX signal. The D/CX is the data/command flag. When D/CX=’1’, D[17:0]
bits are display RAM data or command parameters. When D/C=’0’, D[17:0] bits are commands.
w
The 8080-series bi-directional interface can be used for communication between the micro controller and LCD driver chip. The selection of
this interface is done when P68 pin is low state (DGND). Interface bus width can be selected with IM2, IM1 and IM0.
w
w
The interface function of 8080-series parallel interface are given in Table 6.2.2
Table 7.2.2 The function of 8080-series parallel interface
P68 IM2
0
0
0
0
1
1
1
1
IM1
IM0
Interface
0
0
8-bits
Parallel
1
16-bits
Parallel
0
9-bits
Parallel
1
18-bits
Parallel
0
1
1
© ORISE Technology Co., Ltd.
Proprietary & Confidential
D/CX
0
1
1
1
0
1
1
1
0
1
1
1
0
1
1
1
RDX
1
1
↑
↑
1
1
↑
↑
1
1
↑
↑
1
1
↑
↑
WRX
↑
↑
1
1
↑
↑
1
1
↑
↑
1
1
↑
↑
1
1
Function
Write 8-bits command (D7 to D0)
Write 8-bits display data or 8-bits parameter (D7 to D0)
Read 8-bits command (D7 to D0)
Read 8-bits parameter or status (D7 to D0)
Write 8-bits command (D7 to D0)
Write 16-bits display data (D15 to D0) or 8-bits parameter (D7 to D0)
Read 8-bits command (D7 to D0)
Read 8-bits parameter or status (D7 to D0)
Write 8-bits command (D7 to D0)
Write 9-bits display data (D8 to D0) or 8-bits parameter (D7 to D0)
Read 8-bits command (D7 to D0)
Read 8-bits parameter or status (D7 to D0)
Write 8-bits command (D7 to D0)
Write 18-bits display data (D17 to D0) or 8-bits parameter (D7 to D0)
Read 8-bits command (D7 to D0)
Read 8-bits parameter or status (D7 to D0)
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Preliminary
SPFD54126B
7.2.2.1. Write cycle sequence
The write cycle means that the host writes information (command or/and data) to the display via the interface. Each write cycle (WRX
high-low-high sequence) consists of 3 control (D/CX, RDX, WRX) and data signals (D[17:0]). D/CX bit is a control signal, which tells if the
data is a command or a data. The data signals are the command if the control signal is low (=’0’) and vice versa it is data (=’1’).
WRX
D[17:0]
The host stops to
control D[17:0] lines
nd
.co
The display writes
D[17:0] lines when
there is a falling edge
of the WRX
m
The host starts to
control D[17:0] lines
when there is a falling
edge of the WRX
Fig. 7.2.2.1.1 8080-Series WRX Protocol
CMD
CMD
PA1
CMD
PA1
PAN-2
PAN-1
P
‘1’
w
RESX
S
N-byte command (PA=N-1)
.m
D[17:0]
2-byte command
bt
1-byte command
re
Note: WRX is an unsynchronized signal (It can be stopped)
w
w
CSX
D/CX
‘1’
RDX
WRX
D[17:0]
S
CMD
CMD
PA1
CMD
PA1
PAN-2
PAN-1
P
Host [17:0]
Host to LCD
S
CMD
CMD
PA1
CMD
PA1
PAN-2
PAN-1
P
Driver [17:0]
LCD to Host]
Hi-Z
CMD: Write command code
PA: Parameter or RAM data
Signal on D[17:0], DCX. R/WX, E pins
during CSX=’1’ are ignored
Fig. 7.2.2.1.2 8080-Series parallel bus protocol, Write to register or display RAM
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7.2.2.2. Read Cycle Sequence
The read cycle (RDX high-low-high sequence) means that the host reads information from display via interface. The display sends data
(D[17:0]) to the host when there is a falling edge of RDX and the host reads data when there is a rising edge of RDX.
RDX
The display starts to
control D[17:0] lines
when there is a falling
edge of the RDX
m
D[17:0]
The host reads
D[17:0] lines when
there is a rising edge
of RDX
nd
.co
The display stops to
control D[17:0]
Fig. 7.2.2.2.1 8080-Series RDX Protocol
re
Note: RDX is an unsynchronized signal (It can be stopped)
S
CMD
D[17:0]
S
CMD
Host [17:0]
Host to LCD
S
CMD
Driver [17:0]
LCD to Host]
S
‘1’
PA
CMD
DM
data
data
P
CMD
DM
data
data
P
w
RESX
DM
.m
D[17:0]
Read display RAM data
bt
Read Parameter
w
w
CSX
D/CX
RDX
WRX
Hi-Z
DM
PA
Hi-Z
DM
CMD
PA
Hi-Z
CMD: Write command code
PA: Parameter or RAM data
DM: Dummy
Hi-Z
DM
P
data
data
P
Signal on D[17:0], DCX. R/WX, E pins
during CSX=’1’ are ignored
Fig. 7.2.2.2.2 8080-Series parallel bus protocol, Read data from register or display RAM
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7.2.3.
6800-Series Parallel Interface (P68=’1’)
The MCU uses a 11-wires 8-data parallel interface or 19-wires 16-data parallel interface or 12-wires 9-data parallel interface or 21-wires
18-data parallel interface. The chip-select CSX(active low) enables and disables the parallel interface. RESX (active low) is an external
reset signal. The R/WX is the Read/Write flag and D[17:0] is parallel data.
The Graphics Controller Chip reads the data at the falling edge of E signal when R/WX=’1’ and Writes the data at the falling of the E signal
when R/WX=’0’. The D/CX is the data/command flag. When D/CX=’1’, D[17:0] bits are display RAM data or command parameters. When
D/C=’0’, D[17:0] bits are commands.
The 6800-series bi-directional interface can be used for communication between the micro controller and LCD driver chip. The selection of
this interface is done when P68 pin is high state (VDDI). Interface bus width can be selected with IM2, IM1 and IM0.
The interface functions of 6800-series parallel interface are given in Table 7.2.3.
Table 7.2.3 The function of 6800-series parallel interface
1
1
0
1
16-bits
Parallel
1
1
1
0
9-bits
Parallel
1
1
1
1
18-bits
Parallel
m
8-bits
Parallel
nd
.co
0
Function
Write 8-bits command (D7 to D0)
Write 8-bits display data or 8-bits parameter (D7 to D0)
Read 8-bits command (D7 to D0)
Read 8-bits parameter or status (D7 to D0)
Write 8-bits command (D7 to D0)
Write 16-bits display data (D15 to D0) or 8-bits parameter (D7 to D0)
Read 8-bits command (D7 to D0)
Read 8-bits parameter or status (D7 to D0)
Write 8-bits command (D7 to D0)
Write 9-bits display data (D8 to D0) or 8-bits parameter (D7 to D0)
Read 8-bits command (D7 to D0)
Read 8-bits parameter or status (D7 to D0)
Write 8-bits command (D7 to D0)
Write 18-bits display data (D17 to D0) or 8-bits parameter (D7 to D0)
Read 8-bits command (D7 to D0)
Read 8-bits parameter or status (D7 to D0)
re
0
E
↓
↓
↓
↓
↓
↓
↓
↓
↓
↓
↓
↓
↓
↓
↓
↓
bt
1
R/WX
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
w
w
1
D/CX
0
1
1
1
0
1
1
1
0
1
1
1
0
1
1
1
.m
Interface
w
P68 IM2 IM1 IM0
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Preliminary
SPFD54126B
7.2.3.1. Write cycle sequence
The write cycle means that the host writes information (command or/and data) to the display via the interface. Each write cycle (E
low-high-low sequence) consists of 3 control (D/CX, E, R/WX) and data signals (D[17:0]). D/CX bit is a control signal, which tells if the data
is a command or a data. The data signals are the command if the control signal is low (=’0’) and vice versa it is data (=’1’).
R/WX
‘0’
E
The host starts to
control D[17:0] lines
when there is a rising
edge of the E
The host stops to
control D[17:0] lines
nd
.co
The display writes
D[17:0] lines when
there is a falling edge
of the E
m
D[17:0]
re
Fig. 7.2.3.1.1 6800-Series Write Protocol
D[17:0]
CMD
w
CMD
N-byte command (PA=N-1)
PA1
CMD
PA1
PAN-2
PAN-1
P
w
RESX
S
2-byte command
w
1-byte command
.m
bt
Note: E is an unsynchronized signal (It can be stopped)
‘1’
CSX
D/CX
R/WX
‘0’
E
D[17:0]
S
CMD
CMD
PA1
CMD
PA1
PAN-2
PAN-1
P
Host [17:0]
Host to LCD
S
CMD
CMD
PA1
CMD
PA1
PAN-2
PAN-1
P
Driver [17:0]
LCD to Host]
Hi-Z
CMD: Write command code
PA: Parameter or RAM data
Signal on D[17:0], DCX. R/WX, E pins
during CSX=’1’ are ignored
Fig. 7.2.3.1.2 6800-Series parallel bus protocol, Write to register or display RAM
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Preliminary
SPFD54126B
7.2.3.2. Read cycle sequence
The read cycle means that the host reads information (command or/and data) to the display via the interface. Each read cycle (E
low-high-low sequence) consists of 3 control (D/CX, E, R/WX) and data signals (D[17:0]). D/CX bit is a control signal, which tells if the data
is a command or a data. The data signals are the command if the control signal is low (=’0’) and vice versa it is data (=’1’).
R/WX
‘1’
E
The display starts to
control D[17:0] lines
when there is a rising
edge of the E
m
D[17:0]
The host reads
D[17:0] lines when
there is a falling edge
of the E
nd
.co
The display stops to
control D[17:0] lines
re
Fig. 7.2.3.2.1 6800-Series Read Protocol
RESX
S
CMD
DM
w
D[17:0]
w
Read Parameter
w
.m
bt
Note: E is an unsynchronized signal (It can be stopped)
Read display RAM data
PA
CMD
DM
data
data
P
PA
CMD
DM
data
data
P
‘1’
CSX
D/CX
R/WX
‘1’
‘0’
E
D[17:0]
S
CMD
Host [17:0]
Host to LCD
S
CMD
Driver [17:0]
LCD to Host]
S
Hi-Z
DM
Hi-Z
DM
Hi-Z
CMD
PA
Hi-Z
DM
CMD: Write command code
PA: Parameter or RAM data
DM: Dummy
P
data
data
P
Signal on D[17:0], DCX. R/WX, E pins
during CSX=’1’ are ignored
Fig. 7.2.3.2.2 6800-Series parallel bus protocol, Read data from register or display RAM
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Preliminary
SPFD54126B
7.2.4.
Serial Peripheral interface (SPI)
The selection of this interface is done by IM2. See the Table 7.2.4.
The serial interface is a 3-pin 9-bits bi-directional interface for communication between the micro controller and the LCD driver chip. The
3-pin serial use: CSX (chip enable), SCL (serial clock) and SDA (serial data input/output). Serial clock (SCL) is used for interface with MCU
only, so it can be stopped when no communication is necessary.
Table 7.2.4 Serial Interface Type Selection
P68
‘-‘
IM2
0
IM1
‘-‘
IM0
Interface
‘-‘ 3-Pin Serial interface
Read back selection
Via the read instruction (8-bits, 24-bits and 32-bits read parameter
7.2.4.1. Command Write Mode
nd
.co
m
The write mode of the interface means the micro controller writes commands and data to the 3-Pin serial data packet contains a control bit
D/CX and a transmission byte. If D/CX is low, the transmission byte is interpreted as command byte. If D/CX is high, the transmission byte
is stored in the display data RAM (Memory write command), or command register as parameter.
Any instruction can be sent in any order to the DRIVER. The MSB is transmitted first. The serial interface is initialized when CSX is high. In
this state, SCL clock pulse or SDA data have no effect. A falling edge on CSX enables the serial interface and indicates the start of data
transmission.
Transmission byte(TB) may be a command or a data
.m
D/CX
bt
MSB
LSB
D/CX D7 D6 D5 D4 D3 D2 D1 D0
D/CX
D/CX
(TB)
(TB)
w
(TB)
re
3-pin Serial Data Stream Format
w
Fig. 7.2.4.1.1 Serial interface data Stream format
w
When CSX is high, SCL clock is ignored. During the high time of CSX the serial interface is initialized. At the falling edge of CSX, SCL can
be high or low. SDA is sampled at the rising edge of CSX. D/CX indicates, whether the byte is command code (D/CX=’0’) or parameter/RAM
data (D/CX=’1’). It is sampled when first rising edge of CSX. If CSX stay low after the last bit of command/data byte, the serial interface
expects the D/CX bit of the next byte at the next rising edge of SCL.
S
TB
TB
P
CSX
Host
(MCU to
Driver)
SDA
0
D7
D6
D5
D4
D3
D2
D1
D/C
D0
D7
D6
D5
D4
D3
D2
D1
D0
SCL
Command
Command / Parameter
CSX can be ‘H’ between parameter / command and
parameter /command SCL and SDA during CSX=’H’ is
i
lid
Fig. 7.2.4.1.2 Serial interface Write protocol (Write to register with control bit in transmission)
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SPFD54126B
7.2.4.2. Read Functions
The read mode of the interface means that the micro controller reads register value from the Driver. To do the micro controller first has to
send a command (Read ID or register command) and then the following byte is transmitted in the opposite direction. After the read status
command has been sent, the SDA lin must be set to tri-state no later than at the falling edge of SCL of the last bit.
3-Pin Serial Protocol (for RDID1/RDID2/RDID3/0Ah/0Bh/0Ch/0Dh/0Eh/0Fh command: 8-bit read)
S
TB
TB
P
S
Driver
SDA
(SDI)
D/CX
D7
D6
SDA
(SDO)
D5
D4
D3
D2
D1
High-Z
D0
High-Z
D7
D6
D5
TB
D/CX
D3
D2
D1 D0
TB
S
bt
P
.m
SDA
(SDI)
D/CX D7
D6
D5
D4
w
SCL
D3
w
Host
CSX
D2
D1
High-Z
SDA
(SDO)
High-Z
D0
D23
w
Driver
D4
re
3-Pin Serial Protocol (for RDDID command: 24-bit read)
S
m
SCL
nd
.co
Host
CSX
D22 D21
D/CX
D20 D19
D3
D2
D1 D0
Dummy Clock Cycle
3-Pin Serial Protocol (for RDDST command: 32-bit read)
TB
S
TB
P
S
Host
CSX
SCL
Driver
SDA
(SDI)
D/CX
D7
SDA
(SDO)
D6
D5
D4
High-Z
D3
D2
D1
High-Z
D0
D31 D30 D29
D28 D27
D/CX
D3
D2
D1 D0
Dummy Clock Cycle
Fig. 7.2.4.2.1 3-pin Serial interface Read protocol
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SPFD54126B
7.2.5.
Data Transfer Break and Recovery
If there is a break in data transmission by RESX pulse, while transferring a Command or Frame Memory Data or Multiple Parameter
command Data, before Bit D0 of the byte has been completed, then DRIVER will reject the previous bits and have reset the interface such
that it will be ready to receive command data again when the chip select line (CSX) is next activated after RESX have been High state. See
the following example
S
TB
TB
P
CSX
Wait for more than 10µs
m
(MPU to
Driver)
RESX
SCL
SDA
D7
D/CX
D6
D5
D4
D3
nd
.co
Host
D2
D/CX
Command /
Parameter / Data
D7
D6
D5
D4
D3
D2
D1
D0
Command
bt
re
SCL and SDA during RESX = “L” is invalid and next
byte becomes command
.m
Fig. 7.2.5.1 Serial bus protocol, write mode – interrupted by RESX
w
w
w
If there is a break in data transmission by CSX pulse, while transferring a Command or Frame Memory Data or Multiple Parameter
command Data, before Bit D0 of the byte has been completed, then DRIVER will reject the previous bits and have reset the interface such
that it will be ready to receive the same byte re-transmitted when the chip select line (CSX) is next activated. See the following example
S
TB
TB
P
CSX
SCL
Host
SDA
D/CX
(MPU to
Driver)
D7
D6
D5
D4
Command /
Parameter /
Data
D/CX
Break
D7
D6
D5
D4
D3
D2
D1
D0
Command /
Parameter /
Data
Fig. 7.2. 5.2 Serial bus protocol, write mode – interrupted by CSX
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If 1, 2 or more parameter command is being sent and a break occurs while sending any parameter before the last one and if the host then
sends a new command rather than re-transmitting the parameter that was interrupted, then the parameters that were successfully sent are
stored and the parameter where the break occurred is rejected. The interface is ready to receive next byte as shown below.
PARA11 is sucessfully sended but PARA12
is breaked and need to be transfered again
Break
PARA11
CMD2
PARA12
PARA11
PARA12
PARA13
nd
.co
CMD1
m
CMD1
Command1 with 1st parameter (PARA11) should
be executed again to write remained parameter
(PARA12 and PARA13)
re
Fig.7.2.5.3 Write interrupts recovery (serial interface)
bt
If a 2 or more parameter command is being sent and a break occurs by the other command before the last one is sent, then the parameters
that were successfully sent are stored and the other parameter of that command remains previous value.
CMD1
.m
PARA11 is sucessfully sent but the other parameters
are not sent and break happeds by the other
command.
CMD2
w
w
PARA11
w
Break
CMD1
PARA11
PARA12
PARA13
Command1 with 1st parameter (PARA11) should
be executed again to write remained parameter
(PARA12 and PARA13)
Fig. 7.2.5.4 Write interrupts recovery (both serial and parallel interface)
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Preliminary
SPFD54126B
7.2.6.
Data Transfer Pause
It will be possible when transferring a Command, Frame Memory Data or Multiple Parameter Data to invoke a pause in the data
transmission. If the Chip Select Line is released after a whole byte of a Frame Memory Data or Multiple Parameter Data has been
completed, then DRIVER will wait and continue the Frame Memory Data or Parameter Data Transmission from the point where it was
paused. If the Chip Select Line is released after a whole byte of a command has been completed, then the Display Module will receive
either the command’s parameters (if appropriate) or a new command when the Chip Select Line is next enabled as shown below.
This applies to the following 4 conditions:
1) Command-Pause-Command
2) Command-Pause-Parameter
3) Parameter-Pause-Command
nd
.co
m
4) Parameter-Pause-Parameter
7.2.6.1. Serial Interface Pause
TB
bt
D7
D6
D5
D4
D3
D2
D1
D0
D/CX
w
D/CX
.m
SCL
(MPU to
Driver)
SDA
P
Pause
CSX
Host
TB
re
S
D6
D5
D4
D3
D2
D1
D0
Command / Parameter / Data
w
Command / Parameter / Data
D7
w
SCL and SDA during CSX = “H” is invalid
Fig. 7.2.6.1 Serial interface Pause Protocol (pause by CSX)
7.2.6.2. Parallel Interface Pause
CSX
Pause
D/CX
RDX
WRX
D[17:0]
D17 to D0
D17 to D0
Command /
Parameter
Pause
Command /
Parameter
Fig. 7.2.6.2 Parallel bus Pause Protocol (paused by CSX)
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Preliminary
SPFD54126B
7.2.7.
Data Transfer Modes
The Module has three kinds colour modes for transferring data to the display RAM. These are 12-bit colour per pixel, 16-bit colour per pixel
and 18-bit colour per pixel. The data format is described for each interface. Data can be downloaded to the Frame Memory by 2 methods.
7.2.7.1. Method 1
The Image data is sent to the Frame Memory in successive Frame writes, each time the Frame Memory is filled, the Frame Memory pointer
is reset to the start point and the next Frame is written.
Start
Image
Data
Frame 1
Image
Data
Frame 2
Image
Data
Frame 3
Any
Command
m
Start Frame
Memory
Write
Stop
nd
.co
7.2.7.2. Method 2
Start
Any
Command
Image
Data
Frame 2
Any
Command
w
w
w
Stop
Any
Command
Start Frame
Memory
Write
bt
Image
Data
Frame 1
.m
Start Frame
Memory
Write
re
Image Data is sent and at the end of each Frame Memory download, a command is sent to stop Frame Memory Write. Then Start Memory
Write command is sent, and a new Frame is downloaded.
Note:
1) These apply to all data transfer Colour modes on both serial and parallel interfaces.
2) The frame memory can contain both odd and even number of pixels for both methods. Only complete pixel data will be stored in the
frame memory.
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SPFD54126B
7.3.
MCU Data Colour Coding
7.3.1.
MCU Data Colour Coding for RAM data Write
- Parallel 8-Bits Bus Interface (IM1, IM0= “00”)
D7
0
D7
R3
B3
G3
R4
G2
R5
G5
B5
re
- Parallel 16-Bits Bus Interface (IM1, IM0= “01”)
D8
x
D8
x
x
x
x
x
x
x
x
Table 7.3.1.2 16-Bits Parallel Interface Set Table
Register
D17 D16 D15 D14 D13 D12 D11 D10 D9
Command
x
x
x
x
x
x
x
x
x
3AH
D17 D16 D15 D14 D13 D12 D11 D10 D9
03h
x
x
x
x
x
x
R3 R2 R1
05h
x
x
R4 R3 R2 R1 R0 G5 G4
x
x
R5 R4 R3 R2 R1 R0
x
06h
x
x
B5 B4 B3 B2 B1 B0
x
x
x
G5 G4 G3 G2 G1 G0
x
D6
0
D6
R2
B2
G2
R3
G1
R4
G4
B4
D5
1
D5
R1
B1
G1
R2
G0
R3
G3
B3
D4
0
D4
R0
B0
G0
R1
B4
R2
G2
B2
D3
1
D3
G3
R3
B3
R0
B3
R1
G1
B1
D2
1
D2
G2
R2
B2
G5
B2
R0
G0
B0
D1
0
D1
G1
R1
B1
G4
B1
x
x
x
D0
Command
0
2CH
D0
Colour
G0
4K-Colour
R0 (2-pixels/ 3-byyes)
B0
G3
65K-Colour
B0 (1-pixels/ 2-byyes)
x
262K-Colour
x (1-pixels/ 3byyes)
x
m
D9
x
D9
x
x
x
x
x
x
x
x
nd
.co
Table 7.3.1.1 8-Bits Parallel Interface Set Table
Register
D17 D16 D15 D14 D13 D12 D11 D10
Command
x
x
x
x
x
x
x
x
3AH
D17 D16 D15 D14 D13 D12 D11 D10
x
x
x
x
x
x
x
x
03h
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
05h
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
06h
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
D7
0
D7
G3
G2
G5
R5
B5
D6
0
D6
G2
G1
G4
R4
B4
D5
1
D5
G1
G0
G3
R3
B3
D4
0
D4
G0
B4
G2
R2
B2
D3
1
D3
B3
B3
G1
R1
B1
D2
1
D2
B2
B2
G0
R0
B0
D1
0
D1
B1
B1
x
x
x
D0
0
D0
B0
B0
x
x
x
D9
x
D9
x
x
D8
x
D8
R5
G2
D7
0
D7
R4
G1
D6
0
D6
R3
G0
D5
1
D5
R2
B5
D4
0
D4
R1
B4
D3
1
D3
R0
B3
D2
1
D2
G5
B2
D1
0
D1
G4
B1
D0
0
D0
G3
B0
Register
2CH
Colour
262K-Colour
(1-pixels/ 2bytes)
Table 7.3.1.4 18-Bits Parallel Interface Set Table
Register
D17 D16 D15 D14 D13 D12 D11 D10 D9
Command
x
x
x
x
x
x
x
x
x
3AH
D17 D16 D15 D14 D13 D12 D11 D10 D9
03h
x
x
x
x
x
x
R3 R2 R1
05h
x
x
R4 R3 R2 R1 R0 G5 G4
06h
R5 R4 R3 R2 R1 R0 G5 G4 G3
D8
x
D8
R0
G3
G2
D7
0
D7
G3
G2
G1
D6
0
D6
G2
G1
G0
D5
1
D5
G1
G0
B5
D4
0
D4
G0
B4
B4
D3
1
D3
B3
B3
B3
D2
1
D2
B2
B2
B2
D1
0
D1
B1
B1
B1
D0
0
D0
B0
B0
B0
Register
2CH
Colour
4K-Colour
65K-Colour
262K-Colour
Command
2CH
Colour
4K-Colour
65K-Colour
262K-Colour
(2-pixels/ 3byyes)
w
w
w
.m
bt
D8
x
D8
R0
G3
x
x
x
- Parallel 9-Bits Bus Interface (IM1, IM0= “10”)
Table 7.3.1.3 9-Bits Parallel Interface Set Table
Register
D17 D16 D15 D14 D13 D12 D11 D10
Command
x
x
x
x
x
x
x
x
3AH
D17 D16 D15 D14 D13 D12 D11 D10
x
x
x
x
x
x
x
x
06h
x
x
x
x
x
x
x
x
- Parallel 18-Bits Bus Interface (IM1, IM0= “11”)
Note: ‘x’ Don’t care, but need to set VDDI or DGND level.
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7.3.1.1. Parallel 8-Bits Bus Interface for RAM Data Write (IM1, IM0= “00”)
Different display data formats are available for three colours depth supported by listed below.
- 4K-Colours, RGB 4,4,4-bits input data. (3AH=”03h”)
- 65K-Colours, RGB 5,6,5-bits input data. (3AH=”05h”)
- 262K-Colours, RGB 6,6,6-bits input data. (3AH=”06h”)
(1). 8-bits data bus for 12-bits/pixel (RGB 4-4-4-bits input), 4K-colours, 3AH=”03h”
There are 2 pixels (6 sub-pixels) per 3-bytes.
‘1’
m
RESX
IM1, IM0 = ”00”
nd
.co
IM1/IM0
CSX
D/CX
R/WX
‘0’
8080-Series control pins
bt
‘1’
6800-Series control pins
.m
RDX
re
WRX
D7
0
D6
0
D5
w
E
B1, Bit 3
G2, Bit 3
R3, Bit 3
R1, Bit 2
B1, Bit 2
G2, Bit 2
R3, Bit 2
1
R1, Bit 1
B1, Bit 1
G2, Bit 1
R3, Bit 1
D4
0
R1, Bit 0
B1, Bit 0
G2, Bit 0
R3, Bit 0
D3
1
G1, Bit 3
R2, Bit 3
B2, Bit 3
G3, Bit 3
D2
1
G1, Bit 2
R2, Bit 2
B2, Bit 2
G3, Bit 2
D1
0
G1, Bit 1
R2, Bit 1
B2, Bit 1
G3, Bit 1
D0
0
G1, Bit 0
R2, Bit 0
B2, Bit 0
G3, Bit 0
Pixel n
Pixel n+1
w
w
R1, Bit 3
12-bits
12-bits
Look-Up Table for 4K-colors or data mapping (12-Bits to 18-Bits)
18-bits
Frame
Memory
18-bits
R1 G1 B1 R2 G2 B2 R3 G3 B3
Note1. The data order is ad follows, MSB=D7, LSB=D0 and picture data is MSB=Bit 3, LSB=Bit 0 for Red, Green and Blue data.
Note 2.3-times transfer is used to transmit 1 pixel data with the 12-bits color depth information.
Note 3. ‘-‘ = Don't care - Can be set to VDDI or DGND level
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Preliminary
SPFD54126B
(2). 8-bits data bus for 16-bits/pixel (RGB 5-6-5-bits input), 65K-colours, 3AH=”05h”
There are 1 pixels (3 sub-pixels) per 2-bytes.
RESX
‘1’
IM1, IM0 = ”00”
IM1/IM0
CSX
D/CX
‘1’
R/WX
‘0’
nd
.co
RDX
m
WRX
D7
0
R1, Bit 4
D6
0
R1, Bit 3
D5
1
R1, Bit 2
D4
0
D3
1
.m
E
D2
1
D1
0
D0
0
6800-Series control pins
R2, Bit 4
G2, Bit 2
G1, Bit 1
R2, Bit 3
G2, Bit 1
G1, Bit 0
R2, Bit 2
G2, Bit 0
R1, Bit 1
B1, Bit 5
R2, Bit 1
B2, Bit 5
R1, Bit 0
B1, Bit 3
R2, Bit 0
B2, Bit 3
G1, Bit 5
B1, Bit 2
G2, Bit 5
B2, Bit 2
G1, Bit 4
B1, Bit 1
G2, Bit 4
B2, Bit 1
G1, Bit 3
B1, Bit 0
G2, Bit 3
B2, Bit 0
bt
re
G1, Bit 2
w
w
w
8080-Series control pins
Pixel n+1
Pixel n
16-bits
16-bits
Look-Up Table for 4K-colors or data mapping (16-Bits to 18-Bits)
18-bits
Frame
Memory
18-bits
R1 G1 B1 R2 G2 B2 R3 G3 B3
Note1. The data order is ad follows, MSB=D7, LSB=D0 and picture data is MSB=Bit 5, LSB=Bit 0 for Green and MSB=Bit 4, LSB=Bit 0 for
Red and Blue data.
Note 2.2-times transfer is used to transmit 1 pixel data with the 16-bits color depth information.
Note 3. ‘-‘ = Don't care - Can be set to VDDI or DGND level
© ORISE Technology Co., Ltd.
Proprietary & Confidential
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Preliminary Version: 0.1
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Preliminary
SPFD54126B
(3). 8-bits data bus for 18-bits/pixel (RGB 6-6-6-bits input), 262K-colours, 3AH=”06h”
There are 1 pixels (3 sub-pixels) per 3-bytes.
RESX
‘1’
IM1, IM0 = ”00”
IM1/IM0
CSX
D/CX
R/WX
‘0’
nd
.co
‘1’
E
0
R1, Bit 5
D6
0
R1, Bit 4
D5
1
D4
0
D3
1
D2
1
D1
0
D0
0
R2, Bit 5
G1, Bit 4
B1, Bit 4
R2, Bit 4
R1, Bit 3
G1, Bit 3
B1, Bit 3
R2, Bit 3
R1, Bit 2
G1, Bit 2
B1, Bit 2
R2, Bit 2
R1, Bit 1
G1, Bit 1
B1, Bit 1
R2, Bit 1
R1, Bit 0
G1, Bit 0
B1, Bit 0
R2, Bit 0
-
-
-
-
-
-
-
-
bt
B1, Bit 5
w
w
w
6800-Series control pins
G1, Bit 5
Pixel n+1
Pixel n
18-bits
Frame
Memory
© ORISE Technology Co., Ltd.
Proprietary & Confidential
8080-Series control pins
.m
D7
re
RDX
m
WRX
141
18-bits
R1 G1 B1 R2 G2 B2 R3 G3 B3
Apr. 25, 2006
Preliminary Version: 0.1
Evaluation Only. Created with Aspose.Pdf.Kit. Copyright 2002-2005 Aspose Pty Ltd
Preliminary
SPFD54126B
7.3.1.2. Parallel 16-Bits Bus Interface for RAM Data Write (IM1, IM0=”01”)
Different display data formats are available for three colors depth supported by listed below.
- 4K-Colours, RGB 4,4,4-bits input data. (3AH=”03h”)
- 65K-Colours, RGB 5,6,5-bits input data. (3AH=”05h”)
- 262K-Colours, RGB 6,6,6-bits input data. (3AH=”06h”)
(1). 16-bits data bus for 12-bits/pixel (RGB 4-4-4-bits input), 4K-colours, 3AH=”03h”
There are 1 pixel (3 sub-pixels) per 1 bytes
RESX ‘1’
m
IM1/IM0 IM1 IM0=”01”
nd
.co
CSX
D/CX
WRX
RDX ‘1’
8080-Series control
R/WX ‘0’
re
6800-Series control
-
-
-
-
-
-
-
-
-
-
-
-
R1 Bit 3
R2 Bit 3
R3 Bit 3
R4 Bit 3
R1 Bit 2
R2 Bit 2
R3 Bit 2
R4 Bit 2
R1 Bit 1
R2 Bit 1
R3 Bit 1
R4 Bit 1
R1 Bit 0
R2 Bit 0
R3 Bit 0
R4 Bit 0
0
G1 Bit 3
G2 Bit 3
G3 Bit 3
G4 Bit 3
D6
0
G1 Bit 2
G2 Bit 2
G3 Bit 2
G4 Bit 2
D5
1
G1 Bit 1
G2 Bit 1
G3 Bit 1
G4 Bit 1
D4
0
G1 Bit 0
G2 Bit 0
G3 Bit 0
G4 Bit 0
D3
1
B1 Bit 3
B2 Bit 3
B3 Bit 3
B4 Bit 3
D2
1
B1 Bit 2
B2 Bit 2
B3 Bit 2
B4 Bit 2
D1
0
B1 Bit 1
B2 Bit 1
B3 Bit 1
B4 Bit 1
D0
0
-
-
D14
-
-
D13
-
-
D12
-
D11
-
D10
-
D9
-
D8
-
D7
w
D15
.m
bt
E
w
w
-
B1 Bit 0
Pixel n
12-bits
B2 Bit 0
Pixel n+1
B3 Bit 0
B4 Bit 0
Pixel n+2
Pixel n+3
12-bits
Look-Up Table for 4K-colors or data mapping (12-Bits to 18-Bits)
18-bits
Frame
Memory
18-bits
R1 G1 B1 R2 G2 B2 R3 G3 B3
Note1. The data order is ad follows, MSB=D15, LSB=D0 and picture data is MSB=Bit 3, LSB=Bit 0 for Red, Green and Blue data.
Note 2.1-times transfer is used to transmit 1 pixel data with the 12-bits color depth information.
Note 3. ‘-‘ = Don't care - Can be set to VDDI or DGND level
© ORISE Technology Co., Ltd.
Proprietary & Confidential
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Preliminary Version: 0.1
Evaluation Only. Created with Aspose.Pdf.Kit. Copyright 2002-2005 Aspose Pty Ltd
Preliminary
SPFD54126B
(2). 16-bits data bus for 16-bits/pixel (RGB 5-6-5-bits input), 65K-colours, 3AH=”05h”
There are 1 pixel (3 sub-pixels) per 1 bytes
RESX
‘1’
IM1, IM0=”01”
IM1/IM0
CSX
D/CX
WRX
‘1’
8080-Series control pins
R/WX
‘0’
6800-Series control pins
m
RDX
-
R1, Bit 4
D14
-
R1, Bit 3
D13
-
R1, Bit 2
D12
-
D11
-
D10
-
D9
-
D8
-
D7
0
R3, Bi
R4, Bit 4
R2, Bit 3
R3, Bit 3
R4, Bit 3
R2, Bit 2
R3, Bit 2
R4, Bit 2
R1, Bit 1
R2, Bit 1
R3, Bit 1
R4, Bit 1
R1, Bit 0
R2, Bit 0
R3, Bit 0
R4, Bit 0
G1, Bit 5
G2, Bit 5
G3, Bit 5
G4, Bit 5
G1, Bit 4
G2, Bit 4
G3, Bit 4
G4, Bit 4
G1, Bit 3
G2, Bit 3
G3, Bit 3
G4, Bit 3
G1, Bit 2
G2, Bit 2
G3, Bit 2
G4, Bit 2
0
G1, Bit 1
G2, Bit 1
G3, Bit 1
G4, Bit 1
D5
1
G1, Bit 0
G2, Bit 0
G3, Bit 0
G4, Bit 0
D4
0
B1, Bit 4
B2, Bit 4
B3, Bit 4
B4, Bit 4
D3
1
B1, Bit 3
B2, Bit 3
B3, Bit 3
B4, Bit 3
D2
1
B1, Bit 2
B2, Bit 2
B3, Bit 2
B4, Bit 2
D1
0
B1, Bit 1
B2, Bit 1
B3, Bit 1
B4, Bit 1
D1
0
bt
w
w
w
D6
re
R2, Bit 4
.m
D15
nd
.co
E
B1, Bit 0
Pixel n
B2, Bit 0
Pixel n+1
16-bits
B4, Bit 0
Pixel n+2
Pixel n+3
16-bits
Look-Up Table for 4K-colors or data mapping (16-Bits to 18-Bits)
18-bits
Frame
Memory
18-bits
R1 G1 B1 R2 G2 B2 R3 G3 B3
Note1. The data order is ad follows, MSB=D15, LSB=D0 and picture data is MSB=Bit 5, LSB=Bit 0 for Green, and MSB=Bit 4, LSB=Bit 0 for
Red and Blue data.
Note 2.1-times transfer is used to transmit 1 pixel data with the 16-bits color depth information.
Note 3. ‘-‘ = Don't care - Can be set to VDDI or DGND level
© ORISE Technology Co., Ltd.
Proprietary & Confidential
143
Apr. 25, 2006
Preliminary Version: 0.1
Evaluation Only. Created with Aspose.Pdf.Kit. Copyright 2002-2005 Aspose Pty Ltd
Preliminary
SPFD54126B
(3). 16-bits data bus for 18-bits/pixel (RGB 6-6-6-bits input), 262K-colours, 3AH=”06h”
There are 2 pixel (6 sub-pixels) per 3 bytes
RESX
‘1’
IM1, IM0=”01”
IM1/IM0
CSX
D/CX
WRX
‘1’
8080-Series control pins
R/WX
‘0’
6800-Series control pins
m
RDX
D15
-
R1, Bit 5
D14
-
R1, Bit 4
D13
-
R1, Bit 3
D12
-
R1, Bit 2
D11
-
R1, Bit 1
D10
-
D9
-
D8
-
D7
0
D6
0
nd
.co
E
G2, Bit 5
R3, Bit 5
B1, Bit 4
G2, Bit 4
R3, Bit 4
B1, Bit 3
G2, Bit 3
R3, Bit 3
B1, Bit 2
G2, Bit 2
R3, Bit 2
B1, Bit 1
G2, Bit 1
R3, Bit 1
R1, Bit 0
B1, Bit 0
G2, Bit 0
R3, Bit 0
-
-
-
-
-
-
-
-
G1, Bit 5
R2, Bit 5
B2, Bit 5
G3, Bit 5
G1, Bit 4
R2, Bit 4
B2, Bit 4
G3, Bit 4
1
G1, Bit 3
R2, Bit 3
B2, Bit 3
G3, Bit 3
D4
0
G1, Bit 2
R2, Bit 2
B2, Bit 2
G3, Bit 2
D3
1
G1, Bit 1
R2, Bit 1
B2, Bit 1
G3, Bit 1
D2
1
G1, Bit 0
R2, Bit 0
B2, Bit 0
G3, Bit 0
D1
0
-
-
-
-
D0
0
-
-
-
-
bt
.m
w
w
w
D5
re
B1, Bit 5
Pixel n
Pixel n+1
18-bits
Frame
Memory
18-bits
R1 G1 B1 R2 G2 B2 R3 G3 B3
Note1. The data order is ad follows, MSB=D15, LSB=D0 and picture data is MSB=Bit 5, LSB=Bit 0 for Red, Green and Blue data.
Note 2.3-times transfer is used to transmit 1 pixel data with the 18-bits color depth information.
Note 3. ‘-‘ = Don't care - Can be set to VDDI or DGND level
© ORISE Technology Co., Ltd.
Proprietary & Confidential
144
Apr. 25, 2006
Preliminary Version: 0.1
Evaluation Only. Created with Aspose.Pdf.Kit. Copyright 2002-2005 Aspose Pty Ltd
Preliminary
SPFD54126B
7.3.1.3. Parallel 9-Bits Bus Interface for RAM Data Write (IM1, IM0=”10”)
Different display data formats are available for three colors depth supported by listed below.
- 262K-Colours, RGB 6,6,6-bits input data. (3AH=”06h”)
(1). 9-bits data bus for 18-bits/pixel (RGB 6-6-6-bits input), 262K-colours, 3AH=”06h”
There is 1 pixel (3 sub-pixels) per 2 bytes
RESX
‘1’
IM1, IM0 = “10”
IM1/IM0
m
CSX
nd
.co
D/CX
RDX
‘1’
R/WX
‘0’
8080-Series control pins
6800-Series control pins
re
WRX
.m
G1, Bit 2
R2, Bit 5
G2, Bit 2
R1, Bit 4
G1, Bit 1
R2, Bit 4
G2, Bit 1
R1, Bit 3
G1, Bit 0
R2, Bit 3
G2, Bit 0
w
bt
E
1
R1, Bit 2
B1, Bit 5
R2, Bit 2
B2, Bit 5
D4
0
R1, Bit 0
B1, Bit 4
R2, Bit 1
B2, Bit 4
D3
1
R1, Bit 0
B1, Bit 3
R2, Bit 0
B2, Bit 3
D2
1
G1, Bit 5
B1, Bit 2
G2, Bit 5
B2, Bit 2
D1
0
G1, Bit 4
B1, Bit 1
G2, Bit 4
B2, Bit 1
D0
0
G1, Bit 3
B1, Bit 0
G2, Bit 3
B2, Bit 0
D7
0
D6
0
D5
R1, Bit 5
w
-
w
D8
Pixel n
Pixel n+1
18-bits
Frame
Memory
18-bits
R1 G1 B1 R2 G2 B2 R3 G3 B3
Note1. The data order is ad follows, MSB=D8, LSB=D0 and picture data is MSB=Bit 5, LSB=Bit 0 for Red, Green and Blue data.
Note 2.3-times transfer is used to transmit 1 pixel data with the 18-bit color depth information.
Note 3. ‘-‘ = Don't care - Can be set to VDDI or DGND level
© ORISE Technology Co., Ltd.
Proprietary & Confidential
145
Apr. 25, 2006
Preliminary Version: 0.1
Evaluation Only. Created with Aspose.Pdf.Kit. Copyright 2002-2005 Aspose Pty Ltd
Preliminary
SPFD54126B
7.3.1.4. Parallel 18-Bits Bus Interface for RAM Data Write (IM1, IM0=”11”)
Different display data formats are available for three colors depth supported by listed below.
- 4K-Colours, RGB 4,4,4-bits input data. (3AH=”03h”)
- 65K-Colours, RGB 5,6,5-bits input data. (3AH=”05h”)
- 262K-Colours, RGB 6,6,6-bits input data. (3AH=”06h”)
(1). 18-bits data bus for 12-bits/pixel (RGB 4-4-4-bits input), 4K-colours, 3AH=”03h”
There is 1 pixel (3 sub-pixels) per 1 bytes
RESX ‘1’
IM1/IM0 IM1 IM0=”11”
m
CSX
nd
.co
D/CX
WRX
RDX ‘1’
8080-Series control
R/WX ‘0’
6800-Series control
D17
-
-
D16
-
-
D12
-
re
E
-
-
-
-
-
-
-
-
-
R1 Bit
R2 Bit
R3 Bit
R4 Bit
R1 Bit
R2 Bit
R3 Bit
R4 Bit
R1 Bit
R2 Bit
R3 Bit
R4 Bit
R1 Bit
R2 Bit
R3 Bit
R4 Bit
w
.m
bt
-
-
D9
-
D8
-
D7
0
G1 Bit
G2 Bit
G3 Bit
G4 Bit
D6
0
G1 Bit
G2 Bit
G3 Bit
G4 Bit
D5
1
G1 Bit
G2 Bit
G3 Bit
G4 Bit
D4
0
G1 Bit
G2 Bit
G3 Bit
G4 Bit
D3
1
B1 Bit
B2 Bit
B3 Bit
B4 Bit
D2
1
B1 Bit
B2 Bit
B3 Bit
B4 Bit
D1
0
B1 Bit
B2 Bit
B3 Bit
B4 Bit
D0
0
w
w
D11
D10
B1 Bit
Pixel n
12-bits
B2 Bit
Pixel n+1
B3 Bit
Pixel n+2
B4 Bit
Pixel n+3
12-bits
Look-Up Table for 4K-colors or data mapping (12-Bits to 18-Bits)
18-bits
18-bits
Frame
Memory R1 G1 B1 R2 G2 B2 R3 G3 B3
Note1. The data order is ad follows, MSB=D17, LSB=D0 and picture data is MSB=Bit 3, LSB=Bit 0 for Red, Green and Blue data.
Note 2.1-times transfer is used to transmit 1 pixel data with the 12-bits color depth information.
Note 3. ‘-‘ = Don't care - Can be set to VDDI or DGND level
© ORISE Technology Co., Ltd.
Proprietary & Confidential
146
Apr. 25, 2006
Preliminary Version: 0.1
Evaluation Only. Created with Aspose.Pdf.Kit. Copyright 2002-2005 Aspose Pty Ltd
Preliminary
SPFD54126B
(2). 18-bits data bus for 16-bits/pixel (RGB 5-6-5-bits input), 65K-colours, 3AH=”05h”
There are 1 pixel (3 sub-pixels) per 1 bytes
RESX
‘1’
IM1, IM0=”11”
IM1/IM0
CSX
D/CX
WRX
‘1’
8080-Series control pins
R/WX
‘0’
6800-Series control pins
m
RDX
-
-
D16
-
-
D15
-
R1, Bit 4
D14
-
R1, Bit 3
D13
-
D12
-
D11
-
D10
-
D9
-
D8
-
-
-
-
-
-
R2, Bit 4
R3, Bi
R4, Bit 4
R2, Bit 3
R3, Bit 3
R4, Bit 3
R1, Bit 2
R2, Bit 2
R3, Bit 2
R4, Bit 2
R1, Bit 1
R2, Bit 1
R3, Bit 1
R4, Bit 1
R1, Bit 0
R2, Bit 0
R3, Bit 0
R4, Bit 0
G1, Bit 5
G2, Bit 5
G3, Bit 5
G4, Bit 5
G1, Bit 4
G2, Bit 4
G3, Bit 4
G4, Bit 4
G1, Bit 3
G2, Bit 3
G3, Bit 3
G4, Bit 3
0
G1, Bit 2
G2, Bit 2
G3, Bit 2
G4, Bit 2
D6
0
G1, Bit 1
G2, Bit 1
G3, Bit 1
G4, Bit 1
D5
1
G1, Bit 0
G2, Bit 0
G3, Bit 0
G4, Bit 0
D4
0
B1, Bit 4
B2, Bit 4
B3, Bit 4
B4, Bit 4
D3
1
B1, Bit 3
B2, Bit 3
B3, Bit 3
B4, Bit 3
D2
1
B1, Bit 2
B2, Bit 2
B3, Bit 2
B4, Bit 2
D1
0
B1, Bit 1
B2, Bit 1
B3, Bit 1
B4, Bit 1
D0
0
bt
w
w
w
D7
re
-
.m
D17
nd
.co
E
B1, Bit 0
B2, Bit 0
Pixel n
Pixel n
16-bits
B1, Bit 0
Pixel n
B4, Bit 0
Pixel n
16-bits
Look-Up Table for 65K-colors or data mapping (16-Bits to 18-Bits)
18-bits
Frame
Memory
18-bits
R1 G1 B1 R2 G2 B2 R3 G3 B3
Note1. The data order is ad follows, MSB=D17, LSB=D0 and picture data is MSB=Bit 5, LSB=Bit 0 for Green, and MSB=Bit 4, LSB=Bit 0 for
Red and Blue data.
Note 2.1-times transfer is used to transmit 1 pixel data with the 16-bits color depth information.
Note 3. ‘-‘ = Don't care - Can be set to VDDI or DGND level
© ORISE Technology Co., Ltd.
Proprietary & Confidential
147
Apr. 25, 2006
Preliminary Version: 0.1
Evaluation Only. Created with Aspose.Pdf.Kit. Copyright 2002-2005 Aspose Pty Ltd
Preliminary
SPFD54126B
(3). 18-bits data bus for 18-bits/pixel (RGB 6-6-6-bits input), 262K-colours, 3AH=”06h”
There are 1 pixel (6 sub-pixels) per 1 bytes
RESX
‘1’
IM1, IM0=”11”
IM1/IM0
CSX
D/CX
WRX
‘1’
8080-Series control pins
R/WX
‘0’
6800-Series control pins
m
RDX
R1, Bit 5
D16
-
R1, Bit 4
D15
-
R1, Bit 3
D14
-
R1, Bit 2
D13
-
D12
-
D11
-
D10
-
D9
R3, Bit5
R4, Bit 5
R2, Bit 4
R3, Bit5
R4, Bit 4
R3, Bit 3
R4, Bit 3
R2, Bit 2
R3, Bit 2
R4, Bit 2
R1, Bit 1
R2, Bit 1
R3, Bit 1
R4, Bit 1
R1, Bit 0
R2, Bit 0
R3, Bit 0
R4, Bit 0
G1, Bit 5
G2, Bit 5
G3, Bit 5
G4, Bit 5
G1, Bit 4
G2, Bit 4
G3, Bit 4
G4, Bit 4
-
G1, Bit 3
G2, Bit 3
G3, Bit 3
G4, Bit 3
D8
-
G1, Bit 2
G2, Bit 2
G3, Bit 2
G4, Bit 2
D7
0
G1, Bit 1
G2, Bit 1
G3, Bit 1
G4, Bit 1
D6
0
G1, Bit 0
G2, Bit 0
G3, Bit 0
G4, Bit 0
D5
1
B1, Bit 5
B2, Bit 5
B3, Bit 5
B4, Bit 5
D4
0
B1, Bit 4
B2, Bit 4
B3, Bit 4
B4, Bit 4
D3
1
B1, Bit 3
B2, Bit 3
B3, Bit 3
B4, Bit 3
D2
1
B1, Bit 2
B2, Bit 2
B3, Bit 2
B4, Bit 2
D1
0
B1, Bit 1
Pixel
n
B2, Bit 1
Pixel
n+1
B3, Bit 1
Pixel
n+2
B4, Bit 1
Pixel
n+3
D0
0
B1, Bit 0
B2, Bit 0
B1, Bit 0
B4, Bit 0
re
R2, Bit 5
.m
-
w
D17
nd
.co
E
w
w
bt
R2, Bit 3
18-bits
Frame
Memory
18-bits
R1 G1 B1 R2 G2 B2 R3 G3 B3
Note1. The data order is ad follows, MSB=D17, LSB=D0 and picture data is MSB=Bit 5, LSB=Bit 0 for Red, Green and Blue data.
Note 2.1-times transfer is used to transmit 1 pixel data with the 18-bits color depth information.
Note 3. ‘-‘ = Don't care - Can be set to VDDI or DGND level
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Preliminary
SPFD54126B
7.3.2.
MCU Data Colour Coding for RAM data Read
- Parallel 8-Bits Bus Interface (IM1, IM0= “00”)
Table 7.3.2.1 8-Bits Parallel Interface Set Table
Register
D17 D16 D15 D14 D13 D12 D11 D10
Command
x
x
x
x
x
x
x
x
D17 D16 D15 D14 D13 D12 D11 D10
x
x
x
x
x
x
x
x
Read
Data Format
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
D9
x
D9
x
x
x
D8
x
D8
x
x
x
D7
0
D7
R5
G5
B5
D6
0
D6
R4
G4
B4
D5
1
D5
R3
G3
B3
D4
0
D4
R2
G2
B2
D9
x
D9
x
x
x
D8
x
D8
x
x
x
D7
0
D7
G5
R5
B5
D6
0
D6
G4
R4
B4
D5
1
D5
G3
R3
B3
D4
0
D4
G2
R2
B2
D3
1
D3
R1
G1
B1
D2
1
D2
R0
G0
B0
D1
1
D1
x
x
x
D0
0
D0
x
x
x
D3
1
D3
G1
R1
B1
D2
1
D2
G0
R0
B0
D1
1
D1
x
x
x
D0
0
D0
x
x
x
Command
2EH
Colour
262K-Colour
(1-pixels/ 3byyes)
nd
.co
Command
2EH
Colour
262K-Colour
(2-pixels/ 3byyes)
bt
re
Table 7.3.2.2 16-Bits Parallel Interface Set Table
Register
D17 D16 D15 D14 D13 D12 D11 D10
Command
x
x
x
x
x
x
x
x
D17 D16 D15 D14 D13 D12 D11 D10
x
x
R5 R4 R3 R2 R1 R0
Read
Data Format
x
x
B5 B4 B3 B2 B1 B0
x
x
G5 G4 G3 G2 G1 G0
m
- Parallel 16-Bits Bus Interface (IM1, IM0= “01”)
- Parallel 9-Bits Parallel Interface (IM1, IM0= “10”)
D9
x
D9
x
x
D8
x
D8
R5
G2
D7
0
D7
R4
G1
D6
0
D6
R3
G0
D5
1
D5
R2
B5
D4
0
D4
R1
B4
D3
1
D3
R0
B3
D2
1
D2
G5
B2
D1
1
D1
G4
B1
D0
0
D0
G3
B0
Register
2EH
Colour
262K-Colour
(1-pixels/ 2bytes)
D8
x
D7
0
D6
0
D5
1
D4
0
D3
1
D2
1
D1
1
D0
0
Register
2EH
G2
G1
G0
B5
B4
B3
B2
B1
B0
262K-Colour
w
w
w
.m
Table 7.3.2.3 9-Bits Parallel Interface Set Table
Register
D17 D16 D15 D14 D13 D12 D11 D10
Command
x
x
x
x
x
x
x
x
D17 D16 D15 D14 D13 D12 D11 D10
Read
x
x
x
x
x
x
x
x
Data Format
x
x
x
x
x
x
x
x
- Parallel 18-Bits Parallel Interface (IM1, IM0= “11”)
Table 7.3.2.4 18-Bits Parallel Interface Set Table
Register
D17 D16 D15 D14 D13 D12 D11 D10 D9
Command
x
x
x
x
x
x
x
x
x
Read
R5 R4 R3 R2 R1 R0 G5 G4 G3
Data Format
Note . ‘x’ Don’t care, but need to set VDDI or DGND level.
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Preliminary
SPFD54126B
7.3.2.1. Parallel 8-Bits Bus Interface for RAM Data Read (IM1, IM0= “00”)
There are 1 pixels (3 sub-pixels) per 3-bytes. (RGB 6-6-6-bits output)
RESX
‘1’
IM1, IM0 = ”00”
IM1/IM0
CSX
D/CX
RDX
WRX
m
‘0’
8080-Series control pins
‘1’
nd
.co
R/WX
‘1’
D7
0
---
D6
0
---
D5
1
---
D4
0
---
D3
1
D2
1
.m
E
D1
1
D0
0
B1, Bit 5
R1, Bit 4
G1, Bit 4
B1, Bit 4
R1, Bit 3
G1, Bit 3
B1, Bit 3
R1, Bit 2
G1, Bit 2
B1, Bit 2
---
R1, Bit 1
G1, Bit 1
B1, Bit 1
---
R1, Bit 0
G1, Bit 0
B1, Bit 0
---
-
-
-
---
-
-
-
Dummy Pixel
Pixel n
bt
re
G1, Bit 5
w
R1, Bit 5
w
w
6800-Series control pins
18-bits
Frame
Memory
R1 G1 B1 R2 G2 B2 R3 G3 B3
Note1. The data order is ad follows, MSB=D7, LSB=D0 and picture data is MSB=Bit 5, LSB=Bit 0 for Red, Green and Blue data.
Note 2.3-times transfer is used to transmit 1 pixel data with the 18-bits color depth information.
Note 3. ‘-‘ = Don't care - Can be set to VDDI or DGND level
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Preliminary
SPFD54126B
7.3.2.2. Parallel 16-Bits Bus Interface for RAM Data Read (IM1, IM0= “01”)
There are 2 pixel (6 sub-pixels) per 3 bytes (RGB 6-6-6-bits output)
RESX
‘1’
IM1, IM0 = ”01”
IM1/IM0
CSX
D/CX
RDX
WRX
m
‘0’
8080-Series control pins
‘1’
nd
.co
R/WX
‘1’
E
D15
-
---
D14
-
---
D13
-
---
D12
-
D11
-
D10
-
D9
-
D8
-
D7
0
6800-Series control pins
B1, Bit 5
G2, Bit 5
R1, Bit 4
B1, Bit 4
G2, Bit 4
R1, Bit 3
B1, Bit 3
G2, Bit 3
---
R1, Bit 2
B1, Bit 2
G2, Bit 2
---
R1, Bit 1
B1, Bit 1
G2, Bit 1
---
R1, Bit 0
B1, Bit 0
G2, Bit 0
---
-
-
-
---
-
-
-
---
G1, Bit 5
R2, Bit 5
B2, Bit 5
0
---
G1, Bit 4
R2, Bit 4
B2, Bit 4
D5
1
---
G1, Bit 3
R2, Bit 3
B2, Bit 3
D4
0
---
G1, Bit 2
R2, Bit 2
B2, Bit 2
D3
1
---
G1, Bit 1
R2, Bit 1
B2, Bit 1
D2
1
---
G1, Bit 0
R2, Bit 0
B2, Bit 0
D1
1
---
-
-
-
D0
0
---
-
-
-
bt
.m
w
w
w
D6
re
R1, Bit 5
Dummy Pixel
Pixel n
Pixel n+1
18-bits
Frame
Memory
18-bits
R1 G1 B1 R2 G2 B2 R3 G3 B3
Note1. The data order is ad follows, MSB=D15, LSB=D0 and picture data is MSB=Bit 5, LSB=Bit 0 for Red, Green and Blue data.
Note 2.3-times transfer is used to transmit 1 pixel data with the 18-bits color depth information.
Note 3. ‘-‘ = Don't care - Can be set to VDDI or DGND level
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Preliminary
SPFD54126B
7.3.2.3. Parallel 9-Bits Bus Interface for RAM Data Read (IM1, IM0= “10”)
There are 1 pixel (3 sub-pixels) per 2 bytes (RGB 6-6-6-bits output)
RESX
‘1’
IM1, IM0 = ”10”
IM1/IM0
CSX
D/CX
RDX
WRX
m
‘0’
8080-Series control pins
‘1’
nd
.co
R/WX
‘1’
E
-
---
D7
0
---
D6
0
---
D5
1
---
D4
0
---
D3
1
D2
1
D1
1
D0
0
R2, Bit 5
R1, Bit 4
G1, Bit 1
R2, Bit 4
G1, Bit 0
R2, Bit 3
R1, Bit 2
B1, Bit 5
R2, Bit 2
R1, Bit 0
B1, Bit 4
R2, Bit 1
---
R1, Bit 0
B1, Bit 3
R2, Bit 0
---
G1, Bit 5
B1, Bit 2
G2, Bit 5
---
G1, Bit 4
B1, Bit 1
G2, Bit 4
---
G1, Bit 3
B1, Bit 0
G2, Bit 3
w
w
re
G1, Bit 2
w
R1, Bit 5
.m
D8
6800-Series control pins
bt
R1, Bit 3
Dummy Pixel
Pixel n
Pixel n+1
18-bits
Frame
Memory
18-bits
R1 G1 B1 R2 G2 B2 R3 G3 B3
Note1. The data order is ad follows, MSB=D8, LSB=D0 and picture data is MSB=Bit 5, LSB=Bit 0 for Red, Green and Blue data.
Note 2.3-times transfer is used to transmit 1 pixel data with the 18-bit color depth information.
Note 3. ‘-‘ = Don't care - Can be set to VDDI or DGND level
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Preliminary
SPFD54126B
7.3.2.4. Parallel 18-Bits Bus Interface for RAM Data Read (IM1, IM0= “11”)
There are 1 pixel (3 sub-pixels) per 1 bytes (RGB 6-6-6-bits output)
RESX
‘1’
IM1, IM0 = ”11”
IM1/IM0
CSX
D/CX
RDX
WRX
m
‘0’
‘1’
nd
.co
R/WX
‘1’
E
-
---
D16
-
---
D15
-
---
D14
-
---
D13
-
D12
-
D11
-
D10
-
D9
6800-Series control pins
R2, Bit 5
R3, Bit5
R1, Bit 4
R2, Bit 4
R3, Bit5
R1, Bit 3
R2, Bit 3
R3, Bit 3
R1, Bit 2
R2, Bit 2
R3, Bit 2
---
R1, Bit 1
R2, Bit 1
R3, Bit 1
---
R1, Bit 0
R2, Bit 0
R3, Bit 0
--
G1, Bit 5
G2, Bit 5
G3, Bit 5
---
G1, Bit 4
G2, Bit 4
G3, Bit 4
-
---
G1, Bit 3
G2, Bit 3
G3, Bit 3
D8
-
---
G1, Bit 2
G2, Bit 2
G3, Bit 2
D7
0
---
G1, Bit 1
G2, Bit 1
G3, Bit 1
D6
0
--
G1, Bit 0
G2, Bit 0
G3, Bit 0
D5
1
---
B1, Bit 5
B2, Bit 5
B3, Bit 5
D4
0
---
B1, Bit 4
B2, Bit 4
B3, Bit 4
D3
1
---
B1, Bit 3
B2, Bit 3
B3, Bit 3
D2
1
---
B1, Bit 2
B2, Bit 2
B3, Bit 2
D1
1
---
B1, Bit 1
B2, Bit 1
B3, Bit 1
D0
0
w
w
.m
bt
re
R1, Bit 5
w
D17
8080-Series control pins
---
B1, Bit 0
Dummy Pixel
Pixel n
B2, Bit 0
Pixel n+1
18-bits
Frame
Memory
B1, Bit 0
Pixel n+2
18-bits
R1 G1 B1 R2 G2 B2 R3 G3 B3
Note1. The data order is ad follows, MSB=D17, LSB=D0 and picture data is MSB=Bit 5, LSB=Bit 0 for Red, Green and Blue data.
Note 2.1-times transfer is used to transmit 1 pixel data with the 18-bits color depth information.
Note 3. ‘-‘ = Don't care - Can be set to VDDI or DGND level
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Preliminary
SPFD54126B
7.3.3.
Serial Interface (IM2 = ‘0’)
Different display data formats are available for three colors depth supported by the LCM listed below.
- 4K-Colours, RGB 4,4,4-bits input data. (3AH=”03h”)
- 65K-Colours, RGB 5,6,5-bits input data. (3AH=”05h”)
- 262K-Colours, RGB 6,6,6-bits input data. (3AH=”06h”)
7.3.3.1. Write data for 12-bits/pixel (RGB 4-4-4-bits input), 4K-colours, 3AH=”03h”
IM2
‘0’
IM1,IM0= “xx”
m
‘1’
CSX
Pixel n
D8
SDA
1
D7
D6
D5
D4
D3
D2
nd
.co
RESX
Pixel n+1
D1
D0
D8
R13 R12 R11 R10 G13 G12 G11 G10
1
D7
D6
D0
D8
B13 B12 B11 B10 R23 R22 R21 R20
1
D4
D3
D2
D1
D7
D6
D5
D4
D3
D2
D1
D0
G23 G22 G21 G20 B23 B22 B21 B20
re
SCL
D5
12-bits
12-bits
bt
Look-Up Table for 4K-colors mapping (12-Bits to 18-Bits)
.m
18-bits
R1 G1 B1 R2 G2 B2 R3 G3 B3
w
w
w
Frame
Memory
18-bits
Note 1. pixel data with the 12-bits color depth information
Note 2. The most significant bits are: Rx3, Gx3 and Bx3
Note 3. The least significant bits are: Rx0, Gx0 and Bx0
Note 4. ‘-‘ = Don't care - Can be set to VDDI or DGND level
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Preliminary
SPFD54126B
7.3.3.2. Write data for 16-bits/pixel (RGB 5-6-5-bits input), 65K-colours, 3AH=”05h”
RESX
‘1’
IM2
‘0’
IM1,IM0= “xx”
CSX
Pixel n
D8
SDA
1
D7
D6
D5
D4
D3
D2
D1
D0
D8
R14 R13 R12 R11 R10 G15 G14 G13
1
Pixel n+1
D7
D6
D5
D4
D3
D2
D1
D0
D8
G12 G11 G10 B14 B13 B12 B11 B10
1
D7
D6
D5
D4
D3
D2
D1
D0
R24 R23 R22 R21 R20 G25 G24 G23
SCL
m
16-bits
nd
.co
Look-Up Table for 65k-colors mapping (16-Bits to 18-Bits)
18-bits
Frame
Memory
bt
re
R1 G1 B1 R2 G2 B2 R3 G3 B3
Note 1. pixel data with the 16-bits color depth information
.m
Note 2. The most significant bits are: Rx4, Gx5 and Bx4
Note 3. The least significant bits are: Rx0, Gx0 and Bx0
w
w
Note 4. ‘-‘ = Don't care - Can be set to VDDI or DGND level
RESX
‘1’
IM2
‘0’
w
7.3.3.3. Write data for 18-bits/pixel (RGB 6-6-6-bits input), 262K-colours, 3AH=”06h”
IM1,IM0= “xx”
CSX
Pixel n
D8
SDA
1
D7
D6
D5
D4
D3
D2
R15 R14 R13 R12 R11 R10
D1
D0
D8
-
-
1
D7
D6
D5
D4
D3
D2
G15 G14 G13 G12 G11 G10
D1
D0
D8
-
-
1
D7
D6
D5
D4
D3
D2
B15 B14 B13 B12 B11 B10
D1
D0
-
-
SCL
18-bits
Frame
Memory
R1 G1 B1 R2 G2 B2 R3 G3 B3
Note 1. pixel data with the 18-bits color depth information
Note 2. The most significant bits are: Rx5, Gx5 and Bx5
Note 3. The least significant bits are: Rx0, Gx0 and Bx0
Note 4. ‘-‘ = Don't care - Can be set to VDDI or DGND level
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Preliminary
SPFD54126B
Host
7.3.3.4. Read data for Serial Interface (RGB 6-6-6-bits output)
RESX
‘1’
IM2
‘0’
IM1,IM0= “xx”
CSX
(SPI CSX)
SCL
Driver
SDA
SDA
-
High-Z
R2Eh
0
High-Z
-
D23 D22 D21 D20 D19 D18 D17 D16
D1
D0 D23 D22 D21 D20 D19
1-Pixel data
Read Data format as below
nd
.co
m
9 Dummy Clock
D2
D23 D22 D21 D20 D19 D18 D17 D16 D15 D14 D13 D12 D11 D10 D9
-
-
G15 G14 G13 G12 G11 G10
-
D8
-
D7
D6
D5
D4
D3
D2
B15 B14 B13 B12 B11 B10
D1
D0
-
-
.m
bt
re
R15 R14 R13 R12 R11 R10
w
w
w
Note: ‘-‘ = Don't care - Can be set to VDDI or DGND level
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Preliminary
SPFD54126B
7.4.
RGB interface
7.4.1.
General Description
The module uses 6, 16 and 18-bits parallel RGB interface which includes: VS, HS, DE, PCLK, D[17:0]. The interface is activated after
Power On sequence.
Pixel clock (PCLK) is running all the time without stoping and it is used to entering VS, HS, DE and D[17:0] states when there is a rising
edge of the PCLK. The PCLK cannot be used as continues internal clock for other functions of the display module e.g. Sleep In –mode etc.
Vertical synchronization (VS) is used to tell when there is received a new frame of the display. This is negative (‘0’, low) active and its state
is read to the display module by a rising edge of he PCLK signal.
Horizontal synchronization (HS) is used to tell when there is received a new line of the frame. This is negative (‘0’, low) active and its state
is read to the display module by a rising edge of the PCLK signal.
Data Enable (DE) is used to tell when there is received a RGB information that should be transferred on the display. This is a positive (‘1’,
high) active and its state is read to the display module by a rising edge of the PCLK signal.
nd
.co
m
D[17:0] (18-bit: R5-R0, G5-G0 and B5-B0; 16-bit: R4-R0, G5-G0 and B4-B0) are used to tell what is the information of the image that is
transferred on the display (When DE=’1’ and there is a rising edge of PCLK). D[17:0] can be ‘0’ (low) or ‘1’ (high). These lines are read by a
rising edge of the PCLK signal.
re
The PCLK cycle is described in the following figure.
bt
PCLK
w
.m
VS, HS, DE
D[17:0]
The driver read the D[17:0], VS,
HS and DE lines when there is a
falling edge of the PCLK
w
w
The host changes D[17:0], VS,
HS and DE lines when there is a
falling edge of the PCLK
Fig. 7.4.1 PCLK cycle
Note: PCLK is an unsynchronized signal (It can be stopped).
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Preliminary
SPFD54126B
7.4.2.
General Timing Diagram
Vertical Sync.
0 1
VS
Invisible Image
= Timing information what is not possible to see on the display
= Blanking Time
VBP
DE = ‘0’ (Low)
VP
m
Visible Image
= Image which can see on the display
= Active
DE = ‘1’ (high)
re
nd
.co
HDISP
1
0
w
Horizontal Sync.
.m
bt
VFP
HBP
HDISP
w
HPW
HFP
w
HP
Fig. 7.4.2 RGB General Timing diagram
The image information must be correct on the display, when the timings are in range on the interface.
However, the image information can be incorrect on the display, when timings are not out of range on the interface (Out of the range timings
cannot on the host side). The correct image information must be displayed automatically (by the display module) on the next frame (vertical
sync.) when there is returned from out of the range to in range interface timing.
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Preliminary
SPFD54126B
7.4.3.
Updating Order on Display Active Area (Normal Display Mode On + Sleep Out)
There is defined different kind of updating orders for display. These updating orders are controlled by H/W (SMX, SMY) and S/W (MX, MY,)
bits.
Physical
(0,0)
Point
Physical
(0,0)
Point
Active areaa on the LCD
Active area on the LCD
Start Point
(0,0)
m
Vertical
Active counter (0-219)
Vertical
Active counter (0-219)
End Point
(175,219)
End Point
(175,219)
Horizontal
Active counter (0-175)
bt
re
Horizontal
Active counter (0-175)
nd
.co
Start Point
(0,0)
Fig. 7.4.3.2 Updating order when MADCTL’s
MX=’1’ and MY = ‘0’
w
w
.m
Fig. 7.4.3.1 Updating order when MADCTL’s
MX=’0’ and MY = ‘0’
Physical
(0,0)
Point
w
Physical
(0,0)
Point
Active area on the LCD
End Point
(175,219)
Active area on the LCD
Vertical
Active counter (0-219)
Vertical
Active counter (0-219)
Start Point
(0,0)
End Point
(0,0)
Start Point
(175,219)
Horizontal
Active counter (0-175)
Horizontal
Active counter (0-175)
Fig. 7.4.3.3 Updating order when MADCTL’s
MX=’0’ and MY = ‘1’
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Fig. 7.4.3.4 Updating order when MADCTL’s
MX=’1’ and MY = ‘1’
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Table 7.4.3.1 Rules for Updating Order
Horizontal
Counter
Return to 0
Increment by 1
Return to 0
Return to 0
Condition
An active VS signal is received
Signal Pixel information of the active area is received
An active HS signal between two active area lines
The Horizontal counter is larger than 127 and the Vertical counter is larger than 159
Vertical
Counter
Return to 0
No change
Increment by 1
Return to 0
Note 1. Pixel order is RGB on the display.
Note 2. Data streaming direction from the host to the display is described in the following figure.
B
Data Stream from RGB I/F is like in this figure
m
ORISE
nd
.co
E
w
w
w
.m
bt
re
Fig. 7.4.3.5 Data streaming order from RGB I/F
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Preliminary
SPFD54126B
7.4.4.
RGB Interface Bus Width set
All 4-kinds of bus width can be available during RGB interface mode (selected by COLMOD (3Ah) command for 8-bits, 16-bits and 18-bits
data width)
Table 7.4.4.1 RGB interface Bus Width Set Table
VIPF[3:0] D17 D16 D15 D14 D13 D12 D11 D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
Bus width
16-bits
data
18-bits
data
Bus width
0101
R4
R3
R2
R1
R0
x
G5
G4
G3
G2
G1
G0
B4
B3
B2
B1
B0
x
0110
R5
R4
R3
R2
R1
R0
G5
G4
G3
G2
G1
G0
B5
B4
B3
B2
B1
B0
D17 D16 D15 D14 D13 D12 D11 D10
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
D9
x
x
x
D8
x
x
x
D7
R5
G5
B5
D6
R4
G4
B4
D5
R3
G3
B3
D4
R2
G2
B2
D3
R1
G1
B1
D2
R0
G0
B0
D1
x
x
x
D0
x
x 6-bits data
x
VIPF[3:0]
1110
Note 2: Only VIPF[3:0]= ”0101”,”0110” and “1110” are valid on RGB I/F, Others are invalid.
7.4.5.
nd
.co
Note 3. ‘x’ Don’t care, but need to set VDDI or DGND level.
RGB Interface Mode Set
VS
HS
RGB Mode 1
RGB Mode 2
Used
Used
Used
Used
Used
Used
Used
Used
Video Data bus
D[17:0]
Used
Used
bt
DE
Register for Blanking
Porch setting
Not Used
Used
Reference clock for
Display
Internal Oscillator
Internal Oscillator
.m
PCLK
re
Table 7.4.5.1 RGB Interface Mode Set
RGB I/F Mode
m
Note 1: When VIPF[3:0]=”1110”, 6-bits data width of 3-times transfer is used to transmit 1 pixel data with the 18-bits color depth information.
w
w
There are 2-kinds of RGB mode which is selected by RCM1 & RCM0 hardware pins.
w
In RGB Mode 1 (RCM1, RCM0 = “10”), writing data to frame memory is done by PCLK and Video Data Bus (D[17:0]), when DE is high
state. The external synchronization signals (PCLK, VS and HS) are used for internal display signals. So, controller (host) must always
transfer PCLK, VS, HS and DE signals to SPFD54126B.
In RGB Mode 2 (RCM1, RCM0 = “11”), blanking porch setting of VS and HS signals are defined by RGBBPCTR (B5h) command. When DE
pin is high, valid data is directly stored to frame memory.
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SPFD54126B
7.4.6.
RGB Interface Timing Diagram
7.4.6.1. General Timings for RGB I/F
TVSST
TVSST
VIH
TVSHT
THSST
VIH
THSHT
VIL
TPCLKCYC
PCLK
TPCLKHT
TPCLKLT
VIH
VIL
TDST/TDEST
D[17:0]
DE
VIH
VIL
TDHT/TDEHT
m
HS
VIL
nd
.co
VS
Table 7.4.6.1.1 General Timing for RGB I/F
.m
Condition
Min
Specification
Type.
15
15
15
15
15
15
15
15
15
15
w
TPCLKLT
TPCLKHT
TVSST
TVSSHT
THSST
TVSSHT
TDEST
TDEHT
TDST
TDHT
w
Pixel low pulse width
Pixel high pulse width
Vertical Sync. set-up time
Vertical Sync. hold time
Horizontal Sync. set-up time
Horizontal Sync. hold time
Data Enable set-up time
Data Enable hold time
Data set-up time
Data hold time
Symbol
w
Item
bt
re
Fig. 7.4.6.1.1 General Timing for RGB I/F
Max
Unit
ns
ns
ns
ns
Note 1: VDDI=1.6 to 3.6V, VDD=2.6 to 3.5V, AGND=DGND=0V, Ta=-30 to 70℃ (to +85℃ no damage)
Note 2: The input signal rise time and fall time (tr, tf) is specified at 15 ns or less.
Note 3. Data lines can be set to “High” or “Low” during blanking time – Don’t care.
Note 4. Logic high and low levels are specified as 30% and 70% of VDDI for Input signals.
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SPFD54126B
N Frame
VS
N+1 Frame
N+2 Frame
HS
PCLK
DE *
DE **
Don’t care
Frame data
Frame data
Updating from
SDA
Frame data
Updating from
Data bus
nd
.co
m
Data Bus
Data transfer (ICM=’0’)
re
RAM write command (2Ch)
Address set command (2Ah), (2Bh)
DE* : RGB Mode 1
DE** : RGB Mode 2
bt
Data transfer (ICM=’1’)
w
w
w
.m
Fig. 7.4.6.1.2 RAM Access via SPI Interface in RGB Mode
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Preliminary
SPFD54126B
7.4.6.2. RGB Interface Mode 1 Timing Diagram
1-Frame (TVP)
V Back Porch (TVS+TVBP)
VS
V Front Porch (TVFP)
HS
m
DE
nd
.co
1-Line (THP)
H Back Porch (THS+THBP)
HS
Valid data area (THDISP)
re
PCLK
© ORISE Technology Co., Ltd.
Proprietary & Confidential
.m
D1 D2 D3 D4 D5
In-Valid
In-Valid
Dn
Dn
D1 D2 D3 D4 D5
w
w
RAM WEN
In-Valid
w
Latch data
bt
DE
Data Bus
H Front Porch (THFP)
Fig. 7.4.6.2.1 RGB Mode 1 Timing Diagram
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SPFD54126B
Vertical Timing for RGB I/F
VS
TVFP
D
[17:0]
TVS
TVBP
TVFP
Note 3
Note 3
TVBL
TDSIP
DE
TVP
m
HS
nd
.co
Horizontal Timing for RGB I/F
HS
THFP
THS
THBP
THDSIP
DE
re
THBL
D
[17:0]
THFP
bt
Note 3
TPCLK
Note 3
.m
THP
PCLK
w
w
w
Fig. 7.4.6.2.2 Vertical and Horizontal timing for RGB I/F
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SPFD54126B
Table 7.4.6.2.1 Vertical and Horizontal Timing for RGB I/F
Item
Symbol
Condition
Vertical cycle period
TVP
GM=”00”
GM=”01”
GM=”11”
Vertical low pulse width
Vertical front porch
Vertical back porch
Vertical data start line
Vertical blanking period
TVS
TVFP
TVBP
Min
Specification
Type.
Max
Unit
Vertical Timing
TVS + TVBP
TVS + TVBP + TVFP
GM=”00”
GM=”01”
GM=”11”
Frame rate
Vertical active area
TVDISP
Vertical refresh rate
Horizontal Timing
Horizontal cycle period
Horizontal low pulse width
Horizontal front porch
Horizontal back porch
TVRR
THS + THBP
ffHS + fHBP
re
GM=”00”
TVRR=65Hz
GM=”01”
TVRR=65Hz
GM=”10”
TVRR=65Hz
bt
THBL
THDISP
TPCLKCYC
fPCLKCYC
TPCLKCYC
fPCLKCYC
TPCLKCYC
fPCLKCYC
100
2.82
100
2.27
100
1.72
HS
HS
HS
HS
HS
HS
HS
HS
68.25
Hz
512
256
256
256
256
PCLK
PCLK
PCLK
PCLK
PCLK
µs
PCLK
PCLK
ns
MHz
ns
MHz
ns
MHz
256
176
355
10
440
10
581
10
w
w
w
.m
Pixel clock cycle
220
176
132
65
208
2
2
2
30
1.0
32
nd
.co
THP
THS
THFP
THBP
Horizontal data start point
Horizontal blanking period
Horizontal active area
61.75
230
186
183
4
4
4
8
12
m
TVBL
226
182
179
2
2
2
4
6
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Preliminary
SPFD54126B
7.4.6.3. RGB Interface Mode 2 Timing Diagram
1-Frame (TVP)
V Back Porch (TVS+TVBP)
VS
V Front Porch (TVFP)
HS
DE
m
1-Line (THP)
nd
.co
H Back Porch (THS+THBP)
HS
Valid data area (THDISP)
re
PCLK
DE
Latch data
bt
In-Valid
D1 D2 D3 D4 D5
.m
Data Bus
H Front Porch (THFP)
In-Valid
Dn
D1 D2 D3 D4 D5
w
RAM WEN
In-Valid
Dn
w
w
Fig. 7.4.6.3.1 RGB Mode 2 Timing Diagram
1-Frame (TVP = 224Hs)
TVS+TVBP = 3Hs
VS
TVDISP= 220Hs
TVFP = 1Hs
HS
Line 1
Line 220
DE
Fig. 7.4.6.3.2 RGB Mode 2 Vertical Timing Diagram
Note: DP=’0’, EP=’0’, HSP=’0’ and VSP=’0’ of RGBCTR (B0h) command.
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SPFD54126B
-176xRGBx220
THP = 196 PCLK
THS+THBP = 10PCLK
HS
THFP = 10PCLK
THDISP = 176PCLK
PCLK
In-Valid
D1 D2 D3 D4 D5
Dn
In-Valid
nd
.co
Data Bus
m
DE
Fig. 7.4.6.3.3 RGB Mode 2 Horizontal Timing Diagram
bt
re
Note: DP=’0’, EP=’0’, HSP=’0’ and VSP=’0’ of RGBCTR (B0h) command.
.m
IDM
Full-color mode
Idle mode
Full-color mode
w
Data Bus
w
VS
w
Fig. 7.4.6.3.4 RGB Mode 2 Idle mode Timing Diagram
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Preliminary
SPFD54126B
Vertical Timing for RGB I/F
VS
TVFP
D
[17:0]
TVS
TVBP
TVFP
Note 3
Note 3
TVBL
TDSIP
DE
TVP
HS
nd
.co
m
Horizontal Timing for RGB I/F
HS
THFP
THS
THBP
THDSIP
DE
re
THBL
D
[17:0]
THFP
Note 3
bt
Note 3
TPCLK
.m
THP
PCLK
w
w
w
Fig. 7.4.6.3.5 Vertical and Horizontal timing for RGB I/F
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Preliminary
SPFD54126B
Table 7.4.6.3.1 Vertical and Horizontal Timing for RGB I/F
Item
Symbol
Min
Specification
Type.
GM=”00”
223
224
HS
GM=”01”
176
180
HS
GM=”11”
135
136
Condition
Max
Unit
Vertical Timing
TVP
TVS
TVFP
TVBP
TVS + TVBP
TVS + TVBP + TVFP
GM=”00”
GM=”01”
GM=”11”
Frame rate
TVBL
Vertical active area
TVDISP
Vertical refresh rate
Horizontal Timing
Horizontal cycle period
Horizontal low pulse width
Horizontal front porch
Horizontal back porch
TVRR
w
GM=”00”
TVRR=65Hz
GM=”01”
TVRR=65Hz
GM=”10”
TVRR=65Hz
100
2.40
100
1.92
100
1.45
bt
Pixel clock cycle
THBL
THDISP
TPCLKCYC
fPCLKCYC
TPCLKCYC
fPCLKCYC
TPCLKCYC
fPCLKCYC
THS + THBP
ffHS + fHBP
THS + THBP + THFP
.m
Horizontal blanking period
Horizontal active area
61.75
176
1
1
1
2
TBD
3
re
THP
THS
THFP
THBP
Horizontal data start point
1
1
1
2
3
nd
.co
Vertical low pulse width
Vertical front porch
Vertical back porch
Vertical data start line
Vertical blanking period
m
Vertical cycle period
1
3
4
220
176
132
65
196
10
10
20
176
380
2.63
472
2.12
625
1.60
4
1023
1022
1023
1023
68.25
511
63
63
62
63
256
418
10
520
10
690
10
HS
HS
HS
HS
HS
HS
HS
Hz
PCLK
PCLK
PCLK
PCLK
PCLK
µs
PCLK
PCLK
Ns
MHz
Ns
MHz
Ns
MHz
Note 1. VDD1=1.6 to 3.6V, VDD=2.6 to 3.5V, AGND=DGND=0V, Ta=-30 to 70℃ (to +85℃ no damage)
w
w
Note 2. Data lines can be set to “High” or “Low” during blanking time – Don’t care.
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Preliminary
SPFD54126B
7.4.6.4. Power On Sequence on RGB Mode 2
The Driver operates power up and display ON by VDD, VDDI, SHUT, VS, HS, DE, PCLK on RGB mode 2 as show as following figure.
VDDI
TVDD-VDDI
VDD
TVDD-SH
PCLK
TPCLK -SH
m
SHUT
TRS-SH
HS
DE
1
.m
Display High
Voltage
5
6
7
8
9
10
11
12
13
14
15
TSH-LCD
Display ON
Display OFF
w
TSH-ON
w
w
Display
VCOM Output
4
bt
Driver IC
Source Output
3
re
VS
Host
2
nd
.co
RESX
Normal Display
Normal Display
Blanking Display (Over 1 frame display)
Normal Display
Gate Output
Internal Counter
Internal oscillator
Fig. 7.4.6.4.1 Power On Sequence on RGB Mode 2
Table 7.4.6.4.1 Power ON AC Characteristics
Characteristics
Symbol
Min
Typ
Max
Unit
Remark
VDDI On to VDD On
TVDDI-VDD
0
ns
Note1
VDDI/VDD on to falling edge of SHUT
TVDD-SH
1
ms
RESX to falling of SHUT
TRS-SH
10
us
Signals input to falling edge of SHUT *
TCLK-SH
1
PCLK
Note2
Falling edge of SHUT to LCD power ON
TSH-LCD
120
ms
Falling edge of SHUT to Display start
TSH-ON
10
VS
Note 1: TVDDI-VDD can be <=0ns, >0ns. In any case, VDDI and VDD power up sequence should not have any impact on the driver / display
functionalities / performance.
Note 2: Signals mean VS, HS, DE and PCLK signal.
Note 3: DP=’0’, EP=’0’, HSP=’0’ and VSP=’0’ of RGBCTR (B0h) command.
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Preliminary
SPFD54126B
7.4.6.5. Power OFF Sequence on RGB Mode 2
The Driver operates power off and display OFF by VDD, VDDI, SHUT, VS, HS and DE on RGB mode 2 as show as following figure.
VDDI
TVDD-VDDI
VDD
RESX
SHUT
TOFF-VDD
nd
.co
m
PCLK
HS
TSH-OFF
DE
bt
re
VS
Host
Display High
Voltage
.m
Driver IC
Display ON
Normal Display
Source Output
Normal Display
w
0V
Normal Display
0V
w
VCOM Output
w
Display
Display OFF
Blanking Display (Over 1 frame display)
Gate Output
Internal Counter
Internal oscillator
Fig. 7.4.6.5.1 Power OFF Sequence on RGB Mode 2
Table 7.4.6.5.1 Power OFF AC Characteristics
Characteristics
Symbol
Min
Typ
Max
Unit
Remark
VDDI On to VDD On
TVDDI-VDD
0
ns
Note1
Signals input to VDDI/VDD off
Toff-VDD
1
us
Note2
Rising edge of SHUT to Display off
TSH-OFF
2
VS
Note 1: TVDDI-VDD can be <=0ns, >0ns. In any case, VDDI and VDD power up sequence should not have any impact on the driver / display
functionalities / performance.
Note 2: Signals mean VS, HS, DE and PCLK signal.
Note 3: DP=’0’, EP=’0’, HSP=’0’ and VSP=’0’ of RGBCTR (B0h) command.
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SPFD54126B
7.4.7.
RGB Data Color Coding
7.4.7.1. 16-bits/pixel Colour Order on the RGB Interface
RESX
‘1’
RCM = ‘1’
RCMx
VS
‘1’
HS
‘1’
DE
‘1’
PCLK
R1, Bit 4
R2, Bit 4
R3, Bit 4
R4, Bit 4
R5, Bit 4
D16, R3
R1, Bit 3
R2, Bit 3
R3, Bit 3
R4, Bit 3
R5, Bit 3
D15, R2
R1, Bit 2
R2, Bit 2
R3, Bit 2
R4, Bit 2
D14, R1
R1, Bit 1
R2, Bit 1
R3, Bit 1
D13, R0
R1, Bit 0
R2, Bit 0
R3, Bit 0
D12
-
-
-
D11, G5
G1, Bit 5
G2, Bit 5
D10, G4
G1, Bit 4
G2, Bit 4
D9, G3
G1, Bit 3
G2, Bit 3
D8, G2
G1, Bit 2
G2, Bit 2
D7, G1
G1, Bit 1
D6, G0
G1, Bit 0
D5, B4
B1, Bit 4
D4, B3
m
D17, R4
R5, Bit 1
R4, Bit 0
R5, Bit 0
-
-
G3, Bit 5
G4, Bit 5
G5, Bit 5
G3, Bit 4
bt
G4, Bit 4
G5, Bit 4
G3, Bit 3
G4, Bit 3
G5, Bit 3
G3, Bit 2
G4, Bit 2
G5, Bit 2
G2, Bit 1
G3, Bit 1
G4, Bit 1
G5, Bit 1
G2, Bit 0
G3, Bit 0
G4, Bit 0
G5, Bit 0
B2, Bit 4
B3, Bit 4
B4, Bit 4
B5, Bit 4
B1, Bit 3
B2, Bit 3
B3, Bit 3
B4, Bit 3
B5, Bit 3
D3, B2
B1, Bit 2
B2, Bit 2
B3, Bit 2
B4, Bit 2
B5, Bit 2
D2, B1
B1, Bit 1
B2, Bit 1
B3, Bit 1
B4, Bit 1
B5, Bit 1
D1, B0
B1, Bit 0
B2, Bit 0
B3, Bit 0
B4, Bit 0
B5, Bit 0
D0
-
-
-
-
-
.m
w
w
Pixel n
16-bits
re
R4, Bit 1
w
nd
.co
R5, Bit 2
Pixel n+1
Pixel n+2
16-bits
Pixel n+3
Pixel n+4
16-bits
Look-Up Table for 65K-colors or data mapping (16-Bits to 18-Bits)
Frame
Memory
18-bits
18-bits
R1 G1 B1 R2 G2 B2 R3 G3 B3
Note 1: The data order is as follows, MSB=D23, LSB=D0 and picture data is MSB=Bit5, LSB=Bit0 for Green data and MSB=Bit4, LSB=Bit0
for Red and Blue data.
Note 2. ‘-’ Don’t care, but need set to VDDI or DGND level.
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SPFD54126B
7.4.7.2. 18-bits/pixel Colour Order on the RGB Interface
RESX
RCM
‘1’
IM1=’0’ / IM0=’0’
VS
‘1’
HS
‘1’
DE
‘1’
WRX
R2, Bit 5
R3, Bit 5
R4, Bit 5
D16, R5
R1, Bit 4
R2, Bit 4
R3, Bit 4
R4, Bit 4
D15, R4
R1, Bit 3
R2, Bit 3
R3, Bit 3
R4, Bit 3
D14, R3
R1, Bit 2
R2, Bit 2
R3, Bit 2
D13, R2
R1, Bit 1
R2, Bit 1
R3, Bit 1
D12, R1
R1, Bit 0
R2, Bit 0
R3, Bit 0
D11, G5
G1, Bit 5
G2, Bit 5
D10, G4
G1, Bit 4
G2, Bit 4
D9, G3
G1, Bit 3
G2, Bit 3
D8, G2
G1, Bit 2
D7, G1
G1, Bit 1
D6, G0
G1, Bit 0
D5, B5
B1, Bit 5
D4, B4
R5, Bit 5
m
R1, Bit 5
R5, Bit 4
R5, Bit 3
R5, Bit 2
R4, Bit 1
R5, Bit 1
R4, Bit 0
R5, Bit 0
G3, Bit 5
G4, Bit 5
G5, Bit 5
G3, Bit 4
bt
G4, Bit 4
G5, Bit 4
G3, Bit 3
G4, Bit 3
G5, Bit 3
G2, Bit 2
G3, Bit 2
G4, Bit 2
G5, Bit 2
G3, Bit 1
G4, Bit 1
G5, Bit 1
G2, Bit 0
G3, Bit 0
G4, Bit 0
G5, Bit 0
B2, Bit 5
B3, Bit 5
B4, Bit 5
B5, Bit 5
B1, Bit 4
B2, Bit 4
B3, Bit 4
B4, Bit 4
B5, Bit 4
D3, B3
B1, Bit 3
B2, Bit 3
B3, Bit 3
B4, Bit 3
B5, Bit 3
D2, B2
B1, Bit 2
B2, Bit 2
B3, Bit 2
B4, Bit 2
B5, Bit 2
D1, B1
B1, Bit 1
B2, Bit 1
B3, Bit 1
B4, Bit 1
B5, Bit 1
D0, B0
B1, Bit 0
B2, Bit 0
B3, Bit 0
B4, Bit 0
B5, Bit 0
Frame
Memory
.m
w
G2, Bit 1
w
Pixel n
18-bit
re
R4, Bit 2
w
nd
.co
D17, R6
Pixel n+1
18-bit
Pixel n+2
Pixel n+3
Pixel n+4
18-bit
R1 G1 B1 R2 G2 B2 R3 G3 B3
Note 1: The data order is as follows, MSB=D23, LSB=D0 and picture data is MSB=Bit5, LSB=Bit0 for Red, Green and Blue data.
Note 2. ‘-’ Don’t care, but need set to VDDI or DGND level.
© ORISE Technology Co., Ltd.
Proprietary & Confidential
174
Apr. 25, 2006
Preliminary Version: 0.1
Evaluation Only. Created with Aspose.Pdf.Kit. Copyright 2002-2005 Aspose Pty Ltd
Preliminary
SPFD54126B
7.4.7.3. 6-bits/pixel Colour Order on the RGB Interface
RESX
RCM
‘1’
IM1=’0’ / IM0=’0’
VS
‘1’
HS
‘1’
DE
‘1’
D17
-
-
-
-
-
D16
-
-
-
-
m
D9
-
-
-
D8
-
-
-
D7
R1, Bit 5
G1, Bit 5
B1, Bit 5
nd
.co
WRX
D6
R1, Bit 4
G1, Bit 4
D5
R1, Bit 3
G1, Bit 3
D4
R1, Bit 2
G1, Bit 2
D3
R1, Bit 1
D2
R1, Bit 0
D1
-
D0
-
-
-
-
R2, Bit 5
G2, Bit 5
B1, Bit 4
R2, Bit 4
G2, Bit 4
B1, Bit 3
R2, Bit 3
G2, Bit 3
B1, Bit 2
R1, Bit 2
G2, Bit 2
G1, Bit 1
w
B1, Bit 1
R2, Bit 1
G2, Bit 1
G1, Bit 0
B1, Bit 0
R2, Bit 0
G2, Bit 0
-
-
-
-
-
-
-
-
.m
bt
re
-
w
w
-
Pixel n
Pixel n+1
8-bit
Frame
Memory
R1 G1 B1 R2 G2 B2 R3 G3 B3
Note 1: The data order is as follows, MSB=D17, LSB=D0 and picture data is MSB=Bit5, LSB=Bit0 for Red, Green and Blue data.
Note 2. ‘-’ Don’t care, but need set to VDDI or DGND level.
© ORISE Technology Co., Ltd.
Proprietary & Confidential
175
Apr. 25, 2006
Preliminary Version: 0.1
Evaluation Only. Created with Aspose.Pdf.Kit. Copyright 2002-2005 Aspose Pty Ltd
Preliminary
SPFD54126B
7.5.
Display Data RAM
7.5.1.
Configuration
The display module has an integrated 176x220x18-bit graphic type static RAM. This 696,960-bits memory allows to store on-chip a
176xRGBx220 image with an 18-bpp resolution (262K-color).
There will be no abnormal visible effect on the display when there is a simultaneous Panel Read
and interface Read or Write to the same location of the Frame Memory.
Display Data RAM Organization (GM=’00’)
LCD Glass
Latch
re
Look-up table
MPU
I/F
nd
.co
m
(176 x RGB x 220)
Display Data RAM
bt
(176 x 220 x 18-bit)
.m
Row
Address
Counter
Scan
Address
Counter
w
w
Line
Address
Counter
Column
Address
Counter
w
Host Interface
Fig. 7.5.1.1 Display Date RAM Organization
© ORISE Technology Co., Ltd.
Proprietary & Confidential
176
Apr. 25, 2006
Preliminary Version: 0.1
Evaluation Only. Created with Aspose.Pdf.Kit. Copyright 2002-2005 Aspose Pty Ltd
Preliminary
SPFD54126B
7.5.2.
Memory to Display Address Mapping
7.5.2.1. When using 176RGB x 220 resolution (GM1, GM0 = “00”, SMX=SMY=SRGB=’0’)
--------
S523 S524 S525 S526 S527 S528
RGB
Order
RGB=1
S6
Pixel 176
RGB=0
S5
Pixel 175
RGB=1
S4
--------
RGB=0
RA
S3
RGB=0
S2
RGB=1
S1
RGB=0
Gate Out Source Out
Pixel 2
RGB=1
Pixel 1
SA
MY=’0’ MY=’1’
ML=’0’ ML=’1’
219
1
218
--------
3
2
217
--------
4
3
216
5
4
215
6
5
214
7
6
213
8
7
212
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
213
212
7
214
213
6
215
214
5
216
215
4
217
216
3
218
217
2
219
218
220
219
CA
R0
G0
B0
R1
G1
B1
--------
R174 G174 B174 R175 G175 B175
0
219
1
218
2
217
--------
3
216
--------
4
215
--------
5
214
--------
6
213
--------
7
212
|
|
|
|
|
|
|
|
|
|
m
0
2
|
|
|
|
|
re
.m
nd
.co
1
--------
212
7
--------
213
6
--------
214
5
--------
215
4
--------
216
3
--------
217
2
1
--------
218
1
0
--------
219
0
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
bt
|
|
|
|
|
w
w
w
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
MX=’0’
0
1
--------
174
175
MX=’1’
175
174
--------
1
0
|
|
|
|
|
Note
RA = Row Address,
CA = Column Address
SA = Scan Address
MX = Mirror X-axis (Column address direction parameter), D6 parameter of MADCTL command
MY = Mirror Y-axis (Column address direction parameter), D7 parameter of MADCTL command
MX =Scan direction parameter, D4 parameter of MADCTL command
RGB = Red, Green and Blue pixel position change, D3 parameter of MADCTL command
© ORISE Technology Co., Ltd.
Proprietary & Confidential
177
Apr. 25, 2006
Preliminary Version: 0.1
Evaluation Only. Created with Aspose.Pdf.Kit. Copyright 2002-2005 Aspose Pty Ltd
Preliminary
SPFD54126B
7.5.2.2. When using 176RGB x 176 resolution (GM1, GM0 = “01”, SMX=SMY=SRGB=’0’)
--------
S523 S524 S525 S526 S527 S528
RGB
Order
RGB=1
S6
Pixel 176
RGB=0
S5
Pixel 175
RGB=1
S4
--------
RGB=0
RA
S3
RGB=0
S2
RGB=1
S1
RGB=0
Gate Out Source Out
Pixel 2
RGB=1
Pixel 1
SA
MY=’0’ MY=’1’
ML=’0’ ML=’1’
0
175
0
175
2
1
174
--------
1
174
3
2
173
--------
2
173
4
3
172
--------
3
172
5
4
171
--------
4
171
6
5
170
--------
5
170
7
6
169
--------
6
169
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
170
169
6
171
170
5
172
171
4
173
172
3
174
173
2
175
174
1
176
175
0
Note
|
|
|
|
|
R1
|
|
|
|
|
G1
|
|
|
|
|
B1
|
|
|
|
|
--------
R118 G118 B118 R119 G119 B119
nd
.co
|
|
|
|
|
B0
|
|
|
|
|
re
G0
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
.m
w
|
|
|
|
|
169
6
--------
170
5
--------
171
4
--------
172
3
--------
173
2
--------
174
1
--------
175
0
bt
--------
w
MX=’1’
|
|
|
|
|
w
CA
MX=’0’
R0
m
1
0
1
--------
174
175
175
174
--------
1
0
RA = Row Address,
CA = Column Address
SA = Scan Address
MX = Mirror X-axis (Column address direction parameter), D6 parameter of MADCTL command
MY = Mirror Y-axis (Column address direction parameter), D7 parameter of MADCTL command
MX =Scan direction parameter, D4 parameter of MADCTL command
RGB = Red, Green and Blue pixel position change, D3 parameter of MADCTL command
© ORISE Technology Co., Ltd.
Proprietary & Confidential
178
Apr. 25, 2006
Preliminary Version: 0.1
Evaluation Only. Created with Aspose.Pdf.Kit. Copyright 2002-2005 Aspose Pty Ltd
Preliminary
SPFD54126B
7.5.2.3. When using 176RGB x 132 resolution (GM1, GM0 = “11”, SMX=SMY=SRGB=’0’)
--------
S523 S524 S525 S526 S527 S528
RGB
Order
RGB=1
S12
Pixel 176
RGB=0
S11
Pixel 175
RGB=1
S10
--------
RGB=0
RA
S9
RGB=0
S8
RGB=1
S7
RGB=0
Gate Out Source Out
Pixel 2
RGB=1
Pixel 1
SA
ML=’0’ ML=’1’
0
131
0
131
2
1
130
--------
1
130
3
2
129
--------
2
129
4
3
128
--------
3
128
5
4
127
--------
4
127
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
128
127
4
--------
127
4
129
128
3
--------
128
3
130
129
2
--------
129
2
131
130
1
--------
130
1
132
131
0
--------
131
0
|
|
|
|
|
G1
|
|
|
|
|
B1
|
|
|
|
|
--------
0
MX=’1’
175
.m
MX=’0’
R174 G174 B174 R175 G175 B175
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
1
--------
174
175
174
--------
1
0
|
|
|
|
|
RA = Row Address,
w
CA = Column Address
w
Note
SA = Scan Address
|
|
|
|
|
R1
nd
.co
|
|
|
|
|
B0
bt
|
|
|
|
|
G0
w
CA
R0
m
1
re
MY=’0’ MY=’1’
MX = Mirror X-axis (Column address direction parameter), D6 parameter of MADCTL command
MY = Mirror Y-axis (Column address direction parameter), D7 parameter of MADCTL command
MX =Scan direction parameter, D4 parameter of MADCTL command
RGB = Red, Green and Blue pixel position change, D3 parameter of MADCTL command
© ORISE Technology Co., Ltd.
Proprietary & Confidential
179
Apr. 25, 2006
Preliminary Version: 0.1
Evaluation Only. Created with Aspose.Pdf.Kit. Copyright 2002-2005 Aspose Pty Ltd
Preliminary
SPFD54126B
7.5.3.
Normal Display On or Partial Mode On, Vertical Scroll Off
7.5.3.1. When using 176RGB x 220 resolution (GM1, GM0 = “00”)
In this mode, content of the frame memory within an area where column pointer is 00h to AFh and page pointer is 00h to DBh is displayed.
To display a dot on leftmost top corner, store the dot data at (column pointer, row pointer) = (0, 0).
(1) Example for Normal Display On (MX=MY=ML=’0’ ,SMX=SMY=’0’)
176 Columns
176 Columns
Scan
Order
0Z G1
0Z G2
2Z G3
3Z |
4Z |
4Z |
6Z |
176 x 220 x18-bits
Frame RAM
S0
U0 U1
V0 V1
W0 W1
X0 X1
Y0 Y1
Z0 Z1
V2
W2
X2
Y2 Y3
Z2 Z3
SZ
UY UZ
VX VY VZ
WX WY WZ
XX XY XZ
YW YX YY YZ
ZW ZX ZY ZZ
|
|
|
|
|
|
|
|
G218
G219
G220
00h
01h
02h
|
|
|
|
|
|
|
|
|
|
|
|
D9h
DAh
DBh
00
10
20
30
40
50
60
01
11
21
31
41
51
02 03
12 13
22
32
42
0W 0X 0Y
1W 0X 0Y
2X 2Y
3X 3Y
4X 4Y
5Y
m
0W 0X 0Y
1W 0X 0Y
2X 2Y
3X 3Y
4X 4Y
5Y
nd
.co
02 03
12 13
22
32
42
0Z G1
0Z G2
2Z G3
3Z |
4Z |
4Z |
6Z |
176 RGB x 220
LCD Panel
S0
U0 U1
V0 V1
W0 W1
X0 X1
Y0 Y1
Z0 Z1
re
01
11
21
31
41
51
bt
00
10
20
30
40
50
60
V2
W2
X2
Y2 Y3
Z2 Z3
SZ
UY UZ
VX VY VZ
WX WY WZ
XX XY XZ
YW YX YY YZ
ZW ZX ZY ZZ
|
|
|
|
|
|
|
|
G218
G219
G220
Display area
=220 lines
.m
220 Lines
00h 01h ---- ---- ---- ---- ---- AEh AFh
00h
01h
02h
|
|
|
|
|
|
|
|
|
|
|
|
D9h
DAh
DBh
w
176 Columns
w
w
(2). Example for Partial Display On (PSL[7:0]=04h,PEL[7:0]=D7h, MX=MV=ML=’0’ ,SMX=SMY=’0’)
176 Columns
Scan
Order
220 Lines
00h 01h ---- ---- ---- ---- ---- AEh AFh
00h
01h
02h
|
|
|
|
|
|
|
|
|
|
|
|
D9h
DAh
DBh
00
10
20
30
40
50
60
01
11
21
31
41
51
02 03
12 13
22
32
42
0W 0X 0Y
1W 0X 0Y
2X 2Y
3X 3Y
4X 4Y
5Y
0Z G1
0Z G2
2Z G3
3Z |
4Z |
4Z |
6Z |
176 x 220 x18-bits
Frame RAM
S0
U0 U1
V0 V1
W0 W1
X0 X1
Y0 Y1
Z0 Z1
V2
W2
X2
Y2 Y3
Z2 Z3
© ORISE Technology Co., Ltd.
Proprietary & Confidential
SZ
UY UZ
VX VY VZ
WX WY WZ
XX XY XZ
YW YX YY YZ
ZW ZX ZY ZZ
|
|
|
|
|
|
|
|
G218
G219
G220
00h
01h
02h
|
|
|
|
|
|
|
|
|
|
|
|
D9h
DAh
DBh
180
00
10
20
30
40
50
60
01
11
21
31
41
51
02 03
12 13
22
32
42
0W 0X 0Y
1W 0X 0Y
2X 2Y
3X 3Y
4X 4Y
5Y
0Z G1
0Z G2
2Z G3
3Z |
4Z |
4Z |
6Z |
176 RGB x 220
LCD Panel
S0
U0 U1
V0 V1
W0 W1
X0 X1
Y0 Y1
Z0 Z1
V2
W2
X2
Y2 Y3
Z2 Z3
SZ
UY UZ
VX VY VZ
WX WY WZ
XX XY XZ
YW YX YY YZ
ZW ZX ZY ZZ
|
|
|
|
|
|
|
|
G218
G219
G220
Non-Display
area =4 lines
Display area
=212 lines
Non-Display
area =4 lines
Apr. 25, 2006
Preliminary Version: 0.1
Evaluation Only. Created with Aspose.Pdf.Kit. Copyright 2002-2005 Aspose Pty Ltd
Preliminary
SPFD54126B
7.5.3.2. When using 176RGB x 176 resolution (GM1, GM0 = “01”)
In this mode, contents of the frame memory within an area where column pointer is 00h to AFh and page pointer is 00h to AFh is displayed.
To display a dot on leftmost top corner, store the dot data at (column pointer, row pointer) = (0, 0).
(1) Example for Normal Display On (MX=MY=ML=’0’, SMX=SMY=’0’)
176 Columns
176 Columns
Scan
Order
No Used
00
10
20
30
40
01 02 03
11 12
21
31
0W 0X 0Y 0Z G1
0X 0Y 0Z G2
2Y 2Z G3
3Y 3Z |
4Z |
|
176 RGB x 176
LCD Panel
|
W0
WZ |
X0 X1
XY XZ |
Y0 Y1 Y2
YX YY YZ G175
Z0 Z1 Z2 Z3
ZW ZX ZY ZZ G176
Display area
=176 lines
re
|
|
|
|
G218
G219
G220
00h
01h
02h
|
|
|
|
|
|
AEh
AFh
m
0W 0X 0Y 0Z G1
0X 0Y 0Z G2
2Y 2Z G3
3Y 3Z |
4Z |
|
176 x 176 x18-bits
Frame RAM
|
W0
WZ |
X0 X1
XY XZ |
Y0 Y1 Y2
YX YY YZ G175
Z0 Z1 Z2 Z3
ZW ZX ZY ZZ G176
nd
.co
01 02 03
11 12
21
31
bt
00
10
20
30
40
.m
176 Lines
00h 01h ---- ---- ---- ---- ---- AEh AFh
00h
01h
02h
|
|
|
|
|
|
AEh
AFh
|
|
|
|
D9h
DAh
DBh
w
176 Columns
w
w
(2) Example for Partial Display On (PSL[7:0]=03h,PEL[7:0]=ACh, MX=MV=ML=’0’, SMX=SMY=’0’)
176 Columns
Scan
Order
176 Lines
00h 01h ---- ---- ---- ---- ---- AEh AFh
00h
01h
02h
|
|
|
|
|
|
AEh
AFh
|
|
|
|
D9h
DAh
DBh
00
10
20
30
40
01 02 03
11 12
21
31
0W 0X 0Y 0Z G1
0X 0Y 0Z G2
2Y 2Z G3
3Y 3Z |
4Z |
|
176 x 176 x18-bits
Frame RAM
|
W0
WZ |
X0 X1
XY XZ |
Y0 Y1 Y2
YX YY YZ G175
Z0 Z1 Z2 Z3
ZW ZX ZY ZZ G176
No Used
© ORISE Technology Co., Ltd.
Proprietary & Confidential
00h
01h
02h
|
|
|
|
|
|
AEh
AFh
00
10
20
30
40
01 02 03
11 12
21
31
0W 0X 0Y 0Z G1
0X 0Y 0Z G2
2Y 2Z G3
3Y 3Z |
4Z |
|
176 RGB x 176
LCD Panel
|
W0
WZ |
X0 X1
XY XZ |
Y0 Y1 Y2
YX YY YZ G175
Z0 Z1 Z2 Z3
ZW ZX ZY ZZ G176
Non-Display
area =3 lines
Display area
=170 lines
Non-Display
area =3 lines
|
|
|
|
G218
G219
G220
181
Apr. 25, 2006
Preliminary Version: 0.1
Evaluation Only. Created with Aspose.Pdf.Kit. Copyright 2002-2005 Aspose Pty Ltd
Preliminary
SPFD54126B
7.5.3.3. When using 176RGB x 132 resolution (GM1, GM0 = “11”)
In this mode, contents of the frame memory within an area where column pointer is 00h to AFh and page pointer is 000h to 83h is displayed.
To display a dot on leftmost top corner, store the dot data at (column pointer, row pointer) = (0, 0).
(1) Example for Normal Display On (MX=MY=ML=’0’ ,SMX=SMY=’0’)
176 Columns
176 Columns
Scan
Order
|
|
XZ |
YY YZ G131
ZY ZZ G132
|
|
|
|
G218
G219
G220
00 01 02 03
0W 0X
10 11 12
0X
20 21
30
176 RGB x 132
LCD Panel
X0
Y0 Y1 Y2
YX
Z0 Z1 Z2 Z3
ZW ZX
0Y 0Z G1
0Y 0Z G2
2Y 2Z G3
3Z |
|
|
XZ |
YY YZ G131
ZY ZZ G132
m
00h
01h
02h
|
|
|
|
82h
83h
nd
.co
No Used
0Y 0Z G1
0Y 0Z G2
2Y 2Z G3
3Z |
Display area
=132 lines
re
00 01 02 03
0W 0X
10 11 12
0X
20 21
30
176 x 132 x18-bits
Frame RAM
X0
Y0 Y1 Y2
YX
Z0 Z1 Z2 Z3
ZW ZX
.m
bt
132 Lines
00h 01h ---- ---- ---- ---- ---- AEh AFh
00h
01h
02h
|
|
|
|
82h
83h
|
|
|
|
D9h
DAh
DBh
w
176 Columns
w
w
(2) Example for Partial Display On (PSL[7:0]=02h,PEL[7:0]=81h, MX=MV=ML=’0’ ,SMX=SMY=’0’)
176 Columns
Scan
Order
132 Lines
00h 01h ---- ---- ---- ---- ---- AEh AFh
00h
01h
02h
|
|
|
82h
83h
|
|
|
|
D9h
DAh
DBh
00
10
20
30
01 02 03
0W 0X
11 12
0X
21
31 176 x 132 x18-bits
Frame RAM
Y0 Y1 Y2
Z0 Z1 Z2 Z3
© ORISE Technology Co., Ltd.
Proprietary & Confidential
0Y
0Y
2Y
3Y
0Z G1
0Z G2
2Z G3
3Z |
|
|
YX YY YZ G131
ZW ZX ZY ZZ G132
|
|
|
|
G218
G219
G220
00h
01h
02h
|
|
|
82h
83h
|
|
|
|
D9h
DAh
DBh
182
00
10
20
30
01 02 03
0W 0X
11 12
0X
21
31 176 RGB x 132
LCD Panel
Y0 Y1 Y2
Z0 Z1 Z2 Z3
0Y
0Y
2Y
3Y
0Z G1
0Z G2
2Z G3
3Z |
|
|
YX YY YZ G131
ZW ZX ZY ZZ G132
|
|
|
|
G218
G219
G220
Non-Display
area =2 lines
Display area
=128 lines
Non-Display
area =2 lines
Apr. 25, 2006
Preliminary Version: 0.1
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Preliminary
SPFD54126B
7.5.4.
Vertical Scroll Mode
There is vertical scrolling, which are determined by the commands “Vertical Scrolling Definition” (33h) and “Vertical Scrolling Start Address”
(37h).
T FA
V SA
V SA
B FA
B FA
m
T FA
O riginal
nd
.co
Scrolling
w
w
w
.m
bt
re
Fig. 7.5.4.1 Difference between Scrolling and original
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Preliminary
SPFD54126B
7.5.4.1. When using 176RGB x 220 resolution (GM1, GM0 = “00”)
When Vertical Scrolling Definition Parameters (TFA+VSA+BFA)=220. In this case, scrolling is applied as shown below.
(1) Example for TFA =3, VSA=215, BFA=2, SSA=4, ML=0: Scrolling
176 Columns
176 Columns
Scan
Order
02 03
12 13
22
32
42
0W 0X 0Y
1W 1X 1Y
2X 2Y
3X 3Y
4X 4Y
5Y
0Z
1Z
2Z
3Z
4Z
5Z
6Z
176 x 220 x18-bits
Frame RAM
T0
U0 U1
V0 V1
W0 W1
X0 X1
Y0 Y1
Z0 Z1
V2
W2
X2
Y2 Y3
Z2 Z3
TZ
UY UZ
VX VY VZ
WX WY WZ
XX XY XZ
YW YX YY YZ
ZW ZX ZY ZZ
00h 01h ---- ---- ---- ---- ---- AEh AFh
1
2
3
|
|
|
|
|
|
|
|
|
|
|
|
218
219
220
00h
01h
02h
|
|
|
|
|
|
|
|
|
|
|
|
D9h
DAh
DBh
SSA
00
10
20
40
50
60
01
11
21
41
51
02 03
12 13
22
42
0W 0X 0Y
1W 1X 1Y
2X 2Y
4X 4Y
5Y
0Z G1
1Z G2
2Z G3
4Z |
4Z |
6Z |
176 RGB x 220
LCD Panel
m
01
11
21
31
41
51
T0
U0 U1
V0 V1 V2
W0 W1 W2
X0 X1 X2
30 31 32
Y0 Y1 Y2 Y3
Z0 Z1 Z2 Z3
TZ
UY UZ
VX VY VZ
WX WY WZ
XX XY XZ
3X 3Y 3Z
YW YX YY YZ
ZW ZX ZY ZZ
nd
.co
00
10
20
30
40
50
60
|
|
|
|
|
|
|
|
|
G218
G219
G220
TFA
VSA
BFA
.m
bt
re
220 Lines
00h 01h ---- ---- ---- ---- ---- AEh AFh
00h
01h
02h
|
|
|
|
|
|
|
|
|
|
|
|
D9h
DAh
DBh
w
176 Columns
w
(2) Example for TFA =3, VSA=215, BFA=2, SSA=215, ML=1: Scrolling: TFA and BFT are exchanged
176 Columns
Scan
Order
220 Lines
00
10
20
30
40
50
60
01
11
21
31
41
51
w
00h 01h ---- ---- ---- ---- ---- AEh AFh
00h
01h
02h
|
|
|
|
|
|
|
|
|
|
|
|
D9h
DAh
DBh
02 03
12 13
22
32
42
0W 0X
1W 1X
2X
3X
4X
0Y
1Y
2Y
3Y
4Y
5Y
176 x 220 x18-bits
Frame RAM
S0
U0 U1
V0 V1
W0 W1
X0 X1
Y0 Y1
Z0 Z1
V2
W2
X2
Y2 Y3
Z2 Z3
© ORISE Technology Co., Ltd.
Proprietary & Confidential
00h 01h ---- ---- ---- ---- ---- AEh AFh
0Z 220
1Z 219
2Z 218
3Z |
4Z |
4Z |
6Z |
SZ
UY UZ
VX VY VZ
WX WY WZ
XX XY XZ
YW YX YY YZ
ZW ZX ZY ZZ
|
|
|
|
|
|
|
|
3
2
1
SSA
184
00h
01h
02h
|
|
|
|
|
|
|
|
|
|
|
|
D9h
DAh
DBh
00
10
60
70
80
90
A0
01 02 03
11 12 13
61 62
71
81
0W 0X 0Y
1W 1X 1Y
6X 6Y
7Y
7Y
0Z G1
1Z G2
6Z G3
7Z |
8Z |
9Z |
AZ |
176 RGB x 220
LCD Panel
20
30
40
50
X0
Y0
Z0
21
31
41
51
X1
Y1
Z1
22
32
42
X2
Y2 Y3
Z2 Z3
2X 2Y 2Z
3X 3Y 3Z
4X 4Y 4Z
5Y 4Z
XX XY XZ
YW YX YY YZ
ZW ZX ZY ZZ
|
|
|
|
|
|
|
|
G218
G219
G220
BFA
VSA
TFA
Apr. 25, 2006
Preliminary Version: 0.1
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Preliminary
SPFD54126B
7.5.5.
Vertical Scroll Example
Vertical Scroll Example (GM1, GM0 = “00”)
There are 2 types of vertical scrolling, which are determined by the commands “ Vertical Scrolling Definition” (33h) and “Vertical Scrolling
Start Address” (37h).
Case 1: TFA + VSA + BFA≠220
N/A. Do not set TFA + VSA + BFA≠160. In that case, unexpected picture will be shown.
Case 2: TFA + VSA + BFA=220 (Scrolling)
2
bt
.m
Display
Axis (0,0)
1
2
w
Increment
1
w
Display
2
w
Physical Line
Pointer
VSCSAD
2
re
1
Frame
Memory
1
VSCSAD
Display
Axis (0,0)
nd
.co
Physical Line
Pointer
Memory Physical Axis
(0,0)
m
Example1) When MADCTR parameter ML=”0”, TFA=0, VSA=220, BFA=0 and VSCSAD=80.
Display
Frame
Memory
Example2) When MADCTR parameter ML=”1”, TFA=30, VSA=190, BFA=0 and VSCSAD=80.
Physical Line
Memory Physical Axis
(0,0)
Display
Axis (0,0)
Pointer
2
3
3
2
VSCSAD
TFA
1
1
TFA
Frame
Memory
Display
Increment
Physical Line
Memory Physical Axis
(0,0)
Pointer
Display
Axis (0,0)
2
3
VSCSAD
3
Frame
Memory
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2 1
1
TFA
TFA
Display
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SPFD54126B
7.6.
Address Counter
The address counter sets the addresses of the display data RAM for writing and reading. (Example for GM1, GM0 = “00”)
Data is written pixel-wise into the RAM matrix of DRIVER. The data for one pixel or two pixels is collected (RGB 8-8-8-bit), according to the
data formats. As soon as this pixel-data information is complete the “Write access” is activated on the RAM. The locations of RAM are
addressed by the address pointers. The address ranges are X=0 to X=175 (AFh) and Y=0 to Y=219 (DBh). Addresses outside these ranges
are not allowed. Before writing to the RAM a window must be defined into which will be written. The window is programmable via the
command registers XS, YS designating the start address and XE, YE designating the end address.
For example the whole display contents will be written, the window is defined by the following values: XS=0 (0h) YS=0 (0h) and XE=175
(AFh), YE=219 (DBh).
In vertical addressing mode (MV=1), the Y-address increments after each byte, after the last Y-address (Y=YE), Y wraps around to YS and
X increments to address the next column. In horizontal addressing mode (V=0), the X-address increments after each byte, after the last
X-address (X=XE), X wraps around to XS and Y increments to address the next row. After the every last address (X=XE and Y=YE) the
address pointers wrap around to address (X=XS and Y=YS).
nd
.co
m
For flexibility in handling a wide variety of display architectures, the commands “CASET, RASET” and “MADCTR” , define flags MX and MY,
which allows mirroring of the X-address and Y-address. All combinations of flags are allowed. Fig. 6.6.1 show the available combinations of
writing to the display RAM. When MX, MY and MV will be changed the data bust be rewritten to the display RAM.
For each image condition, the controls for the column and row counters apply as Fig. 7.6.1 below:
Condition
re
When RAMWR/RAMRD command is accepted
bt
Complete Pixel Read / Write action
The Column counter value is larger than “End Column (XE)”
Row Counter
Return to “Start
Column (XS)”
Return to “Start Row
(YS)”
Increment by 1
No change
Return to “Start
Column (XS)”
Return to “Start
Column (XS)”
Return to “Start Row
(YS)”
Increment by 1
w
w
w
.m
The Column counter value is larger than “End Column (XE)” and the Row
counter value is larger than “End Row (YE)”
Column Counter
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SPFD54126B
7.7.
Memory Data Write/ Read Direction
The data is written in the order illustrated above. The Counter which dictates where in the physical memory the data is to be written is
controlled by “Memory Data Access Control” Command, bits B5 (MV), B6 (MX), B7 (MY) as described below.
B
Data Stream order is like in this figure
ORISE
E
Fig. 7.7.1 Data streaming order
nd
.co
Physical Column
Pointer
Virtual (0,0) when
MV=don’t care,
MX=’0’, MY=’0’
Physical Row
Pointer
MY
CASET (2Ah)
(0,0)
.m
RASET (2Bh)
Virtual (0,0)
when MV=don’t care,
MX=’1’, MY=’0’
re
MX
Virtual to Physical Pointer translator
(175,0)
bt
MADCTR
(36h)
MV
m
-When 176RGBx220 (GM=’00’)
Physical
axes
(175,219)
w
(0,219)
Virtual (0,0)
when MV=don’t care,
MX=’1’, MY=’1’
w
w
Virtual (0,0)
when MV=don’t care,
MX=’0’, MY=’1’
MV
0
0
0
0
1
1
1
1
MX
0
0
1
1
0
0
1
1
MV
0
1
0
1
0
1
0
1
CASET
Direct to Physical Column Pointer
Direct to Physical Column Pointer
Direct to (127-Physical Column Pointer)
Direct to (127-Physical Column Pointer)
Direct to Physical Row Pointer
Direct to (159-Physical Row Pointer)
Direct to Physical Row Pointer
Direct to (159-Physical Row Pointer)
RASET
Direct to Physical Row Pointer
Direct to (219-Physical Row Pointer)
Direct to Physical Row Pointer
Direct to (219-Physical Row Pointer)
Direct to Physical Column Pointer
Direct to Physical Column Pointer
Direct to (175-Physical Column Pointer)
Direct to (175-Physical Column Pointer)
Note: Data is always written to the Frame Memory in the same order, regardless of the Memory Write Direction set by MADCTL bits B7
(MY), B6 (MX), B5 (MV). The write order for each pixel unit is
D17 D16 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
R5 R4 R3 R2 R1 R0 G5 G4 G3 G2 G1 G0 B5 B4 B3 B2 B1 B0
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SPFD54126B
Frame Data Write Direction According to the MADCTR parameters (MV, MX and MY)
Normal
MADCTR
Parameter
Image in the Driver
(DDRAM)
Image in the Host
(MPU)
MV MX MY
0
0
0
H/W position (0,0)
B
B
F
0
1
H/W position (0,0)
F
X-Mirror
0
1
0
1
F
X-Y Exchange
X-Mirror
X-Y Exchange
X-Mirror
Y-Mirror
E
H/W position (0,0)
E
1
0
0
1
0
1
B
F
1
0
1
© ORISE Technology Co., Ltd.
Proprietary & Confidential
1
E
H/W position (0,0)
E
B
B
B
H/W position (0,0)
H/W position (0,0)
F
X-Y address (0,0)
X: RASET
Y: CASET
E
E
B
X-Y address (0,0)
X: CASET
Y: RASET
E
E
X-Y address (0,0)
X: RASET
Y: CASET
X-Y address (0,0)
X: CASET
Y: RASET
B
X-Y address (0,0)
X: RASET
Y: CASET
B
F
1
B
H/W position (0,0)
B
F
1
E
w
w
X-Y Exchange
Y-Mirror
E
B
w
X-Y Exchange
B
H/W position (0,0)
bt
1
E
E
E
.m
0
X-Y address (0,0)
X: CASET
Y: RASET
B
F
X-Mirror
Y-Mirror
E
B
nd
.co
0
re
Y-Mirror
F
X-Y address (0,0)
X: CASET
Y: RASET
m
Display Data
Direction
E
E
B
188
X-Y address (0,0)
X: RASET
Y: CASET
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Preliminary
SPFD54126B
7.8.
Tearing Effect Output Line
The Tearing Effect output line supplies to the MPU a Panel synchronization signal. This signal can be enabled or disabled by the Tearing
Effect Line Off & On commands. The mode of the Tearing Effect signal is defined by the parameter of the Tearing Effect Line On command.
The signal can be used by the MPU to synchronize Frame Memory Writing when displaying video images.
7.8.1.
Tearing Effect Line Modes
Mode 1, the Tearing Effect Output signal consists of V-Blanking Information only:
t vdl
t vdh
tvdl
tvdh
m
Vertical T im e Scale
tvdh= The LCD display is not updated from the Frame Memory
nd
.co
tvdl= The LCD display is updated from the Frame Memory (except Invisible Line – see below)
t h dh
thdl
thdh
bt
t hd l
re
Mode 2, the Tearing Effect Output signal consists of V-Blanking and H-Blanking Information, there is one V-sync and 162 H-sync pulses per
field.
1
st
Line
2
nd
Line
V -S ync
219
th
Line
th
220 Line
w
Invisible
Line
.m
V-S ync
w
thdh= The LCD display is not updated from the Frame Memory
w
thdl= The LCD display is updated from the Frame Memory (except Invisible Line – see above)
Bottom Line
T op Line
2
nd
Line
T E (M ode2)
T E (M ode1)
t vdh
tvdh
Note: During Sleep In Mode, the Tearing Output Pin is active Low.
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7.8.2.
Tearing Effect Line Timings
The Tearing Effect signal is described below:
tvdl
t vdl
tvdh
t vdh
Vertical T im ing
H orizontal T im ing
thdl
thdh
t hd h
nd
.co
m
t hd l
Table 7.8.2.1 AC characteristics of Tearing Effect Signal Idle Mode Off (Frame Rate = 58.9 Hz)
min
max
unit
tvdl
Vertical Timing Low Duration
13
-
ms
tvdh
Vertical Timing High Duration
1000
-
μs
thdl
Horizontal Timing Low Duration
33
-
μs
thdh
Horizontal Timing High Duration
25
500
μs
re
Parameter
bt
Symbol
description
.m
NOTE: The timings in Table 7.8.2.1 apply when MADCTR ML=0 and ML=1
Input Signal Slope
w
w
w
The signal’s rise and fall times (tf, tr) are stipulated to be equal to or less than 15ns.
TR
Output Signal
TF
TR
VIH=0.7*VDDI
VIL=0.3*VDDI
TF
VOH=0.8*VDDI
VOL=0.2*VDDI
TR=TF<= 15ns
TR=TF<= 15ns
Fig. 7.8.2.2 Rising and Falling timing for Input and Output signal
The Tearing Effect Output Line is fed back to the MPU and should be used as shown below to avoid Tearing Effect:
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SPFD54126B
7.8.3.
Example 1: MPU Write is faster than panel read.
M CU to
M em ory
1
st
162
tim e
nd
TE Output
Signal
tim e
M em ory to
LCD
st
162
b
nd
c
m
1
a
d
tim e
nd
.co
Im age on LCD
a
© ORISE Technology Co., Ltd.
Proprietary & Confidential
.m
b
c
d
w
A A
B B B
w
Im age on LCD
bt
B
w
Data to be sent
re
Data write to Frame Memory is now synchronized to the Panel Scan. It should be written during the vertical sync pulse of the Tearing Effect
Output Line. This ensures that data is always written ahead of the panel scan and each Panel Frame refresh has a complete new image:
191
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SPFD54126B
7.8.4.
Example 2: MPU write is slower than panel read.
M CU to
M em ory
1
st
16 2
tim e
nd
TE Output
Signal
tim e
1
a
st
16 2
b
nd
c
d
nd
.co
Im age on LCD
m
M em ory to
LCD
tim e
f
e
.m
b
c
d
e
f
w
a
w
B
w
Data to be sent
bt
re
The MPU to Frame Memory write begins just after Panel Read has commenced i.e. after one horizontal sync pulse of the Tearing Effect
Output Line. This allows time for the image to download behind the Panel Read pointer and finishing download during the subsequent
Frame before the Read Pointer “catches” the MPU to Frame memory write position.
Im age on LCD
AA A A A
BB
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SPFD54126B
7.9.
Preset Values
ORISE has already set all preset values in SPFD54126B. Any of these preset values do not need customer’s SW support.
7.10.
Power ON/OFF Sequence
VDDI and VDD can be applied in any order.
VDDI and VDD can be powered down in any order.
During power off, if LCD is in the Sleep Out mode, VDD and VDDI must be powered down minimum 120msec after RESX has been
released.
nd
.co
m
During power off, if LCD is in the Sleep In mode, VDDI or VDD can be powered down minimum 0msec after RESX has been released.
CSX can be applied at any timing or can be permanently grounded. RESX has priority over CSX.
Note 1: There will be no damage to the display module if the power sequences are not met.
Note 2: There will be no abnormal visible effects on the display panel during the Power On/Off Sequences.
bt
re
Note 3: There will be no abnormal visible effects on the display between end of Power On Sequence and before receiving Sleep Out
command. Also between receiving Sleep In command and Power Off Sequence.
.m
If RESX line is not held stable by host during Power On Sequence, then it will be necessary to apply a Hardware Reset (RESX) after Host
Power On Sequence is complete to ensure correct operation. Otherwise function is not guaranteed.
w
The power on/off sequence is illustrated below:
w
7.10.1. Case 1 – RESX Line is held High or Unstable by Host at Power On
w
If RESX line is held High or unstable by the host during Power On, then a Hardware Reset must be applied after both VDD and VDDI have
been applied – otherwise correct functionality is not guaranteed. There is no timing restriction upon this hardware reset.
TrPW = +/- no limit
tfPW
=
+/- no limit
VDD1
VDDI
VDD2
VDD
Time when the latter signal rises up to 90% of its Typical Value.
e.g. When VDD2 comes later, This time is defined at the cross point
of 90% of 2.5V/2.75V,
notof90% of 2.3V.
2.75V,not 90%
Time when the former signal falls down to 90% of its Typical Value.
e.g. When VDD2 falls earlier, This time is defined at the cross point
of 90% of 2.5V/2.75V,
notof90% of 2.3V.
2.75V,not 90%
tfPW!CS
CSX= +/- no limit
trPW!CS
CSX= +/- no limit
CSX
!CS
H or L
trPW!RES
RESX= + no limit
RESX
!RES
(Power down in
Sleep Out mode)
RESX
!RES
30%
tfPW!RES1
RESX1= min.120ms
trPW!RES
RES = + no limit
30%
tfPW!RES2
RESX2= min.0ns
(Power down in
Sleep In mode)
tfPW!RES1 is applied to !RES
RESX falling in the Sleep Out Mode.
TfpwRESX1
tfPW!RES2 is applied to !RES
TfpwRESX2
RESX falling in the Sleep In Mode.
Note: Unless otherwise specified, timings herein show cross point at 50% of signal/power level.
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7.10.2. Case 2 – RESX Line is Held Low by Host at Power On
If RESX line is held Low (and stable) by the host during Power On, then the RESX must be held low for minimum 10µsec after both VDD
and VDDI have been applied.
TrPW = +/- no limit
tfPW
=
+/- no limit
VDD1
VDDI
VDD2
VDD
Time when the latter signal rises up to 90% of its Typical Value.
e.g. When VDD2 comes later, This time is defined at the cross point
of 90% of 2.5V/2.75V,
notof90% of 2.3V.
2.75V,not 90%
CSX= +/- no limit
tfPW!CS
trPW!CS
CSX= +/- no limit
H or L
nd
.co
CSX
!CS
m
Time when the former signal falls down to 90% of its Typical Value.
e.g. When VDD2 falls earlier, This time is defined at the cross point
2.75V,not 90%
of 90% of 2.5V/2.75V,
notof90% of 2.3V.
RESX= min.10µs
trPW!RES
!RES
RESX
(Power down in
Sleep Out mode)
RESX1= min.120ms
tfPW!RES1
RESX= min.10µs
trPW!RES
re
!RES
RESX
RESX2= min.0ns
tfPW!RES2
bt
(Power down in
Sleep In mode)
.m
tfPW!RES1 is applied to RESX
!RES falling in the Sleep Out Mode.
TfpwRESX1
TfpwRESX2
tfPW!RES2 is applied to RESX
!RES falling in the Sleep In Mode.
w
Note: Unless otherwise specified, timings herein show cross point at 50% of signal/power level.
7.10.3. Uncontrolled Power Off
w
w
The uncontrolled power off means a situation when e.g. there is removed a battery without the controlled power off sequence. There will not
be any damages for the display module or the display module will not cause any damages for the host or lines of the interface.
At an uncontrolled power off the display will go blank and there will not be any visible effects within (TBD) second on the display (blank
display) and remains blank until “Power On Sequence” powers it up.
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Preliminary
SPFD54126B
7.11.
Power Level Definition
7.11.1. Power Level
6 level modes are defined they are in order of Maximum Power consumption to Minimum Power Consumption:
1. Normal Mode On (full display), Idle Mode Off, Sleep Out.
In this mode, the display is able to show maximum 262,144 colors.
2. Partial Mode On, Idle Mode Off, Sleep Out.
In this mode part of the display is used with maximum 262,144 colors.
3. Normal Mode On (full display), Idle Mode On, Sleep Out.
m
In this mode, the full display area is used but with 8 colors.
4. Partial Mode On, Idle Mode On, Sleep Out.
nd
.co
In this mode, part of the display is used but with 8 colors.
5. Sleep In Mode
In this mode, the DC: DC converter, Internal oscillator and panel driver circuit are stopped. Only the MCU interface and memory works
with VDDI power supply. Contents of the memory are safe.
re
6. Power Off Mode
bt
In this mode, both VDD and VDDI are removed.
.m
Note: Transition between modes 1-5 is controllable by MCU commands. Mode 6 is entered only
w
w
w
when both Power supplies are removed.
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Preliminary
SPFD54126B
7.11.2. Power Flow Chart
Normal display mode on = NORON
Partial mode on = PTLON
Idle mode off = IDMOFF
Power on sequence
HW reset
SW reset
Idle mode on = IDMON
Sleep out = SLPOUT
Sleep in = SLPIN
NORON
NORON
SLPIN
Sleep out
Normal display mode on
Idle mode off
IDMON
m
SLPOUT
PTLON
nd
.co
PTLON
Sleep in
Normal display mode on
Idle mode off
IDMOFF
IDMON
IDMOFF
SLPIN
re
Sleep out
Normal display mode on
Idle mode on
Sleep in
Normal display mode on
Idle mode on
w
.m
bt
SLPOUT
IDMON
Sleep in
Partial mode on
Idle mode off
SLPOUT
IDMOFF
PTLON
NORON
SLPIN
w
w
Sleep out
Partial mode on
Idle mode off
IDMON
IDMOFF
PTLON
SLPIN
Sleep out
Partial mode on
Idle mode on
SLPOUT
Sleep out
Sleep in
Partial mode on
Idle mode on
NORON
Sleep in
Note 1: There is not any abnormal visual effect when there is changing from one power mode to another power mode.
Note 2: There is not any limitation, which is not specified by this spec, when there is changing from one power mode to another power
mode.
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Preliminary
SPFD54126B
7.12.
Gamma Curves
Gamma Curve
1.0
0.9
0.8
Gamma = 1.0
0.7
Gamma = 2.5
0.6
Gamma = 2.2
Y 0.5
Gamma = 1.8
m
0.4
0.2
Optical Gamma
Curve according to the GC0 to GC3 bit
0.1
0.0
0.0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1.0
w
w
w
.m
bt
re
X
nd
.co
0.3
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Preliminary
SPFD54126B
7.13.
Reset
7.13.1. Reset Value
7.13.1.1. Reset Table (Default Value, GM=00, 176RGB x 220)
Item
Frame memory
Sleep In/Out
Display On/Off
Display mode (normal/partial)
Display Inversion On/Off
Display Idle Mode On/Off
Column: Start Address (XS)
After Power On
Random
In
Off
Normal
Off
Off
0000h
After Hardware Reset
No Change
In
Off
Normal
Off
Off
0000h
After Software Reset
No Change
In
Off
Normal
Off
Off
0000h
00AFh
00AFh
00AFh (175d) (when MV=0)
00DBh (219d) (when MV=1)
Column: End Address (XE)
0000h
0000h
0000h
Row: End Address (YE)
00DBh
00DBh
00DBh (219d) (when MV=0)
00AFh (175d) (when MV=1)
GC0
See Section 6.14
0000h
00DBh
Off
0000h
00DBh
0000h
0000h
Off
0 (Mode1)
GC0
See Section 6.14
0000h
00DBh
Off
0000h
00DBh
0000h
0000h
Off
0 (Mode1)
GC0
No Change
0000h
00DBh
Off
0000h
00DBh
0000h
0000h
Off
0 (Mode1)
0/0/0/0/0
No Change
6 (18-Bit/Pixel)
08h
00h
6 (18-Bit/Pixel)
00h
00h
00h
38h
80h
62h
No Change
08h
No Change
No Change
00h
00h
00h
38h
80h
62h
nd
.co
re
bt
.m
0/0/0/0/0
6 (18-Bit/Pixel)
08h
00h
6 (18-Bit/Pixel)
00h
00h
00h
38h
80h
62h
w
w
w
Gamma setting
RGB for 256, 4k and 65k Color Mode
Partial: Start Address (PSL)
Partial: End Address (PEL)
Scroll: Vertical scrolling
Scroll: Top Fixed Area (TFA)
Scroll: Scroll Area (VSA)
Scroll: Bottom Fixed Area (BFA)
Scroll Start Address (SSA)
Tearing: On/Off
Tearing Effect Mode *3)
Memory Data Access Control
(MY/MX/MV/ML/RGB)
Interface Pixel Color Format
RDDPM
RDDMADCTR
RDDCOLMOD
RDDIM
RDDSM
RDDSDR
ID1
ID2
ID3
m
Row: Start Address (YS)
Notes 1. There will be no abnormal visible effects on the display when S/W or H/W Reset is applied.
Notes:2. Powered-On Reset finishes within 10µs after both VDD & VDDI are applied.
Notes:3. TE Mode 1 means Tearing Effect Output Line consists of V-Blanking Information only.
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Preliminary
SPFD54126B
7.13.1.2. Reset Table (GM=01, 176RGB x 176)
After Hardware Reset
No Change
In
Off
Normal
Off
Off
0000h
After Software Reset
No Change
In
Off
Normal
Off
Off
0000h
Column: End Address (XE)
00AFh
00AFh
00AFh (175d) (when MV=0)
00AFh (175d) (when MV=1)
Row: Start Address (YS)
0000h
0000h
0000h
00DBh
00DBh
00AFh (175d) (when MV=0)
00AFh (175d) (when MV=1)
GC0
See Section 6.14
0000h
00AFh
Off
0000h
00AFh
0000h
0000h
Off
0 (Mode1)
GC0
See Section 6.14
0000h
00AFh
Off
0000h
00AFh
0000h
0000h
Off
0 (Mode1)
GC0
No Change
0000h
00AFh
Off
0000h
00AFh
0000h
0000h
Off
0 (Mode1)
0/0/0/0/0
No Change
6 (18-Bit/Pixel)
08h
00h
6 (18-Bit/Pixel)
00h
00h
00h
38h
80h
62h
No Change
08h
No Change
No Change
00h
00h
00h
38h
80h
62h
Row: End Address (YE)
re
0/0/0/0/0
w
w
.m
bt
6 (18-Bit/Pixel)
08h
00h
6 (18-Bit/Pixel)
00h
00h
00h
38h
80h
62h
w
Gamma setting
RGB for 256, 4k and 65k Color Mode
Partial: Start Address (PSL)
Partial: End Address (PEL)
Scroll: Vertical scrolling
Scroll: Top Fixed Area (TFA)
Scroll: Scroll Area (VSA)
Scroll: Bottom Fixed Area (BFA)
Scroll Start Address (SSA)
Tearing: On/Off
Tearing Effect Mode *3)
Memory Data Access Control
(MY/MX/MV/ML/RGB)
Interface Pixel Color Format
RDDPM
RDDMADCTR
RDDCOLMOD
RDDIM
RDDSM
RDDSDR
ID1
ID2
ID3
m
After Power On
Random
In
Off
Normal
Off
Off
0000h
nd
.co
Item
Frame memory
Sleep In/Out
Display On/Off
Display mode (normal/partial)
Display Inversion On/Off
Display Idle Mode On/Off
Column: Start Address (XS)
Notes 1. There will be no abnormal visible effects on the display when S/W or H/W Reset is applied.
Notes:2. Powered-On Reset finishes within 10µs after both VDD & VDDI are applied.
Notes:3. TE Mode 1 means Tearing Effect Output Line consists of V-Blanking Information only.
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Preliminary
SPFD54126B
7.13.1.3. Reset Table (GM=11, 176RGB x 132)
After Hardware Reset
No Change
In
Off
Normal
Off
Off
0000h
After Software Reset
No Change
In
Off
Normal
Off
Off
0000h
Column: End Address (XE)
00AFh
00AFh
00AFh (175d) (when MV=0)
0083h (131d) (when MV=1)
Row: Start Address (YS)
0000h
0000h
0000h
00DBh
00DBh
0083h (131d) (when MV=0)
00AFh (175d) (when MV=1)
GC0
See Section 6.14
0000h
0083h
Off
0000h
0083h
0000h
0000h
Off
0 (Mode1)
GC0
See Section 6.14
0000h
0083h
Off
0000h
0083h
0000h
0000h
Off
0 (Mode1)
GC0
No Change
0000h
0083h
Off
0000h
0083h
0000h
0000h
Off
0 (Mode1)
0/0/0/0/0
No Change
6 (18-Bit/Pixel)
08h
00h
6 (18-Bit/Pixel)
00h
00h
00h
38h
80h
62h
No Change
08h
No Change
No Change
00h
00h
00h
38h
80h
62h
Row: End Address (YE)
re
0/0/0/0/0
w
w
.m
bt
6 (18-Bit/Pixel)
08h
00h
6 (18-Bit/Pixel)
00h
00h
00h
38h
80h
62h
w
Gamma setting
RGB for 256, 4k and 65k Color Mode
Partial: Start Address (PSL)
Partial: End Address (PEL)
Scroll: Vertical scrolling
Scroll: Top Fixed Area (TFA)
Scroll: Scroll Area (VSA)
Scroll: Bottom Fixed Area (BFA)
Scroll Start Address (SSA)
Tearing: On/Off
Tearing Effect Mode *3)
Memory Data Access Control
(MY/MX/MV/ML/RGB)
Interface Pixel Color Format
RDDPM
RDDMADCTR
RDDCOLMOD
RDDIM
RDDSM
RDDSDR
ID1
ID2
ID3
m
After Power On
Random
In
Off
Normal
Off
Off
0000h
nd
.co
Item
Frame memory
Sleep In/Out
Display On/Off
Display mode (normal/partial)
Display Inversion On/Off
Display Idle Mode On/Off
Column: Start Address (XS)
Notes 1. There will be no abnormal visible effects on the display when S/W or H/W Reset is applied.
Notes:2. Powered-On Reset finishes within 10µs after both VDD & VDDI are applied.
Notes:3. TE Mode 1 means Tearing Effect Output Line consists of V-Blanking Information only.
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Preliminary
SPFD54126B
7.13.2. Module Input/Output Pins
7.13.2.1. Output or Bi-directional (I/O) Pins
Output or Bi-directional pins
After Power On
After Hardware Reset
After Software Reset
TE
Low
Low
Low
D7 to D0 (Output driver)
High-Z (Inactive)
High-Z (Inactive)
High-Z (Inactive)
Note: There will be no output from D7-D0 during Power On/Off sequence, Hardware Reset and Software Reset.
7.13.2.2. Input Pins
During Power On
Process
After Power On
After Hardware
Reset
After Software
Reset
During Power Off
Process
RESX
See 6.10
Input valid
Input valid
Input valid
See 6.10
CSX
Input invalid
Input valid
Input valid
D/CX
Input invalid
Input valid
Input valid
WRX
Input invalid
Input valid
RDX
Input invalid
Input valid
D7 to D0
Input invalid
Input valid
P/SX
Input invalid
Input valid
m
Input pins
Input invalid
Input valid
Input invalid
Input valid
Input valid
Input invalid
Input valid
Input valid
Input invalid
Input valid
Input valid
Input invalid
Input valid
Input invalid
re
nd
.co
Input valid
w
w
w
.m
bt
Input valid
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Preliminary
SPFD54126B
7.13.3. Reset Timing
Shorter than 5µs
tRESW
!RES
RESX
tREST
Internal Status
Initial Condition
(Default for H/W reset)
Resetting
Normal Operation
Table 7.13.3.1 Reset input timing
m
VSS=0V, VDDI=1.6V to 3.6V, VDD=2.6V to 3.5V,Ta = -30 to 70°C)
Parameter
Related Pins
MIN
TYP
MAX
tRESW
*1) Reset low pulse width
RESX
10
-
-
tREST
-
*2) Reset complete time
-
5
-
120
re
-
nd
.co
Symbol
Note
Unit
-
µs
When reset applied during
Sleep in mode
When reset applied during
Sleep out mode
ms
ms
Note 1) Spike due to an electrostatic discharge on RESX line does not cause irregular system reset according to the table below.
bt
RESX Pulse
Shorter than 5µs
Reset Rejected
.m
Longer than 10µs
w
Between 5µs and 10µs
Action
Reset
Reset starts
(It depends on voltage and temperature condition.)
w
Note 2. During the resetting period, the display will be blanked (The display is entering blanking sequence, which maximum time is 120 ms,
when Reset Starts in Sleep Out –mode. The display remains the blank state in Sleep In –mode) and then return to Default condition
for H/W reset.
w
Note 3. During Reset Complete Time, ID2 and VCOMOF value in OTP will be latched to internal register during this period. This loading is
done every time when there is H/W reset complete time (tREST) within 5ms after a rising edge of RESX.
Note 4. Spike Rejection also applies during a valid reset pulse as shown below:
10µs
Reset is accepted
10µs
Note 5. It is necessary to wait 5msec after releasing RESX before sending commands. Also Sleep Out command cannot be sent for
120msec.
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Preliminary
SPFD54126B
7.14.
Colour Depth Conversion Look Up Tables
7.14.1. 4096 and 65536 Colour to 262,144 Colour
RGBSET
Parameter
000000
000100
001000
001100
010001
010101
011001
011101
100010
100110
101010
101110
110011
110111
111011
111111
000000
000010
000100
000110
001000
001010
001100
001110
010000
010010
010100
010110
011000
011010
011100
011110
100001
100011
100101
100111
101001
101011
101101
101111
110001
110011
110101
110111
111001
111011
111101
111111
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
w
© ORISE Technology Co., Ltd.
Proprietary & Confidential
re
bt
Not Used
Look Up Table Input Data
203
4k Colour
65k Colour
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
00000
00001
00010
00011
00100
00101
00110
00111
01000
01001
01010
01011
01100
01101
01110
01111
10000
10001
10010
10011
10100
10101
10110
10111
11000
11001
11010
11011
11100
11101
11110
11111
m
65k Colour
nd
.co
4k Colour
.m
RED
R005R004 R003 R002 R001 R000
R015R014 R013 R012 R011 R010
R025R024 R023 R022 R021 R020
R035R034 R033 R032 R031 R030
R045R044 R043 R042 R041 R040
R055R054 R053 R052 R051 R050
R065R064 R063 R062 R061 R060
R075R074 R073 R072 R071 R070
R085R084 R083 R082 R081 R080
R095R094 R093 R092 R091 R090
R105R104 R103 R102 R101 R100
R115R114 R113 R112 R111 R110
R125R124 R123 R122 R121 R120
R135R134 R133 R132 R131 R130
R145R144 R143 R142 R141 R140
R155R154 R153 R152 R151 R150
R165R164 R163 R162 R161 R160
R175R174 R173 R172 R171 R170
R185R184 R183 R182 R181 R180
R195R194 R193 R192 R191 R190
R205R204 R203 R202 R201 R200
R215R214 R213 R212 R211 R210
R225R224 R223 R222 R221 R220
R235R234 R233 R232 R231 R230
R245R244 R243 R242 R241 R240
R255R254 R253 R252 R251 R250
R265R264 R263 R262 R261 R260
R275R274 R273 R272 R271 R270
R285R284 R283 R282 R281 R280
R295R294 R293 R292 R291 R290
R305R304 R303 R302 R301 R300
R315R314 R313 R312 R311 R310
Default value after H/W Reset
w
Look Up Table Outputs
Frame Memory Data (6-bit)
w
Colour
Not Used
Apr. 25, 2006
Preliminary Version: 0.1
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Preliminary
SPFD54126B
65k Colour
RGBSET
Parameter
000000
000100
001000
001100
010001
010101
011001
011101
100010
100110
101010
101110
110011
110111
111011
111111
000000
000001
000010
000011
000100
000101
000110
000111
001000
001001
001010
001011
001100
001101
001110
001111
010000
010001
010010
010011
010100
010101
010110
010111
011000
011001
011010
011011
011100
011101
011110
011111
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
nd
.co
re
bt
Not Used
Look Up Table Input Data
4k Colour
65k Colour
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
000000
000001
000010
000011
000100
000101
000110
000111
001000
001001
001010
001011
001100
001101
001110
001111
010000
010001
010010
010011
010100
010101
010110
010111
011000
011001
011010
011011
011100
011101
011110
011111
m
4k Colour
.m
GREEN
G005 G004 G003 G002 G001 G000
G015 G014 G013 G012 G011 G010
G025 G024 G023 G022 G021 G020
G035 G034 G033 G032 G031 G030
G045 G044 G043 G042 G041 G040
G055 G054 G053 G052 G051 G050
G065 G064 G063 G062 G061 G060
G075 G074 G073 G072 G071 G070
G085 G084 G083 G082 G081 G080
G095 G094 G093 G092 G091 G090
G105 G104 G103 G102 G101 G100
G115 G114 G113 G112 G111 G110
G125 G124 G123 G122 G121 G120
G135 G134 G133 G132 G131 G130
G145 G144 G143 G142 G141 G140
G155 G154 G153 G152 G151 G150
G165 G164 G163 G162 G161 G160
G175 G174 G173 G172 G171 G170
G185 G184 G183 G182 G181 G180
G195 G194 G193 G192 G191 G190
G205 G204 G203 G202 G201 G200
G215 G214 G213 G212 G211 G210
G225 G224 G223 G222 G221 G220
G235 G234 G233 G232 G231 G230
G245 G244 G243 G242 G241 G240
G255 G254 G253 G252 G251 G250
G265 G264 G263 G262 G261 G260
G275 G 274 G273 G272 G271 G270
G285 G 284 G283 G282 G281 G280
G295 G 294 G293 G292 G291 G290
G305 G 304 G303 G302 G301 G300
G315 G 314 G313 G312 G311 G310
Default value after H/W Reset
w
Look Up Table Outputs
Frame Memory Data (6-bit)
Not Used
w
w
Colour
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Preliminary
SPFD54126B
RGBSET
parameter
100000
100001
100010
100011
100100
100101
100110
100111
101000
101001
101010
101011
101100
101101
101110
101111
110000
110001
110010
110011
110100
110101
110110
110111
111000
111001
111010
111011
111100
111101
111110
111111
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
bt
re
nd
.co
Not Used
65k Colour
Look Up Table Input Data
4k Colour
m
4k Colour
.m
GREEN
G325 G324 G323 G322 G321 G320
G335 G334 G333 G332 G331 G330
G345 G344 G343 G342 G341 G340
G355 G354 G353 G352 G351 G350
G365 G364 G363 G362 G361 G360
G375 G374 G373 G372 G371 G370
G385 G384 G383 G382 G381 G380
G395 G394 G393 G392 G391 G390
G405 G404 G403 G402 G401 G400
G415 G414 G413 G412 G411 G410
G425 G424 G423 G422 G421 G420
G435 G434 G433 G432 G431 G430
G445 G444 G443 G442 G441 G440
G455 G454 G453 G452 G451 G450
G465 G464 G463 G462 G461 G460
G475 G474 G473 G472 G471 G470
G485 G484 G483 G482 G481 G480
G495 G494 G493 G492 G491 G490
G505 G504 G503 G502 G501 G500
G515 G514 G513 G512 G511 G510
G525 G524 G523 G522 G521 G520
G535 G534 G533 G532 G531 G530
G545 G544 G543 G542 G541 G540
G555 G554 G553 G552 G551 G550
G565 G564 G563 G562 G561 G560
G575 G574 G573 G572 G571 G570
G585 G584 G583 G582 G581 G580
G595 G594 G593 G592 G591 G590
G605 G604 G603 G602 G601 G600
G615 G614 G613 G612 G611 G610
G625 G624 G623 G622 G621 G620
G635 G634 G633 G632 G631 G630
Default value after H/W Reset
w
Look Up Table Outputs
Frame Memory Data (6-bit)
Not Used
65k Colour
100000
100001
100010
100011
100100
100101
100110
100111
101000
101001
101010
101011
101100
101101
101110
101111
110000
110001
110010
110011
110100
110101
110110
110111
111000
111001
111010
111011
111100
111101
111110
111111
w
w
Colour
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Preliminary
SPFD54126B
65k Colour
RGBSET
parameter
000000
000100
001000
001100
010001
010101
011001
011101
100010
100110
101010
101110
110011
110111
111011
111111
000000
000011
000101
000111
001001
001011
001101
001111
010001
010011
010101
010111
011001
011011
011101
011111
100001
100011
100101
100111
101001
101011
101101
101111
110001
110011
110101
110111
111001
111011
111101
111111
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
nd
.co
re
bt
Not Used
Look Up Table Input Data
4k Colour
65k Colour
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
00000
00001
00010
00011
00100
00101
00110
00111
01000
01001
01010
01011
01100
01101
01110
01111
10000
10001
10010
10011
10100
10101
10110
10111
11000
11001
11010
11011
11100
11101
11110
11111
m
4k Colour
.m
BLUE
B005B004 B003 B002 B001 B000
B015B014 B013 B012 B011 B010
B025B024 B023 B022 B021 B020
B035B034 B033 B032 B031 B030
B045B044 B043 B042 B041 B040
B055B054 B053 B052 B051 B050
B065B064 B063 B062 B061 B060
B075B074 B073 B072 B071 B070
B085B084 B083 B082 B081 B080
B095B094 B093 B092 B091 B090
B105B104 B103 B102 B101 B100
B115B114 B113 B112 B111 B110
B125B124 B123 B122 B121 B120
B135B134 B133 B132 B131 B130
B145B144 B143 B142 B141 B140
B155B154 B153 B152 B151 B150
B165B164 B163 B162 B161 B160
B175B174 B173 B172 B171 B170
B185B184 B183 B182 B181 B180
B195B194 B193 B192 B191 B190
B205B204 B203 B202 B201 B200
B215B214 B213 B212 B211 B210
B225B224 B223 B222 B221 B220
B235B234 B233 B232 B231 B230
B245B244 B243 B242 B241 B240
B255B254 B253 B252 B251 B250
B265B264 B263 B262 B261 B260
B275B274 B273 B272 B271 B270
B285B284 B283 B282 B281 B280
B295B294 B293 B292 B291 B290
B305B304 B303 B302 B301 B300
B315B314 B313 B312 B311 B310
Default value after H/W Reset
w
Look Up Table Outputs
Frame Memory Data (6-bit)
Not Used
w
w
Colour
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Preliminary
SPFD54126B
7.15.
Sleep Out-Command and Self-Diagnostic Functions of the Display Module
7.15.1. Register Loading Detection
Sleep Out-command is a trigger for an internal function of the display module, which indicates, if the display module loading function of
factory default values from OTP (one-time programming memory) to registers of the display controller is working properly.
There are compared factory values of the OTP and register values of the display controller by the display controller. If those both values
(OTP and register values) are same, there is inverted (=increased by 1) a bit in “Read Display Self-Diagnostic Result (0Fh)” (=RDDSDR)
(The used bit of this command is D7). If those both values are not same, this bit (D7) is not inverted (= increased by 1).
The flow chart for this internal function is following:
Power on sequence
HW reset
SW reset
nd
.co
Sleep Out Mode
m
Sleep In (10h)
Sleep In Mode
bt
re
Sleep Out (11h)
RDDSDR’s D7=0
Compares OTP and
register values
w
No
w
w
.m
Loads values from
OTP to registers
Are OTP and register
values same ?
Yes
D7 inverted
Note: There is not compared and loaded register values, which can be changed by user (00h to AFh and DAh to DDh), by the display
module.
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SPFD54126B
7.15.2. Functionality Detection
Sleep Out-command is a trigger for an internal function of the display module, which indicates, if the display module is still running and
meets functionality requirements.
The internal function (= the display controller) is comparing, if the display module is still meeting functionality requirements (only Booster
voltage level). If functionality requirement is met, there is inverted (= increased by 1) a bit in “Read Display Self- Diagnostic Result (0Fh)” (=
RDDSDR) (The used bit of this command is D6). If functionality requirement is not same, this bit (D6) is not inverted (= increased by 1).
The flow chart for this internal function is following:
Power on sequence
HW reset
SW reset
Sleep In Mode
RDDSDR’s D6=0
re
Sleep Out (11h)
nd
.co
Sleep Out Mode
m
Sleep In (10h)
w
.m
bt
Checks Booster voltage levels
and other functionalities
w
w
No
Is functionality
requirement met ?
Yes
D6 inverted
Note: There is needed 120msec after Sleep Out -command, when there is changing from Sleep In –mode to Sleep Out -mode, before there
is possible to check if functionality requirements are met and a value of RDDSDR’s D6 is valid. Otherwise, there is 5msec delay for
D6’s value, when Sleep Out –command is sent in Sleep Out -mode.
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SPFD54126B
7.15.3. Chip Attachment Detection
Sleep Out-command is a trigger for an internal function of the display module, which indicates, if a chip or chips (e.g. driver, etc.) of the
display module is/are attached to the circuit route of a flex foil or display glass ITO.
There is inverted (= increased by 1) a bit in command “Read Display Self- Diagnostic Result (0Fh)” (= RDDSDR) (The used bit of this
command is D5), if the chip or chips is/are attached to the circuit route of the flex or display glass. If this chip is or those chips are not
attached to the circuit route of the flex or display glass, this bit (D5) is not inverted (= increased by 1).
The following figure is for reference purposes; how this chip attachment can be implemented e.g. there are connected together 2 bumps via
route of ITO or the flex foil on 4 corners of the driver (chip).
Routing
between
bumps
nd
.co
Through view of driver to
m
Bump
re
Substrate of display glass
Routing
between
bumps
.m
bt
The flow chart for this internal function is following:
w
Sleep In (10h)
Sleep In Mode
RDDSDR’s D5=0
w
w
Sleep Out Mode
Power on sequence
HW reset
SW reset
Sleep Out (11h)
Checks, if chip is attached to
route
No
Is chip attached to
routes?
Yes
D5 inverted
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Preliminary
SPFD54126B
7.15.4. Display Glass Break Detection
Sleep Out-command is a trigger for an internal function of the display module, which indicates, if the display glass of the display module is
broken or not.
There is inverted (= increased by 1) a bit in “Read Display Self-Diagnostic Result (0Fh)” (= RDDSDR) (The used bit of this command is D4),
if the display glass is not broken. If this display glass is broken, this bit (D4) is not inverted (= increased by 1).
The following figure is a reference, how this glass break detection can be implemented e.g. there is connected together 2 bumps via route
of ITO. This route of ITO is the nearest route of the edge of the display glass.
nd
.co
m
Active area of the display glass
bt
re
Through view of driver to
w
.m
Substrate of display glass
w
w
The flow chart for this internal function is following:
Sleep In (10h)
Sleep Out Mode
Sleep In Mode
Power on sequence
HW reset
SW reset
RDDSDR’s D4=0
Sleep Out (11h)
Checks, if display glass is broken
Yes
Is the display glass
broken?
No
D4 inverted
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SPFD54126B
7.16.
Oscillator
The chip has on-chip oscillator that does not require external components. This oscillator output signal is used for system clock generation
for internal display operation.
7.17.
System Colck Generator
The timing generator produces the various signals to dirver the internal circuitty. Internal chip operation is not affected by operations on the
data bus.
7.18.
Instruction Decoder and Register
Source Driver
nd
.co
7.19.
m
The instruction decoder indentifies command words arriving at the interface and routes the following data bytes to their destination. The
command set can be found in “ Command” section.
The source driver block includes 176x3 source outputs (S1 to S528), which should be connected directly to the TFT-LCD. The source
output signals are generated in the data processing block after the data is read out of the RAM and latched, which represent the
simulatance selected rows.
Gate Driver
re
7.20.
bt
The gate dirver block include 220 chanel gate output (G1 to G220) which should be connected directly to the TFT-LCD.
S1-S528
1
2
3
G5
7
8
9
10
11
12
w
G4
6
w
G2
G3
5
w
G1
4
.m
7.20.1. Gate Driver
G6
G7
VGH
G8
VGL
G9
G10
G11
G12
Fig. 7.20.1 Gate Driver Output Option 1
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SPFD54126B
7.21.
γ-CORRECTION FUNCTION
The SPFD54126B adopts true 6-bit OP-AMP with adjustable γ -correction function to display in 262,144 colors. The adjustable γ
-correction can be set by 10 groups of registers to determine eight reference grayscale levels, which are gradient adjustment, amplitude
adjustment and fine-adjustment registers. Each register group can be set independently to other register groups.
7.22.
VSYNC Interface
The SPFD54126 incorporates a VSYNC-I/F, which enables to display a moving picture with only a system interface and
frame-synchronizing signal (VS). This interface enables to display moving pictures with minimum modification to a conventional system.
SPFD54126
Host
RESX
RESX
TE
VS
VS
‘0’
SCL
nd
.co
‘0’
SDA
‘0’
SPI_CSX
CSX
CSX
D/CX (SCL)
D/CX
WRX (R/WX)
RDX (E)
WRX (R/WX)
re
RDX (E)
D7 to D1
D7 to D1
bt
D0
“0”
.m
“0”
w
IM1, IM0
IM2 = ‘1’
IM2
HS, DE
w
w
D15 to D8
P68
“00”
IM2=’1’, MCU I/F
P68=’0’, 8080-MCU I/F
P68=’1’, 6800-MCU I/F
D0
D17 to D16
‘0’ or ‘1’
Note:
RCM = ‘01’
m
TE
RPCLK
DGND
Fig. 7.21.1 VSYNC Interface for 8-bits data bus (Example)
The VSYNC-I/F is truned ON by VSYNC-I/F ON (ADH) command and turned OFF by VSYNC-I/F OFF (ACH) command. In VSYNC-I/F
mode, internal display operations are synchronized with VS. The VSYNC-I/F enables to display a moving picture through a system interface
and update screens without flicker by writing data to RAM through a system interface in higher speed than the internal display operations by
some degree.
The VSYNC-I/F executes display operations only with internal clocks generated by internal oscillators and VS input. All display data are
stored in RAM so that only the data relevant to updating a screen are transferred to minimize data transmission while displaying a moving
picture.
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- Leading Mode
(1)
Internal Frame
Sync. Signal
(3)
(4)
(5)
(6)
(7)
1 Frame
L1
L220
L1
L90
A
L1
A
14H
2H 14H
External
VS Signal
L220
L1
L220
B
L1
B
14H
L1
L220
B
2H 14H
C
2H 14H
> 1H
14H
2H
> 1H
L1
RAM Update
Write D[B:0]
L90
L1
B
C
> 2H
> 2H
m
Display
Operation
(2)
< 1Frame
(1)
(2)
nd
.co
A BB B B CC
(1)
(2)
Internal Frame
Sync. Signal
L1
L90
L1
L220
14H
L220
(7)
w
(4)
L1
L90
(5)
L1
2H 14H
L1
B
2H 14H
L1
L1
C
> 2H
> 2H
> 1Frame
(1)
2H
> 16H
B
A
L220
C
14H
> 1H
(6)
L220
B
B
2H 14H
> 16H
> 1H
RAM Update
Write D[B:0]
L1
(3)
w
External
VS Signal
A
w
A
14H
.m
1 Frame
bt
- Lagging Mode
Display
Operation
(4)
re
(3)
(6)
(1)
A
(2)
> 1Frame
B
(3)
B
(4)
B
(5)
C
(6)
1. In RCM1, RCM0 = “01” mode, writing data to RAM on rising edge of VS signal
2. If high pulse of VS signal shoule large than 1-lines.
3. The BP and FP should follow conditions : BP ≧2-lines , FP≧2-lines and BP+FP = 16-lines
4. The signals (CSX, WRX, D/CX and VS) of VSYNC I/F should follow MCU Parallel Interface AC timing.
5. B=17.
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The VSYNC-I/F has limits on the minimum RAM write speed through the system interface and the frequency of the internal clocks. It
requires a RAM write speed more than the calculated result from the following formula.
- Internal clock frequency (fosc) [Hz]
= Frame Frequency x (DisplayLines +Front Porch(VSFP)+BackPorch (VSBP)) x 16(clocks) x fluctuation
RAM Write Speed (Min) (Hz) =
176 × Display Line (220 Line)
BackPorch (VSBP ) + Display Line − m arg ins ) x16 (clocks ) × 1
fosc
nd
.co
m
Note 1: When RAM write does not start right after the falling edge of VS, the time from the falling edge of VS until RAM write starts must
also be taken into account.
Example of RAMs writes speed and the frequency of the internal clocks in VSYNC-I/F mode is as follows.
Example:
Display size: 176 RGB × 220 lines
re
Raster-rows: 220 lines
-When Frame frequency: 60 Hz
w
Internal clock frequency (fosc) [Hz] =
.m
bt
Back/ Front porch: 14/ 2 lines (VSBP = 1110/ VSFP = 0010 of AFH)
w
60Hz × (220+2+14) lines × 16 Clocks × 1.1 / 0.9 = 277kHz
w
When calculating an internal clock frequency, possible causes of fluctuations must also be taken into consideration. In this example, the
allowance for the fluctuation is ± 10 % from the center value, and the frequency must be within a VS cycle.
Also in this example, variations attributed to LSI fabrication and room temperature are taken into consideration as causes of fluctuations.
Other possible causes of fluctuations, such as variations in external resistors or voltage changes are not considered in this example. It is
necessary to make a setting with enough margins to accommodate
-When Frame frequency: 60Hz
Minimum speed for RAM writing [Hz] >
176 × 220 / {((14+220-2) lines × 16 clock) / 300 kHz} = 2.89MHz
Note 2: The above calculation is premised on the case of writing data to RAM on the falling edge of VS.
Note 3: There must at least be a margin of 2 processing lines when all one-frame data are written to RAM before the SPFD54126 starts
processing display lines.
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By writing data to RAM on rising edge of VS signal at speed of 2.89MHz (Frame rate=60Hz) or more, it is possible to overwrite an entire
screen without flicker by completing data write operation of a line before it starts display operation of that line.
Display
Operation
220
RAM Write
RAM write at
2.89MHz
Line Processing
Display
Operation
Display (220-lines)
Display
Operation
Front Porch (2-lines)
0
4.22
13.41
nd
.co
Blanking period
m
Back Porch (14-lines)
RC oscillation
10%
RAM write at 10MHz
38,720 times
Lines
VS
Back porch (14-lines)
VS
ms
13.55
16.74
(60Hz)
bt
re
Fig. 7.28.3 Write/Display Operation Timing via VSYNC-I/F
Notes to the VSYNC Interface
.m
1. The aforementioned example of calculation is just a result of calculation. In actual settings, possible causes of fluctuations should be
taken into consideration. It is necessary to give enough margins when setting a RAM writing speed.
w
w
w
2. The aforementioned example of calculation is the value in case of overwriting full screen. If a moving picture display area is limited, it will
result in more margins between RAMs write and display operations.
Back Porch (14-lines)
16-lines
RAM Write
205
Display
Operation
Moving picture area
(188-lines)
16-lines
Front Porch (2-lines)
Blanking period
Display
Operation
220
Line Processing
VS
RC oscillation
10%
Lines
RAM write at
3.15MHz
Display
Operation
17
ms
0
11.17
Back porch (14-lines)
13.55
16.74
(60Hz)
VS
Fig. 7.28.4 RAM write speed margin
3. A front porch period continues after completion of 1 frame and until the next input of VS.
4. The partial display and vertical scroll functions are not available with the VSYNC-I/F.
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8. ELECTRICAL SPECIFICATIONS
DC CharacteristicAC Characteristic (VDD=2.6V~3.0V, VDDIO = 1.6V~3.0V, Ta = -40℃ ~ 85℃)
Source output settling time
Output deviation voltage
(Source output channel)
Output offset voltage
Booster Operation
Internal reference voltage
1st Booster (VDDx2) voltage
1st Booster (VDDx2) Drop
voltage
Linear range
Conditions
VDD
VDDI
VGH
VGL
Operating Voltage
I/O supply voltage-
MIN
Specification
TYP
MAX
Unit Related Pins
3.5
3.6
13.5
-9.0
30
V
V
V
V
V
Note 2
Note 2
Note 3
Note 3
Note 3
VIH
VIL
-
0.7VDDI
VSS
-
VDDI
0.3VDDI
V
V
Note 1, 2, 3
Note 1, 2, 3
VOH
IOH = -1.0mA
0.8VDDI
-
VDDI
V
Note 1, 2, 3
VOL
IIH
IIL
IIL
IOL = +1.0mA
VSS
-
0.2VDDI
1
VIN = VDDI or VSS
-1
-0.1
-
+0.1
V
µA
µA
µA
Note 1, 2, 3
Note 1, 2, 3
Note 1, 2, 3
Note 1, 2, 3
VCOMH
VCOML
VCOMA
Ccom=19nF
Ccom=19nF
|VCOMH-VCOML|
2.5
-2.5
4.0
5.0
0.0
6.0
V
V
V
Note 3
Note 3
Note 3
0.1
3.0
AVDD-0.1
5.0
V
V
Note 4
Note 3
30
µs
Note 4, 5
20
15
35
mV
mV
mv
Note 6
1
5.5 *7)
%
V
Note 3
Note 3
5%
%
Note 3
AVDD-0.2
V
Tr
nd
.co
re
bt
.m
VSout
GVDD
V,dev
m
2.78
1.8/2.78
|VGH-VGL|
2.6
1.6
10.0
-11.5
19
w
Power & Operation Voltage
Analog Operating voltage
Logic Operating voltage
Gate Driver High voltage
Gate Driver Low voltage
Driver Supply voltage
Input / Output
Logic High level input voltage
Logic Low level input voltage
Logic High level output
voltage
Logic Low level output voltage
Logic High level input current
Logic Low level input current
Logic Input leakage current
VCOM Operation
VCOM High voltage
VCOM Low voltage
VCOM Amplitude voltage
Source Driver
Source output range
Gamma reference voltage
Symbol
Below with 99%
precision
25
w
Parameter
w
8.1.
Sout >=4.2V, Sout<=0.8V
4.2V>Sout>0.8V
VOFSET
VREF
AVDD
VDDx2,d
rop
4.75 *6)
I AVDD = 1.3mA
(include Panel loading)
VLinear
0.2
Note 4
Note 1: VDD1=1.6 to 3.6V, VDD=2.6 to 3.5V, AGND=DGND=0V, Ta=-30 to 70℃ (to +85℃ no damage)
Note 2, 3, 4: When the measurements are performed with LCD module, Measurement Points are like below.
Note 3: CSX, RDX, WRX, D[17:0], D/CX, RESX, TE, PCLK, P/SX, VS, HS, DE, DIN, DOUT, SCL, GM1, GM0, LCM, RCM,
P68, IM2, IM1, IM0, SRGB, SINV, SMX, SMY and Test pins
Note 5, Source channel loading= 15pF/channel, Gate channel loading= 50pF/channel.
Note 6, The Max. value is between with Note 4 measure point and Gamma setting value.
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8.2.
AC timing Characteristics
8.2.1.
Parallel Interface Characteristics 18, 16 ,9 or 8-bits bus (8080-series MCU)
TCHW
TCHW
CSX
VIH
TCSF
VIL
TCSH
TCS
D/CX
TCSF
VIH
VIL
TAST
TAHT
TWC
VIH
WRX
TWRL
TWRH
m
VIL
D[17:0]
Write
VIH
VIL
TRCS/TRCSFM
TAST
TDHT
TAHT
re
TRC/TRCFM
VIH
RDX
nd
.co
TDST
TRDL/TRDLFM
D[17:0]
Read
TODH
.m
TRAT/ TRATFM
TRDH/ TRDHFM
bt
VIL
VIH
w
VIL
w
Fig. 8.2.1.1 Parallel Interface characteristics (8080-Series MCU)
Signal
D/CX
CSX
WRX
RDX (ID)
RDX (FM)
D[17:0]
Symbol
TAST
TAHT
TCHW
TCS
TRCS
TRCSFM
TCSF
TCSH
TWC
TWRH
TWRL
TRC
TRDH
TRDL
TRCFM
TRDHFM
TRDLFM
TDST
TDHT
TRAT
TRATFM
TODH
w
Table 8.2.1.1: AC Characteristics for Parallel Interface18, 16, 9, 8-bits bus (8080-series MCU)
Parameter
MIN
Address setup time
Address hold time (Write/Read)
Chip select “H” pulse width
Chip select setup time (Write)
Chip select setup time (Read ID)
Chip select setup time (Read FM)
Chip select wait time (Write/Read)
Chip select hold time
Write cycle
Control pulse “H” duration
Control pulse “L” duration
Read cycle (ID)
Control pulse “H” duration (ID)
Control pulse “L” duration (ID)
Read cycle (FM)
Control pulse “H” duration (FM)
Control pulse “L” duration (FM)
Data setup time
Data hold time
Read access time (ID)
Read access time (FM)
Output disable time
MAX
Unit
40
340
80
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
10
10
0
35
45
355
10
10
100
35
35
160
90
45
450
90
355
10
10
20
Description
-
-(3-transfer for one pixel)
When read ID data
When read from frame memory
For maximum CL=30pF
For minimum CL=8pF
Note 1: VDD1=1.6 to 3.6V, VDD=2.6 to 3.5V, AGND=DGND=0V, Ta=-30 to 70℃ (to +85℃ no damage)
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Proprietary & Confidential
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Preliminary Version: 0.1
Evaluation Only. Created with Aspose.Pdf.Kit. Copyright 2002-2005 Aspose Pty Ltd
Preliminary
SPFD54126B
Input Signal Slope
Output Signal
TR
TF
TR
TF
VIH=0.7*VDDI
VIL=0.3*VDDI
VOH=0.8*VDDI
VOL=0.2*VDDI
TR=TF<= 15ns
TR=TF<= 15ns
VIH
CSX
VIL
VIL
Min. 5ns
.m
TCSF
bt
VIH
WRX
RDX
TCHW
re
nd
.co
m
Fig. 8.2.1.2 Rising and Falling timing for Input and Output signal
w
w
Fig.8.2.1.3 Chip selection (CSX) timing
WRX
w
CSX
VIH
VIH
VIL
VIL
VIH
RDX
TWRH
VIL
TWRH /TRDHFM
Fig. 8.2.1.4 Write to read and Read to write timing
NOTE: The input signal rise time and fall time (Tr, Tf) is specified at 15 ns or less.
Logic high and low levels are specified as 30% and 70% of VDDI for Input signals.
© ORISE Technology Co., Ltd.
Proprietary & Confidential
218
Apr. 25, 2006
Preliminary Version: 0.1
Evaluation Only. Created with Aspose.Pdf.Kit. Copyright 2002-2005 Aspose Pty Ltd
Preliminary
SPFD54126B
8.3.
Parallel Interface Characteristics 18, 16 ,9 or 8-bits bus (6800-series MCU)
TCHW
CSX
TCS
TRCS/TRCSFM
VIH
VIL
TCSH
TCSF
VIH
D/CX
VIL
TAHT
TAST
VIH
TWC
VIL
VIH
TDST
VIL
TDHT
VIH
TRC/TRCFM
VIL
TRDL/TRDLFM
TRDH/ TRDHFM
VIL
bt
TRAT/ TRATFM
VIH
TODH
VIL
.m
D[17:0]
Read
re
VIH
E
m
TWRH
VIL
D[17:0]
Write
RX
TWRL
VIH
E
nd
.co
/WX
w
Fig. 8.3.1 Parallel Interface characteristics (6800-Series MCU)
D/CX
CSX
WRX
RDX (ID)
RDX (FM)
D[17:0]
Symbol
TAST
TAHT
TCHW
TCS
TRCS
TRCSFM
TCSF
TCSH
TWC
TWRH
TWRL
TRC
TRDH
TRDL
TRCFM
TRDHFM
TRDLFM
TDST
TDHT
TRAT
TRATFM
TODH
Parameter
MIN
Address setup time
Address hold time (Write/Read)
Chip select “H” pulse width
Chip select setup time (Write)
Chip select setup time (Read ID)
Chip select setup time (Read FM)
Chip select wait time (Write/Read)
Chip select hold time
Write cycle
Control pulse “H” duration
Control pulse “L” duration
Read cycle (ID)
Control pulse “H” duration (ID)
Control pulse “L” duration (ID)
Read cycle (FM)
Control pulse “H” duration (FM)
Control pulse “L” duration (FM)
Data setup time
Data hold time
Read access time (ID)
Read access time (FM)
Output disable time
MAX
Unit
40
340
80
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
10
10
0
35
45
355
10
10
100
35
35
160
90
45
450
90
355
10
10
w
Signal
w
Table 8.3.1: AC Characteristics for Parallel Interface 18, 16, 9, 8-bits bus (6800-series MCU)
20
Description
-
-
When read ID data
When read from frame
memory
For maximum CL=30pF
For minimum CL=8pF
Note 1: VDD1=1.6 to 3.6V, VDD=2.6 to 3.5V, AGND=DGND=0V, Ta=-30 to 70℃ (to +85℃ no damage)
Note 2: The input signal rise time and fall time (tr, tf) is specified at 15 ns or less.
Logic high and low levels are specified as 30% and 70% of VDDI for Input signals.
© ORISE Technology Co., Ltd.
Proprietary & Confidential
219
Apr. 25, 2006
Preliminary Version: 0.1
Evaluation Only. Created with Aspose.Pdf.Kit. Copyright 2002-2005 Aspose Pty Ltd
Preliminary
SPFD54126B
8.4.
Serial Interface Characteristics (3-pin Serial)
CSX
VIH
TCHW
VIL
TCSS
TSCYCW /TSCYCR
VIH
VIL
TSHW /TSHR
TSDS
TSDH
VIH
VIL
TOH
TACC
SDA
(DOUT)
m
SDA
(DIN)
TSCC
TSLW /TSLR
VIH
VIL
nd
.co
SCL
TCSH
Fig. 8.4.1 3-pin Serial Interface Characteristics
SCL
SDA
(DIN)
(DOUT)
.m
bt
Parameter
Chip select setup time
Chip select hold time
Chip select setup time
Chip select setup time
Serial clock cycle (Write)
SCL “H” pulse width (Write)
SCL “L” pulse width (Write)
Serial clock cycle (Read)
SCL “H” pulse width (Read)
SCL “L” pulse width (Read)
Data setup time
Data hold time
Access time
Output disable time
w
TCSS
TCSH
TSCC
TCHW
TSCYCW
TSHW
TSLW
TSCYCR
TSHR
TSLR
TSDS
TSDH
TACC
TOH
w
CSX
Symbol
w
Signal
re
Table 8.4.1: 3-pin Serial Interface Characteristics
MIN
MAX
60
65
20
40
100
35
35
150
60
60
30
30
10
15
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Description
-
For maximum CL=30pF
For minimum CL=8pF
Note 1: VDD1=1.6 to 3.6V, VDD=2.6 to 3.5V, AGND=DGND=0V, Ta=-30 to 70℃ (to +85℃ no damage)
Note 2: The input signal rise time and fall time (tr, tf) is specified at 15 ns or less.
Logic high and low levels are specified as 30% and 70% of VDDI for Input signals.
© ORISE Technology Co., Ltd.
Proprietary & Confidential
220
Apr. 25, 2006
Preliminary Version: 0.1
Evaluation Only. Created with Aspose.Pdf.Kit. Copyright 2002-2005 Aspose Pty Ltd
Preliminary
SPFD54126B
9. PAD LOCATIONS
PAD Assignment
Chip Information:
Chip thickness: 300um(Typ)
Coordinates origin: Pad Left-bottom side
Au Bump: Height = 15um (Typ)
Output Pads
Boundary (Include Scribe Land)
F
E
D
A
23um
Bump Width
B
21um
Bump height
C
96um
Bump space 1
D
35um
Bump space 2
E
25um
Chip boundary
2.
BxC
2016um2
F
45~70um
Input Pads
D
Item
Bump Pitch
Symbol
Size
A
64um
Bump Pitch1
B
80um
Bump Width
C
55um
96um
Bump height
D
Bump space 1
E
9um
Bump space 2
F
25um
Bump area
Chip boundary
3.
F
w
E
C
w
B
BxC
5280um2
G
45~70um
Alignment Marks
A
E
E
B
C
B
C
C
C
A
C
C
B
B
E
E
E
D
C
Al layer
C
B
E
Clearance area
A
E
Polyomide
B C
C
C
B
E
Size
A
105um
Clearance gap1
B
15um
Clearance gap2
D
40um
Alignment mark width
C
25um
AxA
11025um 2
E
40~48um
Alignment area
Gap width
© ORISE Technology Co., Ltd.
Proprietary & Confidential
G
2 1 3
G
G
M
5
1
Y
D U M
M
Y
M
M
Y
Y
S 5 2 2
S 5 2 4
S 5 2 6
S 5 2 8
D U M M
Y
S 2
S 4
S 6
S 8
S 1 0
M
D U M M
S 1
S 3
S 5
S 7
S 9
S 1 1
Y
Y
V C L
V C L
V C L
2 1 P
2 1 P
2 1 P
2 1 N
2 1 N
2 1 N
2 2 P
2 2 P
2 2 P
2 2 N
2 2 N
2 2 N
2 3 P
2 3 P
2 3 P
2 3 N
2 3 N
2 3 N
V G L
V G L
V G L
V G H
V G H
V G H
D B 0
C O M
C O M
C O M
C O M
C O M
C O M
D A 2
D B 2
S 2 6 3
S 2 6 4
D U M
D U M
S 2 6 5
D U M
M
D U M
D U M
M
M
Y
Y
D U M M
S 2 6 6
Y
S 5 2 1
S 5 2 3
S 5 2 5
S 5 2 7
D U M M
Y
Y
G 2
G 6
G 1 0
D U M
G 4
G 8
M
Y
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
Gap
Symbol
Alignment mark size
P A D B 4
P A D A 4
D U M M Y
G 2 1 7
Y
Y
D U M
(Top View)
A
T
T
T
T
T
T
T
T
w
Boundary (Include Scribe Land)
G
2 1 5
G 7
G 3
D U M
SPFD54126B
.m
Bump area
T
bt
Size
Bump Pitch
2 1 9
G
re
B
Symbol
D G N D O
L C M 1
L C M 0
V D D IO
T E S T /D U M M Y 1
T E S T /D U M M Y 2
T E S T /D U M M Y 3
T E S T /D U M M Y 4
T E S T /D U M M Y 5
D 1 7
D 1 7
D 1 6
D 1 6
D 1 5
D 1 5
D 1 4
D 1 4
D 1 3
D 1 3
D 1 2
D 1 2
D 1 1
D 1 1
D 1 0
D 1 0
D 9
D 9
D 8
D 8
D G N D O
D G N D O
D 7
D 7
D 6
D 6
D 5
D 5
D 4
D 4
D 3
D 3
D 2
D 2
D 1
D 1
D 0 ( S D A )
D 0 ( S D A )
T E S T /D U M M Y 6
T E S T /D U M M Y 7
T E S T /D U M M Y 8
T E S T /D U M M Y 9
E S T /D U M M Y 1 0
O S C
T E
C S X
R D X
W R X
S D A
E S T /D U M M Y 1 1
E S T /D U M M Y 1 2
E S T /D U M M Y 1 3
R E S X
D G N D
D /C X
D G N D
S C L
D G N D
P C L K
D G N D
D E
H S
V S
D U M M Y
E S T /D U M M Y 1 4
E S T /D U M M Y 1 5
E S T /D U M M Y 1 6
E S T /D U M M Y 1 7
E S T /D U M M Y 1 8
D G N D
D G N D
D G N D
D G N D
D G N D
D G N D
D G N D
D G N D
D G N D
D G N D
D G N D
D G N D
V D D _ 1 8 V
V D D _ 1 8 V
V D D _ 1 8 V
V D D _ 1 8 V
V D D _ 1 8 V
V D D IO
V D D IO
V D D IO
V D D IO
V D D IO
V D D IO
V D D IO
V D D IO
V D D
V D D
V D D
V D D
V D D
V D D
V D D
V D D
V D D
V D D
G V D D
G V D D
G V D D
G V D D
A G N D
A G N D
A G N D
A G N D
A G N D
A G N D
A G N D
A G N D
A G N D
A G N D
V R E F
V R E F
V R E F
V R E F
V R E F
D R V
D R V
F B
V C O M H
V C O M H
V C O M H
V C O M H
V C O M L
V C O M L
V C O M L
V C O M L
V C I1
V C I1
V C I1
V C I1
V C I1
A V D D
A V D D
A V D D
A V D D
A V D D
A V D D
C 1 1 P
C 1 1 P
C 1 1 P
C 1 1 P
C 1 1 N
C 1 1 N
C 1 1 N
C 1 1 N
C 1 2 P
C 1 2 P
C 1 2 P
C 1 2 P
C 1 2 N
C 1 2 N
C 1 2 N
C 1 2 N
A G N D
A G N D
A G N D
A G N D
A G N D
nd
.co
A
C
Item
M
M
G
V O T P
VE OX TT P
C
V D D IO
IM 0
IM 1
IM 2
P 6 8
D G N D O
S P I_ C S X
D U M M Y
D U M M Y
V D D IO
R C M 0
R C M 1
D G N D O
S R G B
S M X
S M Y
V D D IO
P R E G
R L
T B
S H U T
ID M
R E V
D G N D O
G M 1
G M 0
V D D IO
Chip Size: 18650 um x 950 um
1.
D U M
D U M
P A D A 1
P A D B 1
P A D A 0
Basic Information:
m
9.1.
P A
V
V
V
V
V
V
P A
P A
221
G 2
G 2
G 2
G 2
G 2
D U
D U
0 4
0 8
1 2
1 6
2 0
M M Y
M M Y
G
G
G
G
D
P
P
2
2
2
2
U
A
A
0 6
1 0
1 4
1 8
M M Y
D B 3
D A 3
Apr. 25, 2006
Preliminary Version: 0.1
Evaluation Only. Created with Aspose.Pdf.Kit. Copyright 2002-2005 Aspose Pty Ltd
Preliminary
SPFD54126B
PAD Locations
Y
Name
X
Y
Name
X
Y
125
93
55
DB11
4749
93
109
TEST/Dummy
8861
93
2
PADB1
205
93
56
DB11
4813
93
110
TEST/Dummy
8941
93
3
PADA0
285
93
57
DB10
4893
93
111
TEST/Dummy
9021
93
4
VOTP
365
93
58
DB10
4957
93
112
DGND
9101
93
5
VOTP
445
93
59
DB9
5037
93
113
DGND
9165
93
6
EXTC
525
93
60
DB9
5101
93
114
DGND
9229
93
7
VDDIO
605
93
61
DB8
5181
93
115
DGND
9293
93
8
IM0
685
93
62
DB8
5245
93
116
DGND
9357
93
9
IM1
765
93
63
DGNDO
5325
93
117
DGND
9421
93
10
IM2
845
93
64
DGNDO
5389
93
118
DGND
9485
93
11
P68
925
93
65
DB7
5469
93
119
DGND
9549
93
12
DGNDO
1005
93
66
DB7
5533
93
120
DGND
9613
93
13
SPI_CSX
1085
93
67
DB6
5613
93
121
DGND
9677
93
14
Dummy
1165
93
68
DB6
5677
93
122
DGND
9741
93
15
Dummy
1245
93
69
DB5
5757
93
123
DGND
9805
93
16
VDDIO
1325
93
70
DB5
5821
93
124
VCC
9885
93
17
RCM0
1405
93
71
DB4
5901
93
125
VCC
9949
93
18
RCM1
1485
93
72
DB4
5965
93
126
VCC
10013
93
19
DGNDO
1565
93
73
DB3
6045
93
127
VCC
10077
93
20
SRGB
1645
93
74
DB3
6109
93
128
VCC
10141
93
21
SMX
1725
93
75
DB2
6189
93
129
VDDI
10221
93
22
SMY
1805
93
76
DB2
6253
93
130
VDDI
10285
93
23
VDDIO
1885
93
77
DB1
6333
93
131
VDDI
10349
93
24
PREG
1965
93
78
DB1
6397
93
132
VDDI
10413
93
25
RL
2045
93
79
DB0
6477
93
133
VDDI
10477
93
26
TB
2125
93
80
DB0
6541
93
134
VDDI
10541
93
27
SHUT
2205
93
81
TEST/Dummy
6621
93
135
VDDI
10605
93
28
IDM
2285
93
82
TEST/Dummy
6701
93
136
VDDI
10669
93
29
REV
2365
93
83
TEST/Dummy
6781
93
137
VDD
10749
93
30
DGNDO
2445
93
84
TEST/Dummy
6861
93
138
VDD
10813
93
31
GM1
2525
93
85
TEST/Dummy
6941
93
139
VDD
10877
93
32
GM0
2605
93
86
OSC
7021
93
140
VDD
10941
93
33
VDDIO
2685
93
87
TE
7101
93
141
VDD
11005
93
34
DGNDO
3165
93
88
CSX
7181
93
142
VDD
11069
93
35
LCM1
3245
93
89
RDX
7261
93
143
VDD
11133
93
36
LCM0
3325
93
90
WRX
7341
93
144
VDD
11197
93
37
VDDIO
3405
93
91
SDA
7421
93
145
VDD
11261
93
38
TEST/Dummy
3485
93
92
TEST/Dummy
7501
93
146
VDD
11325
93
39
TEST/Dummy
3565
93
93
TEST/Dummy
7581
93
147
GVDD
11405
93
40
TEST/Dummy
3645
93
94
TEST/Dummy
7661
93
148
GVDD
11469
93
41
TEST/Dummy
3725
93
95
RESX
7741
93
149
GVDD
11533
93
42
TEST/Dummy
3805
93
96
DGNDO
7821
93
150
GVDD
11597
93
43
DB17
3885
93
97
DCX
7901
93
151
AGND
11677
93
44
DB17
3949
93
98
DGNDO
7981
93
152
AGND
11741
93
45
DB16
4029
93
99
SCL
8061
93
153
AGND
11805
93
46
DB16
4093
93
100
DGNDO
8141
93
154
AGND
11869
93
47
DB15
4173
93
101
PCLK
8221
93
155
AGND
11933
93
48
DB15
4237
93
102
DGNDO
8301
93
156
AGND
11997
93
49
DB14
4317
93
103
DE
8381
93
157
AGND
12061
93
50
DB14
4381
93
104
HS
8461
93
158
AGND
12125
93
51
DB13
4461
93
105
VS
8541
93
159
AGND
12189
93
52
DB13
4525
93
106
Dummy
8621
93
160
AGND
12253
93
53
DB12
4605
93
107
TEST/Dummy
8701
93
161
VREF
12333
93
54
DB12
4669
93
108
TEST/Dummy
8781
93
162
VREF
12397
93
© ORISE Technology Co., Ltd.
Proprietary & Confidential
w
w
bt
re
nd
.co
m
X
PADA1
w
Name
1
.m
9.2.
222
Apr. 25, 2006
Preliminary Version: 0.1
Evaluation Only. Created with Aspose.Pdf.Kit. Copyright 2002-2005 Aspose Pty Ltd
Preliminary
Name
X
X
Y
93
G174
17841
777
93
274
G172
17818
646
16765
93
275
G170
17795
777
C22N
16845
93
276
G168
17772
646
222
C22N
16909
93
277
G166
17749
777
93
223
C22N
16973
93
278
G164
17726
646
12909
93
224
C23P
17053
93
279
G162
17703
777
VCOMH
12973
93
225
C23P
17117
93
280
G160
17680
646
171
VCOMH
13037
93
226
C23P
17181
93
281
G158
17657
777
172
VCOMH
13101
93
227
C23N
17261
93
282
G156
17634
646
173
VCOML
13181
93
228
C23N
17325
93
283
G154
17611
777
174
VCOML
13245
93
229
C23N
17389
93
284
G152
17588
646
175
VCOML
13309
93
230
VGL
17469
93
285
G150
17565
777
176
VCOML
13373
93
231
VGL
17533
93
286
G148
17542
646
177
VCI1
13453
93
232
VGL
17597
93
287
G146
17519
777
178
VCI1
13517
93
233
VGH
17677
93
288
G144
17496
646
179
VCI1
13581
93
234
VGH
17741
93
289
G142
17473
777
180
VCI1
13645
93
235
VGH
17805
93
290
G140
17450
646
181
VCI1
13709
93
236
PADB0
17885
93
291
G138
17427
777
182
AVDD
13789
93
237
VCOM
17965
93
292
G136
17404
646
183
AVDD
13853
93
238
VCOM
18029
93
293
G134
17381
777
184
AVDD
13917
93
239
VCOM
18093
93
294
G132
17358
646
185
AVDD
13981
93
240
VCOM
18157
93
295
G130
17335
777
186
AVDD
14045
93
241
VCOM
18221
93
296
G128
17312
646
187
AVDD
14109
93
242
VCOM
18285
93
297
G126
17289
777
188
C11P
14189
93
243
PADA2
18365
93
298
G124
17266
646
189
C11P
14253
93
244
PADB2
18445
93
299
G122
17243
777
190
C11P
14317
93
245
PADA3
18485
777
300
G120
17220
646
191
C11P
14381
93
246
Dummy7
18462
646
301
G118
17197
777
192
C11N
14461
93
247
PADB3
18439
777
302
G116
17174
646
193
C11N
14525
93
248
Dummy8
18416
646
303
G114
17151
777
194
C11N
14589
93
249
Dummy9
18393
777
304
G112
17128
646
195
C11N
14653
93
250
G220
18370
646
305
G110
17105
777
196
C12P
14733
93
251
G218
18347
777
306
G108
17082
646
197
C12P
14797
93
252
G216
18324
646
307
G106
17059
777
198
C12P
14861
93
253
G214
18301
777
308
G104
17036
646
199
C12P
14925
93
254
G212
18278
646
309
G102
17013
777
200
C12N
15005
93
255
G210
18255
777
310
G100
16990
646
201
C12N
15069
93
256
G208
18232
646
311
G98
16967
777
202
C12N
15133
93
257
G206
18209
777
312
G96
16944
646
203
C12N
15197
93
258
G204
18186
646
313
G94
16921
777
204
AGND
15277
93
259
G202
18163
777
314
G92
16898
646
205
AGND
15341
93
260
G200
18140
646
315
G90
16875
777
206
AGND
15405
93
261
G198
18117
777
316
G88
16852
646
207
AGND
15469
93
262
G196
18094
646
317
G86
16829
777
208
AGND
15533
93
263
G194
18071
777
318
G84
16806
646
209
VCL
16013
93
264
G192
18048
646
319
G82
16783
777
210
VCL
16077
93
265
G190
18025
777
320
G80
16760
646
211
VCL
16141
93
266
G188
18002
646
321
G78
16737
777
212
C21P
16221
93
267
G186
17979
777
322
G76
16714
646
213
C21P
16285
93
268
G184
17956
646
323
G74
16691
777
214
C21P
16349
93
269
G182
17933
777
324
G72
16668
646
215
C21N
16429
93
270
G180
17910
646
325
G70
16645
777
216
C21N
16493
93
271
G178
17887
777
326
G68
16622
646
217
C21N
16557
93
272
G176
17864
646
327
G66
16599
777
16637
93
219
C22P
16701
165
VREF
12589
93
220
C22P
166
DRV
12669
93
221
167
DRV
12749
93
168
FB
12829
169
VCOMH
170
© ORISE Technology Co., Ltd.
Proprietary & Confidential
Y
nd
.co
93
bt
12525
X
C22P
.m
VREF
Name
218
w
12461
164
Y
w
VREF
w
163
m
Name
273
re
SPFD54126B
223
Apr. 25, 2006
Preliminary Version: 0.1
Evaluation Only. Created with Aspose.Pdf.Kit. Copyright 2002-2005 Aspose Pty Ltd
Preliminary
Name
X
X
Y
646
S454
13701
777
777
439
S453
13678
646
14920
646
440
S452
13655
777
S506
14897
777
441
S451
13632
646
387
S505
14874
646
442
S450
13609
777
777
388
S504
14851
777
443
S449
13586
646
16438
646
389
S503
14828
646
444
S448
13563
777
G50
16415
777
390
S502
14805
777
445
S447
13540
646
336
G48
16392
646
391
S501
14782
646
446
S446
13517
777
337
G46
16369
777
392
S500
14759
777
447
S445
13494
646
338
G44
16346
646
393
S499
14736
646
448
S444
13471
777
339
G42
16323
777
394
S498
14713
777
449
S443
13448
646
340
G40
16300
646
395
S497
14690
646
450
S442
13425
777
341
G38
16277
777
396
S496
14667
777
451
S441
13402
646
342
G36
16254
646
397
S495
14644
646
452
S440
13379
777
343
G34
16231
777
398
S494
14621
777
453
S439
13356
646
344
G32
16208
646
399
S493
14598
646
454
S438
13333
777
345
G30
16185
777
400
S492
14575
777
455
S437
13310
646
346
G28
16162
646
401
S491
14552
646
456
S436
13287
777
347
G26
16139
777
402
S490
14529
777
457
S435
13264
646
348
G24
16116
646
403
S489
14506
646
458
S434
13241
777
349
G22
16093
777
404
S488
14483
777
459
S433
13218
646
350
G20
16070
646
405
S487
14460
646
460
S432
13195
777
351
G18
16047
777
406
S486
14437
777
461
S431
13172
646
352
G16
16024
646
407
S485
14414
646
462
S430
13149
777
353
G14
16001
777
408
S484
14391
777
463
S429
13126
646
354
G12
15978
646
409
S483
14368
646
464
S428
13103
777
355
G10
15955
777
410
S482
14345
777
465
S427
13080
646
356
G8
15932
646
411
S481
14322
646
466
S426
13057
777
357
G6
15909
777
412
S480
14299
777
467
S425
13034
646
358
G4
15886
646
413
S479
14276
646
468
S424
13011
777
359
G2
15863
777
414
S478
14253
777
469
S423
12988
646
360
Dummy
15840
646
415
S477
14230
646
470
S422
12965
777
361
Dummy
15817
777
416
S476
14207
777
471
S421
12942
646
362
Dummy
15449
777
417
S475
14184
646
472
S420
12919
777
363
Dummy
15426
646
418
S474
14161
777
473
S419
12896
646
364
S528
15403
777
419
S473
14138
646
474
S418
12873
777
365
S527
15380
646
420
S472
14115
777
475
S417
12850
646
366
S526
15357
777
421
S471
14092
646
476
S416
12827
777
367
S525
15334
646
422
S470
14069
777
477
S415
12804
646
368
S524
15311
777
423
S469
14046
646
478
S414
12781
777
369
S523
15288
646
424
S468
14023
777
479
S413
12758
646
370
S522
15265
777
425
S467
14000
646
480
S412
12735
777
371
S521
15242
646
426
S466
13977
777
481
S411
12712
646
372
S520
15219
777
427
S465
13954
646
482
S410
12689
777
373
S519
15196
646
428
S464
13931
777
483
S409
12666
646
374
S518
15173
777
429
S463
13908
646
484
S408
12643
777
375
S517
15150
646
430
S462
13885
777
485
S407
12620
646
376
S516
15127
777
431
S461
13862
646
486
S406
12597
777
377
S515
15104
646
432
S460
13839
777
487
S405
12574
646
378
S514
15081
777
433
S459
13816
646
488
S404
12551
777
379
S513
15058
646
434
S458
13793
777
489
S403
12528
646
380
S512
15035
777
435
S457
13770
646
490
S402
12505
777
381
S511
15012
646
436
S456
13747
777
491
S401
12482
646
382
S510
14989
777
437
S455
13724
646
492
S400
12459
777
14966
777
384
S508
14943
330
G60
16530
646
385
S507
331
G58
16507
777
386
332
G56
16484
646
333
G54
16461
334
G52
335
© ORISE Technology Co., Ltd.
Proprietary & Confidential
Y
nd
.co
646
bt
16553
X
S509
.m
G62
Name
383
w
16576
329
Y
w
G64
w
328
m
Name
438
re
SPFD54126B
224
Apr. 25, 2006
Preliminary Version: 0.1
Evaluation Only. Created with Aspose.Pdf.Kit. Copyright 2002-2005 Aspose Pty Ltd
Preliminary
Name
X
X
Y
777
S289
9906
646
646
604
S288
9883
777
11125
777
605
S287
9860
646
S341
11102
646
606
S286
9837
777
552
S340
11079
777
607
S285
9814
646
777
553
S339
11056
646
608
S284
9791
777
12298
646
554
S338
11033
777
609
S283
9768
646
S392
12275
777
555
S337
11010
646
610
S282
9745
777
501
S391
12252
646
556
S336
10987
777
611
S281
9722
646
502
S390
12229
777
557
S335
10964
646
612
S280
9699
777
503
S389
12206
646
558
S334
10941
777
613
S279
9676
646
504
S388
12183
777
559
S333
10918
646
614
S278
9653
777
505
S387
12160
646
560
S332
10895
777
615
S277
9630
646
506
S386
12137
777
561
S331
10872
646
616
S276
9607
777
507
S385
12114
646
562
S330
10849
777
617
S275
9584
646
508
S384
12091
777
563
S329
10826
646
618
S274
9561
777
509
S383
12068
646
564
S328
10803
777
619
S273
9538
646
510
S382
12045
777
565
S327
10780
646
620
S272
9515
777
511
S381
12022
646
566
S326
10757
777
621
S271
9492
646
512
S380
11999
777
567
S325
10734
646
622
S270
9469
777
513
S379
11976
646
568
S324
10711
777
623
S269
9446
646
514
S378
11953
777
569
S323
10688
646
624
S268
9423
777
515
S377
11930
646
570
S322
10665
777
625
S267
9400
646
516
S376
11907
777
571
S321
10642
646
626
S266
9377
777
517
S375
11884
646
572
S320
10619
777
627
S265
9354
646
518
S374
11861
777
573
S319
10596
646
628
Dummy
9331
777
519
S373
11838
646
574
S318
10573
777
629
Dummy
9308
646
520
S372
11815
777
575
S317
10550
646
630
Dummy
9285
777
521
S371
11792
646
576
S316
10527
777
631
Dummy
9262
646
522
S370
11769
777
577
S315
10504
646
632
Dummy
9239
777
523
S369
11746
646
578
S314
10481
777
633
S264
9216
646
524
S368
11723
777
579
S313
10458
646
634
S263
9193
777
525
S367
11700
646
580
S312
10435
777
635
S262
9170
646
526
S366
11677
777
581
S311
10412
646
636
S261
9147
777
527
S365
11654
646
582
S310
10389
777
637
S260
9124
646
528
S364
11631
777
583
S309
10366
646
638
S259
9101
777
529
S363
11608
646
584
S308
10343
777
639
S258
9078
646
530
S362
11585
777
585
S307
10320
646
640
S257
9055
777
531
S361
11562
646
586
S306
10297
777
641
S256
9032
646
532
S360
11539
777
587
S305
10274
646
642
S255
9009
777
533
S359
11516
646
588
S304
10251
777
643
S254
8986
646
534
S358
11493
777
589
S303
10228
646
644
S253
8963
777
535
S357
11470
646
590
S302
10205
777
645
S252
8940
646
536
S356
11447
777
591
S301
10182
646
646
S251
8917
777
537
S355
11424
646
592
S300
10159
777
647
S250
8894
646
538
S354
11401
777
593
S299
10136
646
648
S249
8871
777
539
S353
11378
646
594
S298
10113
777
649
S248
8848
646
540
S352
11355
777
595
S297
10090
646
650
S247
8825
777
541
S351
11332
646
596
S296
10067
777
651
S246
8802
646
542
S350
11309
777
597
S295
10044
646
652
S245
8779
777
543
S349
11286
646
598
S294
10021
777
653
S244
8756
646
544
S348
11263
777
599
S293
9998
646
654
S243
8733
777
545
S347
11240
646
600
S292
9975
777
655
S242
8710
646
546
S346
11217
777
601
S291
9952
646
656
S241
8687
777
547
S345
11194
646
602
S290
9929
777
657
S240
8664
646
11171
777
549
S343
11148
495
S397
12390
646
550
S342
496
S396
12367
777
551
497
S395
12344
646
498
S394
12321
499
S393
500
© ORISE Technology Co., Ltd.
Proprietary & Confidential
Y
nd
.co
646
bt
12413
X
S344
.m
S398
Name
548
w
12436
494
Y
w
S399
w
493
m
Name
603
re
SPFD54126B
225
Apr. 25, 2006
Preliminary Version: 0.1
Evaluation Only. Created with Aspose.Pdf.Kit. Copyright 2002-2005 Aspose Pty Ltd
Preliminary
Name
X
X
Y
646
S129
6111
777
777
769
S128
6088
646
7330
646
770
S127
6065
777
S181
7307
777
771
S126
6042
646
717
S180
7284
646
772
S125
6019
777
646
718
S179
7261
777
773
S124
5996
646
8503
777
719
S178
7238
646
774
S123
5973
777
S232
8480
646
720
S177
7215
777
775
S122
5950
646
666
S231
8457
777
721
S176
7192
646
776
S121
5927
777
667
S230
8434
646
722
S175
7169
777
777
S120
5904
646
668
S229
8411
777
723
S174
7146
646
778
S119
5881
777
669
S228
8388
646
724
S173
7123
777
779
S118
5858
646
670
S227
8365
777
725
S172
7100
646
780
S117
5835
777
671
S226
8342
646
726
S171
7077
777
781
S116
5812
646
672
S225
8319
777
727
S170
7054
646
782
S115
5789
777
673
S224
8296
646
728
S169
7031
777
783
S114
5766
646
674
S223
8273
777
729
S168
7008
646
784
S113
5743
777
675
S222
8250
646
730
S167
6985
777
785
S112
5720
646
676
S221
8227
777
731
S166
6962
646
786
S111
5697
777
677
S220
8204
646
732
S165
6939
777
787
S110
5674
646
678
S219
8181
777
733
S164
6916
646
788
S109
5651
777
679
S218
8158
646
734
S163
6893
777
789
S108
5628
646
680
S217
8135
777
735
S162
6870
646
790
S107
5605
777
681
S216
8112
646
736
S161
6847
777
791
S106
5582
646
682
S215
8089
777
737
S160
6824
646
792
S105
5559
777
683
S214
8066
646
738
S159
6801
777
793
S104
5536
646
684
S213
8043
777
739
S158
6778
646
794
S103
5513
777
685
S212
8020
646
740
S157
6755
777
795
S102
5490
646
686
S211
7997
777
741
S156
6732
646
796
S101
5467
777
687
S210
7974
646
742
S155
6709
777
797
S100
5444
646
688
S209
7951
777
743
S154
6686
646
798
S99
5421
777
689
S208
7928
646
744
S153
6663
777
799
S98
5398
646
690
S207
7905
777
745
S152
6640
646
800
S97
5375
777
691
S206
7882
646
746
S151
6617
777
801
S96
5352
646
692
S205
7859
777
747
S150
6594
646
802
S95
5329
777
693
S204
7836
646
748
S149
6571
777
803
S94
5306
646
694
S203
7813
777
749
S148
6548
646
804
S93
5283
777
695
S202
7790
646
750
S147
6525
777
805
S92
5260
646
696
S201
7767
777
751
S146
6502
646
806
S91
5237
777
697
S200
7744
646
752
S145
6479
777
807
S90
5214
646
698
S199
7721
777
753
S144
6456
646
808
S89
5191
777
699
S198
7698
646
754
S143
6433
777
809
S88
5168
646
700
S197
7675
777
755
S142
6410
646
810
S87
5145
777
701
S196
7652
646
756
S141
6387
777
811
S86
5122
646
702
S195
7629
777
757
S140
6364
646
812
S85
5099
777
703
S194
7606
646
758
S139
6341
777
813
S84
5076
646
704
S193
7583
777
759
S138
6318
646
814
S83
5053
777
705
S192
7560
646
760
S137
6295
777
815
S82
5030
646
706
S191
7537
777
761
S136
6272
646
816
S81
5007
777
707
S190
7514
646
762
S135
6249
777
817
S80
4984
646
708
S189
7491
777
763
S134
6226
646
818
S79
4961
777
709
S188
7468
646
764
S133
6203
777
819
S78
4938
646
710
S187
7445
777
765
S132
6180
646
820
S77
4915
777
711
S186
7422
646
766
S131
6157
777
821
S76
4892
646
712
S185
7399
777
767
S130
6134
646
822
S75
4869
777
7376
646
714
S183
7353
660
S237
8595
777
715
S182
661
S236
8572
646
716
662
S235
8549
777
663
S234
8526
664
S233
665
© ORISE Technology Co., Ltd.
Proprietary & Confidential
Y
nd
.co
777
bt
8618
X
S184
.m
S238
Name
713
w
8641
659
Y
w
S239
w
658
m
Name
768
re
SPFD54126B
226
Apr. 25, 2006
Preliminary Version: 0.1
Evaluation Only. Created with Aspose.Pdf.Kit. Copyright 2002-2005 Aspose Pty Ltd
Preliminary
Name
X
X
Y
777
G65
1971
777
646
934
G67
1948
646
3535
777
935
G69
1925
777
S16
3512
646
936
G71
1902
646
882
S15
3489
777
937
G73
1879
777
777
883
S14
3466
646
938
G75
1856
646
4708
646
884
S13
3443
777
939
G77
1833
777
S67
4685
777
885
S12
3420
646
940
G79
1810
646
831
S66
4662
646
886
S11
3397
777
941
G81
1787
777
832
S65
4639
777
887
S10
3374
646
942
G83
1764
646
833
S64
4616
646
888
S9
3351
777
943
G85
1741
777
834
S63
4593
777
889
S8
3328
646
944
G87
1718
646
835
S62
4570
646
890
S7
3305
777
945
G89
1695
777
836
S61
4547
777
891
S6
3282
646
946
G91
1672
646
837
S60
4524
646
892
S5
3259
777
947
G93
1649
777
838
S59
4501
777
893
S4
3236
646
948
G95
1626
646
839
S58
4478
646
894
S3
3213
777
949
G97
1603
777
840
S57
4455
777
895
S2
3190
646
950
G99
1580
646
841
S56
4432
646
896
S1
3167
777
951
G101
1557
777
842
S55
4409
777
897
Dummy
3144
646
952
G103
1534
646
843
S54
4386
646
898
Dummy
3121
777
953
G105
1511
777
844
S53
4363
777
899
Dummy
2753
777
954
G107
1488
646
845
S52
4340
646
900
Dummy
2730
646
955
G109
1465
777
846
S51
4317
777
901
G1
2707
777
956
G111
1442
646
847
S50
4294
646
902
G3
2684
646
957
G113
1419
777
848
S49
4271
777
903
G5
2661
777
958
G115
1396
646
849
S48
4248
646
904
G7
2638
646
959
G117
1373
777
850
S47
4225
777
905
G9
2615
777
960
G119
1350
646
851
S46
4202
646
906
G11
2592
646
961
G121
1327
777
852
S45
4179
777
907
G13
2569
777
962
G123
1304
646
853
S44
4156
646
908
G15
2546
646
963
G125
1281
777
854
S43
4133
777
909
G17
2523
777
964
G127
1258
646
855
S42
4110
646
910
G19
2500
646
965
G129
1235
777
856
S41
4087
777
911
G21
2477
777
966
G131
1212
646
857
S40
4064
646
912
G23
2454
646
967
G133
1189
777
858
S39
4041
777
913
G25
2431
777
968
G135
1166
646
859
S38
4018
646
914
G27
2408
646
969
G137
1143
777
860
S37
3995
777
915
G29
2385
777
970
G139
1120
646
861
S36
3972
646
916
G31
2362
646
971
G141
1097
777
862
S35
3949
777
917
G33
2339
777
972
G143
1074
646
863
S34
3926
646
918
G35
2316
646
973
G145
1051
777
864
S33
3903
777
919
G37
2293
777
974
G147
1028
646
865
S32
3880
646
920
G39
2270
646
975
G149
1005
777
866
S31
3857
777
921
G41
2247
777
976
G151
982
646
867
S30
3834
646
922
G43
2224
646
977
G153
959
777
868
S29
3811
777
923
G45
2201
777
978
G155
936
646
869
S28
3788
646
924
G47
2178
646
979
G157
913
777
870
S27
3765
777
925
G49
2155
777
980
G159
890
646
871
S26
3742
646
926
G51
2132
646
981
G161
867
777
872
S25
3719
777
927
G53
2109
777
982
G163
844
646
873
S24
3696
646
928
G55
2086
646
983
G165
821
777
874
S23
3673
777
929
G57
2063
777
984
G167
798
646
875
S22
3650
646
930
G59
2040
646
985
G169
775
777
876
S21
3627
777
931
G61
2017
777
986
G171
752
646
877
S20
3604
646
932
G63
1994
646
987
G173
729
777
3581
777
879
S18
3558
825
S72
4800
646
880
S17
826
S71
4777
777
881
827
S70
4754
646
828
S69
4731
829
S68
830
© ORISE Technology Co., Ltd.
Proprietary & Confidential
Y
nd
.co
646
bt
4823
X
S19
.m
S73
Name
878
w
4846
824
Y
w
S74
w
823
m
Name
933
re
SPFD54126B
227
Apr. 25, 2006
Preliminary Version: 0.1
Evaluation Only. Created with Aspose.Pdf.Kit. Copyright 2002-2005 Aspose Pty Ltd
Preliminary
SPFD54126B
Name
X
Name
X
Y
777
1010
G219
200
646
646
1011
Dummy
177
777
407
777
1012
Dummy
154
646
G203
384
646
1013
PADA4
131
777
1003
G205
361
777
1014
Dummy
108
646
777
1004
G207
338
646
1015
PADB4
85
777
568
646
1005
G209
315
777
545
777
1006
G211
292
646
522
646
1007
G213
269
777
G193
499
777
1008
G215
246
646
G195
476
646
1009
G217
223
777
G175
706
989
G177
683
990
G179
991
Y
Name
X
646
999
G197
453
777
1000
G199
430
660
646
1001
G201
G181
637
777
1002
992
G183
614
646
993
G185
591
994
G187
995
G189
996
G191
997
998
Y
w
w
w
.m
bt
re
nd
.co
m
988
© ORISE Technology Co., Ltd.
Proprietary & Confidential
228
Apr. 25, 2006
Preliminary Version: 0.1
Evaluation Only. Created with Aspose.Pdf.Kit. Copyright 2002-2005 Aspose Pty Ltd
Preliminary
SPFD54126B
9.3.
1
2
Wiring Resistance
Name
Resistance
Priority
PADA1
open
4
PADB1
VOTP
10 ohm
3
6
EXTC
200 ohm
7
VDDIO
8
Name
Resistance
Priority
TEST/Dummy
open
4
TEST/Dummy
open
4
111
TEST/Dummy
open
4
112
DGND
113
DGND
114
DGND
115
DGND
116
DGND
10 ohm
1
10 ohm
2
10 ohm
2
10 ohm
1
10 ohm
1
20 ohm
3
10 ohm
1
10 ohm
3
109
DB11
110
100 ohm
4
100 ohm
4
57
DB10
58
DB10
59
DB9
4
60
DB9
4
4
61
DB8
IM0
open
200 ohm
62
DB8
9
IM1
200 ohm
4
63
DGNDO
open
4
117
DGND
10
IM2
200 ohm
4
64
DGNDO
open
4
118
DGND
11
P68
200 ohm
4
65
DB7
100 ohm
4
119
DGND
12
DGNDO
open
4
66
DB7
120
DGND
13
SPI_CSX
100 ohm
4
67
DB6
121
DGND
14
Dummy
open
4
68
DB6
122
DGND
15
Dummy
open
4
69
DB5
123
DGND
16
VDDIO
DB5
124
VCC
RCM0
4
4
70
17
open
200 ohm
71
DB4
125
VCC
18
RCM1
200 ohm
4
72
DB4
126
VCC
19
DGNDO
DB3
127
VCC
SRGB
4
4
73
20
open
200 ohm
74
DB3
21
SMX
200 ohm
4
75
DB2
22
SMY
200 ohm
4
76
23
VDDIO
open
4
77
24
PREG
DB1
RL
4
4
78
25
open
200 ohm
79
DB0
26
TB
200 ohm
4
27
SHUT
200 ohm
4
28
IDM
200 ohm
4
29
REV
200 ohm
4
30
DGNDO
31
GM1
open
200 ohm
32
GM0
33
100 ohm
100 ohm
4
4
m
VOTP
5
4
nd
.co
4
Priority
100 ohm
100 ohm
100 ohm
4
4
100 ohm
4
100 ohm
4
100 ohm
4
re
4
Resistance
DB11
bt
(200 ohm)
56
Name
DB2
DB1
.m
PADA0
4
w
3
open
55
100 ohm
4
128
VCC
129
VDDI
130
VDDI
131
VDDI
132
VDDI
133
VDDI
DB0
134
VDDI
81
TEST/Dummy
open
4
135
VDDI
82
TEST/Dummy
open
4
136
VDDI
83
TEST/Dummy
open
4
137
VDD
4
4
84
TEST/Dummy
open
4
138
VDD
85
TEST/Dummy
open
4
139
VDD
200 ohm
4
86
OSC
4
87
TE
4
4
VDD
open
open
100 ohm
140
VDDIO
141
VDD
34
DGNDO
CSX
100 ohm
4
142
VDD
LCM1
4
4
88
35
open
200 ohm
89
RDX
100 ohm
4
143
VDD
36
LCM0
200 ohm
4
90
WRX
100 ohm
4
144
VDD
VDD
w
w
80
37
VDDIO
open
4
91
SDA
100 ohm
4
145
38
TEST/Dummy
open
4
92
TEST/Dummy
open
4
146
VDD
39
TEST/Dummy
open
4
93
TEST/Dummy
open
4
147
GVDD
40
TEST/Dummy
4
4
TEST/Dummy
open
4
148
GVDD
TEST/Dummy
open
open
94
41
95
RESX
200 ohm
4
149
GVDD
42
TEST/Dummy
open
4
96
DGNDO
open
4
150
GVDD
43
DB17
100 ohm
4
97
DCX
100 ohm
4
151
AGND
44
DB17
98
DGNDO
open
4
152
AGND
45
DB16
99
SCL
100 ohm
4
153
AGND
46
DB16
100
DGNDO
open
4
154
AGND
47
DB15
101
PCLK
100 ohm
4
155
AGND
48
DB15
102
DGNDO
AGND
DB14
103
DE
4
4
156
49
open
100 ohm
157
AGND
50
DB14
104
HS
100 ohm
4
158
AGND
51
DB13
105
VS
100 ohm
4
159
AGND
52
DB13
106
Dummy
open
4
160
AGND
53
DB12
107
TEST/Dummy
open
4
161
VREF
54
DB12
108
TEST/Dummy
open
4
162
VREF
100 ohm
100 ohm
100 ohm
100 ohm
100 ohm
© ORISE Technology Co., Ltd.
Proprietary & Confidential
4
4
4
4
4
229
Apr. 25, 2006
Preliminary Version: 0.1
Evaluation Only. Created with Aspose.Pdf.Kit. Copyright 2002-2005 Aspose Pty Ltd
Preliminary
SPFD54126B
Name
Resistance
Priority
Name
Resistance
Priority
Name
163
VREF
194
C11N
225
164
VREF
195
C11N
226
C23P
165
VREF
196
C12P
227
C23N
166
DRV
197
C12P
228
C23N
167
DRV
198
C12P
229
C23N
168
FB
199
C12P
230
VGL
169
VCOMH
200
C12N
231
VGL
170
VCOMH
201
C12N
232
VGL
171
VCOMH
202
C12N
233
VGH
172
VCOMH
203
C12N
234
VGH
173
VCOML
204
AGND
235
VGH
174
VCOML
205
AGND
236
PADB0
175
VCOML
206
AGND
237
VCOM
176
VCOML
207
AGND
177
VCI1
208
AGND
178
VCI1
209
VCL
179
VCI1
210
VCL
180
VCI1
211
VCL
181
VCI1
212
C21P
4
30 ohm
30 ohm
10 ohm
2
2
2
182
AVDD
213
183
AVDD
214
C21P
184
AVDD
215
C21N
185
AVDD
186
AVDD
217
187
AVDD
218
C22P
188
C11P
219
C22P
189
C11P
190
C11P
191
C11P
192
C11N
193
C11N
216
© ORISE Technology Co., Ltd.
Proprietary & Confidential
2
w
1
3
20 ohm
3
30 ohm
30 ohm
C21N
3
C22P
221
C22N
222
C22N
223
C22N
224
C23P
Priority
30 ohm
3
10 ohm
2
10 ohm
2
10 ohm
2
(200 ohm)
4
10 ohm
1
C23P
238
VCOM
239
VCOM
240
VCOM
241
VCOM
242
VCOM
243
PADA2
open
4
PADB2
open
4
244
245
246
3
C21N
220
w
10 ohm
2
w
10 ohm
2
20 ohm
bt
1
10 ohm
.m
20 ohm
C21P
10 ohm
2
m
(30 ohm)
10 ohm
nd
.co
3
re
(30 ohm)
Resistance
247
248
249
230
30 ohm
3
30 ohm
3
30 ohm
3
250
Apr. 25, 2006
Preliminary Version: 0.1
Evaluation Only. Created with Aspose.Pdf.Kit. Copyright 2002-2005 Aspose Pty Ltd
Preliminary
SPFD54126B
10. DISCLAIMER
The information appearing in this publication is believed to be accurate.
Integrated circuits sold by ORISE Technology are covered by the warranty and patent indemnification provisions stipulated in the terms of
sale only. ORISE Technology makes no warranty, express, statutory implied or by description regarding the information in this publication
or regarding the freedom of the described chip(s) from patent infringement.
WARRANTY OF MERCHANTABILITY OR FITNESS FOR ANY PURPOSE.
alter the specifications and prices at any time without notice.
FURTHERMORE, ORISE Technology MAKES NO
ORISE Technology reserves the right to halt production or
Accordingly, the reader is cautioned to verify that the data sheets and other
information in this publication are current before placing orders. Products described herein are intended for use in normal commercial
applications.
Applications involving unusual environmental or reliability requirements, e.g. military equipment or medical life support
equipment, are specifically not recommended without additional processing by ORISE Technology for such applications. Please note that
w
w
w
.m
bt
re
nd
.co
m
application circuits illustrated in this document are for reference purposes only..
© ORISE Technology Co., Ltd.
Proprietary & Confidential
231
Apr. 25, 2006
Preliminary Version: 0.1
Evaluation Only. Created with Aspose.Pdf.Kit. Copyright 2002-2005 Aspose Pty Ltd
Preliminary
SPFD54126B
10. REVISION HISTORY
Date
Revision #
Description
Page
1. Change title: Package/PAD Locations to PAD Locations
2. Modify 2. FEATURE
6
3. Modify Table 6.1.2. (4) to (4) ~ (9)
20-22
4. Modify Description of 6.3.19.
0.2
108
5. Modify 6.3.22 Table
112.113
6. Modify 6.3.23 Table
114.115
7. Modify 6.3.23 Table
116.117
8. Modify 6.3.23 Table
118.119
9. Modify 6.3.23 Table
120.121
m
NOV. 20, 2006
Original
122.123
218
w
w
w
.m
bt
re
0.1
nd
.co
10. Modify 6.3.23 Table
OCT. 26, 2006
220
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Apr. 25, 2006
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