TE6138 TEL Original Products DATA SHEET TE6138 IEEE1284 Peripheral Controller TE6138 TE6138 IEEE Std 1284-1994 TE6138 CPU DMA 64 1. Compatibility, Nibble, Byte, ECP 2. ECP RLE 3. Compatibility, ECP DMA ECP Forward, Reverse 4. CPU,DMA 5. 6. CMOS,5V Rev.1.02 (DMA 86 QFP ) 68 TOKYO ELECTRON DEVICE LIMITED 1 TE6138 TEL Original Products 1 1 2 ................................................................................................................................ 4 ................................................................................................................................ 5 6 CPU 1. 2. ................................................................................................................. 8 ................................................................................................. 9 ................................................................................................................... 9 .................................................................................................................................. 10 ...................................................................................................................................................................... 10 ........................................................................................................................................................................... 11 3. ........................................................................................................................ 19 ..................................................................................................................................................................... 19 ..................................................................................................................................................................... 20 4. ................................................................................................................. 21 Compatibility DMA ............................................................................................................................ 21 Compatibility DMA ............................................................................................................................... 21 Compatibility DMA ............................................................................................................................ 22 Compatibility DMA ............................................................................................................................... 22 Nibble Byte Peripheral Peripheral Host Host DMA RLE DMA RLE Negotiation, Transfer Start.............................................................................................. 23 Negotiation, Transfer Start................................................................................................. 24 ON HostClk ON HostClk ............................................................. 25 ............................................................. 26 DMA RLE ON HostClk ..................................................................................... 27 DMA RLE OFF HostClk ................................................................................... 28 DMA HostClk ................................................................................ 29 DMA ................................................................................................................................................ 30 DMA .................................................................................................................................................... 31 ....................................................................................................................................................................... 32 DMA DMA TE6137 ECP 5. 1.CPU 2. HostClk HostClk ................................................................................................ 33 .................................................................................................... 34 ........................................................................................................................................... 35 Valid termination Compatibility ......................................................................................... 36 .............................................................................................................. 37 ........................................................................................................................... 39 ........................................................................................................................... 39 39 ....................................................................................................................... 39 40 ................................................................................................................ 40 ................................................................................................ 42 DMA ..................................................................................................................................................................... 42 DMA ..................................................................................................................................................................... 44 .................................................................................................................... 46 .................................................................................................................... 46 Rev.1.02 TOKYO ELECTRON DEVICE LIMITED 2 TE6138 TEL Original Products .............................................................................................................................. 47 1. VDD VSS 1 0 H L ”#” 2. #CS, #RD 3. Rev.1.02 TOKYO ELECTRON DEVICE LIMITED 3 TE6138 TEL Original Products RAM TE6138 ROM CPU I/F Register CPU Interrupt Control Protcol Control DMAC DMA Control Rev.1.02 TOKYO ELECTRON DEVICE LIMITED HOST I/F 4 TE6138 TEL Original Products NO. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 I/O O O O I I I I B B B B B B B B I I I I I I I O SYMBOL VSS #INT2 #INT1 #INT0 A3 A2 A1 A0 VSS VDD D7 D6 D5 VSS D4 D3 VSS D2 D1 D0 VDD VSS #RD #WR VSS CLK VSS #RST CIS #CS #DAK1 #DRQ1 NOTES 4 4 4 6 6 6 6 2 2 2 2 2 2 2 2 6 6 6 5 6 6 6 1 NO. 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 I/O I I O O I O B B B B B B B B I I I I O O O O O - SYMBOL VSS #DEND1 #DAK0 #DRQ0 #DEND0 CLS RT VDD VSS BPD7 BPD6 BPD5 VSS BPD4 BPD3 BPD2 VSS BPD1 BPD0 VDD #SEI #AF #INI #STB PE VSS VSS #ACK BY #FT SE VDD NOTES 6 6 1 4 3 1 2 2 2 2 2 2 2 2 6 6 6 6 1 1 1 1 1 I: O: B: NOTES 1 2 3 4 5 6 Output Buffer(I OL=6mA) I/O Buffer(I OL=6mA) Input Buffer with Pull-up Resistor 40K Output Buffer(Open Drain) Input Buffer(CMOS Schmit) Input Buffer(TTL) Rev.1.02 (Typ) TOKYO ELECTRON DEVICE LIMITED 5 TE6138 TEL Original Products Symbol VDD #RST No. 10,21,40 52,64 1,9,14, 17,22,25 27,33, 41,45,49 58,59 28 CIS 29 VSS I/O - - I 23 I #WR Description GROUND I #RD Name POWER SUPPLY 24 RESET CPU INTERFACE SELECT CPU “0” “1” READ/READ WRITE SELECT CIS “0” “1” WRITE/ENABLE CIS “0” “1” 86 68 CPU CPU I CLK #CS D7-0 A3-0 #INT0 26 30 11,12,13 15,16, 18,19,20 5,6,7,8 4 #INT1 3 #INT2 2 #SEI 53 #AF 54 #STB 56 PE 57 #ACK 60 BY 61 #FT 62 SE 63 #INI 55 Rev.1.02 I I CLOCK CHIP SELECT DATA BUS B Compatibility O ADDRESS INTERRUPT REQUEST0 O INTERRUPT REQUEST1 ECP INTERRUPT REQUEST2 ECP O nSelectln Compatibility nSelectln nAutoFd Compatibility nAutoFd nStrobe Compatibility nStrobe PError Compatibility PError nAck Compatibility nAck Busy Compatibility Busy nFault Compatibility nFault Select Compatibility Select nInit Compatibility nInit I I I I O O O O O I Nibble ” Byte ” TOKYO ELECTRON DEVICE LIMITED 6 TE6138 TEL Original Products symbol BPD7-0 RT No. 42,43,44, 46,47,48, 50,51 39 I/O 36 #DEND0 37 #DAK0 35 O O I #DRQ1 32 #DEND1 34 #DAK1 31 CLS 38 O I I INDICATE REVERSE TRANSFER DMA REQUEST0 BPD7-0 Data8-1 DMA ACKNOWLEDGE0 Compatibility,ECP DMAC Compatibility,ECP DMA Compatibility,ECP DMAC DMA REQUEST1 ECP DMAC DMAEND1 ECP (#DRQ1) ECP DMA DMA END0 DMA ACKNOWLEDGE1 Compatibility Mode LEVEL SELECT I Rev.1.02 Description Compatibility,Byte,ECP B O #DRQ0 Name Data8-1 “0” Byte,ECP BY,#FT,SE ”1” DMAC Compatibility,Nibble, #INI,#SEI,#AF,#STB,PE,#ACK, TOKYO ELECTRON DEVICE LIMITED 7 TE6138 TEL Original Products CPU TE6138 CPU CIS CPU CIS=”0” CIS=”1” #RD R#W #WR #EN CIS=”0” Rev.1.02 (#RD,#WR) CIS=”1” TOKYO ELECTRON DEVICE LIMITED 8 TE6138 TEL Original Products TE6138 IEEE Std 1284-1994 Byte,ECP Compatibility,Nibble, DMA Compatibility ECP IC DMA 1. TE6138 ( I/O 55 #INI I 53 #SEI I 54 #AF I 56 #STB I 57 PE O 60 #ACK O 61 BY O 62 #FT O 57 SE O 42 BPD7 B 43 BPD6 B 44 BPD5 B 46 BPD4 B 47 BPD3 B 48 BPD2 B 50 BPD1 B 51 BPD0 B 1) BPD7-0 IEEE1284 Rev.1.02 Compatibility nInit nSelectIn nAutoFd nStrobe PError nAck Busy Fault Select Data8 Data7 Data6 Data5 Data4 Data3 Data2 Data1 Data8-1 Nibble “1” 1284Active HostBusy HostClk AckDataReq PtrClk PtrBusy nDataAvail XFlag - Byte “1” 1284Active HostBusy HostClk AckDataReq PtrClk PtrBusy nDataAvail XFlag Data8 Data7 Data6 Data5 Data4 Data3 Data2 Data1 ECP nReverseRequest 1284Active HostAck HostClk nAckReverse PeriphClk PeriphAck nPeriphRequest XFlag Data8 Data7 Data6 Data5 Data4 Data3 Data2 Data1 TOKYO ELECTRON DEVICE LIMITED 9 TE6138 TEL Original Products 2. A3 0 1 A2 0 A1 0 A0 0 0 0 1 0 0 1 1 1 1 0 0 0 0 1 1 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Rev.1.02 (ECP 1 ) ECP RLE ECP ECP - (ECP ) ACK ACK Nibble/Byte Nibble/Byte ECP DMA ECP 1 2 2 ECP TOKYO ELECTRON DEVICE LIMITED 10 TE6138 TEL Original Products [ 1 ] Address”0”(write only) D7 Initial Value 1 D6 1 D7: 0 D6: Nibble Byte D5: Nibble Byte D5 1 D3 1 D1 0 D0 0 “1”: ID “0”: Immediate Termination 1: 0: Nibble Byte D3: D2:Byte Compatibility 0: 1: 0: 1: 0: 1 BUSY(BY) 0: D0: Compatibility D2 0 1 D4: D1: Compatibility D4 1 ACK(#ACK) 1: STB(#STB) 1: 1 [ ](ECP Address”1”(Read only) D7 Initial Value 0 [ ) D6 0 D5 0 ](ECP Address”1”(Write only) D7 Initial Value 0 Rev.1.02 D4 0 D3 0 D2 0 D1 0 D0 0 D4 0 D3 0 D2 0 D1 0 D0 0 ) D6 0 D5 0 TOKYO ELECTRON DEVICE LIMITED 11 TE6138 TEL Original Products [ ] Address”2”(Read only) D7 Initial Value 1 D6 0 D5 0 D4 0 D3 0 D2 1 D1 1 D0 1 1 D7: Compatibility D6: Nibble D5: Byte D4: Negotiation D3: Termination D2,D1,D0: Nibble 000:Host Busy Data Avail (D6=1) Byte (D5=1) 001:Host Busy Data Not Avail 010:Idle 011:Data Transfer 100:Interrupt 111: (Compatibility [D=7] Negotiation [D=4] Termination [D=3] ECP ) [ ] Address”2”(Write only) D7 Initial Value 1 D6 - D5 - D4 - D3 - D2 - D1 - D0 - D7: 1: Nibble Byte (event1: ) 0: ) 1 Nibble ID Byte ID Rev.1.02 TOKYO ELECTRON DEVICE LIMITED 12 TE6138 TEL Original Products ] [ Address”3”(Read only) D7 Initial Value 1 D6 1 D5 1 D4 1 D7:Compatibility D3 1 D2 1 D1 1 ”H” (BUSY 0: D0 1 ) 1: D6:Compatibility #SEI(nSelectin) 0: ”0” #INI(‘nInit) (Termination phase) 1: D5:Compatibility #AF(nAutofd) 0: 0 (event1) 1: D4:Device ID Reverse Transfer 0: D3:Nibble Byte 1: ID 0: 1: D2:Nibble Byte 0: Termination ( Compatibility ) 1: ) D1:Nibble Byte 0: 1: D0:Compatibility 0: 1: Nibble 1284Active Compatibility N Nibble ID T N T D5 D4 (INT#0) D5 D2 D3 D2 N: Negotiation T: Termination ) [ ] Address”3”(Write only) D7 Initial Value 1 D6 1 D5 1 D4 1 D3 - D2 - D1 - D0 - D7-4 D7: D7 1: 0: D6: 1: D6 0: D5: D5 1: 0: D4: D4 1: 0: Rev.1.02 TOKYO ELECTRON DEVICE LIMITED 13 TE6138 TEL Original Products ] [ Address”4”(Read only) D7 Initial Value - D6 - D5 - D4 - D3 - D2 - - - - - - D5 0 D4 0 D3 0 (02h D2 0 - D1 0 D0 0 2 D1 0 D0 0 D1,D0: [ACK ] Address”4”(Write only) D7 Initial Value 0 CLK 2 D6 0 255 DMA [ACK ] Address”5”(Write only) D7 Initial Value 0 D6 0 CLK 2 D5 0 D4 0 D3 0 (02h D2 0 2 D1 0 D0 0 D5 0 D4 0 D3 0 (00h D2 0 31 D1 0 D0 0 1 Address”6”(Write only) D7 Initial Value 0 31 ] D6 0 8191 ( ”4. ” 32 ’Nibble ’ 32+18 20MHZ 400µs 2 Address”7”(Write only) D7 Initial Value 0 2 IEEE1284 35ms 400µs [Nibble/Byte CLK ) ) ’ ’Byte DataAvail TE6138 ) 255 [Nibble/Byte CLK ) ] D6 0 D5 0 D4 0 D3 0 (02h D2 0 2 D1 0 D0 0 ) D1 0 D0 0 255 ”4. IEEE1284 ” ’Nibble ’ ’Byte ’ 500ns [ECP ] Address”8”(Read only) D7 Initial Value 0 D6 0 D5 0 D4 0 D3 0 D2 0 ECP Rev.1.02 TOKYO ELECTRON DEVICE LIMITED 14 TE6138 TEL Original Products [ECP ] Address”8”(Write only) D7 Initial Value 0 D6 0 D5 0 D4 0 D3 0 D2 0 D1 0 D0 0 D6 1 D5 1 D4 1 D3 1 D2 1 D1 1 D0 1 D6 0 D5 0 D4 0 D3 0 D2 0 D1 0 D0 0 ECP [RLE ] Address”9”(Read only) D7 Initial Value - [ECP ] Address”10”(Read only) D7 Initial Value 0 1 0 D7: Negotiation Phase D6: Termination Phase D5: Forward Idle Phase D4: Reverse Idle Phase D3: D2: D1: ECP RLE D0: ECP RLE (ID (ID ECP Rev.1.02 ) ) ’0’ TOKYO ELECTRON DEVICE LIMITED 15 TE6138 TEL Original Products [ECP ] Address”11”(Read only) D7 Initial Value 0 D6 0 D5 0 D4 0 D3 0 D2 0 D1 0 D0 0 ECP D7: ECP D6: [#INT2: D4=0 D6=0 ] D5: Channel Address Command D4: RLE D3: D2: Host Transfer Recovery D1: Ø Ø 1 Ø 2 ECP Ø 2 ECP D0: ECP Byte RLE RLE ECP Immediate Termination Compatibility ) 1 [ DMA ] Address”11”(Write only) D7 Initial Value - D6 - ECP DMA D5 - D4 - D3 - D2 - D1 - D0 - D5 1 D4 1 D3 1 D2 1 D1 1 D0 1 #DRQ1 [ECP ] Address”12”(Write only) D7 Initial Value 1 D6 1 0: 1: D7: D6: #INT1,#INT2 D5: Channel Address Command D4: RLE D3: D2: Host Transfer Recovery D1: D0: ECP Immediate Termination Rev.1.02 TOKYO ELECTRON DEVICE LIMITED 16 TE6138 TEL Original Products 2 [ ] Address”13”(Write only) D7 Initial Value 0 D6 0 D5 0 D4 0 0: D3 0 D2 0 D1 0 D0 0 1: D7: ECP RLE (1 0 ) 0 ) D6: ECP RLE (1 D5: (Negotiation HostClk ) 0:HostClk 1:HostClk D4: (#INT2) (DMA ) D3: RLE ( RLE D2: ECP Forward D1: Nibble ID ( )DMA 0= ) ) 1= ECP D0: ECP Reverse ECP ( D6 )DMA ECP 2 D4 0 0 #INT1 0 1 1 - #INT2 ECP ECP D6 D6 [ECP ] Address”14”(Write only) D7 Initial Value - D6 - D5 - D4 - D3 0 (00h 1 D2 D1 0 0 D0 0 - - - 23 22 20 - ”0000” CLK 1 21 ) 1 16 event 5~6 event 23~24 event 26~27 event 48~49 Rev.1.02 TOKYO ELECTRON DEVICE LIMITED 17 TE6138 TEL Original Products ] [ Address”15”(Write only) D7 Initial Value 1 D7:1 BY 0 BY ( D6 1 D5 0 D4 0 D3 0 D2 0 D1 1 D0 1 ”H” ECP D6:0 ECP Reverse #FT ”H” D5:Compatibility 0 : 1 ”L” Reverse ”1” DMA : D4:DMA 0 : 86 0 : Forward ”H” Reverse ”L” 1 : Forward ”L” Reverse ”H” D3: 1 : 68 IC PE(PError) D2: Compatibility 0 : PE=”L” 1 D1: Compatibility 0 : #FT=”L” : SE=”L” Rev.1.02 PE=”H” #FT(nFault) 1 D0: Compatibility 0 : : #FT =”H” SE(Select) 1 : SE=”H” TOKYO ELECTRON DEVICE LIMITED 18 TE6138 TEL Original Products 3. CLK 20MHz 16MHz DMA DMAC Compatibility ECP DMA ECP #INT1 ECP ECP D1 TE6138 Compatibility TE6138 ECP (=”L”) Nibble Byte ECP TE6138 CPU DMA DMA Nibble #DEND1 Byte ) (#INT0 D2 Nibble ID Byte ID (#INT0 D3,D4 ) ECP 1 1 2 2 Nibble Rev.1.02 TOKYO ELECTRON DEVICE LIMITED 19 TE6138 TEL Original Products TE6138 TE6137 < TE6137 TE6138 > TE6137 ID ID ID TE6138 ID (BPo#INT0) (#INT0) (D2 ) ”0” [ Address2 ] D0 D7 D6 1 - “1”: - - - - - - Nibble Byte (event1: ) “0”: ) ”1” Nibble ID Byte ID TE6137 [ Adress4 ] D7 D6 - - D0 - - - - D1,D0: P14 ECP HOSTCLK PeriphACK (event35 37 ) ECP nStrobe Busy (event35 36) nStrobe Busy (event36 32) nInit event74 #DRQ0 event75 D7 ) D7=0 ,event35 ,event32 D7=1 nStrobe event75 nStrobe ( nInit #DRQ0 Event35 nStrobe nInit event74 75 #DRQ0 PEerror event75 (CLK) #DRQ0 #DRQ0 ECP ECP ECP D7 nSelectln Rev.1.02 TOKYO ELECTRON DEVICE LIMITED 20 TE6138 TEL Original Products 4. Compatibility DMA #RD #WR "0" #SEI PE "L" # AF " " #ST B #ACK BY # FT "H" "L" SE # INT0 ( ( ( ( 1) 2) 3) 4) 1 ACK STB 2 2 STB ( ( ( ( 5) 6) 7) 8) STB STB BUSY 3 ACK 1 Compatibility D1 DMA #R D #WR "0" #SEI "L" PE #AF "X" #ST B #ACK BY #FT "H" SE "L" #INT0 # DRQ 0 "H" ( ( ( ( ( 1) 2) 3) 4) 5) 1 ACK ACK STB 2 2 STB ( ( ( 6) 7) 8) Rev.1.02 STB DMA (#CS ACK 1 STB 3 ) BUSY CLK 1CLK D1 TOKYO ELECTRON DEVICE LIMITED 21 TE6138 TEL Original Products Compatibility < DMA STB > #RD #W R #SEI #ST B #AC K BY #INT0 ” ” STB+ < STB > #RD #W R #SEI "0" #S TB #ACK BY #INT0 STB+ STB Compatibility D7 D0 1 DMA RD DA K DRQ SEI "0" ST B AC K BY INT0 Compatibility 1 DMA Rev.1.02 BUSY H BUSY STB D7 TOKYO ELECTRON DEVICE LIMITED 22 86 68 #INT0 Xflag 0000 0000 Host Z 4 Host Busy Data Avail Data Avail 2 Data Transfer Data bit 1 Data bit 0 Data bit 3 Data bit 2 2 ( 6 Data bit 5 Data bit 4 Data bit 7 Data bit 6 2 TOKYO ELECTRON DEVICE LIMITED Device ID 3 1 Negotiation, Transfer Start Compatibility Mode Negotiation Z Peripheral Rev.1.02 nDataAvail Ptrbusy Ptrclk Hostclk HostBusy BP D7 AckDataReq 1284Active #WR #WR #RD 86 # W R 68 Nibble TEL Original Products 6 Device ID ( Z 5 H.B. D.N.A or Data Not Avail 3 1 Reverse Idle 2 500ns 3) 4) 5) Hosy Busy Data Not Avail 6) Data bit ( 2) Nibble/Byte 1284 ( ( ( ( 1 Busy Data Not Avail 35ms CLK ( 1) Nibble/Byte 23 Host 1284 8191(20MHz 409 s) TE6138 ) ) #INT0 Xflag 0000 0001 Host Compatibility Mode Negotiation Z "L" Peripheral Rev.1.02 nDataAvail Ptrbusy Ptrclk Hostclk HostBusy BPD 7-0 AckDataReq 1284Active # W R(86 # W R(68 #RD(8 6 ) # W R(68 ) Byte Z or 4 Data byte 0 Host Busy Data Avail Data Transfer Z 2) Device ID 3 Z 1 or 4 ( 2) Nibble/Byte 1284 ( 3) ( 4) 1284 3 1 2 500ns 1 Device ID Data byte 1 Data Transfer 2 ( 1) Nibble/Byte Host Busy Data Avail TOKYO ELECTRON DEVICE LIMITED Device ID 3) 1) Negotiation, Transfer Start TEL Original Products Z 35ms or CLK Host Busy Data Not Avail 24 Host Busy Data Not Avail 8191(20MHz 409 s) Reverse Idle 4 TE6138 P H/P nAckReverse Data(8 H P P P P HostClk PeriphClk PeriphAck nPeriphRequest XFlag E E E &9 E E E E E E E E E event 32 #RD IEEE1284 ECP Rev.1.02 #INT2 #RD #INT1 ECP nReverseRequest H H HostAck 1) H 1284Active CLK DMA ( ) 35mS ) 0000 0000 ) #RD &9 &8 &7 &6 &5 &4 &3 &2 &1 &0 &F ON HostClk E TOKYO ELECTRON DEVICE LIMITED &9 1000 0000 0011 000 0(ECP,RLE 0011 0000(ECP,RLE RLE TEL Original Products E 0000 0001 ( ) 0000 0001 0000 0001( 1010 1010( ) 0000 0001 1010 1010 ) 0000 0000 1111 1111 0101 0101( 1111 1111 E E &9 &8 &7 &6 &5 &4 &3 &2 &1 &0 &F &9 &8 &7 &6 &5 &4 &3 &2 &1 &0 &F Select nFau lt Perror TOKYO ELECTRON DEVICE LIMITED 0000 0001 0101 0101 ) TE6138 25 Busy P H/P nAckReverse Data(8 H P P P P H HostClk PeriphClk PeriphAck nPeriphRequest XFlag nReverseRequest Rev.1.02 #INT2 #RD #INT1 ECP H HostAck 1) H 1284Active CLK E E E &9 E E E E E E E E E RLE ( ) ) 0000 0000 ) &9 &8 &7 &6 &5 &4 &3 &2 &1 &0 &F ON HostClk E E TOKYO ELECTRON DEVICE LIMITED &9 1000 0000 0011 0000(ECP,RLE 0011 0000(ECP,RLE DMA TEL Original Products ) ) 0000 0001 1010 1010 ) 1010 1010( 0000 0001 0000 0001( 0000 0001 ( 0000 0000 1111 1111 ) 1111 1111 E E &9 &8 &7 &6 &5 &4 &3 &2 &1 &0 &F &9 &8 &7 &6 &5 &4 &3 &2 &1 &0 &F Select nFault Perror TOKYO ELECTRON DEVICE LIMITED 0000 0000 0101 0101 0101 0101( 26 Busy TE6138 P H/P H H P P P P Data(8 1) HostAck HostClk PeriphClk PeriphAck nPeriphRequest XFlag Rev.1.02 #DEND0 #DAK0 #DRQ0 #INT2 #RD #INT1 ECP nReverseRequest H H nAckReverse RLE 1284Active CLK DMA Z E E E E E E E E E E ( ) ) ) &9 &8 &7 &6 &5 &4 &3 &2 &1 &0 &F TOKYO ELECTRON DEVICE LIMITED &9 1000 00000000 0000 0011 0000(ECP,RLE E 0011 0000(ECP,RLE E ON HostClk TEL Original Products E E ) 0000 0001 ) ) 0000 0001 Z ) E E &9 &8 &7 &6 &5 &4 &3 &2 &1 &0 &F TOKYO ELECTRON DEVICE LIMITED Z 1111 1111 0000 0000 I/O Read 0101 0101 0101 0101( 0000 0000 1111 1111 I/O Read I/O Read 1010 1010 1010 1010( 0000 0001( 0000 0001 ( 27 &9 &8 &7 &6 &5 &4 &3 &2 &1 &0 &F Select nFault Perror TE6138 Busy RLE R Rev.1.02 #DEND0 #DAK0 #DRQ0 #INT2 #RD #INT1 ECP R nReverseRequest XFlag nPeriphRequest PeriphAck PeriphClk HostClk HostAck Data(8 1) nAckReverse 1284Active CLK DMA TOKYO ELECTRON DEVICE LIMITED OFF HostClk TEL Original Products TOKYO ELECTRON DEVICE LIMITED TE6138 28 H H P P P P H HostAck HostClk PeriphClk PeriphAck nPeriphRequest XFlag nReverseRequest Rev.1.02 #DEND0 #DAK0 #DRQ0 #INT2 #RD #INT1 ECP H/P E Data(8 1) Z E E E E E E E E E E P nAckReverse E H 1284Active CLK DMA ( ) ) 0000 0000 &9 &8 &7 &6 &5 &4 &3 &2 &1 &0 &F TOKYO ELECTRON DEVICE LIMITED &9 1000 0000 ) HostClk 0011 0000(ECP,RLE 0011 0000(ECP,RLE TEL Original Products E E 0010 0000 1000 0001( 1000 0001( ) 0000 0000 ) ) 1010 1010 1010 1010( ) TOKYO ELECTRON DEVICE LIMITED 0101 0101 0101 0101( TE6138 29 P P P H PeriphAck nPeriphRequest XFlag nReverseRequest S S Rev.1.02 #DEND0 #DAK0 #DRQ0 #INT2 #WR #RD #INT1 ECP P PeriphClk R H HostClk R H HostAck E E Z E E E E E E E E E E Data(8 E P H/P E nAckReverse 1) H 1284Active CLK ( 0011 0100(ID DMA ) 0000 0000 ) &9 &8 &7 &6 &5 &4 &3 &2 &1 &0 &F E E Z TOKYO ELECTRON DEVICE LIMITED &9 1000 0000 0011 0100(ID ) TEL Original Products 0000 0000 0000 1000 E E 0000 0001( 0000 0001( )) 0000 0000 0000 1000 ) 1010 1010( 1010 1010( 0000 0000 0000 1000 &9 &8 &7 &6 &5 &4 &3 &2 &1 &0 &F Z TOKYO ELECTRON DEVICE LIMITED ) ) TE6138 30 P P H nPeriphRequest XFlag nReverseRequest S Rev.1.02 #DAK1 #DRQ1 #INT2 #WR #RD #INT1 ECP P PeriphAck R P PeriphClk R H HostClk E E E E E E E E E E E H HostAck E P H/P E Data(8 1) H nAckReverse 1284Active CLK ( ) ) 0000 0000 &9 &8 &7 &6 &5 &4 &3 &2 &1 &0 &F E E Z TOKYO ELECTRON DEVICE LIMITED &9 1000 0000 0001 0000 0001 0000(ECP,RLE DMA TEL Original Products 1010 1010( ) 1010 1010( ) DMA TOKYO ELECTRON DEVICE LIMITED &9 &8 &7 &6 &5 &4 &3 &2 &1 &0 &F Z TE6138 31 H P P P P HostClk PeriphClk PeriphAck nPeriphRequest XFlag Rev.1.02 #DEND0 #DAK0 #DRQ0 #INT2 #RD #INT1 2 nReverseRequest H H HostAck ECP E 1000 000 0( ( 11XX XXXX Z E E E E E E E E ) ) 000 0 0000 ) &9 &8 &7 &6 &5 &4 &3 &2 &1 &0 &F E TOKYO ELECTRON DEVICE LIMITED &9 1000 0000 1000 000 0( Perip hera l Busy Status E H/P E P 1) nAckReverse Data(8 H 1284Active CLK TEL Original Products 00 11 000 0(ECP ) &9 &8 &7 &6 &5 &4 &3 &2 &1 &0 &F RL E 000 1 0000 (ECP ) 0100 0000(EPP &9 &8 &7 &6 &5 &4 &3 &2 &1 &0 &F ) TOKYO ELECTRON DEVICE LIMITED &9 &8 &7 &6 &5 &4 &3 &2 &1 &0 &F RLE E TE6138 32 H P P P P H HostClk PeriphClk PeriphAck nPeriphRequest XFlag nReverseRequest Rev.1.02 #INT2 #RD #INT1 ECP H HostAck P H/P nAckReverse Data(8 1) H 1284Active CLK &1 &0 &F E DMA 1010 1010 ) 0101 0101 0101 0101( TOKYO ELECTRON DEVICE LIMITED E ) HostClk 1010 1010( TEL Original Products E E 0000 0000 0000 0100 35ms ) 0101 0101( 0101 0101( ) TOKYO ELECTRON DEVICE LIMITED TE6138 33 P H/P nAckReverse Data(8 H P P P P H HostClk PeriphClk PeriphAck nPeriphRequest XFlag nReverseRequest Rev.1.02 #DEND0 #DAK0 #DRQ0 INT2 RD BPoINT1 ECP H HostAck 1) H 1284Active BPiCLK Z &F E E 0101 0101 0101 0101( ) TOKYO ELECTRON DEVICE LIMITED Z 1010 1010 ) HostClk 1010 1010( DMA TEL Original Products E E Z 0000 0000 0000 0100 35ms ) Z 0101 0101( 0101 0101( ) TOKYO ELECTRON DEVICE LIMITED TE6138 34 Rev.1.02 INT2 #WR #RD #INT1 ECP nReverseRequest XFlag nPeriphRequest PeriphAck PeriphClk HostClk HostAck Data(8 1) nAckReverse 1284Active CLK TE6137 TOKYO ELECTRON DEVICE LIMITED TEL Original Products TOKYO ELECTRON DEVICE LIMITED TE6138 35 P H/P nAckReverse Data(8 H P P P P H HostClk PeriphClk PeriphAck nPeriphRequest XFlag nReverseRequest Rev.1.02 #INT2 #WR #RD #INT1 ECP H HostAck 1) H 0000 0000 ) 1000 0000 1111 1111 E E &9 &8 &7 &6 &5 &4 &3 &2 &1 &0 &F TOKYO ELECTRON DEVICE LIMITED 0000 0000 ) Compatibility 0101 0101( 0101 0101( Valid termination 1284Active CLK ECP TEL Original Products Busy 1000 0000 &9 &8 &7 &6 &5 &4 &3 &2 &1 &0 &F Select nFault Perror TOKYO ELECTRON DEVICE LIMITED TE6138 36 TE6138 TEL Original Products 5. Compatibility DMA Byte Compatibility Compatibility ,Nibble ,Byte DMA ECP Y ECP ECP D7 Rev.1.02 0 TOKYO ELECTRON DEVICE LIMITED 37 TE6138 TEL Original Products 6.ECP 1 DMA ( 2 RLE 2 ( D2 2 1: D3 3 ( 4 (ECP 1: 2 0: ) 0: ) D4 1: D6 0: 1: ) 0: ) > < 1 - 2 3 - - TE6138 4 - #INT1+ECPIR D5 Peripheral CPU ECPIR ECPIR:ECP < > 1 - 2 0 1 3 < > [DMA ] 1 0 0 0 0 0 0 [DMA 1 1 1 2 0 1 0 1 0 1 TE6138 4 - - 3 0 0 1 1 4 0 0 1 1 0 0 3 4 #INT1+ECPIR D4 Peripheral CPU ECPIR - TE6138 Peripheral CPU #INT1+ECPIR D6 ECPIR ECPIR D6 ECPIR #INT2 ] 2 0 1 - Rev.1.02 - TE6138 Peripheral CPU DMA TOKYO ELECTRON DEVICE LIMITED 38 TE6138 TEL Original Products VDD VI VO TST -0.3 +6.0 -0.3 VDD+0.3 -0.3 VDD+0.3 -55 +150 ( VDD TA ) 4.5 -20 5.5 70 IDDS “1” VIH “0” VIL “H” “L” VOH VOL CIN COUT CI/O Rev.1.02 V V 2.3 3.8 VDD-0.4 - TTL CMOS TTL CMOS IOH=-2mA IOL=6mA 20 20 20 0.2 0.7 1.1 0.4 mA V pF TOKYO ELECTRON DEVICE LIMITED 39 TE6138 TEL Original Products =20pF =20pF 1.CPU CIS ”0” (86 ) T1 T2 T5 T4 T3 T6 T7 T8 T11 T9 T10 T12 T13 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 #RD #RD #RD #RD #RD #RD #RD #WR #WR #WR #WR #WR #WR #WR #CS #CS A3-0 A3-0 #RD D7-0(Z V) D7-0(V Z) #CS #CS #WR A3-0 A3-0 D7-0 D7-0 T14 S H S H W D D S H W S H S H 10 10 15 10 30 10 10 30 10 15 15 0 20 15 - ns S H D W Rev.1.02 TOKYO ELECTRON DEVICE LIMITED 40 TE6138 TEL Original Products CIS ”1” (68 ) T1 5 T1 6 T17 T18 T1 9 T2 0 T21 T22 T2 3 T25 T24 T2 6 T2 8 T2 7 T2 9 T30 T31 T15 T16 T17 T18 T19 T20 T21 T22 T23 T24 T25 T26 T27 T28 T29 T30 T31 T32 Rev.1.02 #WR #WR #WR #WR #WR #WR #WR #WR #WR #WR #WR #WR #WR #WR #WR #WR #WR #WR #CS #CS #RD #RD A3-0 A3-0 #WR D7-0(Z V) D7-0(V Z) #RD #RD #CS #CS #WR A3-0 A3-0 D7-0 D7-0 T32 S H S H S H W D D S H S H W S H S H 10 10 10 10 10 10 30 10 10 10 10 30 10 10 15 0 20 15 - ns - H - W S D TOKYO ELECTRON DEVICE LIMITED 41 TE6138 TEL Original Products 2. DMA CPU 86 68 CPU ” Compatibility DMA ” DAK RD WR(EN) DMA <86 > ECP Mode 0000 0010 0000 0001 0000 0000 1111 1111 #DRQ0 Z Z #DEND0 #DAK0 T47 #RD T 41 T42 T43 T 44 T45 T 46 T48 D7-0 T4 T4 Z <68 > 0000 0010 ECP Mode 0000 0001 0000 0000 1111 1111 #DRQ0 Z Z #DEND0 #DAK0 #W R T4 T T T T D7-0 T5 T5 Z Rev.1.02 TOKYO ELECTRON DEVICE LIMITED 42 TE6138 TEL Original Products <68 > ECP Mode 0000 0000 1111 1111 #DRQ0 0 #DE Z Z # #W R D7-0 T5 T Z T41 T42 T43 T44 T45 T46 T47 T48 T49 T4A T4B T50 T51 T52 T53 T54 T55 T56 T57 T5A T5B #RD #RD #RD #RD #RD #RD #RD #RD #WR #RD #RD #WR #WR #WR #WR #WR #WR #DAK0 #DAK0 #WR #WR Rev.1.02 #DAK0 #RD #RD #DEND0(Z L) #DEND0(L Z) #DRQ0 #DAK0 #RD #DAK0 D7-0(Z V) D7-0(V Z) #WR #WR #DEND0(Z L) #DRQ0 #DEND0(L Z) #WR #DEND0(Z L) #DRQ0 D7-0(Z V) D7-0(V Z) S W W D D D H CT S D D W W D D D CT D D D D 0 30 30 0 2T BC 0 30 30 2T BC - 1.5T BC+20 1.5T BC+20 25 20 20 1.5T BC+20 1.5T BC+20 1.5T BC+20 20 20 20 20 ns TOKYO ELECTRON DEVICE LIMITED S H D W CT TBC=CLK 43 TE6138 TEL Original Products DMA < > # DRQ 1 T64 #DAK1 DMA #WR T6 1 T65 T63 T62 #DEND1 T6 6 T67 D7-0 T6A T6B 1 D RQ 1 < D MA DE ND1 > # DRQ 1 T74 #DAK1 DMA #WR T T 2 T 5 T 3 #DEND1 T 6 T 7 D7-0 T A T B 1 DR Q1 Rev.1.02 D MA DEND1 TOKYO ELECTRON DEVICE LIMITED 44 TE6138 TEL Original Products T61 T62 T63 T64 T65 T66 T67 T6A T6B T71 T72 T73 #WR #WR #WR #DAK1 #WR #DEND1 #DEND1 #WR #WR #WR #WR #WR #DAK1 # WR #DAK1 #DRQ1 #DRQ1 #DEND1 #DRQ1 D7-0 D7-0 #DAK1 #WR #DAK1 S W H D D W D S H S W H 0 30 0 TBC 15 0 0 30 0 2T BC+20 3T BC+20 3T BC+20 - T74 #DAK1 #DRQ1 D - 2T BC+20 T75 T76 T77 T7A T7B #WR #DEND1 #DEND1 #WR #WR #DRQ1 #DEND1 #DRQ1 D7-0 D7-0 D W D S H TBC 15 0 3T BC+20 3T BC+20 - Rev.1.02 - TOKYO ELECTRON DEVICE LIMITED ns S H D W T BC=CLK 45 TE6138 TEL Original Products TE6138 CLK TP TN TF “1” “0” TR TP TN TR TF TC 20 20 50 15 15 62.5 ns TAW 50 - ns TE6138 T AW Rev.1.02 TOKYO ELECTRON DEVICE LIMITED 46 TE6138 TEL Original Products 64 TQFP mm 0.38g 14.0 0.2SQ 12.0 0.2SQ 48 33 49 32 64 17 1 1.125 16 0.32 +0.06 -0.10 0.13 M 0.65TYP 1.0 0.2 0.17 0.10 Rev.1.02 TOKYO ELECTRON DEVICE LIMITED 47 +0.03 -0.07 TE6138 TEL Original Products TOP 224-0045 1 TEL 045-474-7013 FAX 045-474-5617 E-mail [email protected] URL http://www.teldevice.co.jp © 2000 Tokyo Electron Rev.1.02 Device Limited printed in JAPAN TOKYO ELECTRON DEVICE LIMITED 2002 2 48