ETC TMS320C6000

TMS320C6000 FAMILY: EMIF
Ingeniería Electrónica
Sistemas Electrónicos Digitales Avanzados
1
TMS320C6000 FAMILY: EMIF
‹Introduction.
z Characteristics, signals, memory map, alignment.
z Configuration registers.
z Types of interface.
‹ Asynchronous interface.
z Introduction, waveforms.
z Case Study I: Peripheral connection.
z Case Study II: Memory connection.
‹ Interface with synchronous static memories.
z Synchronous static memories.
z Interface description.
z Example.
‹ Interface with synchronous dynamic memories.
z SDRAM memories.
z Interface description.
z Example.
Ingeniería Electrónica
Sistemas Electrónicos Digitales Avanzados
2
Need for an EMIF
Need
for
EMIF
‹ Traditional DSP
(with
noan
EMIF):
Peripheral/
Memory
H/W
Interface
DSP
‹ When interfacing a slow peripheral/memory to a fast
DSP, some hardware interface is required.
‹ This hardware interface requires fast components in
order to keep up with the DSP.
Ingeniería Electrónica
Sistemas Electrónicos Digitales Avanzados
3
Need for an EMIF (II)
Need
for
EMIF
‹ Traditional DSP
(with
noan
EMIF):
Peripheral/
Memory
H/W
Interface
DSP
‹ Drawback of the hardware interface:
z
z
z
z
z
High cost (additional components).
Power consumption.
Difficult to debug.
Cannot be upgraded.
Prone to errors.
Ingeniería Electrónica
Sistemas Electrónicos Digitales Avanzados
4
The EMIF
EMIFinterface to several
‹ The EMIF supportsThe
a glueless
external devices, including:
z
z
z
z
Synchronous burst SRAM (SBSRAM).
Synchronous DRAM (SDRAM).
Asynchronous devices, including SRAM, ROM and FIFO’s.
An external shared-memory device.
‹ For more information on different memory types see
spra631.pdf
‹ A detailed description for each memory type interface
can be found in:
z Asynchronous SRAM: spra542a.pdf
z Synchronous burst SRAM: spra533.pdf
z Synchronous DRAM: spra433b.pdf
Ingeniería Electrónica
5
Sistemas Electrónicos Digitales Avanzados
The EMIF
‹
The C621x/C671x servicesThe
requests
of the external bus from the
EMIF
requestors:
z On-chip Enhanced Direct Memory Access (EDMA) controller.
z External shared-memory device controller.
EMIF
L1P Cache
C6000 DSP core
Instruction Fetch
Other
Peripherals
Enhanced
DMA
Controller
Interrupt
Selector
Control
Registers
Control
Logic
Instruction Dispatch
L2
Memory
Instruction Decode
Data Path A
Data Path B
Test
A Register File
B Register File
In–Circuit
Emulation
L1
S1 M1 D1
D2 M2 S2
L2
Interrupt
Control
Power Down
Logic
Boot
Configuration
Ingeniería Electrónica
PLL
L1D Cache
Sistemas Electrónicos Digitales Avanzados
6
MEMORY MAP
Byte Address
0000_0000
External Memory
64K x 8 Internal
(L2 cache)
‹
‹
0180_0000
On-chip Peripherals
Internal Memory
‹
‹
8000_0000
0 256M x 8 External
9000_0000
1 256M x 8 External
A000_0000
2 256M x 8 External
B000_0000
3 256M x 8 External
Async (SRAM, ROM, etc.)
Sync (SBSRAM, SDRAM)
Unified (data or prog)
prog)
4 blocks - each can be
RAM or cache
Level 1 Cache
‹
‹
‹
4KB Program
4KB Data
Not in map
CPU
L2
64K
4K
D
FFFF_FFFF
Ingeniería Electrónica
4K
P
Sistemas Electrónicos Digitales Avanzados
7
MEMORY MAP (II)
Description
Internal RAM (L2) mem
EMIF control regs
Cache configuration reg
L2 base addr & count regs
L1 base addr & count regs
L2 flush & clean regs
CE0 mem attribute regs
CE1 mem attribute regs
CE2 mem attribute regs
CE3 mem attribute regs
HPI control reg
McBSP0 regs
McBSP1 regs
Timer0 regs
Timer1 regs
Interrupt selector regs
EDMA parameter RAM
EDMA control regs
QDMA regs
QDMA pseudo-regs
McBSP0 data
McBSP1 data
CE0, 256 MBytes
CE1, 256 MBytes
CE2, 256 MBytes
CE3, 256 MBytes
Ingeniería Electrónica
Origin
0x00000000
0x01800000
0x01840000
0x01844000
0x01844020
0x01845000
0x01848200
0x01848240
0x01848280
0x018482c0
0x01880000
0x018c0000
0x01900000
0x01940000
0x01980000
0x019c0000
0x01a00000
0x01a0ffe0
0x02000000
0x02000020
0x30000000
0x34000000
0x80000000
0x90000000
0xA0000000
0xB0000000
Length
0x00010000
0x00000024
0x00000004
0x00000020
0x00000020
0x00000008
0x00000010
0x00000010
0x00000010
0x00000010
0x00000004
0x00000028
0x00000028
0x0000000c
0x0000000c
0x0000000c
0x00000800
0x00000020
0x00000014
0x00000014
0x04000000
0x04000000
0x10000000
0x10000000
0x10000000
0x10000000
Sistemas Electrónicos Digitales Avanzados
8
C6211/C6711 EMIF Features
Features
C621x / C671x
Bus Width
32
# Memory Spaces
4
Addressable Space (Mbytes)
512
Synchronous Clocking
Independent ECLKIN
Width Support
8/16/32
Supported Memory Type at CE1
All types
Control Signals
Mixed all control signals
Synchronous memory in system
Both SDRAM and SBSRAM
Additional registers
SDEXT
PDT Support
No
ROM/Flash
Yes
Asynchronous memory I/O
Yes
Pipeline SBSRAM
Yes
Ingeniería Electrónica
9
Sistemas Electrónicos Digitales Avanzados
C6713 EMIF Signals
C6211/C6711 EMIF Signals
‹ Clock signals:
z ECLKIN
z ECLKOUT
ECLKIN
ECLKOUT
ED[31:0]†
Shared by
all external
interfaces
EA[21:2]
CE[3:0]
BE[3:0]
Enhanced
data
memory
controller
External
memory
interface
(EMIF)
ARDY
AOE/SDRAS/SSOE
ARE/SDCAS/SSADS
AWE/SDWE/SSWE
HOLD
HOLDA
Control
registers
BUSREQ
MUXed
Asynch/SDRAM/SBSRAM
control
‹
‹
‹
‹
Data bus: ED[31:0]
Address bus: EA[21:2]
Byte enable: BE[3:0]
Control signals:
z Asynchronous ready.
z Memory type
depending.
‹ Bus arbitration:
Internal
peripheral bus
z Hold
z Hold acknowledge.
z Bus request.
‹ For a description of the signals see: \Links\signals.pdf
Ingeniería Electrónica
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10
C6211/C6711 EMIF Configuration
C6211/C6711
Configuration
‹ The following
need toEMIF
be configured
when interfacing the
DSP to an external device using the EMIF:
(1) Memory space control registers (software):
These registers describe the type and timing of the external
memory to be used.
(2) EMIF chip enable (hardware):
There are four chip enable (CE0, CE1, CE2 and CE3) that are
used when accessing a specific memory location (e.g. if you try to
access memory 0x9000 0000 then CE1 will be activated, see next
slide).
Ingeniería Electrónica
Sistemas Electrónicos Digitales Avanzados
11
C6211/C6711 EMIF Memory Spaces
Memory Block Description
Block Size (Bytes)
HEX Address Range
Internal RAM (L2)
64K
0000 0000 - 0000 FFFF
Reserved
24M-64K
0001 0000 - 017F FFFF
EMIF Registers
256k
0180 0000 - 0183 FFFF
L2 Registers
256k
0184 0000 - 0187 FFFF
HPI Registers
256k
0188 0000 - 018B FFFF
McBSP 0 Registers
256k
018C 0000 - 018F FFFF
McBSP 1 Registers
256k
0190 0000 - 0193 FFFF
Timer 0 Registers
256k
0194 0000 - 0197 FFFF
Timer 1 Registers
256k
0198 0000 - 019B FFFF
019C 0000 - 019F FFFF
Interrupt selector Registers
256k
EDMA RAM and EDMA Registers
256k
01A0 0000 - 01A3 FFFF
Reserved
64M-256k
01A4 0000 - 01FF FFFF
QDMA Registers
52
0200 0000 - 0200 FFFF
Reserved
736M-52
0200 0034 - 2FFF FFFF
MCBSP 0/1 Data
256M
3000 0000 - 3FFF FFFF
Reserved
1G
4000 0000 - 7FFF FFFF
EMIF CE0
256M
8000 0000 - 8FFF FFFF
EMIF CE1
256M
9000 0000 - 9FFF FFFF
EMIF CE2
256M
A000 0000 - AFFF FFFF
EMIF CE3
256M
B000 0000 - BFFF FFFF
Reserved
1G
C000 0000 - FFFF FFFF
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12
Memory Space Control Registers
Memory Map
Space Control Registers
0000_0000
180_0000
180_0008
180_0004
180_0010
180_0014
180_0018
180_001C
Global Control
0180_0000
CE0 Control
CE1 Control
CE2 Control
CE3 Control
Peripherals
SDRAM Control
SDRAM Refresh Prd
Ingeniería Electrónica
13
Sistemas Electrónicos Digitales Avanzados
Memory Space Control Registers
C6211/C6711
EMIF
‹ Global Control
(GBLCTL):
theRegisters
EMIF global control
register configures parameters that are common to all the
CE spaces.
z
z
Polarity definition (x).
Signal enable (x).
31
16
Rsv
R, +0
15
14
13
12
Rsv
Rsv
Rsv
Rsv
R,+0
RW,+0
RW,+1
RW,+1
Ingeniería Electrónica
7
6
5
BUSREQ
ARDY
HOLD HOLDA
NO
HOLD
Rsv
Rsv
R, +0
R,+x
R,+x
RW, +0
R,+1
R,+1
11
10
9
8
R,+x
4
3
CLK1EN CLK2EN
RW, +1
RW, +1
Sistemas Electrónicos Digitales Avanzados
2
1
0
Rsv
Rsv
Rsv
R,+0
R,+0
R, +0
14
EMIF Registers
Question: Why do we need different spaces?
Answer: Different spaces allow different types of devices to
be used at the same time.
‹
CE0, CE1, CE2, CE3 space control registers (CECTL): are used to
specify the type and the read and write timing used for a particular
space.
31
28
27
22
Write setup
Write strobe
RW, +1111
15
14
RW, +111111
13
8
21
20
19
16
Write hold
Read setup
RW, +11
RW, +1111
7
4
3
2
0
TA
Read strobe
MTYPE
Write hold MSB ‡
Read hold
R, +11
RW, +111111
RW, +0010†
RW, +0
RW, +011
† MTYPE default value is RW, +0000.
‡ For C621x/C671x, this field is reserved. R,+0.
Ingeniería Electrónica
15
Sistemas Electrónicos Digitales Avanzados
EMIF Registers
Field
READ SETUP
WRITE SETUP
Description
†
Setup width. Number of clock cycles of setup for address (EA) and
byte enables (/BE(0-3)) before read strobe (/ARE) or write strobe
(/AWE) falling. On the first access to a CE space, this is also the
setup after /CE falling.
READ STROBE
WRITE STROBE
READ HOLD
WRITE HOLD
Strobe width. The width of read strobe (/ARE) and write strobe
(/AWE) in clock* cycles.
MTYPE
Memory type
‘C6201/’C6202/’C6701 only:
MTYPE = 000b: 8-bit-wide ROM (CE1 only)
MTYPE = 001b: 16-bit-wide ROM (CE1 only)
MTYPE = 010b: 32-bit-wide asynchronous interface
‘C6211/’C6711 only:
MTYPE = 0000b: 8-bit-wide asynchronous interface
MTYPE = 0001b: 16-bit-wide asynchronous interface
MTYPE = 0010b: 32-bit-wide asynchronous interface
TA
‡
†
Hold width. Number of clock cycles that address (EA) and byte
strobes (/BE(0-3)) are held after read strobe (/ARE) or write strobe
(/AWE) rising. These fields are extended by one bit on the
‘C6211/’C6711.
Turnaround time. Controls the number of ECLKOUT cycles between
a read and a write or between two reads.
† Clock = CLKOUT1 for ‘C6201/’C6202/’C6701.Clock = ECLKOUT for ‘C6211/’C6711.
‡ Applies to ‘C6211/’C6711 only.
Ingeniería Electrónica
Sistemas Electrónicos Digitales Avanzados
Avoid bus
contention
16
MEMORY WIDTH & BYTE
ALIGNMENT
Memory
type
ASRAM
SBSRAM
SDRAM
Memory
width
Maximum
addressable
bytes per CE
space
Address
output on
EA[21:2]
Represents
x8
1M
A[19:0]
Byte address
x16
2M
A[20:1]
Halfword address
x32
4M
A[21:2]
Word address
x8
1M
A[19:0]
Byte address
x16
2M
A[20:1]
Halfword address
x32†
4M
A[21:2]
Word address
x8
32M
See
section 10.5
Byte address
x16
64M
See
section 10.5
Halfword address
128M
See
section 10.5
Word address
x32
Ingeniería Electrónica
ED[31:24]
TMS320C621x/C671x
ED[23:16]
ED[15:8]
ED[7:0]
32-bit device
16-bit device
big endian
16-bit device
little endian
8-bit
device
big endian
Sistemas Electrónicos Digitales Avanzados
8-bit
device
little endian
17
TMS320C6000 FAMILY: EMIF
‹ Introduction.
z Characteristics, signals, memory map, alignment.
z Configuration registers.
z Types of interface.
‹Asynchronous interface.
z Introduction, waveforms.
z Case Study I: Peripheral connection.
z Case Study II: Memory connection.
‹ Interface with synchronous static memories.
z Synchronous static memories.
z Interface description.
z Example.
‹ Interface with synchronous dynamic memories.
z SDRAM memories.
z Interface description.
z Example.
Ingeniería Electrónica
Sistemas Electrónicos Digitales Avanzados
18
ASYNCHRONOUS INTERFACE
‹ It uses a Intel approach: two command signals to define the
access direction and validate the rest of the signals used for
decoding:
z Read: ARE
z Write: AWE
‹ These signals define the active part of the access cycle.
‹ The rest of signals used for decoding must be stables during the
active part.
Address and
control signals
/ARE
/AWE
Ingeniería Electrónica
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19
ASYNCHRONOUS INTERFACE
Asynchronous read timing example (2/3/1)
Setup
2
Strobe
3
Hold
1
ECLKOUT
z
z
CE
BE[3:0]
BE
EA[21:2]
Address
ED[31:0]
z
Read D
z
AOE
ARE
AWE
z
Active part: 3 cycles.
Decoded signals are
stable 2 cycles before
active part.
Data captured at the
end of active part.
Decoded signals remain
stable 1 cycle after
active part.
RDY signal is tested at
the beginning of the last
cycle of the active part.
ARDY
Ingeniería Electrónica
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20
ASYNCHRONOUS INTERFACE
Asynchronous write timing example (2/3/1)
Setup
2
Strobe
3
Hold
1
Strobe
3
Setup
2
Hold
1
ECLKOUT
CE
BE[3:0]
BE1
BE2
EA[21:2]
A1
A2
ED[31:0]
D1
D2
AOE
ARE
AWE
ARDY
Ingeniería Electrónica
21
Sistemas Electrónicos Digitales Avanzados
ASYNCHRONOUS INTERFACE
Ready operation: Wait state insertion
Setup
2
Strobe extended
3
Programmed strobe
4
Ready sampled
Hold
1
Data
latched
ECLKOUT
CE
BE[3:0]
BE
EA[21:2]
Address
ED[31:0]
D
AOE
ARE
AWE
ARDY
Ingeniería Electrónica
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22
ASYNCHRONOUS INTERFACE
Turnaround Time
HOLD
TA = 2
SETUP
ECLKOUT
td
td
td
td
/CEx
/BE[3:0]
td
EA [21:2]
tohz(m)
td
ED [31:0]
td
/AOE
/ARE
/AWE
ARDY
Ingeniería Electrónica
23
Sistemas Electrónicos Digitales Avanzados
REAL WAVEFORMS: READ ACCESS
Setup = 2
Strobe = 3
Not Ready
Hold = 2
ECLKOUT
1
2
CEx
1
2
BE[3:0]
BE
1
2
EA[21:2]
Address
3
4
ED[31:0]
1
2
Read Data
AOE/SDRAS/SSOE
5
5
ARE/SDCAS/SSADS
AWE/SDWE/SSWE
7
6
7
6
ARDY
Outputs:
Delay time max: 7 ns
Ingeniería Electrónica
Data capture:
Setup time min: 6.5 ns
Hold time min: 1 ns
ARDY test:
Setup time min: 3 ns
Hold time min: 2.3 ns
Sistemas Electrónicos Digitales Avanzados
24
REAL WAVEFORMS: WRITE ACCESS
Setup = 2
Strobe = 3
Hold = 2
Not Ready
ECLKOUT
8
9
CEx
8
9
BE[3:0]
BE
8
9
EA[21:2]
Address
8
9
ED[31:0]
Write Data
AOE/SDRAS/SSOE
ARE/SDCAS/SSADS
10
10
AWE/SDWE/SSWE
7
7
6
6
ARDY
Outputs:
Delay time max: 7 ns
Ingeniería Electrónica
ARDY test:
Setup time min: 3 ns
Hold time min: 2.3 ns
Sistemas Electrónicos Digitales Avanzados
25
PROGRAMMABLE PARAMETERS
All of then are expressed as TECLKOUT units:
z
z
z
z
SETUP ≥ 1
(0 is treated as 1)
STROBE ≥ 1
(0 is treated as 1)
HOLD ≥ 0
TURNAROUND ≥ 0
TECLKOUT depends on system design:
z For DSK6713: TECLKOUT= 50 MHz => TECLKOUT = 20 ns.
Ingeniería Electrónica
Sistemas Electrónicos Digitales Avanzados
26
TYPICAL APPLICATIONS
‹ The asynchronous interface is usually used to add extend the
system resources by adding:
z External peripheral with parallel interface: This kind of peripherals
usually have an asynchronous interface.
z Asynchronous memory banks: Easy design but reduced band width
=> restricted to non volatile memories (i.e FLASH)
‹ We will see two examples:
z Peripheral connection: A/D y D/A.
z Asynchronous memory banks connection.
Ingeniería Electrónica
Sistemas Electrónicos Digitales Avanzados
27
TMS320C6000 FAMILY: EMIF
‹ Introduction.
z Characteristics, signals, memory map, alignment.
z Configuration registers.
z Types of interface.
‹ Asynchronous interface.
z Introduction, waveforms.
z Case Study I: Peripheral connection.
z Case Study II: Memory connection.
‹ Interface with synchronous static memories.
z Synchronous static memories.
z Interface description.
z Example.
‹ Interface with synchronous dynamic memories.
z SDRAM memories.
z Interface description.
z Example.
Ingeniería Electrónica
Sistemas Electrónicos Digitales Avanzados
28
EMIF CASE STUDY (I)
Case Study
‹ DSK interface EMIF
to:
z
z
AD768 DAC.
AD9220 ADC.
DSK
Ingeniería Electrónica
E
M
I
F
AD9220
ADC
Channel 1
AD9220
ADC
Channel 2
AD768
DAC
Channel 1
AD768
DAC
Channel 2
Sistemas Electrónicos Digitales Avanzados
29
EMIF CASE STUDY: AD768 DAC
‹ Specification:
EMIF Case Study: AD768 DAC
FEATURES:
30 msps Update Rate
16-Bit Resolution
Linearity: 1/2 LSB DNL @ 14 Bits
1 LSB INL @ 14 Bits
Fast Settling: 25ns Full-Scale Settling to 0.025%
SFDR @ 1 MHZ Output: 86 dBc
THD @ 1 MHZ Output: 71 dBc
Low Glitch Impulse: 35 pV-s
Power Dissipation: 465 mW
On-chip 2.5V reference
Edge Triggered Latches
Multiplying Reference Capability
APPLICATIONS:
Arbitrary Waveform Generation
Communications Waveform Reconstruction
Vector Stroke Display
‹ AD768 data sheet
Ingeniería Electrónica
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30
EMIF CASE STUDY: AD768 DAC
EMIF
Case
Study: AD768 DAC
‹ Functional
Block
Diagram:
FUNCTIONAL BLOCK DIAGRAM
DCOM
VDD
DB15 (MSB)
AD768
MSBs: SEGMENTED
CURRENT SOURCES
AND SWITCHES
MS B
DECODER
and EDGETRIGGERED
BIT
LATCHES
LSBs:
CURRENT SOURCES,
SWITCHES, AND 12k R-2R
LADDERS
INOUTA
INOUTB
1K
1K
LADCOM
2.5 v
BANDGAP
REFERENCE
CONTROL
AMP
VEE
DB0 (LSB)
CLOCK
NC
REFCOM REFOUT IREFIN NR
‹ AD768 data sheet
Ingeniería Electrónica
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31
EMIF CASE STUDY: AD768 DAC
EMIF Case Study: AD768 DAC
‹ Timing:
tS = 10 ns
tH = 5 ns
tLPW = 10 ns
NOTE: for DSK6713 TECLKOUT= 50 MHz => TECLKOUT = 20 ns.
‹ AD768 data sheet
Ingeniería Electrónica
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32
EMIF CASE STUDY: AD768 DAC
Case Study:
AD768 DAC
‹ C6713EMIF
Asynchronous
Write Timing:
Setup = 2
Strobe = 3
Hold = 2
Not Ready
ECLKOUT
8
9
CEx
8
9
BE[3:0]
BE
8
9
EA[21:2]
Address
8
9
ED[31:0]
Write Data
AOE/SDRAS/SSOE
ARE/SDCAS/SSADS
10
10
AWE/SDWE/SSWE
7
7
6
6
ARDY
Ingeniería Electrónica
33
Sistemas Electrónicos Digitales Avanzados
SETTING ASYNC TIMING
31
28 27
22 21
20 19
Write Setup
Write Strobe
Write
Hold
RW, +1111
RW, +111111
RW, +11
15
TA
14 13
8
7
MTYPE
Read Strobe
RW, + 111111
RW, +0010
Set CE3 and to 32-bit ASYNC
CE3
.equ
mvkl.s1
mvkh.s1
ldw
nop 4
and
set
stw .d1
Ingeniería Electrónica
1800014h
CE3, A0
CE3, A0
*A0, A1
A1,
A1,
A1,
4
16
Read Setup
RW, +1111
3
Write Hold
MSB
RW, +0
2
0
Read
Hold
RW, +11
000b = 8-bit-wide ROM
001b = 16-bit-wide ROM
010b = 32-bit-wide Async
011b = 32-bit-wide SDRAM
100b = 32-bit-wide SBSRAM
0xff0f, A1
Note: There are more
5, 5, A1
MTYPE options. See:
*A0
\Links\spru190d.pdf
Sistemas Electrónicos Digitales Avanzados
34
SETTING ASYNC TIMING
EMIF
Case Study: AD768 DAC
‹ Hardware
Interface:
D/A
Analogue
Buffering
16
XD[0..15]
CLK
/XAWE
/XCE3
Analogue
Out
(Chan1)
CLK
D/A
16
XD[16..31]
DaughtercardConnector
Analogue
Out
(Chan2)
‹ AD768 data sheet
Ingeniería Electrónica
Sistemas Electrónicos Digitales Avanzados
35
EMIF CASE STUDY: AD768 DAC
EMIF Case Study: AD9220 ADC
‹ Specifications:
FEATURES
Monolithic 12-Bit A/D Converter Product Family
Family Members Are: AD9221, AD9223, and AD9220
Flexible Sampling Rates: 1.5 MSPS, 3.0 MSPS and 10 MSPS
Low Power Dissipation: 59 mW, 100 mW and 250 mW
Single +5V Supply
Integral Nonlinearity Error: 0.5 LSB
Differential Nonlinearity Error: 0.3 LSB
Input Referred Noise: 0.09LSB
Complete On-Chip Sample-and-Hold Amplifier and
Voltage Reference
Signal-to-Noise and Distortion Ratio: 70dB
Spurious-Free Dynamic Range: 86dB
Out-of-range Indicator
Straight Binary Output Data
28-Lead SOIC and 28-Lead SSOP
‹ AD9220 data sheet
Ingeniería Electrónica
Sistemas Electrónicos Digitales Avanzados
36
EMIF CASE STUDY: AD9220 ADC
‹ Functional Block Diagram:
‹ AD9220 data sheet
Ingeniería Electrónica
Sistemas Electrónicos Digitales Avanzados
37
EMIF CASE STUDY: AD9220 ADC
EMIF Case Study: AD9220 ADC
‹ Timing:
tC = 100 ns
tCH = 45 ns
tCL = 45 ns
tOD = 19 ns
NOTE: for DSK6713 TECLKOUT= 50 MHz => TECLKOUT = 20 ns.
‹ AD9220 data sheet
Ingeniería Electrónica
Sistemas Electrónicos Digitales Avanzados
38
EMIF CASE STUDY: AD9220 ADC
Case Study:
AD9220 ADC
‹ C6713EMIF
Asynchronous
Read Timing:
Setup = 2
Strobe = 3
Not Ready
Hold = 2
ECLKOUT
1
2
CEx
1
2
BE[3:0]
BE
1
2
EA[21:2]
Address
3
4
ED[31:0]
1
2
Read Data
AOE/SDRAS/SSOE
5
5
ARE/SDCAS/SSADS
AWE/SDWE/SSWE
7
7
6
6
ARDY
Ingeniería Electrónica
39
Sistemas Electrónicos Digitales Avanzados
SETTING ASYNC TIMING
31
28 27
22 21
20 19
Write Setup
Write Strobe
Write
Hold
RW, +1111
RW, +111111
RW, +11
15
TA
14 13
8
Read Strobe
RW, + 111111
7
.equ
mvkl.s1
mvkh.s1
ldw
nop 4
and
set
stw .d1
Ingeniería Electrónica
Read Setup
RW, +1111
3
Hold
MTYPE Write
MSB
RW, +0010
Set CE3 and to 32-bit ASYNC
CE3
4
16
1800014h
CE3, A0
CE3, A0
*A0, A1
A1, 0xff0f, A1
A1, 5, 5, A1
A1, *A0
RW, +0
2
0
Read
Hold
RW, +011
000b = 8-bit-wide ROM
001b = 16-bit-wide ROM
010b = 32-bit-wide Async
011b = 32-bit-wide SDRAM
100b = 32-bit-wide SBSRAM
Note: There are more
MTYPE options. See:
\Links\spru190d.pdf
\Links\spru190d.pdf
Sistemas Electrónicos Digitales Avanzados
40
EMIF CASE STUDY: AD9220 ADC
‹ Hardware Interface:
A/D
Analogue
Buffering
16
Latch
CLK /OE
CLK
16
XD[0..15]
XTOUT0
/XAOE
/XCE3
Analogue
In
(Chan1)
CLK /OE
CLK
A/D
16
Latch
16 XD[16..31]
DaughtercardConnector
Analogue
In
(Chan2)
‹ AD9220 data sheet
Ingeniería Electrónica
41
Sistemas Electrónicos Digitales Avanzados
EMIF CASE STUDY: Sharing the bus
A/D
16
/XAWE
1
0
x
/OE
0
1
1
XTOUT0
/XCE3
DAC_CLK
1
0
1
/XAOE activates the latched A/D
output only during the read sequence
CLK /OE
16
Latch
D/A
Sistemas Electrónicos Digitales Avanzados
16
XD[16..31]
16
XD[0..15]
CLK
/XAWE
/XCE3
CLK
D/A
Ingeniería Electrónica
XD[0..15]
/XAOE
A/D
/XAOE
0
1
x
16
CLK /OE
CLK
CLK
/CE3
0
0
1
Latch
DaughtercardConnector
‹ Both ADCs and DACs are
mapped to the same address
space (CE3 = 0xB000 0000).
16
XD[16..31]
42
EMIF CASE STUDY: Daughter board
interface
Ingeniería Electrónica
Sistemas Electrónicos Digitales Avanzados
43
EMIF CASE STUDY: Hardware
‹ The INTDSK1115 daughter card from ATE
Communications contains:
z
z
z
CODEC.
2 x ADC (AD9920).
2 x DAC (AD768).
‹ See schematics for further details:
z
z
z
z
\Links\Schematics Page 1.pdf
\Links\Schematics Page 2.pdf
\Links\Schematics Page 3.pdf
\Links\Schematics Page 4.pdf
Ingeniería Electrónica
Sistemas Electrónicos Digitales Avanzados
44
EMIF CASE STUDY: Hardware
‹ It requires +12V, -12V and 5V power supplies:
Daughter card
Connector
Pin
1
2
3
4
Signal
+12V
-12V
DGND
+5V
+12V -12V GND +5V
DSK
Warning: Do NOT supply power to J4 and J8 at the same time.
Ingeniería Electrónica
Sistemas Electrónicos Digitales Avanzados
45
EMIF CASE STUDY: Hardware
‹ Procedure:
(1) Set the EMIF registers.
(2) Set the internal timer to generate the
sampling frequency.
(3) Ensure that the DSK6211_6711.gel is loaded.
(4) Write the functions for reading and writing
from/to the ADC and DAC respectively.
(5) Set the interrupts.
Ingeniería Electrónica
Sistemas Electrónicos Digitales Avanzados
46
EMIF CASE STUDY: Software EMIF
EMIF
Case Study:
(1) Setting
the Global
ControlSoftware
Register: - EMIF
16
31
Rsv
15
14
13
12
11
Rsv
Rsv
Rsv
Rsv
BUSREQ
0
0
1
10
9
8
ARDY HOLD HOLDA
7
6
5
4
3
2
1
0
NO
HOLD
Rsv
Rsv
CLK1EN
CLK2EN
Rsv
Rsv
Rsv
0
0
0
0
0
Slight changes for ‘6713
3
1
0
0
1
3
1
0
0
0
0
0
‹ The GBLCTL register is common to all spaces and can be
configured as follows:
#define EMIF_GCTL 0x01800000
*(unsigned int *) EMIF_GCTL = 0x3300
Ingeniería Electrónica
Sistemas Electrónicos Digitales Avanzados
47
EMIF CASE STUDY: Software EMIF
Setting the CE Control Register:
z Which space can be used to access the ADCs?
z From the DSK6211_6711.gel
(DSK6211_6711_gel.pdf) file we can see that the
CE2 and CE3 are not used and are available on
the Daughter card interface.
z In this application the CE3 space has been used.
Ingeniería Electrónica
Sistemas Electrónicos Digitales Avanzados
48
EMIF CASE STUDY: Software EMIF
Setting the CE3 Control Register:
z MTYPE?
Memory
A/D 2
A/D 1
address
B0000000
D/A 1
D/A 2
32-bits
The memory is configured as 32-bit asynchronous.
Therefore: MTYPE = 0010b.
Ingeniería Electrónica
Sistemas Electrónicos Digitales Avanzados
49
EMIF CASE STUDY: Software EMIF
Setting the CE3 Control Register:
z
z
z
z
MTYPE = 0010b: 32-bit async
Read/Write Hold = 011b: 3 x ECLKOUT
Read/Write Strobe = 111111b: 31 x ECLKOUT
Read/Write Setup = 1111b: 15 x ECLKOUT
‹ Therefore the CE3 space can be configured as
follows:
Too conservative timing desing
#define EMIF_CE3
0x01800014
*(unsigned int *) EMIF_CE3 = 0xffffff23
Ingeniería Electrónica
Sistemas Electrónicos Digitales Avanzados
50
EMIF CASE STUDY: Software Timer
Setting the sample rate: Using the internal timer
(2) Select a timer: there are two timers available, Timer 0 and
Timer 1.
‹ The two internal timers are controlled by six memorymapped registers (3 registers each):
(a) Timer control registers: sets the operating modes.
(b) Timer period registers: holds the number of timer clock cycles to
count.
(c) Timer counters: holds current value of the incrementing
counter.
Note: the timer clock is the CPU clock divided by 4.
Ingeniería Electrónica
Sistemas Electrónicos Digitales Avanzados
51
EMIF CASE STUDY: Software Timer
Timer control
Timer period
Address
Timer 0
Timer 1
0x0194 0000 0x0198 0000
0x0194 0004 0x0198 0004
Timer counter
0x0194 0008
Register
Ingeniería Electrónica
Description
Sets the operating mode
Holds the number of timer
clock cycles to count
0x0198 0008 Holds the current counter
value
Sistemas Electrónicos Digitales Avanzados
52
EMIF CASE STUDY: Software Timer
Initialise the timer:
CPU Frequency = FCPU
= 150000000 Hz
Sampling rate = SRATE =
TPRD =
4000 Hz
FCPU
150000000
=
= 468.75
4 x 2 x 4000
32000
= 0x01D5
Ingeniería Electrónica
Sistemas Electrónicos Digitales Avanzados
53
EMIF CASE STUDY: Software Timer
#define FCPU
#define SRATE
#define TPRD
150000000
/* CPU clock frequency */
800000
/* data sample rate 800kHz */
(FCPU/(4*2*SRATE)) /* timer period, using the clock mode */
TIMER_Handle hTimer;
/* Handle for the timer device
*/
void start_timer1()
{
*(unsigned volatile int *)TIMER1_CTRL = 0x000; /* Disable output of Timer 1 */
IRQ_map(IRQ_EVT_TINT1,8);
hTimer = TIMER_open(TIMER_DEV1, TIMER_OPEN_RESET);
/* Configure up the timer. */
TIMER_configArgs(hTimer,
TIMER_CTL_OF(0x000003c1),
TIMER_PRD_OF(TPRD),
TIMER_CNT_OF(0) );
/* Start Timer 1 in clock mode */
*(unsigned volatile int *)TIMER1_CTRL = 0x3C1;//clock mode
/* Finally, enable the timer which will drive everything. */
TIMER_start(hTimer);
}
Ingeniería Electrónica
Sistemas Electrónicos Digitales Avanzados
54
EMIF CASE STUDY: Loading GEL
(3) For the DSK6211 and DSK6711 select the
DSK6211_6711.gel using:
Method 1: File:Load GEL
Location: ti\cc\gel\
Method 2: You can automatically execute a specific
GEL function at startup as follows:
(1) Select Setup CCS.
(2) Select the C6x11 DSK and right click.
(3) Select the “Startup GEL file(s)”.
(4) Type the file location as shown:
Ingeniería Electrónica
Sistemas Electrónicos Digitales Avanzados
55
EMIF CASE STUDY: Loading GEL
Ingeniería Electrónica
Sistemas Electrónicos Digitales Avanzados
56
EMIF CASE STUDY: Reading and
writing to the A/D y D/A
(4) The ADC and DAC are memory-mapped and therefore
can be accessed just like accessing a memory.
#define INTDSK_CE3 0xB0000000
unsigned int analogue_in = 0;
unsigned int analogue_out = 0;
interrupt void timerINT1 (void)
{
analogue_in = *(unsigned volatile int *) INTDSK_CE3;
/* data processing */
ad1 = analogue_in & 0xffff0000;
/* mask ad2 */
ad2 = analogue_in & 0x0000ffff;
/* mask ad1 */
ad1 = ad1 << 4;
ad2 = ad2 << 4;
*(unsigned volatile int *) INTDSK_CE3 = analogue_out;
}
Ingeniería Electrónica
Sistemas Electrónicos Digitales Avanzados
57
EMIF CASE STUDY: Setting the
Interrupt
(5) Timer1 is used to generate the interrupts:
The interrupt causes the execution of an ISR to take
place (e.g. “InoutISR”).
Procedure for setting interrupt:
(1) Map the CPU interrupt
and the source:
#include <intr.h>
#include <regs.h>
IRQ_map (IRQ_EVT_TINIT, 8);
(2) Enable the appropriate
bit of the IER:
IRQ_enable (IRQ_EVT_TINT1);
(3)
Enable the NMI:
IRQ_nmiEnable ();
(4)
Enable global interrupts:
IRQ_globalEnable ();
Ingeniería Electrónica
Sistemas Electrónicos Digitales Avanzados
58
TMS320C6000 FAMILY: EMIF
‹ Introduction.
z Characteristics, signals, memory map, alignment.
z Configuration registers.
z Types of interface.
‹ Asynchronous interface.
z Introduction, waveforms.
z Case Study I: Peripheral connection.
z Case Study II: Memory connection.
‹ Interface with synchronous static memories.
z Synchronous static memories.
z Interface description.
z Example.
‹ Interface with synchronous dynamic memories.
z SDRAM memories.
z Interface description.
z Example.
Ingeniería Electrónica
Sistemas Electrónicos Digitales Avanzados
59
CASE STUDY II:
ASYNC SRAM CONNECTION
CY7C1011BV33
128Kx16 15ns
Ingeniería Electrónica
Sistemas Electrónicos Digitales Avanzados
60
ASYNC SRAM OVERVIEW
Which waveforms take into account?
‹ Access cycle controlled by XXX signal.
z Read: XXX is the last one to get active (signaling the new data
appearing) and the first one to get disable (signaling its disappearing).
z Write: XXX is the last one to get active (the rest of the signals should
be stables at this moment) and the first one to get inactive (signaling
the data capture).
READ CYCLE: address controlled.
tRC
ADDRESS
tAA
tOHA
DATA OUT
PREVIOUS DATA VALID
Ingeniería Electrónica
DATA VALID
61
Sistemas Electrónicos Digitales Avanzados
CASE STUDY: ASYNC SRAM
CONNECTION
READ CYCLE: /OE or /BE controlled.
ADDRESS
tRC
CE
tACE
OE
tHZOE
tDOE
tLZOE
BHE, BLE
tHZCE
tDBE
tLZBE
DATA OUT
tHZBE
HIGH IMPEDANCE
DATA VALID
tLZCE
VCC
SUPPLY
CURRENT
Ingeniería Electrónica
HIGH
IMPEDANCE
tPD
tPU
50%
Sistemas Electrónicos Digitales Avanzados
50%
IICC
CC
IISB
SB
62
CASE STUDY: ASYNC SRAM
CONNECTION
WRITE CYCLE: /CE controlled
tWC
ADDRESS
tSA
CE
tSCE
tAW
tHA
tPWE
WE
tBW
BHE, BLE
tSD
tHD
DATA I/O
Ingeniería Electrónica
Sistemas Electrónicos Digitales Avanzados
63
CASE STUDY: ASYNC SRAM
CONNECTION
WRITE CYCLE: /BE controlled
tWC
ADDRESS
BHE, B LE
tSA
tBW
tAW
tHA
tPWE
WE
tSCE
CE
tSD
tHD
DATA I/O
Ingeniería Electrónica
Sistemas Electrónicos Digitales Avanzados
64
CASE STUDY: ASYNC SRAM
CONNECTION
WRITE CYCLE:
/WE controlled, /OE low
,
tWC
ADDRESS
tSCE
CE
tAW
tHA
tSA
tPWE
WE
tBW
BHE, BLE
tHZWE
tSD
tHD
DATA I/O
tLZWE
Ingeniería Electrónica
65
Sistemas Electrónicos Digitales Avanzados
CASE STUDY: ASYNC SRAM
CONNECTION
Asynchronous read timing example (1/2/1)
Setup
Strobe
1
2
Hold
Setup
Strobe
1
1
'C6x Samples Data
Hold
2
1
C6x Samples Data
ECLKOUT
/CEx
/BE[3:0]
BE1
EA [21:2]
A1
BE2
trc(m)
td
td
A2
toh(m)
tacc(m)
ED [31:0]
D1
tisu
th
D2
/AOE
td
td
/ARE
/AWE
ARDY
Ingeniería Electrónica
Sistemas Electrónicos Digitales Avanzados
66
CASE STUDY: ASYNC SRAM
CONNECTION
Asynchronous write timing example (1/1/1)
Setup
Strobe
Hold
Setup
Strobe
Hold
1
1
1
1
1
1
ECLKOUT
/CEx
/BE[3:0]
BE1
BE2
twc(m)
twr(m)
EA [21:2]
A1
ED [31:0]
D1
A2
td
td
tih(m)
D2
/AOE
/ARE
td
txw(m)
twp(m)
td
/AWE
ARDY
Ingeniería Electrónica
Sistemas Electrónicos Digitales Avanzados
67
CASE STUDY: FLASH CONNECTION
EMIF-Big-Endian x8 ASRAM Interface
Ingeniería Electrónica
Sistemas Electrónicos Digitales Avanzados
68
TMS320C6000 FAMILY: EMIF
‹ Introduction.
z Characteristics, signals, memory map, alignment.
z Configuration registers.
z Types of interface.
‹ Asynchronous interface.
z Introduction, waveforms.
z Case Study I: Peripheral connection.
z Case Study II: Memory connection.
‹Interface with synchronous static memories.
z Synchronous static memories.
z Interface description.
z Example.
‹ Interface with synchronous dynamic memories.
z SDRAM memories.
z Interface description.
z Example.
Ingeniería Electrónica
Sistemas Electrónicos Digitales Avanzados
69
EMIF: Other interfaces
Field
Description
Read setup
Write setup
Setup width. Number of clock† cycles of setup time for address (EA), chip enable (CE), and
byte enables (BE[0-3]) before read strobe or write strobe falls. For asynchronous read accesses, this is also the setup time of AOE before ARE falls.
Read strobe
Write strobe
Strobe width. The width of read strobe (ARE) and write strobe (AWE) in clock† cycles
Read hold
Write hold
Hold width. Number of clock† cycles that address (EA) and byte strobes (BE[0-3]) are held
after read strobe or write strobe rises. For asynchronous read accesses, this is also the hold
time of AOE after ARE rising.
MTYPE
Memory type of the corresponding CE spaces for C620x/C670x
MTYPE Definitions for C621x/C671x/C64x‡
MTYPE = 0000b: 8-bit-wide asynchronous interface
MTYPE = 0001b: 16-bit-wide asynchronous interface
MTYPE = 0010b: 32-bit-wide asynchronous interface
MTYPE = 0011b: 32-bit-wide SDRAM
MTYPE = 0100b: 32-bit-wide SBSRAM (C621x/C671x)
32-bit-wide programmable synchronous memory (C64x)
MTYPE = 1000b: 8-bit-wide SDRAM
MTYPE = 1001b: 16-bit-wide SDRAM
MTYPE = 1010b: 8-bit-wide SBSRAM (C621x/C671x)
8-bit-wide programmable synchronous memory (C64x)
MTYPE = 1011b: 16-bit-wide SBSRAM (C621x/C671x)
16-bit-wide programmable synchronous memory (C64x)
MTYPE = 1100b: 64-bit-wide asynchronous interface (C64x only)
MTYPE = 1101b: 64-bit-wide SDRAM (C64x only)
MTYPE = 1110b: 64-bit-wide programmable synchronous memory (C64x only)
TA
Turn-around time (C621x/C671x/C64x only). Turn-around time controls the number of
ECLKOUT cycles between a read, and a write, or between reads, to different CE spaces
(asynchronous memory types only).
† Clock cycles are in terms of CLKOUT1 for C620x/C670x, ECLKOUT for the C621x/C671x, and ECLKOUT1 for the C64x.
‡ 32-bit and 64–bit interfaces (MTYPE=0010b, 0011b, 0100b, 1100b, 1101b, 1110b) do not apply to C6712 and C64x EMIFB.
Ingeniería Electrónica
Sistemas Electrónicos Digitales Avanzados
70
SYNCHRONOUS SRAMs
EMIF Case Study
Double
Data Rate
< 200 MHz
<400 MHz Data
Late Write
< 300 MHz
< 166 MHz
Pipelined
SBRAM
Flow thru
SBRAM
ASRAM
ASRAM
ZBT
< 166 MHz
< 133 MHz
< 100 MHz
Not compatible
C6000 Compatible
< 10 MHz
Next Generation
Not Planned
Ingeniería Electrónica
71
Sistemas Electrónicos Digitales Avanzados
SYNCHRONOUS SRAMs
Asynchronous SRAMs present long critical path...
Control
Control
Address
Data
Memory
Array
…and then a high access time
Control
Fast
ASRAM
Address
Data
Control1
Slow
Address1
ASRAM
Data1
Ingeniería Electrónica
Read
A1
A2
tacc = 10 ns
D1
tacc = 10 ns
D2
Read
A1
tacc = 100 ns
D1
Sistemas Electrónicos Digitales Avanzados
72
SYNCHRONOUS SRAMs
Solution: cut the output critical path...
Control
Control
Address
Data
Memory
Array
…and adjust the input path
FLOW-THROUGH SYNCRONOUS SRAM
Ingeniería Electrónica
73
Sistemas Electrónicos Digitales Avanzados
SYNCHRONOUS SRAMs
EMIF Case Study
FLOW-THROUGH SYNCRONOUS SRAM
Address
A
B
Control/Reg
Control
C
Memory
Array
‹
Read:
‹
Incompatible with
EMIF
z
Data
D
1 cycle latency
Reg
Clock
1
2
3
4
5
Clock
Control (A)
Read
Address (A)
A1
Read
A2
Control (B)
Read
Address (B)
A1
Data (C)
Data (D)
Ingeniería Electrónica
Read
A2
D1
D2
D1
D2
Sistemas Electrónicos Digitales Avanzados
74
SYNCHRONOUS SRAMs
A further improvement
Control
Control
Address
Data
Memory
Array
PIPELINED SYNCRONOUS SRAM
Ingeniería Electrónica
75
Sistemas Electrónicos Digitales Avanzados
SYNCHRONOUS SRAMs
PIPELINED SYNCRONOUS SRAM
‹
A
B
Memory
Array
C
Reg
Address
Control/Reg
Control
D
Read:
z
Data
2 cycles latency
E
Reg
Clock
1
2
3
4
5
Clock
Control (A)
Address (A)
Control (B)
Read
A
Data (D)
Data (E)
Ingeniería Electrónica
A2
Read
B
Address (B)
Data (C)
Read
A1
Read
A1
C
A2
D1
D2
D
D1
E
D2
D1
D2
Sistemas Electrónicos Digitales Avanzados
76
PIPELINED SYNCHRONOUS SRAMs
EMIF Case Study
MT58128L32P1
128Kx32 225 MHz
‹ Address bus
Burst control
‹ Output enable
z DQ[31:0]
DQ[31:0]
z /OE
‹ Burst control
ADV
MODE
‹ CLK.
z #ADSP, #ADSC
z #ADV, MODE
BW[3:0]
BWE
GW
Chip
Write
enable control
z /CE, CE2, /CE2
‹ Data bus
SA0,SA1,SA
ADSP
ADSC
‹ Chip enable
z SA0, SA1, SA
‹ Write control
z #BW[3:0], #BWE
z #GW
CE
CE2
CE2
OE
CLK
‹ FEATURES:
z Burst access.
z One cycle Deselect for READ access.
Ingeniería Electrónica
77
Sistemas Electrónicos Digitales Avanzados
PIPELINED SYNCHRONOUS SRAMs
EMIF Case SRAM:
Study BURST MODE
PIPELINED SYNCRONOUS
Upper
Address
bits
Address
Address
Latch
Clk
2
A0
A1
Lower
2 Address
bits
CLK
=
Second
Address
First
Address
Third
Address
Fourth
Address
2
ADV
2-bit Counter
ADV=0
CLK
Mode
=
ADV=0
CLK
=
ADV=0
CLK
=
‹ It allows the automatic generation of the next address.
‹ Linear or interleaved increment.
‹ It automatically rolls over to 00 from 11.
z
if address 0111b were issued in burst mode, the subsequent
access would be to 0100b. => Error!
Ingeniería Electrónica
Sistemas Electrónicos Digitales Avanzados
78
PIPELINED SYNC SRAMs: READ CYCLE
EMIF Case Study
t KC
CLK
t KL
t KH
t ADSS tADSH
ADSP#
t ADSS
tADSH
ADSC#
t AS
tAH
A2
A1
ADDRESS
t WS
A3
Burst continued with
new base address.
tWH
GW#, BWE#,
BWa#-BWd#
t CES
Deselect (NOTE 4)
cycle.
tCEH
CE#
(NOTE 2)
t AAS
tAAH
ADV#
ADV# suspends burst.
OE#
(NOTE 3)
t KQLZ
Q
High-Z
t OEHZ
t OEQ
t KQ
t OELZ
t KQX
Q(A2)
Q(A1)
t KQ
t KQHZ
Q(A2 + 1)
Q(A2 + 2)
Q(A2 + 3)
Q(A2)
BURSTREAD
DON’T CARE
Ingeniería Electrónica
Q(A3)
Burst wraps around
to its initial state.
(NOTE 1)
Single READ
Q(A2 + 1)
UNDEFINED
79
Sistemas Electrónicos Digitales Avanzados
PIPELINED SYNC SRAMs: WRITE CYCLE
EMIF Case Study
t KC
CLK
t KH
t KL
t ADSS tADSH
ADSP#
ADSC# extends burst.
t ADSS t ADSH
t ADSS tADSH
ADSC#
t AS
tAH
A1
ADDRESS
A3
A2
Byte write signals are ignored for first cycle when
ADSP# initiates burst.
t WS
tWH
t AAS
tAAH
BWE#,
BWa#-BWd#
(NOTE 5)
t WS
tWH
GW#
t CES
t CEH
CE#
(NOTE 2)
ADV#
ADV# suspends burst.
(NOTE 4)
OE#
(NOTE 3)
t DS
D
High-Z
tDH
D(A1)
tOEHZ
D(A2)
D(A2 + 1)
D(A2 + 1)
D(A2 + 2)
D(A2 + 3)
D(A3)
D(A3 + 1)
D(A3 + 2)
(NOTE 1)
Q
BURST READ
Single WRITE
BURST WRITE
Extended BURST WRITE
DON’T CARE
Ingeniería Electrónica
Sistemas Electrónicos Digitales Avanzados
UNDEFINED
80
EMIF: SYNC. BURST SRAM INTERFACE
‹ Read deselect.
‹ Burst access, linear increment.
z
Roll over correction: If address 0111b were issued in burst mode,
the subsequent access would be to 0100b. => Error!
Case 1
Case 2
Case 3
A[1:0]
A[1:0]
A[1:0]
A[1:0]
EMIF Address
EA[3:2]
EA[3:2]
EA[3:2]
EA[3:2]
First address
00
01
10
11
01
10
11
00
10
11
00
01
11
00
01
10
SBSRAM Address
Fourth Address
Ingeniería Electrónica
Case 4
81
Sistemas Electrónicos Digitales Avanzados
SYNCHRONOUS BURST SRAM INTERFACE
Case
ReadEMIF
Example:
sixStudy
word read
Read/D1 D2
latched latched
Read
D3
latched
D4
latched
D6
D5
latched latched/deselect
ECLKOUT
CE
BE[3:0]
EA[21:2]
BE1
BE2
BE3
BE4
EA[4:2]=010b
ED[31:0]†
BE5
BE6
EA[4:2]=100b
D1
D2
D3
D4
D5
101
110
111
100
D6
SSADS
SSOE
SSWE
010
Ingeniería Electrónica
011 100
Sistemas Electrónicos Digitales Avanzados
10
82
SYNCHRONOUS BURST SRAM INTERFACE
Case
WriteEMIF
Example:
sixStudy
word write
Write
Write
Deselect
ECLKOUT
CEx
BE1
BE[3:0]
BE2
BE3
BE4
BE5
EA[4:2]=000b
EA[21:2]
ED[31:0]†
D1
D2
BE6
EA[4:2]=100b
D3
D4
D5
D6
SSADS
SSOE
SSWE
Ingeniería Electrónica
83
Sistemas Electrónicos Digitales Avanzados
REAL WAVEFORMS
EMIF
Study
READCase
ACCESS
ECLKOUT
1
1
CEx
BE[3:0]
2
BE1
3
BE2
BE3
4
BE4
5
EA[21:2]
EA
6
ED[31:0]
7
Q1
8
Q2
Q3
Q4
8
SSADS
9
9
SSOE
SSWE
Ingeniería Electrónica
Sistemas Electrónicos Digitales Avanzados
84
REAL WAVEFORMS
EMIF
Case
Study
WRITE
ACCESS
ECLKOUT
1
1
CEx
BE[3:0]
2
BE1
3
BE2
BE3
5
4
EA
EA[21:2]
ED[31:0]
BE4
11
10
Q1
8
Q2
Q3
Q4
8
SSADS
SSOE
12
12
SSWE
Ingeniería Electrónica
Sistemas Electrónicos Digitales Avanzados
85
CONNECTION
EMIF Case Study
MT58L128L36
128Kx32 225 MHz
Ingeniería Electrónica
Sistemas Electrónicos Digitales Avanzados
86
TIMING
EMIF clock
Caseinterface:
Study
External
E
E
ECLKOUT
tdmax
tdmin
'C6211 /'C6711
Output from DSP: Data Bus, Control and Address:
Tcyc
SBSRAM Latches Data
Tcyc
EMIF Clock
tdmax
tih(m)
tisu(m)
tdmin
'C6000 Outputs
Input to DSP: Data Bus:
Tcyc
'C6x Latches Data
Tcyc
EMIF Clock
tsu
tacc(m)
tih
toh(m)
Read Data
Ingeniería Electrónica
Sistemas Electrónicos Digitales Avanzados
87
TMS320C6000 FAMILY: EMIF
‹ Introduction.
z Characteristics, signals, memory map, alignment.
z Configuration registers.
z Types of interface.
‹ Asynchronous interface.
z Introduction, waveforms.
z Case Study I: Peripheral connection.
z Case Study II: Memory connection.
‹ Interface with synchronous static memories.
z Synchronous static memories.
z Interface description.
z Example.
‹Interface with synchronous dynamic memories.
z SDRAM memories.
z Interface description.
z Example.
Ingeniería Electrónica
Sistemas Electrónicos Digitales Avanzados
88
EMIF: SDRAM INTERFACE
TO BE ADDED…
Ingeniería Electrónica
Sistemas Electrónicos Digitales Avanzados
89
FINAL
Ingeniería Electrónica
Sistemas Electrónicos Digitales Avanzados
90