PRELIMINARY Integrated Circuit Systems, Inc. ICS843001I-23 FEMTOCLOCKS™ CRYSTAL-TO-3.3V LVPECL/LVCMOS FREQUENCY SYNTHESIZER GENERAL DESCRIPTION FEATURES The ICS843001I-23 is a highly versatile, low ICS phase noise LVPECL/LVCMOS Synthesizer HiPerClockS™ which can generate low jitter reference clocks for a variety of communication applications and is a member of the HiPerClocksTM family of high performance clock solutions from ICS. The dual crystal interface allows the synthesizer to support up to three communication standards in a given application (i.e. SONET with a 19.44MHz crystal, 1Gb/10Gb Ethernet and Fibre Channel using a 25MHz crystal). The rms phase jitter performance is typically less than 1ps, thus making the device acceptable for use in demanding applications such as OC48 SONET, GbE/10Gb Ethernet and SAN applications. The ICS843001I-23 is packaged in a small 24-pin TSSOP package. • One 3.3V LVPECL output pair and one LVCMOS/LVTTL REF_OUT output • Selectable crystal oscillator interfaces or LVCMOS/LVTTL single-ended input • Crystal and CLK range: 17.5MHz - 29.54MHz • Able to generate GbE/10GbE/12GbE, Fibre Channel (1Gb/4Gb/10Gb), PCI-E and SATA from a 25MHz crystal • VCO range: 1.12GHz - 1.3GHz • Supports the following applications: SONET, Ethernet, Fibre Channel, Serial ATA, and HDTV • RMS phase jitter @ 622.08MHz (12kHz - 20MHz): <1ps (typical) design target • Supply modes: VCC/VCCO 3.3V/3.3V 3.3V/2.5V 2.5V/2.5V • -40°C to 85°C ambient operating temperature • Available in both standard and lead-free RoHS-compliant packages PIN ASSIGNMENT BLOCK DIAGRAM 3 N2:N0 SEL0 Pulldown SEL1 Pulldown N XTAL_IN0 OSC 00 11 XTAL_OUT0 XTAL_IN1 OSC 01 Pulldown 10 11 Phase Detector VCO XTAL_OUT1 CLK 000 001 010 011 100 111 10 01 00 000 001 010 011 100 ÷2 ÷4 ÷5 ÷6 ÷8 (default) 101 110 111 ÷10 ÷12 ÷16 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 REF_OUT VEE OE_REF M2 M1 M0 MR SEL1 SEL0 CLK XTAL_IN0 XTAL_OUT0 ICS843001I-23 M ÷44 ÷45 ÷48 ÷50 ÷51 ÷64 (default) 24-Lead TSSOP 4.40mm x 7.8mm x 0.92mm package body G Package Top View MR Pulldown M2:M0 Pullup VCCO_LVCMOS N0 N1 N2 VCCO_LVPECL Q nQ Q VEE VCCA nQ VCC XTAL_OUT1 XTAL_IN1 3 REF_OUT OE_REF Pulldown The Preliminary Information presented herein represents a product in prototyping or pre-production. The noted characteristics are based on initial product characterization. Integrated Circuit Systems, Incorporated (ICS) reserves the right to change any circuitry or specifications without notice. 843001AGI-23 www.icst.com/products/hiperclocks.html 1 REV. B JANUARY 6, 2006 PRELIMINARY Integrated Circuit Systems, Inc. ICS843001I-23 FEMTOCLOCKS™ CRYSTAL-TO-3.3V LVPECL/LVCMOS FREQUENCY SYNTHESIZER TABLE 1. PIN DESCRIPTIONS Number Name 1 VCCO_CMOS Power Type Description 2, 3 N0, N1 Input 4 N2 Input 5 VCCO_LVPECL Power Output supply pin for LVPECL output. Output supply pin for LVCMOS/LVTTL REF_OUT output. Pulldown Output divider select pins. See Table 3C. LVCMOS/LVTTL interface levels. Pullup 6, 7 Q, nQ Ouput Differential output pair. LVPECL interface levels. 8, 23 VEE Power Negative supply pin. 9 VCCA Power Analog supply pin. 10 11 12 13 14 15 VCC XTAL_OUT1, XTAL_IN1 XTAL_OUT0, XTAL_IN0 CLK Power 16, 17 SEL0, SEL1 Input 18 MR Input 19, 20 , 21 M0, M1, M2 Input 22 OE_REF Input 24 REF_OUT Output Input Input Input Core supply pin. Parallel resonant cr ystal interface. XTAL_OUT1 is the output, XTAL_IN1 is the input. Parallel resonant cr ystal interface. XTAL_OUT0 is the output, XTAL_IN0 is the input. Pulldown LVCMOS/LVTTL clock input. Pulldown Input MUX select pins. LVCMOS/LVTTL interface levels. Active HIGH Master Reset. When logic HIGH, the internal dividers are reset causing the true output Q to go low and the inver ted output nQ to Pulldown go high. When logic LOW, the internal dividers and the outputs are enabled. LVCMOS/LVTTL interface levels. Feedback divider select pins. See Table 3B. Pullup LVCMOS/LVTTL interface levels. Reference clock output enable. Default Low. See Table 3E. Pulldown LVCMOS/LVTTL interface levels. Reference clock output. LVCMOS/LVTTL interface levels. NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values. TABLE 2. PIN CHARACTERISTICS Symbol Parameter CIN Input Capacitance Test Conditions Minimum Typical Maximum 4 Units pF RPULLDOWN Input Pulldown Resistor 51 kΩ RPULLUP Input Pullup Resistor 51 kΩ Rout Output Impedance 843001AGI-23 REF_OUT www.icst.com/products/hiperclocks.html 2 5 7 12 Ω REV. B JANUARY 6, 2006 PRELIMINARY Integrated Circuit Systems, Inc. ICS843001I-23 FEMTOCLOCKS™ CRYSTAL-TO-3.3V LVPECL/LVCMOS FREQUENCY SYNTHESIZER TABLE 3A. COMMON CONFIGURATIONS TABLE Input XTAL Input (MHz) Feedback Divider VCO (MHz) N Divider Value Output Frequency (MHz) Application 27 44 1188 16 74.25 HDTV 24.75 48 1188 16 74.25 HDTV 19.44 64 1244.16 8 155.52 SONET 19.44 64 1244.16 2 622.08 SONET 19.44 64 1244.16 4 311.04 SONET 25 50 1250 10 125 GigE 25 50 1250 8 156.25 10 GigE 25 50 1250 5 25 0 GigE 25 50 1250 4 312.5 XGMII 25 50 1250 2 625 10 GigE 25 45 1125 6 187.5 12 GigE 25 48 1200 12 100 PCI Express 25 48 1200 8 150 SATA 25 48 1200 16 75 SATA 25 51 1275 12 106.25 Fibre Channel 25 51 1275 8 159.375 10 Gig Fibre Channel 25 51 1275 6 212.5 4 Gig Fibre Channel TABLE 3C. PROGRAMMABLE N OUTPUT DIVIDER FUNCTION TABLE TABLE 3B. PROGRAMMABLE M OUTPUT DIVIDER FUNCTION TABLE Inputs M2 M1 M0 M Divider Value Inputs Input Frequency Minimum Maximum N2 N1 N0 N Divide Value 0 0 0 44 25.5 29.54 0 0 0 2 0 0 1 45 24.9 28.88 0 0 1 4 0 1 0 48 23.3 27.08 0 1 0 5 0 1 1 50 22.4 26.0 0 1 1 6 1 0 0 51 22.0 25.49 1 0 0 8 (default) 1 1 1 (default) 17.5 20.31 1 0 1 10 1 1 0 12 1 1 1 16 64 TABLE 3D. BYPASS MODE FUNCTION TABLE Inputs SEL1 SEL0 Reference Input TABLE 3E. OE_REF OUTPUT FUNCTION TABLE PLL Mode Inputs Output OE_REF REF_OUT 0 0 XTAL0 Active 0 Hi-Z 0 1 XTAL1 Active 1 Active 1 0 CLK Active 1 1 CLK Bypass 843001AGI-23 www.icst.com/products/hiperclocks.html 3 REV. B JANUARY 6, 2006 PRELIMINARY Integrated Circuit Systems, Inc. ICS843001I-23 FEMTOCLOCKS™ CRYSTAL-TO-3.3V LVPECL/LVCMOS FREQUENCY SYNTHESIZER ABSOLUTE MAXIMUM RATINGS Supply Voltage, VCC 4.6V Inputs, VI -0.5V to VCC + 0.5V Outputs, IO (LVPECL) Continuous Current Surge Current 50mA 100mA Outputs, VO (LVCMOS) -0.5V to VCCO + 0.5V Package Thermal Impedance, θJA 70°C/W (0 mps) Storage Temperature, TSTG -65°C to 150°C NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VCC = VCCA = VCCO_LVPECL, VCCO_LVCMOS = 3.3V±5%, TA = -40°C TO 85°C Symbol Parameter Minimum Typical Maximum Units VCC Core Supply Voltage Test Conditions 3.135 3.3 3.465 V VCCA Analog Supply Voltage 3.135 3.3 3.465 V VCCO_LVPECL Output Supply Voltage 3.135 3.3 3.465 V VCCO_LVCMOS Output Supply Voltage 3.135 3.3 3.465 V IEE Power Supply Current ICCA Analog Supply Current ICCO_LVPECL Output Supply Current ICCO_LVCMOS Output Supply Current OE_REF = 0 TBD mA OE_REF = 1, REF_OUT = 29.54MHz TBD mA 5 mA OE_REF = 0 TBD mA OE_REF = 1, REF_OUT = 29.54MHz TBD mA TABLE 4B. POWER SUPPLY DC CHARACTERISTICS, VCC = VCCA = 3.3V±5%, VCCO_LVPECL, VCCO_LVCMOS = 2.5V±5%, TA = -40°C TO 85°C Symbol Parameter Minimum Typical Maximum Units VCC Core Supply Voltage 3.135 3.3 3.465 V VCCA Analog Supply Voltage 3.135 3.3 3.465 V VCCO_LVPECL Output Supply Voltage 2.625 2.5 2.625 V VCCO_LVCMOS Output Supply Voltage 2.5 2.625 IEE Power Supply Current Test Conditions 2.625 V OE_REF = 0 TBD mA OE_REF = 1, REF_OUT = 29.54MHz TBD mA ICCA Analog Supply Current TBD mA ICCO_LVPECL Output Supply Current OE_REF = 0 TBD mA ICCO_LVCMOS Output Supply Current OE_REF = 1, REF_OUT = 29.54MHz TBD mA 843001AGI-23 www.icst.com/products/hiperclocks.html 4 REV. B JANUARY 6, 2006 PRELIMINARY Integrated Circuit Systems, Inc. ICS843001I-23 FEMTOCLOCKS™ CRYSTAL-TO-3.3V LVPECL/LVCMOS FREQUENCY SYNTHESIZER TABLE 4C. POWER SUPPLY DC CHARACTERISTICS, VCC = VCCA = VCCO_LVPECL, VCCO_LVCMOS = 2.5V±5%, TA = -40°C TO 85°C Symbol Parameter Minimum Typical Maximum Units VCC Core Supply Voltage Test Conditions 2.625 2.5 2.625 V VCCA Analog Supply Voltage 2.625 2.5 2.625 V VCCO_LVPECL Output Supply Voltage 2.625 2.5 2.625 V VCCO_LVCMOS Output Supply Voltage 2.625 2.5 2.625 V IEE Power Supply Current OE_REF = 0 TBD mA OE_REF = 1, REF_OUT = 29.54MHz TBD mA ICCA Analog Supply Current 5 mA ICCO_LVPECL Output Supply Current OE_REF = 0 TBD mA ICCO_LVCMOS Output Supply Current OE_REF = 1, REF_OUT = 29.54MHz TBD mA TABLE 4D. LVCMOS / LVTTL DC CHARACTERISTICS, VCC = VCCA = VCCO_LVCMOS = 3.3V±5% OR 2.5V±5%, OR VCC = VCCA = 3.3V±5%, VCCO_LVCMOS = 2.5V±5%, TA = -40°C TO 85°C Symbol VIH VIL IIH IIL Parameter Test Conditions Maximum Units 2 VCC + 0.3 V VCC = 2.5V 1.7 VCC + 0.3 V VCC = 3.3V -0.3 0.8 V VCC = 2.5V VCC = VIN = 3.465V or 2.625V VCC = VIN = 3.465V or 2.625V VCC = 3.465V or 2.625V, VIN = 0V -0.3 0.7 V 150 µA 5 µA Input High Voltage Input Low Voltage Input High Current Input Low Current Minimum Typical VCC = 3.3V CLK, SEL0, SEL1, OE_REF, MR, N0, N1 N2, M0:M2 CLK, SEL0, SEL1, OE_REF, MR, N0, N1 N2, M0:M2 VOH Output High Voltage; NOTE 1 REF_OUT VOL Output Low Voltage; NOTE 1 REF_OUT -5 µA VCC = 3.465V or 2.625V, VIN = 0V -150 µA VCCO_LVCMOS = 3.465V 2.6 V VCCO_LVCMOS = 2.625V VCCO_LVCMOS = 3.465V 1.8 V or 2.625V Input Edge Rate CLK 20% - 80% ΔV/ΔT NOTE 1: Output terminated with 50Ω to VCCO _LVCMOS/2. See Parameter Measurement Information Section, "Output Load Test Circuit Diagram" diagrams. 0.5 V TB D V/ns TABLE 4E. LVPECL DC CHARACTERISTICS, VCC = VCCA = VCCO_LVPECL = 3.3V±5% OR 2.5V±5%, OR VCC = VCCA = 3.3V±5%, VCCO_LVPECL = 2.5V±5%, TA = -40°C TO 85°C Symbol Parameter Maximum Units VOH Output High Voltage; NOTE 1 Test Conditions VCCO_LVPECL - 1.4 Minimum Typical VCCO_LVPECL - 0.9 V VOL Output Low Voltage; NOTE 1 VCCO_LVPECL - 2.0 VCCO_LVPECL - 1.7 V VSWING Peak-to-Peak Output Voltage Swing 0.6 1.0 V NOTE 1: Outputs terminated with 50Ω to VCCO_LVPECL - 2V. 843001AGI-23 www.icst.com/products/hiperclocks.html 5 REV. B JANUARY 6, 2006 PRELIMINARY Integrated Circuit Systems, Inc. ICS843001I-23 FEMTOCLOCKS™ CRYSTAL-TO-3.3V LVPECL/LVCMOS FREQUENCY SYNTHESIZER TABLE 5. CRYSTAL CHARACTERISTICS Parameter Test Conditions Minimum Mode of Oscillation Typical Maximum Fundamental Frequency 17.5 Units MHz 29.54 MHz Equivalent Series Resistance (ESR) 50 Ω Shunt Capacitance 7 pF Drive Level 1 mW Maximum Units 650 MH z NOTE: Characterized using an 18pF parallel resonant crystal. TABLE 6A. AC CHARACTERISTICS, VCC = VCCA = VCCO_LVPECL, VCCO_LVCMOS = 3.3V±5%, TA = -40°C TO 85°C Symbol Parameter fOUT Output Frequency Propagation CLK to Delay, NOTE 1 REF_OUT RMS Phase Jitter, (Random); NOTE 2, 3 PLL VCO Lock Range tPD tjit(Ø) fVCO Test Conditions Minimum Typical 56 622.08MHz (12kHz - 20MHz) TBD ns TBD ps 1.12 1.3 GHz tL_SEL Select Time TBD ms tL_M PLL Lock Time TBD ms tR / tF Output Rise/Fall Time Q/nQ 20% to 80% 500 ps REF_OUT 20% to 80% 500 ps 50 50 % % Q/nQ odc Output Duty Cycle REF_OUT NOTE 1: Measured from the VCC/2 of the input to VCCO_LVCMOS/2 of the output. NOTE 2: Phase jitter measured using a 19.44MHz quar tz crystal. NOTE 3: This parameter is defined in accordance with JEDEC Standard 65. TABLE 6B. AC CHARACTERISTICS, VCC = VCCA = 3.3V±5%, VCCO_LVPECL, VCCO_LVCMOS = 2.5V±5%, TA = -40°C TO 85°C Symbol Parameter fOUT fVCO Output Frequency Propagation CLK to Delay, NOTE 1 REF_OUT RMS Phase Jitter, (Random); NOTE 2, 3 PLL VCO Lock Range tL_SEL Select Time tL_M PLL Lock Time tPD tjit(Ø) tR / tF Output Rise/Fall Time Test Conditions Minimum 56 622.08MHz (12kHz - 20MHz) Maximum Units 650 MH z TBD ns TBD ps 1.12 1.3 GHz TBD ms TBD ms Q/nQ 20% to 80% 500 ps REF_OUT 20% to 80% 500 ps 50 50 % % Q/nQ odc Output Duty Cycle REF_OUT NOTE 1: Measured from the VCC/2 of the input to VCCO_LVCMOS/2 of the output. NOTE 2: Phase jitter measured using a 19.44MHz quar tz crystal. NOTE 3: This parameter is defined in accordance with JEDEC Standard 65. 843001AGI-23 Typical www.icst.com/products/hiperclocks.html 6 REV. B JANUARY 6, 2006 PRELIMINARY Integrated Circuit Systems, Inc. ICS843001I-23 FEMTOCLOCKS™ CRYSTAL-TO-3.3V LVPECL/LVCMOS FREQUENCY SYNTHESIZER TABLE 6C. AC CHARACTERISTICS, VCC = VCCA = VCCO_LVPECL, VCCO_LVCMOS = 2.5V±5%, TA = -40°C TO 85°C Symbol Parameter fOUT fVCO Output Frequency Propagation CLK to Delay, NOTE 1 REF_OUT RMS Phase Jitter, (Random); NOTE 2, 3 PLL VCO Lock Range tL_SEL Select Time tL_M PLL Lock Time tPD tjit(Ø) tR / tF Output Rise/Fall Time Test Conditions Minimum 56 622.08MHz (12kHz - 20MHz) Maximum Units 650 MHz TBD ns TBD ps 1.12 1.3 GHz TBD ms TBD ms Q/nQ 20% to 80% 500 ps REF_OUT 20% to 80% 500 ps 50 50 % % Q/nQ odc Output Duty Cycle REF_OUT NOTE 1: Measured from the VCC/2 of the input to VCCO_LVCMOS/2 of the output. NOTE 2: Phase jitter measured using a 19.44MHz quar tz crystal. NOTE 3: This parameter is defined in accordance with JEDEC Standard 65. 843001AGI-23 Typical www.icst.com/products/hiperclocks.html 7 REV. B JANUARY 6, 2006 PRELIMINARY Integrated Circuit Systems, Inc. ICS843001I-23 FEMTOCLOCKS™ CRYSTAL-TO-3.3V LVPECL/LVCMOS FREQUENCY SYNTHESIZER PARAMETER MEASUREMENT INFORMATION 1.65±5% 2V V CC , VCCA, VCCO_LVPECL Qx SCOPE VCC , VCCA, VCCO_LVCMOS LVPECL LVCMOS SCOPE Qx nQx VEE VEE -1.3V±0.165V -1.65V±5% 3.3V LVPECL OUTPUT LOAD AC TEST CIRCUIT 3.3V LVCMOS OUTPUT LOAD AC TEST CIRCUIT 2.8V±0.04V 2V V CC , VCCA 2.05±5% 1.25±5% Qx SCOPE VCC , VCCA VCCO_LVCMOS VCCO_LVPECL LVPECL LVCMOS SCOPE Qx nQx VEE VEE VDDO 2 -0.5V±0.125V -1.25V±5% 3.3V CORE/2.5V LVPECL OUTPUT LOAD AC TEST CIRCUIT 3.3V CORE/2.5V LVCMOS OUTPUT LOAD AC TEST CIRCUIT 1.25±5% 2V VCC , VCCA, VCCO_LVPECL Qx SCOPE V CC , VCCA, VCCO_LVCMOS LVPECL LVCMOS SCOPE Qx nQx VEE VEE -0.5V±0.125V -1.25V±5% 2.5V LVPECL OUTPUT LOAD AC TEST CIRCUIT 843001AGI-23 2.5V LVCMOS OUTPUT LOAD AC TEST CIRCUIT www.icst.com/products/hiperclocks.html 8 REV. B JANUARY 6, 2006 PRELIMINARY Integrated Circuit Systems, Inc. ICS843001I-23 FEMTOCLOCKS™ CRYSTAL-TO-3.3V LVPECL/LVCMOS FREQUENCY SYNTHESIZER Noise Power Phase Noise Plot nQ Q Phase Noise Mask t PW t Offset Frequency f1 f2 odc = PERIOD t PW x 100% t PERIOD RMS Jitter = Area Under the Masked Phase Noise Plot RMS PHASE JITTER LVPECL OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD V CCO_LVCMOS 80% 2 REF_OUT VSW I N G t PW t odc = 80% Clock Outputs PERIOD t PW 20% 20% tR tF x 100% t PERIOD OUTPUT RISE/FALL TIME LVCMOS OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD VCC 2 CLK VCCO_LVCMOS REF_OUT 2 t PD PROPAGATION DELAY 843001AGI-23 www.icst.com/products/hiperclocks.html 9 REV. B JANUARY 6, 2006 PRELIMINARY Integrated Circuit Systems, Inc. ICS843001I-23 FEMTOCLOCKS™ CRYSTAL-TO-3.3V LVPECL/LVCMOS FREQUENCY SYNTHESIZER APPLICATION INFORMATION POWER SUPPLY FILTERING TECHNIQUES As in any high speed analog circuitry, the power supply pins are vulnerable to random noise. The ICS843001I-23 provides separate power supplies to isolate any high switching noise from the outputs to the internal PLL. VCC, VCCA, and VCCO_x should be individually connected to the power supply plane through vias, and bypass capacitors should be used for each pin. To achieve optimum jitter performance, power supply isolation is required. Figure 1 illustrates how a 10Ω resistor along with a 10µF and a .01μF bypass capacitor should be connected to each VCCA. 3.3V or 2.5V VCC .01μF 10Ω VCCA .01μF 10μF FIGURE 1. POWER SUPPLY FILTERING RECOMMENDATIONS FOR UNUSED INPUT AND OUTPUT PINS INPUTS: OUTPUTS: CRYSTAL INPUT: For applications not requiring the use of the crystal oscillator input, both XTAL_IN and XTAL_OUT can be left floating. Though not required, but for additional protection, a 1kΩ resistor can be tied from XTAL_IN to ground. LVCMOS OUTPUT: All unused LVCMOS output can be left floating. We recommend that there is no trace attached. LVPECL OUTPUT All unused LVPECL outputs can be left floating. We recommend that there is no trace attached. Both sides of the differential output pair should either be left floating or terminated. CLK INPUT: For applications not requiring the use of the test clock, it can be left floating. Though not required, but for additional protection, a 1kΩ resistor can be tied from the CLK input to ground. CONTROL PINS: All control pins have internal pull-ups or pull-downs; additional resistance is not required but can be added for additional protection. A 1kΩ resistor can be used. 843001AGI-23 www.icst.com/products/hiperclocks.html 10 REV. B JANUARY 6, 2006 PRELIMINARY Integrated Circuit Systems, Inc. ICS843001I-23 FEMTOCLOCKS™ CRYSTAL-TO-3.3V LVPECL/LVCMOS FREQUENCY SYNTHESIZER CRYSTAL INPUT INTERFACE The ICS843001I-23 has been characterized with 18pF parallel resonant crystals. The capacitor values shown in Figure 2 below were determined using an 18pF parallel resonant crystal and were chosen to minimize the ppm error. XTAL_IN C1 22p X1 18pF Parallel Cry stal XTAL_OUT C2 22p ICS843001I-23 ICS84332 Figure 2. CRYSTAL INPUt INTERFACE TERMINATION FOR 3.3V LVPECL OUTPUT The clock layout topology shown below is a typical termination for LVPECL outputs. The two different layouts mentioned are recommended only as guidelines. FOUT and nFOUT are low impedance follower outputs that generate ECL/LVPECL compatible outputs. Therefore, terminating resistors (DC current path to ground) or current sources must be used for functionality. These outputs are designed to drive 50Ω transmission lines. Matched impedance techniques should be used to maximize operating frequency and minimize signal distortion. Figures 3A and 3B show two different layouts which are recommended only as guidelines. Other suitable clock layouts may exist and it would be recommended that the board designers simulate to guarantee compatibility across all printed circuit and clock component process variations. 3.3V Zo = 50Ω 125Ω FOUT 125Ω FIN Zo = 50Ω Zo = 50Ω FOUT 50Ω RTT = 1 Z ((VOH + VOL) / (VCC – 2)) – 2 o VCC - 2V Zo = 50Ω RTT 84Ω FIGURE 3A. LVPECL OUTPUT TERMINATION 843001AGI-23 FIN 50Ω 84Ω FIGURE 3B. LVPECL OUTPUT TERMINATION www.icst.com/products/hiperclocks.html 11 REV. B JANUARY 6, 2006 PRELIMINARY Integrated Circuit Systems, Inc. ICS843001I-23 FEMTOCLOCKS™ CRYSTAL-TO-3.3V LVPECL/LVCMOS FREQUENCY SYNTHESIZER TERMINATION FOR 2.5V LVPECL OUTPUT Figure 4A and Figure 4B show examples of termination for 2.5V LVPECL driver. These terminations are equivalent to terminating 50Ω to VCC - 2V. For VCC = 2.5V, the VCC - 2V is very close to ground level. The R3 in Figure 4B can be eliminated and the termination is shown in Figure 4C. 2.5V VCC=2.5V 2.5V 2.5V VCC=2.5V R1 250 Zo = 50 Ohm R3 250 + Zo = 50 Ohm + Zo = 50 Ohm - Zo = 50 Ohm 2,5V LVPECL Driv er - R1 50 2,5V LVPECL Driv er R2 62.5 R2 50 R4 62.5 R3 18 FIGURE 4B. 2.5V LVPECL DRIVER TERMINATION EXAMPLE FIGURE 4A. 2.5V LVPECL DRIVER TERMINATION EXAMPLE 2.5V VCC=2.5V Zo = 50 Ohm + Zo = 50 Ohm 2,5V LVPECL Driv er R1 50 R2 50 FIGURE 4C. 2.5V LVPECL TERMINATION EXAMPLE 843001AGI-23 www.icst.com/products/hiperclocks.html 12 REV. B JANUARY 6, 2006 PRELIMINARY Integrated Circuit Systems, Inc. ICS843001I-23 FEMTOCLOCKS™ CRYSTAL-TO-3.3V LVPECL/LVCMOS FREQUENCY SYNTHESIZER RELIABILITY INFORMATION TABLE 7. θJAVS. AIR FLOW TABLE FOR 24 LEAD TSSOP θJA by Velocity (Meters per Second) Multi-Layer PCB, JEDEC Standard Test Boards 0 1 2.5 70°C/W 65°C/W 62°C/W TRANSISTOR COUNT The transistor count for ICS843001I-23 is: 4165 843001AGI-23 www.icst.com/products/hiperclocks.html 13 REV. B JANUARY 6, 2006 PRELIMINARY Integrated Circuit Systems, Inc. PACKAGE OUTLINE - G SUFFIX FOR ICS843001I-23 FEMTOCLOCKS™ CRYSTAL-TO-3.3V LVPECL/LVCMOS FREQUENCY SYNTHESIZER 24 LEAD TSSOP TABLE 8. PACKAGE DIMENSIONS SYMBOL Millimeters Minimum N A Maximum 24 -- 1.20 A1 0.05 0.15 A2 0.80 1.05 b 0.19 0.30 c 0.09 0.20 D 7.70 7.90 E E1 6.40 BASIC 4.30 e 4.50 0.65 BASIC L 0.45 0.75 α 0° 8° aaa -- 0.10 Reference Document: JEDEC Publication 95, MO-153 843001AGI-23 www.icst.com/products/hiperclocks.html 14 REV. B JANUARY 6, 2006 PRELIMINARY Integrated Circuit Systems, Inc. ICS843001I-23 FEMTOCLOCKS™ CRYSTAL-TO-3.3V LVPECL/LVCMOS FREQUENCY SYNTHESIZER TABLE 9. ORDERING INFORMATION Part/Order Number Marking Package Shipping Packaging Temperature ICS843001AGI-23 ICS843001AI23 24 Lead TSSOP tube -40°C to 85°C ICS843001AGI-23T ICS843001AI23 24 Lead TSSOP 2500 tape & reel -40°C to 85°C ICS843001AGI-23LF TBD 24 Lead "Lead-Free" TSSOP tube -40°C to 85°C ICS843001AGI-23LFT TBD 24 Lead "Lead-Free" TSSOP 2500 tape & reel -40°C to 85°C NOTE: Par ts that are ordered with an "LF" suffix to the par t number are the Pb-Free configuration and are RoHS compliant. The aforementioned trademarks, HiPerClockS and FemtoClocks are trademarks of Integrated Circuit Systems, Inc. or its subsidiaries in the United States and/or other countries. While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial and industrial applications. Any other applications such as those requiring high reliability or other extraordinary environmental requirements are not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in life support devices or critical medical instruments. 843001AGI-23 www.icst.com/products/hiperclocks.html 15 REV. B JANUARY 6, 2006