ICS ICS93701YGT

ICS93701
Integrated
Circuit
Systems, Inc.
DDR Phase Lock Loop Clock Driver
Recommended Application:
DDR Clock Driver
Pin Configuration
GND
CLKC0
CLKT0
VDD
CLKT1
CLKC1
GND
GND
CLKC2
CLKT2
VDD
SCLK
CLK_INT
CLK_INC
2
VDDI C
AVDD
AGND
GND
CLKC3
CLKT3
VDD
CLKT4
CLKC4
GND
Switching Characteristics:
• PEAK - PEAK jitter (66MHz): <120ps
• PEAK - PEAK jitter (>100MHz): <75ps
• CYCLE - CYCLE jitter (66MHz):<120ps
• CYCLE - CYCLE jitter (>100MHz):<65ps
• OUTPUT - OUTPUT skew: <100ps
• DUTY CYCLE: 49.5% - 50.5%
• Slew rate: 1V/ns - 2V/ns
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
ICS93701
Product Description/Features:
• Low skew, low jitter PLL clock driver
• I2C for functional and output control
• Feedback pins for input to output synchronization
• Spread Spectrum tolerant inputs
GND
CLKC5
CLKT5
VDD
CLKT6
CLKC6
GND
GND
CLKC7
CLKT7
VDD
SDATA
FB_INC
FB_INT
VDD
FB_OUTT
FB_OUTC
GND
CLKC8
CLKT8
VDD
CLKT9
CLKC9
GND
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
48-Pin TSSOP
Block Diagram
Functionality
INPUTS
AVDD CLK_INT
FB_OUTT
FB_OUTC
CLKT0
CLKC0
CLKT1
CLKC1
SCLK
SDATA
Control
Logic
CLKT2
CLKC2
CLKT3
CLKC3
CLKT4
CLKC4
FB_INT
FB_INC
CLK_INC
CLK_INT
CLKT5
CLKC5
PLL
CLKT6
CLKC6
CLKT7
CLKC7
CLKT8
CLKC8
CLKT9
CLKC9
0417B—10/29/02
2.5V
(nom)
2.5V
(nom)
2.5V
(nom)
OUTPUTS
CLK_INC CLKT CLKC FB_OUTT
FB_OUTC
PLL State
L
H
L
H
L
H
on
H
L
H
L
H
L
on
Z
Z
Z
Z
off
<20MHz)(1)
ICS93701
Pin Descriptions
PIN NUMBER
PIN NAME
TYPE
DESCRIPTION
1, 7, 8, 18, 24, 25,
GND
31, 41, 42, 48
PWR
Ground
26, 30, 40, 43, 47,
CLKC(9:0)
23, 19, 9, 6, 2
OUT
"Complementar y" clocks of differential pair outputs.
27, 29, 39, 44, 46,
CLKT(9:0)
22, 20, 10, 5, 3
OUT
"Tr ue" Clock of differential pair outputs.
Power supply 2.5V
4, 11, 21, 28,
34, 38, 45,
VDD
PWR
12
SCLK
IN
Clock input of I2C input, 5V tolerant input
13
CLK_INT
IN
"True" reference clock input
14
CLK_INC
IN
"Complementar y" reference clock input
15
2
VDDI C
PWR
3.3V power for I2C
16
AVDD
PWR
Analog power supply, 2.5V
17
AGND
PWR
A n a l o g gr o u n d .
32
FB_OUTC
OUT
"Complementar y" Feedback output, dedicated for external feedback. It
switches at the same frequency as the CLK. This output must be wired
to FB_INC.
33
FB_OUTT
OUT
"True" " Feedback output, dedicated for external feedback. It switches
at the same frequency as the CLK. This output must be wired to
FB_INT.
35
FB_INT
IN
"True" Feedback input, provides feedback signal to the internal PLL for
synchronization with CLK_INT to eliminate phase error.
36
FB_INC
IN
"Complementar y" Feedback input, provides signal to the internal PLL
for synchronization with CLK_INC to eliminate phase error.
37
SDATA
IN
Data input for I2C serial input, 5V tolerant input
0417B—10/29/02
2
ICS93701
Byte 0: Output Control
(1= enable, 0 = disable)
BIT
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
PIN#
3, 2
5, 6
10, 9
20, 19
22, 23
46, 47
44, 43
39, 40
PWD
1
1
1
1
1
1
1
1
Byte 1: Output Control
(1= enable, 0 = disable)
DESCRIPTION
CLKT0, CLKC0
CLKT1, CLKC1
CLKT2, CLKC2
CLKT3, CLKC3
CLKT4, CLKC4
CLKT5, CLKC5
CLKT6, CLKC6
CLKT7, CLKC7
BIT
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Byte 2: Reserved
(1= enable, 0 = disable)
BIT
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
PIN#
-
PWD
1
1
1
1
1
1
1
1
PIN#
-
PWD
1
1
1
1
1
1
1
1
PWD
1
1
1
1
1
1
1
1
DESCRIPTION
CLKT8, CLKC8
CLKT9, CLKC9
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Byte 3: Reserved
(1= enable, 0 = disable)
DESCRIPTION
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
BIT PIN# PWD
Bit 7
1
Bit 6
1
Bit 5
1
Bit 4
1
Bit 3
1
Bit 2
1
Bit 1
1
Bit 0
1
Byte 4: Reserved
(1= enable, 0 = disable)
BIT
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
PIN#
29, 30
27, 26
-
DESCRIPTION
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Byte 5: Reserved
(1= enable, 0 = disable)
DESCRIPTION
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
BIT
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
PIN# PWD
0
0
0
0
0
1
1
0
DESCRIPTION
Reser ved (Note)
Reser ved (Note)
Reser ved (Note)
Reser ved (Note)
Reser ved (Note)
Reser ved (Note)
Reser ved (Note)
Reser ved (Note)
Note: Don’t write into this register, writing into this
register can cause malfunction
0417B—10/29/02
3
ICS93701
Absolute Maximum Ratings
Supply Voltage (VDD & AVDD) . . . . . . . . . . .
Logic Inputs . . . . . . . . . . . . . . . . . . . . . . . . .
Ambient Operating Temperature . . . . . . . . . .
Storage Temperature . . . . . . . . . . . . . . . . . . .
-0.5V to 3.6V
GND –0.5 V to V DD + 0.5 V
0°C to +85°C
–65°C to +150°C
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These
ratings are stress specifications only and functional operation of the device at these or any other conditions above those
listed in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions
for extended periods may affect product reliability.
Electrical Characteristics - Input / Supply / Common Output Parameters
TA = 0 - 85oC; Supply Voltage AVDD, VDD = 2.5V +/- 0.2V (unless otherwise stated)
Input High Current
PARAMETER
SYMBOL
IIH
CONDITIONS
VIN = VDD or GND
Input Low Current
IIL
VIN = VDD or GND
Operating Supply
Current
IDD2.5
CL = 0pF @ 100MHz
IDDPD
Output High Current
IOH
CL = 0pF @ 100MHz
VDD = 2.3V, VOUT = 1V
-18
-32
mA
Output Low Current
IOL
VDD = 2.3V, VOUT = 1.2V
26
35
mA
High Impedance Output
Current
IOZ
VDD=2.7V, VOUT=VDD or GND
Input Clamp Voltage
VIK
VDDQ = 2.3V IIN = -18mA
VDD = min to max,
High-level output voltage
VOH
IOH = -1 mA
VDDQ = 2.3V,
IOH = -12 mA
VDD = min to max
Low-level output voltage
VOL
IOL=1 mA
VDDQ = 2.3 V
IOL=12 mA
Input Capacitance1
1
Output Capacitance
1
MIN
TYP
MAX
5
UNITS
µA
5
µA
185
210
mA
0.15
100
mA
0.1
±10
µA
-1.2
V
VDDQ - 0.1
2.45
V
1.7
2.10
V
0.05
0.1
V
0.35
0.6
V
CIN
VIN = GND or VDD
3
pF
COUT
VOUT = GND or VDD
3
pF
Guaranteed by design, not 100% tested in production.
0417B—10/29/02
4
ICS93701
Recommended Operating Condition (see note1)
TA = 0 - 85oC; Supply Voltage AVDD, VDD = 2.5V +/- 0.2V (unless otherwise stated)
PARAMETER
Analog/core Supply
Voltage
SYMBOL
VDDQ, AVDD
Input voltage level
MIN
TYP
MAX
UNITS
2.3
2.5
2.7
V
VDDI2C
2.3
VIL
-0.3
0
3.6
VDD-0.4
VIH
0.4
0.71
VDD+0.3
V
V
DC - CLKT, FB_INT
0.36
VDDQ +0.6
V
AC - CLKT, FB_INT
0.5
VDDQ +0.6
V
VIX
0.45x(VIH-VIL)
0.55x(VIH-VIL)
V
VOX
VDDQ/2 -0.2
VDDQ/2 +0.2
V
Input differential-pair
voltage swing1
VID
Input differential crossing
voltage
Output differential crossing
voltage
1
CONDITIONS
1.25
Differential input signal voltage specifies the differential voltage [VTR - VCP] required for switching,
where VTR is the true input level and VCP is the complementary input level.
Timing Requirements
TA = 0 - 85oC; Supply Voltage AVDD, VDD = 2.5V +/- 0.2V (unless otherwise stated)
PARAMETER
Max clock frequency
SYMBOL
freqop
Application Frequency Range
freqApp
Input clock duty cycle
dtin
CLK stabilization
TSTAB
CONDITIONS
MIN
MAX
UNITS
o
33
270
MHz
o
60
170
MHz
40
60
%
100
µs
2.5V+0.2V @ 25 C
2.5V+0.2V @ 25 C
from VDD = 3.3V to 1%
target freq.
0417B—10/29/02
5
ICS93701
Switching Characteristics
PARAMETER
Low-to high level
propagation delay time
High-to low level
propagation delay time
SYMBOL
CONDITION
MIN
TYP
MAX
UNITS
tPLH
1
CLK_IN to any output
3.5
ns
tPHL
1
CLK_IN to any output
3.5
ns
3
ns
Output enable time
tEN
PD# to any output
Output disable time
tdis
PD# to any output
Period Jitter
3
ns
100/133/166MHz
-40
±25
40
ps
100/133/166MHz
-120
±50
100
ps
Cycle to Cycle Jitter1
t(jit_hper)
Tcyc-Tcyc
30
65
ps
Phase error
t(phase error)
100/133/166Mhz
-150
-100
150
ps
Output to Output Skew
Tskew
60
100
ps
Pulse skew
Tskewp
60
100
ps
Duty cycle
DC
Half-period jitter
Slew Rate
2
tSLEW
100/133/166MHz
66MHz to 100MHz
49.5
50
50.5
%
101MHz to 133MHz
48.5
49
50
%
135MHz to 167MHz
48.5
49
50
%
Load = 120Ω/14pF
1
1.9
2
ps
Notes:
1. Refers to transition on noninverting outputs in PLL bypass mode.
2. While the pulse skew is almost constant over frequency, the duty cycle error increases at
high frequencies. This is due to the formula: duty cycle=twH/tc, where the cycle (tc)
decreases as the frequency goes up.
0417B—10/29/02
6
ICS93701
General I2C serial interface information
The information in this section assumes familiarity with I2C programming.
For more information, contact ICS for an I2C programming application note.
How to Write:
How to Read:
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Controller (host) sends a start bit.
Controller (host) sends the write address D2 (H)
ICS clock will acknowledge
Controller (host) sends a dummy command code
ICS clock will acknowledge
Controller (host) sends a dummy byte count
ICS clock will acknowledge
Controller (host) starts sending first byte (Byte 0)
through byte 5
• ICS clock will acknowledge each byte one at a time.
• Controller (host) sends a Stop bit
Controller (host) will send start bit.
Controller (host) sends the read address D3 (H)
ICS clock will acknowledge
ICS clock will send the byte count
Controller (host) acknowledges
ICS clock sends first byte (Byte 0) through byte 5
Controller (host) will need to acknowledge each byte
Controller (host) will send a stop bit
How to Write:
Controller (Host)
Start Bit
Address
D2(H)
ICS (Slave/Receiver)
How to Read:
Controller (Host)
Start Bit
Address
D3(H)
ACK
Dummy Command Code
ACK
ICS (Slave/Receiver)
ACK
Byte Count
Dummy Byte Count
ACK
ACK
ACK
ACK
ACK
ACK
ACK
ACK
ACK
ACK
ACK
ACK
ACK
ACK
Stop Bit
Byte 0
Byte 0
Byte 1
Byte 1
Byte 2
Byte 2
Byte 3
Byte 3
Byte 4
Byte 4
Byte 5
Byte 5
Stop Bit
Notes:
1.
2.
3.
4.
5.
6.
The ICS clock generator is a slave/receiver, I2C component. It can read back the data stored in the latches for
verification. Read-Back will support Intel PIIX4 "Block-Read" protocol.
The data transfer rate supported by this clock generator is 100K bits/sec or less (standard mode)
The input is operating at 3.3V logic levels.
The data byte format is 8 bit bytes.
To simplify the clock generator I2C interface, the protocol is set to use only "Block-Writes" from the controller.
The bytes must be accessed in sequential order from lowest to highest byte with the ability to stop after any
complete byte has been transferred. The Command code and Byte count shown above must be sent, but the
data is ignored for those two bytes. The data is loaded until a Stop sequence is issued.
At power-on, all registers are set to a default condition, as shown.
0417B—10/29/02
7
ICS93701
Recommended Layout for the ICS93701
General Layout Precautions:
Use copper flooded ground on the top signal layer under the
clock buffer The area under U1 on the right is an example.
Flood over the ground vias.
1) Use power vias for power and ground. Vias 20 mil or
larger in diameter have lower high frequency impedance.
Vias for signals may be minimum drill size.
2) Make all power and ground traces are as wide as the via
pad for lower inductance.
3) VAA for pin 16 has a low pass RC filter to decouple the
digital and analog supplies. The 4.7uF capacitors may be
replaced with a single low ESR device with the same
total capacitance. VAA is routed on a outside signal
layer. Do not cut a power or ground plane and route in it.
4) Notice that ground vias are never shared.
5) When ever possible, VCC (net V2P5 in the schematic)
pins have a decoupling capacitor. Power is always routed
from the plane connection via to the capacitor pad to the
VCC pin on the clock buffer. Moats or plane cuts are not
used to isolate power.
6) Differential mode clock output traces are routed:
a. With a ground trace between the pairs. Trace is
grounded on both ends.
b. Without a ground trace, clock pairs are routed with a
separation of at least 5 times the thickness of the
dielectric. If the dielectric thickness is 4.5 mil, the
trace separation is at least 18 mils.
V2A5
U1
16
Component Values:
Ref Desg. Value
C1,C4,C5,
C7,C11,C12
C2,C3,C8,
C9
C10
C6
R12
R9
U1
Description
Package
.01uF
CERAMIC MLC
0603
4.7uF
CERAMIC MLC
1206
.22uF
2200pF
120 Ω
4.7 Ω
CERAMIC MLC
CERAMIC MLC
ICS93701AG
4
11
15
21
28
34
38
45
V2P5
SCL
SDA
12
37
CLK_IN
CLK_IN#
0603
0603
0603
0603
TSSOP48
13
14
FB_IN
FB_IN#
R12
1
120
35
36
2
1
7
8
18
24
25
31
41
42
48
17
CLKT0
CLKC0
AVDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
CLKT1
CLKC1
CLKT2
CLKC2
CLKT3
CLKC3
SCL
SDA
CLKT4
CLKC4
CLK_INT
CLK_INC
CLKT5
CLKC5
FB_INT
FB_INC
CLKT6
CLKC6
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
AGND
CLKT7
CLKC7
CLKT8
CLKC8
CLKT9
CLKC9
FB_OUTT
FB_OUTC
3
2
5
6
10
9
20
19
22
23
46
47
44
43
39
40
29
30
27
26
33
32
ICS93701
V2P5
V2A5
R9
1
1
1
1
V2A5
1
2
1
1
4.7
0417B—10/29/02
8
2
1
1
2
C11
.01uF
C7
.01uF
2
2
C14
.01uF
C6
.0022pF
2
2
1
2
1
2
2
C10
.22uF
C15
.01uF
C12
.01uF
2
C13
.01uF
2
2
C1
.01uF
C9
4.7uF
C16
.01uF
1
2
C5
.01uF
1
1
2
C4
.01uF
C8
4.7uF
1
2
C3
4.7uF
1
1
2
C2
4.7uF
ICS93701
6.10 mm. Body, 0.50 mm. Pitch TSSOP
(240 mil)
(20 mil)
In Millimeters
In Inches
SYMBOL COMMON DIMENSIONS COMMON DIMENSIONS
MIN
MAX
MIN
MAX
A
-1.20
-.047
A1
0.05
0.15
.002
.006
A2
0.80
1.05
.032
.041
b
0.17
0.27
.007
.011
c
0.09
0.20
.0035
.008
D
SEE VARIATIONS
SEE VARIATIONS
E
8.10 BASIC
0.319 BASIC
E1
6.00
6.20
.236
.244
e
0.50 BASIC
0.020 BASIC
L
0.45
0.75
.018
.030
N
SEE VARIATIONS
SEE VARIATIONS
α
0°
8°
0°
8°
aaa
-0.10
-.004
c
N
L
E1
INDEX
AREA
E
1 2
D
A
A2
VARIATIONS
A1
N
-Ce
48
SEATING
PLANE
b
D mm.
MIN
12.40
D (inch)
MAX
12.60
Reference Doc.: JEDEC Publication 95, MO-153
10-0039
aaa C
Ordering Information
ICS93701yGT
Example:
ICS XXXX y G - PPP - T
Designation for tape and reel packaging
Pattern Number (2 or 3 digit number for parts with ROM code
patterns)
Package Type
G = TSSOP
Revision Designator (will not correlate with datasheet revision)
Device Type (consists of 3 or 4 digit numbers)
Prefix
ICS, AV = Standard Device
0417B—10/29/02
9
MIN
.488
MAX
.496