ICS ICS952623YFT

ICS952623
Advance Information
Integrated
Circuit
Systems, Inc.
Programmable Timing Control Hub™ for Next Gen P4™ processor
Output Features:
•
3 - 0.7V current-mode differential CPU pairs
•
1 - 0.7V current-mode differential SRC pair
•
7 - PCI (33MHz)
•
3 - PCICLK_F, (33MHz) free-running
•
1 - USB, 48MHz
•
1 - DOT, 48MHz
•
2 - REF, 14.318MHz
•
4 - 3V66, 66.66MHz
•
1 - VCH/3V66, selectable 48MHz or 66MHz
Key Specifications:
•
CPU/SRC outputs cycle-cycle jitter < 125ps
•
3V66 outputs cycle-cycle jitter < 250ps
•
PCI outputs cycle-cycle jitter < 250ps
•
CPU outputs skew: < 100ps
•
+/- 300ppm frequency accuracy on CPU & SRC clocks
Functionality
CPU
SRC
3V66 PCI
REF USB/DOT
B6b5 FS_A FS_B MHz
MHz
MHz MHz MHz
MHz
0
0
100 100/200 66.66 33.33 14.318
48.00
0
MID Ref/N0 Ref/N1 Ref/N2 Ref/N3 Ref/N4 Ref/N5
0
1
200 100/200 66.66 33.33 14.318
48.00
0
1
0
133 100/200 66.66 33.33 14.318
48.00
1
1
166 100/200 66.66 33.33 14.318
48.00
1
MID Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
0
0
200 100/200 66.66 33.33 14.318
48.00
0
1
400 100/200 66.66 33.33 14.318
48.00
1
1
0
266 100/200 66.66 33.33 14.318
48.00
1
1
333 100/200 66.66 33.33 14.318
48.00
Features/Benefits:
•
Supports tight ppm accuracy clocks for Serial-ATA
•
Supports spread spectrum modulation, 0 to -0.5%
down spread and +/- 0.25% center spread
•
Supports CPU clks up to 400MHz in test mode
•
Uses external 14.318MHz crystal
•
Supports undriven differential CPU, SRC pair in PD#
and CPU_STOP# for power management.
Pin Configuration
REF0
REF1
VDDREF
X1
X2
GND
PCICLK_F0
PCICLK_F1
PCICLK_F2
VDDPCI
GND
PCICLK0
PCICLK1
PCICLK2
PCICLK3
VDDPCI
GND
PCICLK4
PCICLK5
PCICLK6
PD#
3V66_0
3V66_1
VDD3V66
GND
3V66_2
3V66_3
SCLK
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
ICS952623
Recommended Application:
CK409 clock, Intel Yellow Cover part
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
FS_B
VDDA
GNDA
GND
IREF
FS_A
CPU_STOP#
PCI_STOP#
VDDCPU
CPUCLKT2
CPUCLKC2
GND
CPUCLKT1
CPUCLKC1
VDDCPU
CPUCLKT0
CPUCLKC0
GND
SRCCLKT
SRCCLKC
VDD
Vtt_PWRGD#
VDD48
GND
48MHz_DOT
48MHz_USB
SDATA
3V66_4/VCH
56-pin SSOP & TSSOP
0758—02/08/05
ADVANCE INFORMATION documents contain information on products in the formative or design phase development. Characteristic data and other specifications are design goals.
ICS reserves the right to change or discontinue these products without notice. Third party brands and names are the property of their respective owners.
Integrated
Circuit
Systems, Inc.
ICS952623
Advance Information
Pin Description
PIN
#
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
PIN NAME
REF0
REF1
VDDREF
X1
X2
GND
PCICLK_F0
PCICLK_F1
PCICLK_F2
VDDPCI
GND
PCICLK0
PCICLK1
PCICLK2
PCICLK3
VDDPCI
GND
PCICLK4
PCICLK5
PCICLK6
PIN TYPE
DESCRIPTION
OUT
OUT
PWR
IN
OUT
PWR
OUT
OUT
OUT
PWR
PWR
OUT
OUT
OUT
OUT
PWR
PWR
OUT
OUT
OUT
14.318 MHz reference clock.
14.318 MHz reference clock.
Ref, XTAL power supply, nominal 3.3V
Crystal input, Nominally 14.318MHz.
Crystal output, Nominally 14.318MHz
Ground pin.
Free running PCI clock not affected by PCI_STOP# .
Free running PCI clock not affected by PCI_STOP# .
Free running PCI clock not affected by PCI_STOP# .
Power supply for PCI clocks, nominal 3.3V
Ground pin.
PCI clock output.
PCI clock output.
PCI clock output.
PCI clock output.
Power supply for PCI clocks, nominal 3.3V
Ground pin.
PCI clock output.
PCI clock output.
PCI clock output.
21
PD#
IN
Asynchronous active low input pin used to power down the device
into a low power state. The internal clocks are disabled and the
VCO and the crystal are stopped. The latency of the power down
will not be greater than 1.8ms. Internal pull-up of 150K nominal.
22
23
24
25
26
27
28
3V66_0
3V66_1
VDD3V66
GND
3V66_2
3V66_3
SCLK
OUT
OUT
PWR
PWR
OUT
OUT
IN
3.3V 66.66MHz clock output
3.3V 66.66MHz clock output
Power pin for the 3V66 clocks.
Ground pin.
3.3V 66.66MHz clock output
3.3V 66.66MHz clock output
Clock pin of I2C circuitry 5V tolerant
0758—02/08/05
2
Integrated
Circuit
Systems, Inc.
ICS952623
Advance Information
Pin Description (Continued)
PIN
#
PIN NAME
PIN TYPE
29
3V66_4/VCH
OUT
30
31
32
33
34
SDATA
48MHz_USB
48MHz_DOT
GND
VDD48
I/O
OUT
OUT
PWR
PWR
35
Vtt_PWRGD#
IN
36
VDD
PWR
37
SRCCLKC
OUT
38
SRCCLKT
OUT
39
GND
PWR
40
CPUCLKC0
OUT
41
CPUCLKT0
OUT
42
VDDCPU
PWR
43
CPUCLKC1
OUT
44
CPUCLKT1
OUT
45
GND
PWR
46
CPUCLKC2
OUT
47
CPUCLKT2
OUT
48
VDDCPU
PWR
49
PCI_STOP#
IN
50
CPU_STOP#
IN
51
FS_A
IN
52
IREF
OUT
53
54
55
56
GND
GNDA
VDDA
FS_B
PWR
PWR
PWR
IN
DESCRIPTION
66.66MHz clock output for AGP support. AGP-PCI should be
aligned with a skew window tolerance of 500ps.
VCH is 48MHz clock output for video controller hub.
Data pin for I2C circuitry 5V tolerant
48MHz clock output.
48MHz clock output.
Ground pin.
Power for 48MHz output buffers and fixed PLL core.
This 3.3V LVTTL input is a level sensitive strobe used to determine
when latch inputs are valid and are ready to be sampled. This is an
active low input.
Power supply for SRC clocks, nominal 3.3V
Complement clock of differential pair for S-ATA support.
+/- 300ppm accuracy required.
True clock of differential pair for S-ATA support.
+/- 300ppm accuracy required.
Ground pin.
"Complementary" clocks of differential pair CPU outputs. These are
current mode outputs. External resistors are required for voltage
bias.
"True" clocks of differential pair CPU outputs. These are current
mode outputs. External resistors are required for voltage bias.
Supply for CPU clocks, 3.3V nominal
"Complementary" clocks of differential pair CPU outputs. These are
current mode outputs. External resistors are required for voltage
bias.
"True" clocks of differential pair CPU outputs. These are current
mode outputs. External resistors are required for voltage bias.
Ground pin.
"Complementary" clocks of differential pair CPU outputs. These are
current mode outputs. External resistors are required for voltage
bias.
"True" clocks of differential pair CPU outputs. These are current
mode outputs. External resistors are required for voltage bias.
Supply for CPU clocks, 3.3V nominal
Stops all PCICLKs and SRC pair besides the PCICLK_F clocks at
logic 0 level, when input low. PCI and SRC clocks can be set to
Free_Running through I2C. Internal pull-up of 150K nominal.
Stops all CPUCLK besides the free running clocks. Internal pull-up
of 150K nominal
Frequency select pin, see Frequency table for functionality
IREF establishes the reference current for the CPUCLK pairs. A
fixed precision resistor tied to ground is required to establish the
appropriate current.
Ground pin.
Ground pin for core.
3.3V power for the PLL core.
Frequency select pin, see Frequency table for functionality
0758—02/08/05
3
Integrated
Circuit
Systems, Inc.
ICS952623
Advance Information
General Description
ICS952623 follows Intel CK409 Yellow Cover specification. This clock synthesizer provides a single chip solution for next
generation P4 Intel processors and Intel chipsets. ICS952623 is driven with a 14.318MHz crystal. It generates CPU outputs up
to 200MHz. It also provides a tight ppm accuracy output for Serial ATA support.
Block Diagram
Frequency
Dividers
PLL2
X1
X2
48MHz, USB, DOT
XTAL
REF (1:0)
CPUCLKT (2:0)
CPUCLKC (2:0)
SRCCLKT0
SCLK
SDATA
CPU_STOP#
PCI_STOP#
Vtt_PWRGD#
PD#
FS_A
FS_B
Programmable
Spread
PLL1
Programmable
Frequency
Dividers
SRCCLKC0
3V66(4:0)
PCICLK (6:0)
Control
Logic
PCICLKF (2:0)
I REF
Power Groups
Pin Number
VDD
GND
3
6
24
25
10,16
11,17
36
39
55
54
34
33
N/A
53
48, 42
45
STOP
Logic
Description
Xtal, Ref
3V66 [0:3]
PCICLK outputs
SRCCLK outputs
Master clock, CPU Analog
48MHz, PLL
IREF
CPUCLK clocks
0758—02/08/05
4
Integrated
Circuit
Systems, Inc.
ICS952623
Advance Information
Absolute Max
Symbol
Parameter
Min
Max
Units
VDD_A
VDD_In
3.3V Core Supply Voltage
3.3V Logic Input Supply Voltage
GND - 0.5
V DD + 0.5V
V DD + 0.5V
V
V
Ts
Tambient
Tcase
Storage Temperature
Ambient Operating Temp
Case Temperature
Input ESD protection
human body model
ESD prot
-65
0
°
150
70
115
C
°C
°C
2000
V
Electrical Characteristics - Input/Supply/Common Output Parameters
TA = 0 - 70°C; Supply Voltage V DD = 3.3 V +/-5%
PARAMETER
SYMBOL
CONDITIONS
MIN
Input High Voltage
Input MID Voltage
Input Low Voltage
Input High Current
VIH
VMID
VIL
I IH
3.3 V +/-5%
3.3 V +/-5%
3.3 V +/-5%
VIN = V DD
VIN = 0 V; Inputs with no pullup resistors
2
1
VSS - 0.3
-5
I IL1
Input Low Current
TYP
MAX
VDD + 0.3
1.8
0.8
5
UNITS NOTES
V
V
V
uA
-5
uA
-200
uA
I IL2
VIN = 0 V; Inputs with pull-up
resistors
Operating Supply Current
I DD3.3OP
Full Active, CL = Full load;
350
mA
Powerdown Current
I DD3.3PD
35
12
Input Frequency 3
Pin Inductance1
Fi
Lpin
CIN
COUT
CINX
all diff pairs driven
all differential pairs tri-stated
VDD = 3.3 V
7
5
6
5
mA
mA
MHz
nH
pF
pF
pF
3
1
1
1
1
1.8
ms
1,2
33
kHz
1
15
ns
1
300
us
1
5
5
ns
ns
1
2
10
us
1
5
5
ns
ns
1
2
Input Capacitance1
Clk Stabilization1,2
Modulation Frequency
Tdrive_SRC
Tdrive_PD#
Tfall_Pd#
Trise_Pd#
Tdrive_CPU_Stop#
Tfall_CPU_Stop#
Trise_CPU_Stop#
TSTAB
Logic Inputs
Output pin capacitance
X1 & X2 pins
From VDD Power-Up or deassertion of PD# to 1st clock
Triangular Modulation
SRC output enable after
PCI_Stop# de-assertion
CPU output enable after
PD# de-assertion
PD# fall time of
PD# rise time of
CPU output enable after
CPU_Stop# de-assertion
PD# fall time of
PD# rise time of
1
14.31818
30
Guaranteed by design, not 100% tested in production.
See timing diagrams for timing requirements.
3
Input frequency should be measured at the REF output pin and tuned to ideal 14.31818MHz to meet
ppm frequency accuracy on PLL outputs.
2
0758—02/08/05
5
Integrated
Circuit
Systems, Inc.
ICS952623
Advance Information
Electrical Characteristics - CPU & SRC 0.7V Current Mode Differential Pair
TA = 0 - 70°C; V DD = 3.3 V +/-5%; CL =2pF
1
PARAMETER
SYMBOL
CONDITIONS
MIN
Current Source Output
Impedance
Zo1
VO = Vx
3000
Voltage High
VHigh
Statistical measurement on
single ended signal using
oscilloscope math function.
660
Voltage Low
VLow
Max Voltage
Min Voltage
Crossing Voltage (abs)
Vovs
Vuds
Vcross(abs)
Crossing Voltage (var)
d-Vcross
Long Accuracy
ppm
Average period
Tperiod
Absolute min period
Tabsmin
Rise Time
Fall Time
Rise Time Variation
Fall Time Variation
tr
tf
d-tr
d-tf
Duty Cycle
dt3
Skew
tsk3
Jitter, Cycle to cycle
tjcyc-cyc
Measurement on single ended
signal using absolute value.
Variation of crossing over all
edges
see Tperiod min-max values
200MHz nominal
200MHz spread
166.66MHz nominal
166.66MHz spread
133.33MHz nominal
133.33MHz spread
100.00MHz nominal
100.00MHz spread
200MHz nominal
166.66MHz nominal/spread
133.33MHz nominal/spread
100.00MHz nominal/spread
VOL = 0.175V, V OH = 0.525V
V OH = 0.525V VOL = 0.175V
Measurement from differential
wavefrom
VT = 50%
Measurement from differential
wavefrom
TYP
MAX
UNITS
NOTES
Ω
1
850
1
mV
-150
150
1150
1
550
mV
1
1
1
140
mV
1
-300
4.9985
4.9985
5.9982
5.9982
7.4978
7.4978
9.9970
9.9970
4.8735
5.8732
7.3728
9.8720
175
175
300
5.0015
5.0266
6.0018
6.0320
7.5023
5.4000
10.0030
10.0533
700
700
125
125
ppm
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ps
ps
ps
ps
1,2
2
2
2
2
2
2
2
2
1,2
1,2
1,2
1,2
1
1
1
1
45
55
%
1
100
ps
1
125
ps
1
-300
250
mV
Guaranteed by design, not 100% tested in production.
2
All Long Term Accuracy and Clock Period specifications are guaranteed with the assumption that Ref output is at
14.31818MHz
SRC clock outputs run at only 100MHz or 200MHz, specs for 133.33 and 166.66 do not apply to SRC clock pair.
0758—02/08/05
6
Integrated
Circuit
Systems, Inc.
ICS952623
Advance Information
Electrical Characteristics - 3V66 Mode: 3V66 [4:0]
TA = 0 - 70°C; VDD = 3.3 V +/-5%; CL = 10-30 pF (unless otherwise specified)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
Long Accuracy
ppm
see Tperiod min-max values
-300
66.66MHz output nominal
14.9955
Clock period
Tperiod
66.66MHz output spread
14.9955
I OH = -1 mA
2.4
Output High Voltage
V OH
I OL = 1 mA
Output Low Voltage
V OL
-33
V OH @ MIN = 1.0 V
Output High Current
I OH
V OH @ MAX = 3.135 V
30
VOL @ MIN = 1.95 V
Output Low Current
I OL
VOL @ MAX = 0.4 V
Edge Rate
Rising edge rate
1
Edge Rate
Falling edge rate
1
VOL = 0.4 V, VOH = 2.4 V
0.5
Rise Time
t r1
VOH = 2.4 V, VOL = 0.4 V
0.5
Fall Time
t f1
45
MAX
300
15.0045
15.0799
Notes
1,2
2
2
38
4
4
2
2
UNITS
ppm
ns
ns
V
V
mA
mA
mA
mA
V/ns
V/ns
ns
ns
55
%
1
0.55
-33
1
1
1
1
Duty Cycle
dt1
VT = 1.5 V
Skew
t sk1
VT = 1.5 V
250
ps
1
Jitter
t jcyc-cyc
V T = 1.5 V 3V66
250
ps
1
1
Guaranteed by design, not 100% tested in production.
2
All Long Term Accuracy and Clock Period specifications are guaranteed with the assumption that Ref output is
at 14.31818MHz
Electrical Characteristics - PCICLK/PCICLK_F
TA = 0 - 70°C; VDD = 3.3 V +/-5%; CL = 10-30 pF (unless otherwise specified)
PARAMETER
SYMBOL
CONDITIONS
MIN
Long Accuracy
ppm
Clock period
Tperiod
Output High Voltage
Output Low Voltage
VOH
VOL
see Tperiod min-max values
33.33MHz output nominal
33.33MHz output spread
IOH = -1 mA
IOL = 1 mA
V OH @MIN = 1.0 V
VOH@ MAX = 3.135 V
VOL @ MIN = 1.95 V
V OL @ MAX = 0.4 V
-300
29.9910
29.9910
2.4
Rising edge rate
Falling edge rate
VOL = 0.4 V, VOH = 2.4 V
VOH = 2.4 V, VOL = 0.4 V
V T = 1.5 V
V T = 1.5 V
VT = 1.5 V 3V66
1
1
0.5
0.5
45
Output High Current
Output Low Current
Edge Rate
Edge Rate
Rise Time
Fall Time
Duty Cycle
Skew
Jitter
I OH
IOL
tr1
tf1
dt1
tsk1
tjcyc-cyc
1
TYP
MAX
UNITS
Notes
300
30.0090
30.1598
1,2
2
2
38
ppm
ns
ns
V
V
mA
mA
mA
mA
4
4
2
2
55
500
250
V/ns
V/ns
ns
ns
%
ps
ps
1
1
1
1
1
1
1
0.55
-33
-33
30
Guaranteed by design, not 100% tested in production.
All Long Term Accuracy and Clock Period specifications are guaranteed with the assumption that Ref
output is at 14.31818MHz
2
0758—02/08/05
7
Integrated
Circuit
Systems, Inc.
ICS952623
Advance Information
Electrical Characteristics - 48MHz DOT Clock
TA = 0 - 70°C; VDD = 3.3 V +/-5%; CL = 5-10 pF (unless otherwise specified)
PARAMETER
SYMBOL
Long Accuracy
ppm
Clock period
Output High Voltage
Output Low Voltage
Tperiod
VOH
V OL
Output High Current
Output Low Current
I OH
IOL
Edge Rate
Edge Rate
CONDITIONS
see Tperiod min-max
values
48MHz output nominal
IOH = -1 mA
IOL = 1 mA
V OH @ MIN = 1.0 V
VOH @ MAX = 3.135 V
V OL @ MIN = 1.95 V
V OL @ MAX = 0.4 V
Rising edge rate
Falling edge rate
MIN
TYP
MAX
UNITS
Notes
-200
200
ppm
1,2
20.8257
2.4
20.8340
2
2
2
38
4
4
ns
V
V
mA
mA
mA
mA
V/ns
V/ns
0.55
-33
-33
30
1
1
Rise Time
tr1
VOL = 0.4 V, VOH = 2.4 V
0.5
1
ns
1
Fall Time
tf1
VOH = 2.4 V, V OL = 0.4 V
0.5
1
ns
1
Duty Cycle
dt1
VT = 1.5 V
125us period jitter
(8kHz frequency
modulation amplitude)
45
55
%
1
2
ns
1
Long Term Jitter
1
Guaranteed by design, not 100% tested in production.
All Long Term Accuracy and Clock Period specifications are guaranteed with the assumption that Ref
output is at 14.31818MHz
2
0758—02/08/05
8
Integrated
Circuit
Systems, Inc.
ICS952623
Advance Information
Electrical Characteristics - VCH, 48MHz, USB
TA = 0 - 70°C; VDD = 3.3 V +/-5%; CL = 10-20 pF (unless otherwise specified)
PARAMETER
SYMBOL
CONDITIONS
MIN
Long Accuracy
Clock period
Output High Voltage
Output Low Voltage
ppm
Tperiod
VOH
VOL
-200
20.8257
2.4
Output High Current
IOH
Output Low Current
IOL
see Tperiod min-max values
48MHz output nominal
IOH = -1 mA
IOL = 1 mA
V OH @ MIN = 1.0 V
V OH@ MAX = 3.135 V
VOL @MIN = 1.95 V
VOL @ MAX = 0.4 V
Rising edge rate
Falling edge rate
Edge Rate
Edge Rate
-33
30
1
1
TYP
MAX
UNITS Notes
200
ppm
20.8340 ns
V
0.55
V
mA
-33
mA
mA
38
mA
2
V/ns
2
V/ns
1,2
2
1
1
Rise Time
tr1
V OL = 0.4 V, V OH = 2.4 V
1
2
ns
1
Fall Time
Duty Cycle
tf1
dt1
V OH = 2.4 V, VOL = 0.4 V
VT = 1.5 V
125us period jitter
(8kHz frequency modulation
amplitude)
1
45
2
55
ns
%
1
1
6
ns
1
Long Term Jitter
1
Guaranteed by design, not 100% tested in production.
All Long Term Accuracy and Clock Period specifications are guaranteed with the assumption that Ref
output is at 14.31818MHz
2
0758—02/08/05
9
Integrated
Circuit
Systems, Inc.
ICS952623
Advance Information
Electrical Characteristics - REF-14.318MHz
TA = 0 - 70°C; VDD = 3.3 V +/-5%; CL = 10-20 pF (unless otherwise specified)
PARAMETER
SYMBOL
CONDITIONS
MIN
Long Accuracy
Clock period
Output High Voltage
ppm1
Tperiod
VOH1
see Tperiod min-max values
14.318MHz output nominal
IOH = -1 mA
-300
69.8270
2.4
Output Low Voltage
V OL1
IOL = 1 mA
Output High Current
IOH1
Output Low Current
IOL1
Rise Time
tr11
Fall Time
tf11
tsk11
dt11
Skew
Duty Cycle
Jitter
tjcyc-cyc
V OH @MIN = 1.0 V,
V OH@MAX = 3.135 V
VOL @MIN = 1.95 V,
VOL @MAX = 0.4 V
VOL = 0.4 V, VOH = 2.4 V
MAX
UNITS
300
69.8550
ppm
ns
V
0.4
V
-29
-23
mA
29
27
mA
1
2
ns
1
2
ns
500
ps
55
%
1000
ps
VOH = 2.4 V, VOL = 0.4 V
TYP
VT = 1.5 V
VT = 1.5 V
1
45
VT = 1.5 V
1
Guaranteed by design, not 100% tested in production.
Group to Group Skews at Common Transition Edges
GROUP
SYMBOL
CONDITIONS
MIN
3V66 to PCI
DOT-USB
DOT-VCH
S3V66-PCI
SDOT_USB
SDOT_VCH
3V66 (4:0) leads 33MHz PCI
180 degrees out of phase
in phase
1.50
0.00
0.00
0758—02/08/05
10
TYP
MAX
UNITS
3.50
1.00
1.00
ns
ns
ns
Integrated
Circuit
Systems, Inc.
ICS952623
Advance Information
2
I C Table: Read-Back Register
Byte 0
Pin #
Bit 7
Bit 6
Bit 5
Bit 4
Name
RESERVED
RESERVED
RESERVED
RESERVED
PCI_STOP#
Bit 3
-
Bit 2
-
CPU_STOP#
Bit 1
-
FSB
Bit 0
-
FSA
Control Function
RESERVED
RESERVED
RESERVED
RESERVED
PCI STOP# Read
Back
CPU STOP Read
Back
Freq Select 1 Read
Back
Freq Select 0 Read
Back
1
RESERVED
RESERVED
RESERVED
RESERVED
PWD
X
X
X
X
R
READBACK
X
R
READBACK
X
Type
-
R
R
0
READBACK of CPU(2:0)
Frequency
X
X
2
I C Table: Spreading and Device Behavior Control Register
Byte 1
Pin #
Name
Control Function
SRC Free-Running
37,38
SRC/SRC#
Bit 7
Control
37,38
SRC
Output Control
Bit 6
46,47
CPUT2/CPUC2
Bit 5
CPU FREE-RUNNING
43,44
CPUT1/CPUC1
Bit 4
CONTROL
40,41
CPUT0/CPUC0
Bit 3
46,47
CPUT2/CPUC2
Output Control
Bit 2
CPUT1/CPUC1
Output Control
43,44
Bit 1
CPUT0/CPUC0
Output Enable
40,41
Bit 0
Type
0
1
PWD
RW
FREE-RUN
STOPPABLE
0
RW
RW
RW
RW
RW
RW
RW
Disable
FREE-RUN
FREE-RUN
FREE-RUN
Disable
Disable
Disable
Enable
STOPPABLE
STOPPABLE
STOPPABLE
Enable
Enable
Enable
1
1
1
1
1
1
1
2
I C Table: Output Control Register
Byte 2
Pin #
Control Function
Type
0
1
PWD
Bit 7
37,38
0: Driven in PD#
RW
Driven
Hi-Z
0
Bit 6
37,38
0: Driven in
PCI_Stop#
RW
Driven
Hi-Z
0
RW
Driven
Hi-Z
0
RW
Driven
Hi-Z
0
RW
Driven
Hi-Z
0
RW
Driven
Hi-Z
0
RW
Driven
Hi-Z
0
RW
Driven
Hi-Z
0
Bit 5
46,47
Bit 4
43,44
Bit 3
40,41
Bit 2
46,47
Bit 1
43,44
Bit 0
40,41
Name
SRC_PD#
Drive Mode
SRC_Stop#
Drive Mode
CPUT2_PD# Drive
Mode
CPUT1_PD# Drive
Mode
CPUT0_PD# Drive
Mode
CPUT2_Stop Drive
Mode
CPUT1_Stop Drive
Mode
CPUT0_Stop Drive
Mode
0:driven in PD#
1: Tri-stated
0:driven when stopped
1: Tri-stated
0758—02/08/05
11
Integrated
Circuit
Systems, Inc.
ICS952623
Advance Information
2
I C Table: Output Control Register
Pin #
Byte 3
Name
Control Function
Type
0
1
PWD
PCI_Stop# Control
0:all stoppable PCI
are stopped
RW
Enable
Disable
1
RW
RW
RW
RW
RW
RW
RW
Disable
Disable
Disable
Disable
Disable
Disable
Disable
Enable
Enable
Enable
Enable
Enable
Enable
Enable
1
1
1
1
1
1
1
Bit 7
7,8,9,12,13,14,15,
18,19,20,37,38,
PCI_Stop#
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
20
19
18
15
14
13
12
PCICLK6
PCICLK5
PCICLK4
PCICLK3
PCICLK2
PCICLK1
PCICLK0
I C Table: Output Control Register
Pin #
Byte 4
Name
Control Function
Type
0
1
PWD
48MHz_USB
2x output drive
48MHz_USB
PCIF2
PCIF1
PCIF0
PCICLK_F2
PCICLK_F1
PCICLK_F0
0=2x drive
RW
2x drive
normal
0
Output Control
Output Control
Output Control
Output Control
RW
RW
RW
RW
RW
RW
RW
Disable
FREE-RUN
FREE-RUN
FREE-RUN
Disable
Disable
Disable
Enable
STOPPABLE
STOPPABLE
STOPPABLE
Enable
Enable
Enable
1
0
0
0
1
1
1
Control Function
Output Control
RESERVED
Type
RW
`
0
Disable
-
1
Enable
-
PWD
1
0
Output Select
RW
3V66
VCH
0
Output
Output
Output
Output
Output
RW
RW
RW
RW
RW
Disable
Disable
Disable
Disable
Disable
Enable
Enable
Enable
Enable
Enable
1
1
1
1
1
Output
Output
Output
Output
Output
Output
Output
Control
Control
Control
Control
Control
Control
Control
2
Bit 7
31
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
31
9
8
7
9
8
7
PCI FREE-RUN NING
CONTROL
2
I C Table: Output Control Register
Byte 5
Pin #
Name
32
48MHZ_DOT
Bit 7
RESERVED
Bit 6
3V66_4/VCH
29
Bit 5
Select
29
3V66_4/VCH
Bit 4
27
3V66_3
Bit 3
26
3V66_2
Bit 2
23
3V66_1
Bit 1
3V66_0
22
Bit 0
Control
Control
Control
Control
Control
0758—02/08/05
12
Integrated
Circuit
Systems, Inc.
ICS952623
Advance Information
2
I C Table: Output Control and Fix Frequency Register
Pin #
Name
Control Function
Byte 6
Bit 7
1,2,7,8,9,12,13,14,
15,18,19,20,22,23,2
6,27,29,31,32,37,38
,40,41,43,44,46,47
Test Clock Mode
Bit 6
-
RESERVED
Bit 5
40,41,43,44,46,47
RESERVED
Bit 4
37,38
RESERVED
Spread Type
Bit 3
Bit 2
Type
0
1
PWD
Test Clock Mode
-
Disable
Enable
0
FS_A and FS_B
Operation
SRC Frequency
Select
Down/Center
-
-
-
0
-
Normal
Test Mode
0
-
100MHz
200MHz
0
-
Down
Center
0
Spread
OFF
Spread
ON
0
7,8,9,12,13,14,15,1
8,19,20,22,23,26,27
Spread Spectrum Mode
,29,31,32,37,38,40,
41,43,44,46,47
Bit 1
Bit 0
2
1
REF1
REF0
Output Control
Output Control
RW
RW
Disable
Disable
Enable
Enable
1
1
Control Function
Type
R
R
R
R
R
R
R
R
0
-
1
-
PWD
0
0
0
0
0
0
0
1
Control Function
Type
0
1
PWD
Writing to this register
will configure how
many bytes will be
read back, default is
08 = 8 bytes.
RW
RW
RW
RW
RW
RW
RW
RW
-
-
0
0
0
0
1
0
0
0
2
I C Table: Vendor & Revision ID Register
Byte 7
Pin #
Name
RID3
Bit 7
RID2
Bit 6
RID1
Bit 5
RID0
Bit 4
VID3
Bit 3
VID2
Bit 2
VID1
Bit 1
VID0
Bit 0
REVISION ID
VENDOR ID
2
I C Table: Byte Count Register
Byte 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Pin #
-
Name
BC7
BC6
BC5
BC4
BC3
BC2
BC1
BC0
0758—02/08/05
13
Integrated
Circuit
Systems, Inc.
ICS952623
Advance Information
2
I C Table: Overclocking Output Control Register
Pin #
Name
Byte 9
Reserved
Bit 7
Reserved
Bit 6
Reserved
Bit 5
Reserved
Bit 4
Bit 3
-
Over Clocking
Bit 2
Bit 1
Bit 0
-
Over Clocking
Over Clocking
Reserved
Control Function
Reserved
Reserved
Reserved
Reserved
1: over-clk
0: normal mode
Over Clocking
Over Clocking
Reserved
Type
RW
RW
RW
RW
Control Function
Type
0
1
PWD
R
R
R
RW
0
1
See over clocking per bit 1
and 2
00= +15%, 01 = +20%
10= +5%, 11= +10%
-
PWD
0
0
0
0
0
0
0
0
2
I C Table: VCO Control Select Bit Control Register
Pin #
Byte 10
Name
RW
DISABLED
ENABLED
0
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
Enables prograaming
bytes 11-14
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RW
RW
RW
RW
RW
RW
-
-
0
0
0
0
0
0
RESERVED
RESERVED
RW
-
-
0
Control Function
N Divider Bit 8
Type
RW
0
-
1
-
PWD
X
RW
-
-
X
RW
-
-
X
RW
-
-
X
RW
-
-
X
RW
-
-
X
RW
-
-
X
RW
-
-
X
Bit 7
-
Programming ENABLE
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
-
Bit 0
-
2
I C Table: VCO Frequency Control Register
Pin #
Name
Byte 11
N Div8
Bit 7
Bit 6
-
M Div6
Bit 5
-
M Div5
Bit 4
-
M Div4
Bit 3
-
M Div3
Bit 2
-
M Div2
Bit 1
-
M Div1
Bit 0
M Div0
The decimal
representation of M
Div (6:0) is equal to
reference divider
value. Default at
power up = latch-in or
Byte 0 Rom table.
0758—02/08/05
14
Integrated
Circuit
Systems, Inc.
2
I C Table: VCO Frequency Control
Byte 12
Pin #
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
ICS952623
Advance Information
Register
Name
N Div7
N Div6
N Div5
N Div4
N Div3
N Div2
N Div1
N Div0
Control Function
Type
RW
RW
RW
RW
RW
RW
RW
RW
0
-
1
-
PWD
X
X
X
X
X
X
X
X
Control Function
These Spread
Spectrum bits will
program the spread
pecentage. It is
recommended to use
ICS Spread % table
for spread
programming.
Type
RW
RW
RW
RW
RW
RW
RW
RW
0
-
1
-
PWD
X
X
X
X
X
X
X
X
Control Function
Reserved
Reserved
Type
RW
RW
RW
RW
RW
RW
RW
RW
0
-
1
-
PWD
0
0
X
X
X
X
X
X
The decimal
representation of N
Div (8:0) is equal to
VCO divider value.
Default at power up =
latch-in or Byte 0 Rom
table.
2
I C Table: Spread Spectrum Control Register
Pin #
Name
Byte 13
SSP7
Bit 7
SSP6
Bit 6
SSP5
Bit 5
SSP4
Bit 4
SSP3
Bit 3
SSP2
Bit 2
SSP1
Bit 1
SSP0
Bit 0
2
I C Table: Spread Spectrum Control Register
Pin #
Name
Byte 14
Reserved
Bit 7
Reserved
Bit 6
SSP13
Bit 5
SSP12
Bit 4
SSP11
Bit 3
SSP10
Bit 2
SSP9
Bit 1
SSP8
Bit 0
It is recommended to
use ICS Spread %
table for spread
programming.
0758—02/08/05
15
Integrated
Circuit
Systems, Inc.
ICS952623
Advance Information
PCI Stop Functionality
The PCI_STOP# signal is on an active low input controlling PCI and SRC outputs. If PCIF (2:0) and SRC clocks can be set to
be free-running through I2C programming. Outputs set to be free-running will ignore both the PCI_STOP pin and the
PCI_STOP register bit.
PCI_STOP#
CPU
CPU #
SRC
SRC#
3V66
PCIF/PCI
USB/DOT
REF
1
Normal
Normal
Normal
Normal
66MHz
33MHz
48MHz
14.318MHz
0
Normal
Normal
Iref * 6
or Float
Low
66MHz
Low
48MHz
14.318MHz
Note
PCI_STOP# Assertion (transition from '1' to '0')
The clock samples the PCI_STOP# signal on a rising edge of PCIF clock. After detecting the PCI_STOP# assertion low, all
PCI[6:0] and stoppable PCIF[2:0] clocks will latch low on their next high to low transition. After the PCI clocks are latched low,
the SRC clock, (if set to stoppable) will latch high at Iref * 6 (or tristate if Byte 2 Bit 6 = 1) upon its next low to high transition and
the SRC# will latch low as shown below.
Tsu
PCI_STOP#
PCIF[2:0] 33MHz
PCI[6:0] 33MHz
SRC 100MHz
SRC# 100MHz
PCI_STOP# - De-assertion
The de-assertion of the PCI_Stop# signal is to be sampled on the rising edge of the PCIF free running clock domain. After
detecting PCI_Stop# de-assertion, all PCI[6:0], stoppable PCIF[2:0] and stoppable SRC clocks will resume in a glitch free
manner.
Tsu
Tdrive_SRC
PCI_STOP#
PCIF[2:0] 33MHz
PCI[6:0] 33MHz
SRC 100MHz
SRC# 100MHz
0758—02/08/05
16
Integrated
Circuit
Systems, Inc.
ICS952623
Advance Information
CPU_STOP# Functionality
The CPU_STOP# signal is an active low input controlling the CPU outputs. This signal can be asserted asynchronously.
CPU_STOP#
CPU
CPU #
SRC
SRC#
3V66
PCIF/PCI
USB/DOT
REF
1
Normal
Normal
Normal
Normal
66MHz
33MHz
48MHz
14.318MHz
0
Iref * 6 or
Float
Low
Normal
Normal
66MHz
33MHz
48MHz
14.318MHz
Note
CPU_STOP# - Assertion (transition from '1' to '0')
Asserting CPU_STOP# pin stops all CPU outputs that are set to be stoppable after their next transition. When the I2C
CPU_STOP tri-state bit corresponding to the CPU output of interest is programmed to a '0', CPU output will stop CPU_True
= HIGH and CPU_Complement = LOW. When the I2C CPU_Stop tri-state bit corresponding to the CPU output of interest is
programmed to a '1', CPU outputs will be tri-stated.
CPU_STOP#
CPU
CPU#
CPU_STOP# - De-assertion (transition from '0' to '1')
With the de-assertion of CPU_Stop# all stopped CPU outputs will resume without a glitch. The maximum latency from the
de-assertion to active outputs is 2 - 6 CPU clock periods. If the control register tristate bit corresponding to the output of
interest is programmed to '1', then the stopped CPU outputs will be driven High within 10nS of CPU_Stop# de-assertion to
a voltage greater than 200mV.
CPU_Stop#
CPU
CPU#
CPU Internal
Tdrive_CPU_Stop, 10nS >200mV
0758—02/08/05
17
Integrated
Circuit
Systems, Inc.
ICS952623
Advance Information
PD#, Power Down
PD# is an asynchronous active low input used to shut off all clocks cleanly prior to clock power.
When PD# is asserted low all clocks will be driven low before turning off the VCO. In PD# de-assertion all clocks will start
without glitches.
PWRDWN#
CPU
CPU #
SRC
SRC#
3V66
PCIF/PCI
USB/DOT
REF
1
Normal
Normal
Normal
Normal
66MHz
33MHz
48MHz
14.318MHz
0
Iref * 2 or
Float
Float
Iref * 2
or Float
Float
Low
Low
Low
Low
Note
Notes:
1. Refer to tristate control of CPU and SRC clocks in section 7.7 for tristate timing and operation.
2. Refer to Control Registers in section 16 for CPU_Stop, SRC_Stop and PwrDwn SMBus tristate control addresses.
PD# Assertion
PD# should be sampled low by 2 consecutive CPU# rising edges before stopping clocks. All single ended clocks will be
held low on their next high to low transition.
All differential clocks will be held high on the next high to low transition of the complimentary clock. If the control register
determining to drive mode is set to 'tri-state', the differential pair will be stopped in tri-state mode, undriven.
When the drive mode but corresponding to the CPU or SRC clock of interest is set to '0' the true clock will be driven high at
2 x Iref and the complementary clock will be tristated. If the control register is programmed to '1' both clocks will be tristated.
PWRDWN#
CPU, 133MHz
CPU#, 133MHz
SRC, 100MHz
SRC#, 100MHz
3V66, 66MHz
USB, 48MHz
PCI, 33MHz
REF, 14.31818
0758—02/08/05
18
Integrated
Circuit
Systems, Inc.
ICS952623
Advance Information
PD# De-assertion
The time from the de-assertion of PD# or until power supply ramps to get stable clocks will be less than 1.8ms. If the drive
mode control bit for PD# tristate is programmed to '1' the stopped differential pair must first be driven high to a minimum of
200mV in less than 300µs of PD# deassertion.
Tstable
<1.8mS
PWRDWN#
CPU, 133MHz
CPU#, 133MHz
SRC, 100MHz
SRC# 100MHz
3V66, 66MHz
USB, 48MHz
PCI, 33MHz
REF, 14.31818
Tdrive_PwrDwn#
<300µS, >200mV
3V66_4/VCH Pin Functionality
The 3V66_4/VCH pin can be configured to be a 66.66MHz modulated output or a non-spread 48MHz output. The default is
3V66 clock. The switching is controlled by Byte 5 Bit 5. If it is set to '1' this pin will output the 48MHz VCH clock. The output
will go low on the falling edge of 3V66 for a minimum of 7.49ns. Then the output will transition to 48MHz on the next rising
edge of DOT_48 clock.
3V66
3V66_4/VCH
DOT_48
7.49nS min
0758—02/08/05
19
Integrated
Circuit
Systems, Inc.
ICS952623
Advance Information
Differential Clock Tristate
To minimize power consumption, CPU[2:0] clock outputs are individually configurable through SMBus to be driven or
tristated during PwrDwn# and CPU_Stop# mode and the SRC clock is configurable to be driven or tristated during
PCI_Stop# and PwrDwn# mode. Each differential clock (SRC, CPU[2:0]) output can be disabled by setting the
corresponding output's register OE bit to "0" (disable). Disabled outputs are to be tristated regardless of "CPU_Stop",
"SRC_Stop" and "PwrDwn" register bit settings.
Signal
Pin PD#
Pin
CPU_Stop#
CPU_Stop
Tristate Bit
Pwrdwn
Tristate Bit
Non-Stoppable
Outputs
Stoppable
Outputs
CPU[2:0}
1
1
X
X
Running
Running
CPU[2:0}
1
0
0
X
Running
Driven @ Iref x 6
CPU[2:0}
1
0
1
X
Running
Tristate
CPU[2:0}
0
X
X
0
Driven @ Iref x 2
Driven @ Iref x 2
CPU[2:0}
0
X
X
1
Tristate
Tristate
Notes:
1. Each output has four corresponding control register bits, OE, PwrDwn, CPU_Stop and "Free Running"
2. Iref x 6 and Iref x 2 is the output current in the corresponding mode
3. See Control Registers section for bit address
Signal
Pin PD#
Pin
PCI_Stop#
PCI_Stop
Tristate Bit
Pwrdwn
Tristate Bit
Non-Stoppable
Output
Stoppable
Output
SRC
1
1
X
X
Running
Running
SR C
1
0
0
X
Running
Driven @ Iref x 6
SRC
1
0
1
X
Running
Tristate
SRC
0
X
X
0
Driven @ Iref x 2
Driven @ Iref x 2
SRC
0
X
X
1
Tristate
Tristate
Notes:
1. SRC output has four corresponding control register bits, OE, PwrDwn, SRC_Stop and "Free Running"
2. Iref x 6 and Iref x 2 is the output current in the corresponding mode
3. See Control Registers section for bit address
0758—02/08/05
20
Integrated
Circuit
Systems, Inc.
ICS952623
Advance Information
CPU Clock Tristate Timing
The following diagrams illustrate CPU clock timing during CPU_Stop# and PwrDwn# modes with CPU_PwrDwn and
CPU_Stop tristate control bits set to driven or tristate in byte 2 of the control register.
CPU_Stop = Driven, CPU_Pwrdwn = Driven
1.8mS
CPU_Stop#
PD#
CPU (Free Running)
CPU# (Free Running)
CPU (Stoppable)
CPU# (Stoppable)
Notes:
1. When both bits (CPU_Stop & CPU_Pwrdown tristate bits) are low, the clock chip will never tristate CPU output clocks
(assuming clock's OE bit is set to "1")
CPU_Stop = Tristate, CPU_Pwrdwn = Driven
1.8mS
CPU_Stop#
PD#
CPU (Free Running)
CPU# (Free Running)
CPU (Stoppable)
CPU# (Stoppable)
Notes:
1. Tristate outputs are pulled low by output termination resistors as shown here.
0758—02/08/05
21
Integrated
Circuit
Systems, Inc.
ICS952623
Advance Information
CPU_Stop = Driven, CPU_Pwrdwn = Tristate
1.8mS
CPU_Stop#
PWRDWN#
CPU (Free Running)
CPU# (Free Running)
CPU (Stoppable)
CPU# (Stoppable)
Notes:
1. When CPU_Pwrdwn is set to tristate and CPU_Stop is set to driven, the clock chip will tristate outputs only during the
assertion of PWRDWN#. Differential clock behavior during the assertion/de-assertion of CPU_Stop# will be unaffected.
2. In the case that CPU_Stop# is de-asserted during the 1.8mS PWRDWN# de-assertion resume delay, the clock chip can
sample the CPU_Stop# high with the internal rising edges of clock#. This will result in CPU clocks resuming immediately
after the 1.8mS windows expires. This applies to all control register bit changes as well.
3. Tristate outputs are pulled low by output termination resistors as shown here.
CPU_Stop = Tristate, CPU_Pwrdwn = Tristate
1.8mS
CPU_Stop#
PWRDWN#
CPU (Free Running)
CPU# (Free Running)
CPU (Stoppable)
CPU# (Stoppable)
Notes:
1. When CPU_Stop and CPU_Pwrdwn bits are set to tristate, the clock chip will tristate the outputs during the assertion of
CPU_Stop# and PWRDWN#.
2. Tristate outputs are pulled low by output termination resistors as shown here.
0758—02/08/05
22
Integrated
Circuit
Systems, Inc.
ICS952623
Advance Information
SRC Clock Tristate Timing
The following diagrams illustrate SRC clock timing during PCI_Stop# and PwrDwn# modes with SRC_Pwrdwn and
SRC_Stop tristate control bits set to driven or tristate in byte 2 of the control register.
SRC_Stop = Driven, SRC_Pwrdwn = Driven
1.8mS
PCI_Stop#
PCI (Free Running)
PWRDWN#
CPU (Free Running)
CPU# (Free Running)
SRC (Stoppable)
SRC# (Stoppable)
1 PCI
clock max
Notes:
1. When both bits (SRC_Stop & SRC_Pwrdown tristate bits) are set to driven, the clock chip will never tristate the SRC output
clock (assuming clock's OE bit is set to "1")
SRC_Stop = Tristate, Pwrdwn = Tristate
1.8mS
PCI_Stop#
PCI (Free Running)
PWRDWN#
CPU (Free Running)
CPU# (Free Running)
SRC (Stoppable)
SRC# (Stoppable)
1 PCI
clock max
Notes:
1. When SRC_Stop and SRC_Pwrdwn bits are set to tristate, the clock chip will tristate outputs during the assertion of
PCI_Stop# and PWRDWN#.
2. Tristate outputs are pulled low by output termination resistors as shown here.
0758—02/08/05
23
Integrated
Circuit
Systems, Inc.
ICS952623
Advance Information
PCI_STOP Asserted
SRC_Stop = Tristate, SRC_Pwrdwn = Tristate
1.8mS
PCI_Stop#
PCI (Free Running)
PWRDWN#
CPU (Free Running)
CPU# (Free Running)
SRC (Stoppable)
SRC# (Stoppable)
Notes:
1. When SRC_Pwrdwn and SRC_Stop are set to tristate, the clock chip will tristate outputs during the assertion of PCI_Stop#
and PWRDWN#.
2. In the case that PCI_Stop# is de-asserted during the 1.8mS PWRDWN# de-assertion resume delay, the clock chip can
sample the PCI_Stop# high with the internal rising edges of CPU clock#. This will result in SRC clocks resuming
immediately after the 1.8mS window expires. This applies to all control register bit changes as well.
3. Tristate outputs are pulled low by output termination resistors as shown here.
0758—02/08/05
24
Integrated
Circuit
Systems, Inc.
ICS952623
Advance Information
Shared Pin Operation Input/Output Pins
Figure 1 shows a means of implementing this function
when a switch or 2 pin header is used. With no jumper is
installed the pin will be pulled high. With the jumper in
place the pin will be pulled low. If programmability is not
necessary, than only a single resistor is necessary. The
programming resistors should be located close to the series
termination resistor to minimize the current loop area. It is
more important to locate the series termination resistor
close to the driver than the programming resistor.
The I/O pins designated by (input/output) serve as dual
signal functions to the device. During initial power-up, they
act as input pins. The logic level (voltage) that is present on
these pins at this time is read and stored into a 5-bit internal
data latch. At the end of Power-On reset, (see AC
characteristics for timing values), the device changes the
mode of operations for these pins to an output function. In
this mode the pins produce the specified buffered clocks to
external loads.
To program (load) the internal configuration register for these
pins, a resistor is connected to either the VDD (logic 1) power
supply or the GND (logic 0) voltage potential. A 10 Kilohm (10K)
resistor is used to provide both the solid CMOS programming
voltage needed during the power-up programming period and to
provide an insignificant load on the output clock during the
subsequent operating period.
Via to
VDD
Programming
Header
2K W
Via to Gnd
Device
Pad
8.2K W
Clock trace to load
Series Term. Res.
Fig. 1
0758—02/08/05
25
Integrated
Circuit
Systems, Inc.
ICS952623
Advance Information
300 mil SSOP
c
N
SYMBOL
A
A1
b
c
D
E
E1
e
h
L
N
a
L
E1
E
INDEX
AREA
1 2
α
h x 45°
D
In Millimeters
COMMON DIMENSIONS
MIN
MAX
2.41
2.80
0.20
0.40
0.20
0.34
0.13
0.25
SEE VARIATIONS
10.03
10.68
7.40
7.60
0.635 BASIC
0.38
0.64
0.50
1.02
SEE VARIATIONS
0°
8°
In Inches
COMMON DIMENSIONS
MIN
MAX
.095
.110
.008
.016
.008
.0135
.005
.010
SEE VARIATIONS
.395
.420
.291
.299
0.025 BASIC
.015
.025
.020
.040
SEE VARIATIONS
0°
8°
VARIATIONS
N
A
56
D (inch)
MAX
18.55
Reference Doc.: JEDEC Publication 95, MO-118
A1
-Ce
D mm.
MIN
18.31
10-0034
SEATING
PLANE
b
.10 (.004) C
Ordering Information
ICS952623yFT
Example:
ICS XXXXXX y F - T
Designation for tape and reel packaging
Package Type
F = SSOP
Revis ion Designator (will not correlate with datasheet revision)
Device Type
Prefix
ICS = Standard Device
0758—02/08/05
26
MIN
.720
MAX
.730
Integrated
Circuit
Systems, Inc.
ICS952623
Advance Information
c
N
56-Lead 6.10 mm. Body, 0.50 mm. Pitch TSSOP
(240 mil)
(20 mil)
In Millimeters
In Inches
SYMBOL COMMON DIMENSIONS COMMON DIMENSIONS
MIN
MAX
MIN
MAX
A
-1.20
-.047
A1
0.05
0.15
.002
.006
A2
0.80
1.05
.032
.041
b
0.17
0.27
.007
.011
c
0.09
0.20
.0035
.008
D
SEE VARIATIONS
SEE VARIATIONS
E
8.10 BASIC
0.319 BASIC
E1
6.00
6.20
.236
.244
e
0.50 BASIC
0.020 BASIC
L
0.45
0.75
.018
.030
N
SEE VARIATIONS
SEE VARIATIONS
a
0°
8°
0°
8°
aaa
-0.10
-.004
L
E1
INDEX
AREA
E
1 2
a
D
A
A2
VARIATIONS
A1
N
-Ce
56
SEATING
PLANE
b
D mm.
MIN
MAX
13.90
14.10
Reference Doc.: JEDEC Publication 95, M O-153
10-0039
aaa C
Ordering Information
ICS952623yGT
Example:
ICS XXXXXX y G - T
Designation for tape and reel packaging
Package Type
G = TSSOP
Revis ion Designator (will not correlate with datasheet revision)
Device Type
Prefix
ICS = Standard Device
0758—02/08/05
27
D (inch)
MIN
.547
MAX
.555