ICS91305I Integrated Circuit Systems, Inc. High Performance Communication Buffer General Description Features The ICS91305I is a high performance, low skew, low jitter clock driver. It uses a phase lock loop (PLL) technology to align, in both phase and frequency, the REF input with the CLKOUT signal. It is designed to distribute high speed clocks in communication systems operating at speeds from 10 to 133 MHz. • • • • ICS91305I is a zero delay buffer that provides synchronization between the input and output. The synchronization is established via CLKOUT feed back to the input of the PLL. Since the skew between the input and output is less than +/- 350 pS, the part acts as a zero delay buffer. • • • • • • Zero input - output delay Frequency range 10 - 133 MHz (3.3V) 5V tolerant input REF High loop filter bandwidth ideal for Spread Spectrum applications. Less than 200 ps Jitter between outputs Skew controlled outputs Skew less than 250 ps between outputs Available in 8 pin 150 mil SOIC & 173 mil TSSOP packages 3.3V ±10% operation Supports industrial temperature range -40°C to 85°C The ICS91305I comes in an eight pin 150 mil SOIC package. It has five output clocks. In the absence of REF input, will be in the power down mode. In this mode, the PLL is turned off and the output buffers are pulled low. Power down mode provides the lowest power consumption for a standby condition. REF 1 CLK2 2 CLK1 3 GND 4 ICS91305I Pin Configuration Block Diagram 8 CLKOUT 7 CLK4 6 VDD 5 CLK3 8 pin SOIC & TSSOP 0691F—06/03/05 ICS91305I Pin Descriptions PIN NUMBER 1 2 PIN NAME 2 REF TYPE IN DESCRIPTION Input reference frequency, 5V tolerant input. 3 OUT Buffered clock output 3 OUT Buffered clock output PWR Ground CLK2 3 CLK1 4 GND 3 5 CLK3 OUT Buffered clock output 6 VDD PWR Power Supply (3.3V) 3 7 CLK4 OUT Buffered clock output 8 CLKOUT3 OUT Buffered clock output. Internal feedback on this pin Notes: 1. Guaranteed by design and characterization. Not subject to 100% test. 2. Weak pull-down 3. Weak pull-down on all outputs 0691F—06/03/05 2 ICS91305I Absolute Maximum Ratings Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . 7.0 V Logic Inputs (Except REF) . . . . . . . . . . . . . . GND –0.5 V to VDD + 0.5 V Logic Input REF . . . . . . . . . . . . . . . . . . . . . . GND –0.5 V to GND + 5.5 V Ambient Operating Temperature . . . . . . . . . . -40°C to +85°C Storage Temperature . . . . . . . . . . . . . . . . . . . –65°C to +150°C Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only and functional operation of the device at these or any other conditions above those listed in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. Electrical Characteristics at 3.3V VDD = 3.0 – 3.6 V, TA = -40°C to +85°C unless otherwise stated DC Characteristics PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS 0.8 V Input Low Voltage VIL Input High Voltage VIH Input Low Current IIL VIN=0V 19 100.0 µA Input High Current IIH VIN=VDD 0.10 250.0 µA IOL = 12mA 0.25 0.4 V 2.0 V Output Low Voltage1 VOL Output High Voltage1 VOH Power Down Supply Current IDD REF = 0 MHz 0.3 100.0 µA Supply Current IDD Unloaded oututs at 66.66 MHz SEL inputs at VDD or GND 30.0 80.0 mA IOH = -12mA 2.4 2.9 V Notes: 1. Guaranteed by design and characterization. Not subject to 100% test. 2. All Skew specifications are mesured with a 50Ω transmission line, load teminated with 50Ω to 1.4V. 3. Duty cycle measured at 1.4V. 4. Skew measured at 1.4V on rising edges. Loading must be equal on outputs. 0691F—06/03/05 3 ICS91305I Switching Characteristics PARAMETER SYMBOL CONDITION MIN TYP MAX UNITS Output period t1 With CL=30pF 100.00 (10) 7.5 (133) ns (MHz) Input period t1 With CL=30pF 100.00 (10) 7.5 (133) ns (MHz) Duty Cycle1 Dt1 Measured at 1.4V; CL=30pF Duty Cycle1 Dt2 Measured at VDD/2 Fout <66.6MHz Rise Time1 tr1 Fall Time1 40.0 50 60 % 45 50 55 % Measured between 0.8V and 2.0V: CL=30pF 1.2 1.5 ns tf1 Measured between 2.0V and 0.8V; CL=30pF 1.2 1.5 ns Delay, REF Rising Edge to CLKOUT Rising Edge1, 2 Dr1 Measured at 1.4V 0 ±350 ps Output to Output Skew1 Tskew All outputs equally loaded, CL=20pF 250 ps Device to Device Skew1 Tdsk-Tdsk Measured at VDD/2 on the CLKOUT pins of devices 700 ps Cycle to Cycle Jitter1 Tcyc-Tcyc Measured at 66.66 MHz, loaded outputs 200 ps PLL Lock Time1 tLOCK Stable power supply, valid clock presented on REF pin 1.0 ms Jitter; Absolute Jitter1 Tjabs @ 10,000 cycles CL = 30pF 70 200 ps Jitter; 1 - Sigma1 Tj1s @ 10,000 cycles CL = 30pF 14 60 ps 0 -200 Notes: 1. Guaranteed by design and characterization. Not subject to 100% test. 2. REF input has a threshold voltage of 1.4V 3. All parameters expected with loaded outputs 0691F—06/03/05 4 ICS91305I Output to Output Skew The skew between CLKOUT and the CLK(1-4) outputs is not dynamically adjusted by the PLL. Since CLKOUT is one of the inputs to the PLL, zero phase difference is maintained from REF to CLKOUT. If all outputs are equally loaded, zero phase difference will maintained from REF to all outputs. If applications requiring zero output-output skew, all the outputs must equally loaded. If the CLK(1-4) outputs are less loaded than CLKOUT, CLK(1-4) outputs will lead it; and if the CLK(1-4) is more loaded than CLKOUT, CLK(1-4) will lag the CLKOUT. Since the CLKOUT and the CLK(1-4) outputs are identical, they all start at the same time, but different loads cause them to have different rise times and different times crossing the measurement thresholds. REF input and all outputs loaded Equally REF input and CLK(1-4) outputs loaded equally, with CLKOUT loaded More. REF input and CLK(1_4) outputs loaded equally, with CLKOUT loaded Less. Timing diagrams with different loading configurations 0691F—06/03/05 5 ICS91305I SYMBOL C N L INDE X ARE A H E In Millimeters In Inches COMMON DIMENSIONS COMMON DIMENSIONS MIN MAX MIN MAX A 1.35 1.75 .0532 .0688 A1 0.10 0.25 .0040 .0098 B 0.33 0.51 .013 .020 C 0.19 0.25 SEE VARIATIONS .0075 .0098 SEE VARIATIONS e 3.80 4.0 1.27 BASIC .1497 .1574 0.050 BASIC H 5.80 6.20 .2284 .2440 h 0.25 0.50 .010 .020 L 0.40 1.27 SEE VARIATIONS D E h x 45° 1 2 N α D A α 8° 0° 8° MIN MAX MIN MAX 4.80 5.00 .1890 .1968 VARIATIONS A1 N e 0° .016 .050 SEE VARIATIONS SEATING PLANE B 8 D mm. D (inch) .10 (.004) 150 mil (Narrow Body) SOIC Ordering Information ICS91305yMILF-T Example: ICS XXXX y M LF- T Designation for tape and reel packaging RoHS Compliant (Optional) Package Type M = SOIC Revision Designator (will not correlate with datasheet revision) Device Type Prefix ICS = Standard Device 0691F—06/03/05 6 ICS91305I 4.40 m m . Body, 0.65 m m . Pitch TSSOP c N (173 m il) L E1 SYMBOL A A1 A2 b c D E E1 e L N α aaa E INDEX AREA 1 2 α D A A2 (25.6 m il) In Millimeters COMMON DIMENSIONS MIN MAX -1.20 0.05 0.15 0.80 1.05 0.19 0.30 0.09 0.20 SEE VARIATIONS 6.40 BASIC 4.30 4.50 0.65 BASIC 0.45 0.75 SEE VARIATIONS 0° 8° -0.10 In Inches COMMON DIMENSIONS MIN MAX -.047 .002 .006 .032 .041 .007 .012 .0035 .008 SEE VARIATIONS 0.252 BASIC .169 .177 0.0256 BASIC .018 .030 SEE VARIATIONS 0° 8° -.004 VARIATIONS N A1 8 -Ce SEATING PLANE b aaa C D mm. MIN 2.90 D (inch) MAX 3.10 Reference Doc.: JEDEC Publication 95, MO-153 10-0035 Ordering Information ICS91305yGILF-T Example: ICS XXXX y G LF- T Designation for tape and reel packaging RoHS Compliant (Optional) Package Type G = TSSOP Revision Designator (will not correlate with datasheet revision) Device Type Prefix ICS = Standard Device 0691F—06/03/05 7 MIN .114 MAX .122 ICS91305I Revision History Rev. F Issue Date Description 6/3/2005 Page # 1. Resized Electrical Characteristics Table. 2. Updated LF Ordering Information from "Lead Free" to "RoHS Compliant". 0691F—06/03/05 8 3,6,7