MK1725 Quad Output Spread Spectrum Clock Generator Description Features The MK1725 generates 4 high-quality, high-frequency spread spectrum clock outputs. It is designed to replace spread spectrum clock generators and a buffer in many digital consumer applications. Using ICS’ patented Phase Locked Loop (PLL) techniques, the device runs from a lower frequency clock or crystal input. • Packaged in 16-pin TSSOP • Available in Pb (lead) free package • Replaces a spread spectrum clock generator and a • • • • • • The MK1725 has a 16 location ROM table which provides maximum flexibility for system designers. The chip also has a power down pin which can be used to reduce power. buffer Input clock or crystal frequency of 20-34 MHz Output frequency of 20-136 MHz Four spread spectrum clock outputs Duty cycle of 45/55 Operating voltage of 3.3 V Advanced, low power CMOS process Block Diagram VDD 3 4 S3:0 PLL/Clock Synthesis and Spread Spectrum Circuitry X1/ICLK 20-34 MHz crystal or clock Crystal Oscillator 4 CLK1:4 X2 Optional crystal capacitors. GND 3 PDTS 1 MDS 1725 C Integrated Circuit Systems ● 525 Ra ce St ree t, Sa n Jose, CA 9 5126 Revision 021605 ● tel (40 8) 297-1 201 ● w w w. i c s t. c o m MK1725 Quad Output Spread Spectrum Clock Generator Pin Assignment CLK Output Selection Table S3 S2 S1 S0 CLK1:4 X1 1 16 X2 S0 S3 2 3 15 14 VDD PDTS 0 0 0 0 1 -1% 0 0 1 0 1 -0.5% VDD GND S1 4 5 13 12 S2 VDD 0 0 0 1 1 +/- 0.5% 0 0 1 1 1 +/- 0.25% 6 11 GND 0 1 1 0 2 -1% CLK4 CLK3 0 1 0 1 2 -0.5% 0 1 0 0 2 +/- 0.5% 0 1 1 1 2 +/- 0.25% 1 0 0 0 4 -1% 1 0 1 0 4 -0.5% 1 0 0 1 4 +/- 0.5% 1 0 1 1 4 +/- 0.25% 1 1 1 0 1 OFF 1 1 0 1 2 OFF 1 1 0 0 4 OFF 1 1 1 1 TEST TEST CLK1 7 8 CLK2 10 9 Multiplier 16 pin (173 mil) TSSOP Spread % Pin Descriptions Pin Number Pin Name Pin Type 1 X1 Input Connect to a 20 - 34 MHz crystal or clock input. 2 S0 Input Select pin 0. Determines frequency and spread amount on output clocks as per table above. Internal pull-down. 3 S3 Input Select pin 3. Determines frequency and spread amount on output clocks as per table above. Internal pull-down. 4 VDD Power Connect to +3.3V. 5 GND Power Connect to ground. 6 S1 Input Select pin 1. Determines frequency and spread amount on output clocks as per table above. Internal pull-down. 7 CLK1 Output Clock 1 output. Frequency and spread amount are determined by table above. Weak internal pull-down when tri-state. 8 CLK2 Output Clock 2 output. Frequency and spread amount are determined by table above. Weak internal pull-down when tri-state. 9 CLK3 Output Clock 3 output. Frequency and spread amount are determined by table above. Weak internal pull-down when tri-state. 2 MDS 1725 C In te grated Circu it Systems Pin Description ● 52 5 Race Stre et, San Jose, CA 951 26 Revision 021605 ● te l (4 08) 29 7-120 1 ● w w w. i c s t . c o m MK1725 Quad Output Spread Spectrum Clock Generator Pin Number Pin Name Pin Type 10 CLK4 Output Clock 4 output. Frequency and spread amount are determined by table above. Weak internal pull-down when tri-state. 11 GND Power Connect to ground. 12 VDD Power Connect to +3.3V. 13 S2 Input Select pin 2. Determines frequency and spread amount on output clocks as per table above. Internal pull-down. PDTS Input Power Down Tri-state. Powers down entire chip and tri-states outputs when low. Internal pull-up resistor. 15 VDD Power Connect to +3.3V. 16 X2 Input 20MHz-34MHz crystal input. Float for clock input. 14 Pin Description External Components Decoupling Capacitor As with any high performance mixed-signal IC, the MK1725 must be isolated from system power supply noise to perform optimally. capacitance, each crystal capacitor would be 24 pF [(18-6) x 2] = 24. PCB Layout Recommendations A decoupling capacitor of 0.01µF must be connected between each VDD and the PCB ground plane. For optimum device performance and lowest output phase noise, the following guidelines should be observed. Series Termination Resistor 1) The 0.01µF decoupling capacitors should be mounted on the component side of the board as close to the VDD pin as possible. No vias should be used between the decoupling capacitors and VDD pins. The PCB trace to VDD pins should be kept as short as possible, as should the PCB trace to the ground via. Clock output traces over one inch should use series termination. To series terminate a 50Ω trace (a commonly used trace impedance), place a 33Ω resistor in series with the clock line, as close to the clock output pin as possible. The nominal impedance of the clock output is 20Ω. Crystal Load Capacitors The device crystal connections should include pads for small capacitors from X1 to ground and from X2 to ground. These capacitors are used to adjust the stray capacitance of the board to match the nominally required crystal load capacitance. Because load capacitance can only be increased in this trimming process, it is important to keep stray capacitance to a minimum by using very short PCB traces (and no vias) been the crystal and device. Crystal capacitors must be connected from each of the pins X1 and X2 to ground. The value (in pF) of these crystal caps should equal (CL -6)*2. In this equation, CL= crystal load capacitance in pF. Example: For a crystal with an 18 pF load 3) To minimize EMI the 33Ω series termination resistor (if needed) should be placed close to the clock outputs. 4) An optimum layout is one with all components on the same side of the board, minimizing vias through other signal layers. Other signal traces should be routed away from the MK1725. This includes signal traces just underneath the device, or on layers adjacent to the ground plane layer used by the device. 3 MDS 1725 C In te grated Circu it Systems 2) The external crystal should be mounted just next to the device with short traces. The X1 and X2 traces should not be routed next to each other with minimum spaces, instead they should be separated and away from other traces. ● 52 5 Race Stre et, San Jose, CA 951 26 Revision 021605 ● te l (4 08) 29 7-120 1 ● w w w. i c s t . c o m MK1725 Quad Output Spread Spectrum Clock Generator Absolute Maximum Ratings Stresses above the ratings listed below can cause permanent damage to the MK1725. These ratings, which are standard values for ICS commercially rated parts, are stress ratings only. Functional operation of the device at these or any other conditions above those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods can affect product reliability. Electrical parameters are guaranteed only over the recommended operating temperature range. Item Rating Supply Voltage, VDD 5V All Inputs and Outputs -0.5 V to VDD+0.5 V Ambient Operating Temperature 0 to +70°C Storage Temperature -65 to +150°C Junction Temperature 125°C Soldering Temperature 260°C Recommended Operation Conditions Parameter Min. Ambient Operating Temperature Typ. Max. Units +70 °C +3.465 V 0 Power Supply Voltage (measured in respect to GND) +3.135 +3.3 DC Electrical Characteristics Unless stated otherwise, VDD = 3.3 V ±5%, Ambient Temperature 0 to +70°C Parameter Symbol Conditions Min. Typ. Max. Units 3.135 3.3 3.465 V Operating Voltage VDD Supply Current IDD 20M in S3:0=[0100] Input High Voltage VIH Input selects Input Low Voltage VIL Input selects Input High Voltage VIH ICLK Input Low Voltage VIL ICLK Output High Voltage VOH IOH = -4 mA VDD-0.4 V Output High Voltage VOH IOH = -12 mA 2.4 V Output Low Voltage VOL IOL = 12 mA Short Circuit Current IOS Clock outputs Input Capacitance 22 mA 2 V 0.8 VDD/2+1 V V VDD/2-1 0.4 V V ±70 mA CIN 5 pF Nominal Output Impedance ZOUT 20 Ω Internal Pull-up Resistor RPU PDTS pin 360 kΩ Internal Pull-down Resistor RPD Clock outputs; S3:0 510 kΩ 4 MDS 1725 C In te grated Circu it Systems ● 52 5 Race Stre et, San Jose, CA 951 26 Revision 021605 ● te l (4 08) 29 7-120 1 ● w w w. i c s t . c o m MK1725 Quad Output Spread Spectrum Clock Generator AC Electrical Characteristics Unless stated otherwise, VDD = 3.0 V ±5%, Ambient Temperature 0 to +70°C Parameter Symbol Conditions Min. Typ. Max. Units Input Frequency fIN Crystal or clock input Output Rise Time tOR 20% to 80%, Note 1 1.2 ns Output Fall Time tOF 80% to 20%, Note 1 1.0 ns Output Clock Duty Cycle Absolute Clock Period Jitter Modulation Frequency tJ 20 34 At VDD/2, Note 1 1X, 2X modes 45 50 55 % at VDD/2, Note 1 4X mode 40 50 60 % Cycle to cycle, Note 1 150 ps 25 fmod Output to Output Skew MHz Non-spread modes 50 kHz 250 ps Output Enable Time tOE PDTS high to output spread profile stable 2.6 ms Output Disable Time tOD PDTS low to tri-state 10 ns Note 1: Measured with a 15 pF load. Thermal Characteristics Parameter Symbol Thermal Resistance Junction to Ambient Thermal Resistance Junction to Case Conditions Min. Typ. Max. Units θJA Still air 78 °C/W θJA 1 m/s air flow 70 °C/W θJA 3 m/s air flow 68 °C/W 37 °C/W θJC Marking Diagram 16 9 MK1725GL ###### YYWW 1 8 Notes: 1. ###### is the lot code. 2. YYWW is the last two digits of the year and the week number that the part was assembled. 3. “L” denotes Pb (lead) free package. 4. Bottom marking: (origin). Origin = country of origin of not USA. 5 MDS 1725 C In te grated Circu it Systems ● 52 5 Race Stre et, San Jose, CA 951 26 Revision 021605 ● te l (4 08) 29 7-120 1 ● w w w. i c s t . c o m MK1725 Quad Output Spread Spectrum Clock Generator Package Outline and Package Dimensions (16 pin TSSOP, 173 Mil. Narrow Body) Package dimensions are kept current with JEDEC Publication No. 95 Millimeters 16 Symbol E1 E IN D EX AR EA 1 2 D A 2 Min A A1 A2 b C D E E1 e L α aaa Inches Max -1.20 0.05 0.15 0.80 1.05 0.19 0.30 0.09 0.20 4.90 5.1 6.40 BASIC 4.30 4.50 0.65 Basic 0.45 0.75 0° 8° -0.10 Min Max -0.047 0.002 0.006 0.032 0.041 0.007 0.012 0.0035 0.008 0.193 0.201 0.252 BASIC 0.169 0.177 0.0256 Basic 0.018 0.030 0° 8° -0.004 A A 1 c -C e S E A T IN G P LA N E b L aaa C Ordering Information Part / Order Number Marking Shipping Packaging Package Temperature MK1725GLF MK1725GLFT see page 5 Tubes Tape and Reel 16-pin TSSOP 16-pin TSSOP 0 to +70 °C 0 to +70 °C While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems (ICS) assumes no responsibility for either its use or for the infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in life support devices or critical medical instruments. 6 MDS 1725 C In te grated Circu it Systems ● 52 5 Race Stre et, San Jose, CA 951 26 Revision 021605 ● te l (4 08) 29 7-120 1 ● w w w. i c s t . c o m