Integrated Circuit Systems, Inc. MK9173-01 MK9173-15 Video Genlock PLL General Description Features The MK9173-01 and MK9173-15 provide the analog PLL circuit blocks to implement a frequency multiplier. Because the device is configured to use an external divider in the PLL clock feedback path, a large divider can be used to result in a large frequency multiplication ratio. This is useful when using a low frequency input clock to generate a high frequency output clock. The MK9173-01/15 contains a phase detector, charge pump, loop filter, and voltage-controlled oscillator (VCO). The ICS674-01 can be used as the external feedback divider. • • • • A common application of the MK9173-01/-15 is the implementation of a video genlock circuit. Because of this, the MK9173-01/-15 inputs operate on the negative-going clock edge. • • • • • Designed to replace the AV9173 in most applications Phase-detector/VCO circuit block Ideal for genlock system Reference clock range 12 kHz to 1 M Hz for full output clock range Output clock range 1.25 to 75 M Hz (-01), 0.625 to 37.5 MHz (-15), see Table 1 for conditions On-chip loop filter Single 5 volt power supply Low power CMOS technology Small 8-pin SOIC package The MK9173-01/15 is pin and function compatible to the AV9173-01/15. Please refer to page 4 regarding performance differences. For new video genlock designs, please refer to the ICS673-01, ICS1522 or ICS1523. Block Diagram Integrated Circuit Systems, Incorporated • 525 Race Street • San Jose • CA • 95126 • (408) 295-9800tel • www.icst.com MDS 9173-01/15 B 121400 MK9173-01 MK9173-15 Pin Configuration Pin Descriptions PIN NUMBER 1 2 3 4 5 6 7 8 PIN NAME FBIN IN GND FS0 OE CLK1 VDD CLK2 TYPE Input Input — Input Input Output — Output DESCRIPTION Feedback Input Input for reference sync pulse Ground Frequency Select 0 input Output Enable Clock Output 1 Power Supply (+5V) Clock Output 2 (Divided-by-2 from Clock 1) Table 1: Allowable Input Frequency to Output Frequency (Outputs in MHz)MK9173-01 (MK9173-15 outputs run at exactly 1/2 the MK9173-01 frequencies) fIN (kHz) 12 ≤ fIN ≤ 14 kHz 14 < fIN ≤ 17 kHz 17 < fIN ≤ 30 kHz 30 < fIN ≤ 35 kHz 35 < fIN ≤ 1000 kHz fOUT for FS = 0 (MHz) CLK1 Output CLK2 Output 44.0 to 75 22.0 to 37.5 30.0 to 75 15.0 to 37.5 25.0 to 75 12.5 to 37.5 15.0 to 75 7.5 to 37.5 10.0 to 75 5.0 to 37.5 fOUT for FS = 1 (MHz) CLK1 Output CLK2 Output 11.0 to 18.75 5.5 to 9.375 7.5 to 18.75 3.75 to 9.375 6.25 to 18.75 3.125 to 9.375 3.75 to 18.75 1.875 to 9.375 2.5 to 18.75 1.25 to 9.375 Integrated Circuit Systems, Incorporated • 525 Race Street •San Jose • CA• 95126 • (408) 295-9800 tel • www.icst.com 2 MK9173-01 MK9173-15 Using the MK9173-01/15 in Genlock Applications Most video sources, such as video cameras, are asynchronous, free-running devices. To digitize video or synchronize one video source to another free-running reference video source, a video “genlock” (generator lock) circuit is required. The MK9173-01 and MK9173-15 integrate the analog blocks which make the task much easier. In the complete video genlock circuit, the primary function of the MK9173-01 and MK9173-15 is to provide the analog circuitry required to generate the video dot clock within a PLL. This application is illustrated in Figure 1. The input reference signal for this circuit is the horizontal synchronization (H-SYNC) signal. If a composite video reference source is being used, the h-sync pulses must be separated from the composite signal. A video sync separator circuit, such as the National Semiconductor LM1881, can be used for this purpose. The clock feedback divider shown in Figure 1 is a digital divider used within the PLL to multiply the reference frequency. Its divide ratio establishes how many video dot clock cycles occur per h-sync pulse. For example, if 880 pixel clocks are desired per h-sync pulse, then the divider ratio is set to 880. Hence, together the h-sync frequency and external divider ratio establish the dot clock frequency: fO U T = fI N • N where N is external divide ratio Both input pins IN and FBIN respond only to negative-going clock edges of the input signal. The H-SYNC signal must be constant frequency in the 12 kHz to 1M Hz range and stable (low clock jitter) for creation of a stable output clock. AC specifications (VCO frequency), an input as low as 12kHz (such as NTSC or PAL H-SYNC) can be used. The output hook-ups of the MK9173-01 and MK9173-15 are dictated by the desired dot clock frequency. The primary consideration is the internal VCO which operates over a frequency range of 10 MHz to 75 MHz. Because of the selectable VCO output divider and the additional divider on output CLK2, four distinct output frequency ranges can be achieved. The following Table lists these ranges and the corresponding device configuration. FS0 State 0 0 1 1 CLK1 FrequencyRange MK9173-01 10-75MHz FrequencyRange MK9173-15 5-37.5MHz CLK2 5-37.5MHz 2.5 - 18.75 MHz CLK1 2.5-18.75MHz 1.25 - 9.375 MHz CLK2 1.25 - 9.375 MHz 0.625-4.6875 MHz OutputUsed Note that both outputs, CLK1 and CLK2, are available during operation even though only one is fed back via the external clock divider. Pin 5, OE, tristates both CLK1 and CLK2 upon logic low input. This feature can be used to revert dot clock control to the system clock when not in genlock mode (hence, when in genlock mode the system dot clock must be tristated). When unused, inputs FS0 and OE must be tied to either GND (logic low) or VDD (logic high). Refer to Application Brief (AB01) for additional details on use of input frequencies below 25kHz. By following the guidelines in this brief and meeting the test conditions in the For further discussion of VCO/PLL operation as it applies to the MK9173-01 and MK9173-15, please refer to the AV9170 application note. The AV9170 is a similar device with fixed feedback dividers for skew control applications. Figure 1: Typical Application of MK9173-01/-15 in a Video Genlock System Integrated Circuit Systems, Incorporated• 525 Race Street • San Jose •CA • 95126 • (408) 295-9800tel • www.icst.com 3 MK9173-01 MK9173-15 Using the MK9173-01/15 to replace the AV9173-01/15 Increasing leadtimes from our wafer fab on the AV917x family of products led us to introduce the MK917x family. The MK917x have been designed for a 0.6 micron CMOS process, whereas the AV917x devices are on a 1.2 micron process. There are characteristic differences between the old and new products which may lead to problems in the application. The most commonly reported problem is increased jitter. 2. Due to differences in behavior between the AV and MK parts, the MK parts may not be a viable substitute in some applications. Accordingly, ICS is working to establish a new source of supply for the AV part. 3. Keep in mind the following advice for PLLs, which might help you troubleshoot problems in migrating to the MK917x family: Design Considerations a) Don't open the external clock feedback path. In doing so, the MK917x will start to run as its maximum frequency, which might be faster than the logic in your feedback path is able to handle. The primary difference between old (AV) and new (MK) products is that the MK series is built on a faster process. To compensate for this process difference, we recommend the following design considerations. b) Fast transitions on the input pins reduce jitter. Remove any filters or unneeded loads on the inputs. 1. Because the MK series is faster, good power supply decoupling is more important. A board layout which works well with the AV parts may require better decoupling to work with the MK parts. The recommended decoupling is 0.01 uF mounted as close as possible (within 0.2") to the VDD pin (if a larger value device is in place, such as a 0.1 uF, try replacing this with a 0.01 uF device). To determine if improved decoupling would help performance, connect a disc capacitor directly across the VDD and ground pins. Trim the leads as short as possible. c) Terminate the clock output lines properly. Try adding a 33 ohm series termination resistor. For new video genlock applications, please consider the ICS673-01, ICS1522, or ICS1523. Integrated Circuit Systems, Incorporated • 525 Race Street •San Jose • CA• 95126 • (408) 295-9800 tel • www.icst.com 4 MK9173-01 MK9173-15 Absolute Maximum Ratings VDD (referenced to GND) . . . . . . . . . . . . . . 7.0 V Operating Temperature under Bias . . . . . . . . 0°C to +70°C Storage Temperature . . . . . . . . . . . . . . . . . . – 65°C to +150°C Voltage on I/O pins referenced to GND . . . . . GND – 0.5V to VDD + 0.5V Power Dissipation . . . . . . . . . . . . . . . . . . . . 0.5 watts Stresses above those listed under Absolute Maximum Ratings above may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those listed in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. Electrical Characteristic VDD = +5V ±5%, TA = 0°C to 70°C, unless otherwise stated DC CHARACTERISTICS PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS Input Low Voltage Input High Voltage Input Low Current Input High Current Output Low Voltage1 Output High Voltage 1 VIL VIH IIL IIH VOL VOH1 — 2.0 -5 -5 — VDD -0.4V — — — — — — 0.8 — — 5 0.4 — V V µA µA V V Output High Voltage 1 VOH2 VDD -0.8V — — V Output High Voltage 1 Supply Current VOH3 IDD VDD = 5V VDD = 5V VIN = 0V VIN = VDD IOL = 8mA IOH = -1mA, VDD = 5.0V IOH = -4mA, VDD = 5.0V IOH = -8mA Unloaded, 50 MHZ 2.4 — — 20 — 50 V mA Notes: 1. Duty cycle measured at 1.4V. 2. Input Reference Frequency = 25 kHz, Output Frequency = 25 MHz. Jitter measured between adjacent vertical pixels. 3. CLK1 frequency applies for FS = 0. For FS = 1 condition, divide allowable CLK1 range by the factor of 4. Integrated Circuit Systems, Incorporated• 525 Race Street • San Jose •CA • 95126 • (408) 295-9800tel • www.icst.com 5 MK9173-01 MK9173-15 Electrical Characteristics VDD = +5V ±5%, TA = 0°C to 70°C, unless otherwise stated AC CHARACTERISTICS PARAMETER Input Clock Rise Time 1 Input Clock Fall Time 1 O u t p u t R i s e T i m e1 Output Rise time Output Fall time SYMBOL ICLK r ICLKf tr 1 t r2 1 1 tf 1 O u t p u t F a l l t i m e1 t f2 1 Output Duty Cycle Jitter, one sigma1 , 5 Jitter, absolute 1 , 5 Jitter, one sigma1 , 5 Jitter, absolute 1 , 5 Line-to-line jitter, 1 absolute 2 Input Frequency, 1 IN or FBIN dt T1s1 Ta b s 1 T 1s2 Ta b s 2 T L abs fin C L K 1 F r e q u e n c y 1, 3, 4 MK9173-01 fCLK1 C L K 1 F r e q u e n c y 1, 3, 4 MK9173-15 fCLK1 TEST CONDITIONS 15pF load; 0.8 to 2.0V 15pF load; 2 0 % t o 8 0 % VDD 15pF load; 2.0 to 0.8V 15pF load; 8 0 % t o 2 0 % VDD 15pF load CLK1 frequency ³ 2 5 M H z CLK1 frequency ³ 2 5 M H z CLK1 frequency < 2 5 M H z CLK1 frequency < 2 5 M H z See allowable f i b e l o w : 12 ≤ fin ≤ 1 4 k H z 14 < fin ≤ 1 7 k H z 17 < fin ≤ 3 0 k H z 30 < f i n ≤ 3 5 k H z 35 < f i n ≤ 1 0 0 0 k H z 12 ≤ f i n ≤ 1 4 k H z 14 < f i n ≤ 17 kHz 1 7 < fin ≤ 3 0 k H z 3 0 < fin ≤ 3 5 k H z 3 5 < fin ≤ 1 0 0 0 k H z MIN TYP MAX UNITS — — — — — 0.6 10 10 1.5 ns ns ns — 1.4 3.0 ns — 0.8 2.0 ns — 0.8 2.0 ns 40 — -400 — — — 12 44.0 30.0 25.0 15.0 10.0 22.0 15.0 12.5 7.5 5.0 47 120 ±250 — — ±4 — — — — — — — — — — — 55 250 400 1 2 — 1000 75 75 75 75 75 37.5 37.5 37.5 37.5 37.5 % ps ps % % ns kHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz Notes: 1. Parameter is guaranteed by design and characterization. Not 100% tested in production. 2. Input Reference Frequency = 25 kHz, Output Frequency = 25 MHz. Jitter measured between adjacent vertical pixels. 3. CLK1 frequency applies for FS = 0. For FS = 1 condition, divide allowable CLK1 range by the factor of 4. 4. An Application Brief (AB01) documents the operation of the AV9173 for low input frequencies. This provides guidelines for usable output frequencies and feedback ratios required to use inputs below 25 kHz. By following these guidelines, the MK9173 will operate down to 12 kHz inputs across temperature, voltage and lot-to-lot variation. 5. Jitter values are measured at frequencies ≥25 MHz for MK9173-01, for MK9173-15, jitter is measured at frequency ≥12.5 MHz. Integrated Circuit Systems, Incorporated • 525 Race Street •San Jose • CA• 95126 • (408) 295-9800 tel • www.icst.com 6 MK9173-01 MK9173-15 8-Pin SOIC PACKAGE Millimeters E H h x 450 D A Q c e Inches Symbol Min Max Min Max A 1.35 1.75 0.0532 0.0688 A1 1.10 0.25 0.0040 0.0098 B 0.33 0.51 0.013 0.020 C 0.19 0.25 0.0075 0.0098 D 4.80 5.00 .1890 .1968 E 3.80 4.00 0.1497 0.1574 e 1.27 Basic H 5.80 6.20 0.2284 0.2440 h 0.25 0.50 0.010 0.020 L 0.40 1.27 0.016 0.050 a 0° 8° 0° 8° 0.050 Basic b Ordering Information Order Number Part Marking Package Shipping Packaging MK9173-01CS08 MK73-1 8 pin SOIC Tubes MK9173-01CS08T MK73-1 8 pin SOIC Tape and Reel MK9173-15CS08 MK73-15 8 pin SOIC Tubes MK9173-15CS08T MK73-15 8 pin SOIC Tape and Reel While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems (ICS) assumes no responsibility for either its use or for the infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in life support devices or critical medical instruments. Integrated Circuit Systems, Incorporated• 525 Race Street • San Jose •CA • 95126 • (408) 295-9800tel • www.icst.com 7