IL9001 DMOS FULL BRIDGE DRIVER DESCRIPTION The circuit is a full bridge driver for motor control applications realized in Multipower-BCD technology which combines isolated DMOS power transistors with CMOS and Bipolar circuits on the same chip. By using mixed technology it has been possible to optimize the logic circuitry and the power stage to achieve the best possible performance. The DMOS output transistors can operate at supply voltages up to 42V and efficiently at high switching speeds. All the logic inputs are TTL, CMOS and µC compatible. Each channel (halfbridge) of the device is controlled by a separate logic input, while a common enable controls both channels. Features Supply voltage up to 48V 5A max peak current (2A max. for L6201) Total RMS Current up to 4A; RDS (ON) 0.3 Ohm (typical value at 25 oC) Cross conduction protection TTL Compatible drive Operating frequency up to 100 kHz Thermal shutdown Internal logic supply high efficiency Figure 1. Package and pin connection Figure 2. Simplified Block Diagram 1 IL9001 PIN FUNCTIONS Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 Symbols SENSE 1 IN1 ENABLE 1 OUT1 GND OUT3 ENABLE 2 IN 3 SENSE 2 BOOSTRAP OSC.VCP IN 4 OUT 4 Vs2 Vs1 OUT 2 IN 2 VBOOT Functions Sense resistor to provide the feedback for motor current control of the bridge A Digital input from the motor controller (bridge A) A logic level low on this pin disable the bridge A Output of one half bridge of the bridge A Common Power Ground Ouput of one half bridge of the bridge В A logic level low on this pin disable the bridge В Digital input from the motor controller (bridge B) Sense resistor to provide the feedback for motor current control of the bridge В Oscillator output for the external charge pump Digital input from the motor controller (bridge B) Output of one half bridge of the bridge B Supply voltage bridge B Supply Voltage bridge A Output of one half bridge of the bridge A Digital input from the motor controller (bridge A) Overvoltage input for driving of the upper DMOS ABSOLUTE MAXIMUM RATING Symbol Vs VIM, VEN Io VSENSE VBOOT Ptot Tstg, Tj Parameter Supply Voltage Input or Enable Voltage Range Pulsed Output Current Sensing Voltage Bootstrap Supply Total power dissipation: (Tpins = 80°C) Storage and Junction Temperature Test Conditions 50 -0.3 to +7 3 -1 to 4 60 5 -40 to 150 Unit V V A V V W °C ELECTRICAL CHARACTERISTICS (Vs = 42V, Tj = 25°C unless otherwise specified) Symbol Vs Is Parameter Supply Voltage Total Quiescent Current fc TJ Td Commutation Frequency Thermal Shutdown Dead Time Protection Test Condition Min. 12 Тур. EN1=EN2=H; IN1=IN2=IN3IN4=L EN1 =EN2-L Max. 48 10 10 Unit V mA 20 150 500 mA KHz °C ns 1 1,2 mA Ohm TRANSISTORS IDSS RDS Leakage Current On Resistance OFF ON1 LOGIC LEVELS VINL, VENL VINH, VENH IINL, IENL Input Low Voltage Input High Voltage Input Low Current IINH, IENH Input High Current -0.3 2 IN1 = IN2 = INS = IN4 - EN1 = EN2 = L IN1 = IN2 = INS = IN4 = EN1 = EN2 = H 2 0.8 7 -10 50 V V uА uА IL9001 ELECTRICAL CHARACTERISTICS (Continued) LOGIC CONTROL TO POWER DRIVE TIMING Symbol t1 (Vi) t2 (Vi) t3 (Vi) t4 (Vi) t5 (Vi) t6 (Vi) t7 (Vi) t8 (Vi) Parameter Source Current Turn-off Delay Source Current Fall Time Source Current Turn-on Delay Source Current Rise Time Sink Current Turn-off Delay Sink Current Fall Time Sink Current Turn-on Delay Sink Current Rise Time Test Conditions Min. Typ. 300 200 400 200 300 200 400 200 Max. Unit ns ns ns ns ns ns ns ns (*) Limited by power dissipation (**) In synchronous rectification the drain-source voltage drop VDS is shown in fig. 4 (L6202/03); typical value for the L6201 is of 0.3V. Figure 1: Typical Normalized IS vs. Tj Figure 2: Typical Normalized Quiescent Current vs. Frequency Figure 3: Typical Normalized IS vs. VS Figure 4: Typical RDS(ON) vs. VS ~ Vref 3 IL9001 Figure 5: Normalized RDS(ON) at 25oC vs. Temperature Typical Values Figure 6b: Typical Diode Behaviour in Synchronous Rectification Figure 7b: Typical Power Dissipation vs IL CIRCUIT DESCRIPTION The IL9001 is a monolithic full bridge switching motor driver realized in the new Mul-tipower-BCD technology which allows the integration of multiple, isolated DMOS power transistors plus mixed CMOS/bipolar control circuits. In this way it has been possible to make all the control inputs TTL, CMOS and C compatible and eliminate the necessity of external MOS drive components. The Logic Drive is shown in table 1. Table 1 Inputs Output Mosfets (*) VEN = H VEN = L IN1 L L H H X IN2 L H L H X Sink 1, Sink 2 Sink 1, Source 2 Source 1, Sink 2 Source 1, Source 2 All transistors turned oFF L = Low H = High X = DON’t care (*) Numbers referred to INPUT1 or INPUT2 controlled output stages Although the device guarantees the absence of cross-conduction, the presence of the intrinsic diodes in the POWER DMOS structure causes the generation of current spikes on the sensing terminals. This is due to charge-discharge phenomena in the capacitors C1 & C2 associated with 4 IL9001 the drain source junctions (fig. 14). When the output switches from high to low, a current spike is generated associated with the capacitor C1. On the low-to-high transition a spike of the same polarity is generated by C2, preceded by a spike of the opposite polarity due to the charging of the input capacity of the lower POWER DMOS transistor (fig. 15). Figure 14: Intrinsic Structures in the POWER DMOS Transistors Figure 15: Current Typical Spikes on the Sensing Pin TRANSISTOR OPERATION ON State When one of the POWER DMOS transistor is ON it can be considered as a resistor RDS (ON) throughout the recommended operating range. In this condition the dissipated power is given by : PON = RDS (ON) IDS2 (RMS) The low RDS (ON) of the Multipower-BCD process can provide high currents with low power dissipation. OFF State When one of the POWER DMOS transistor is OFF the V DS voltage is equal to the supply voltage and only the leakage current IDSS flows. The power dissipation during this period is given by : POFF = VS IDSS The power dissipation is very low and is negligible in comparison to that dissipated in the ON STATE. Transitions As already seen above the transistors have an intrinsic diode between their source and drain that can operate as a fast freewheeling diode in switched mode applications. During recirculation with the ENABLE input high, the voltage drop across the transistor is RDS (ON) ID and when it reaches the diode forward voltage it is clamped. When the ENABLE input is low, the POWER MOS is OFF and the diode carries all of the recirculation current. The power dissipated in the transitional times in the cycle depends upon the voltage-current waveforms and in the driving mode. (see Fig. 7ab and Fig. 8abc). Ptrans. = IDS (t) VDS (t) 5