INA3010 INFRARED REMOTE CONTROL TRANSMITTER (RC-5) GENERAL DESCRIPTION The INA3010 is intended as a general purpose (RC-5) infrared remote control system for use where a low voltage supply and a large debounce time are expected. The device can generate 2048 different commands and utilizes a keyboard with a single pole switch for each key. The command are arranged so that 32 systems can be addressed, each system containing 64 different ORDERING INFORMATION commands. The keyboard interconnection is illustrated by INA3010N Plastic Fig.1. INA3010DW SOIC TA = -25° to 85° C FEATURES for all packages • • • • Low voltage requirement Single pin oscillator Biphase transmission technique Test mode facility BLOCK DIAGRAM. 1 INA3010 PINNING PIN No DESIGNATION 1 2 3-6 7 X7 (IPU) SSM (I) Z0-Z3 (IPU) MDATA (OP3) 8 9-13 14 15-17 18 19 20 21-27 28 DATA (OP3) DR7-DR3 (ODN) GND DR2-DR0 (ODN) OSC (I) TP2 (I) TP1 (I) X0-X6 (IPU) Vcc (I) DESCRIPTION sense input from key matrix system mode selection input sense inputs from key matrix generated output data modulated with 1/2 the oscillator frequency at a 25% duty factor generated output information scan drivers ground (0V) scan drivers oscillator input test point 2 test point 1 sense inputs from key matrix voltage supply Note (I) = input (IPU) = input with p-channel pull-up transistor (ODN) = output with open drain n-channel transistor (OP3) = output 3-state KEYBOARD INTERCONNECTION. IN A3 0 1 0 2 INA3010 FUNCTIONAL DESCRIPTION Keyboard operation Every connection of one X-input and one DR-output will be recognized as a legal key operation and will cause the device to generate the corresponding code. The same applies to every connection of one Z-input to one DR-output with the7 proviso that SSM must be LOW. When SSM is HIGH a wired connection must exist between a Z-input and a DRoutput. If no connection is present the system number will not be generated. Activating two or more X-inputs, Z-inputs or Z-inputs and X-inputs at the same time is an illegal action and inhibits further activity (oscillator will not start). When one X- or Z-input is connected to more than one DR-output, the last scan signal will be considered as legal. The maximum value of the contact series resistance of the switched keyboard is 7 kW. Inputs In the quiescent state the command inputs X0 to X7 are held HIGH by an internal pull-up transistor. When the system mode selection (SSM) input is LOW and the system is quiescent, the system inputs Z0 to Z3 are also held HIGH by an internal pull-up transistor. When SSM is HIGH the pull-up transistor for the Z-inputs is switched off, in order to prevent current flow, and a wired connection in the Z-DR matrix provides the system number. Outputs The output signal DATA transmits the generated information in accordance with the format illustrated by Fig.3. The code is transmitted using a biphase technique as illustrated by Fig.4. The code consists of four parts: · Start part -1.5 bits (2 ´ logic 1) · Control part -1 bit · System part -5 bits · Command part -6 bits The output signal MDATA transmits the generated information modulated by 1/12 of the oscillator frequency with a 50% duty factor. In the quiescent state both DATA and MDATA are non-conducting (3-state outputs). The scan driver outputs DR0 to DR7 are open drain n-channel transistors and conduct when the circuit is quiescent. After a legal key operation the scanning cycle is started and the outputs switched to the conductive state one by one. The DR-outputs were switched off at the end of the preceding debounce cycle. Command matrix (X-DR) Code no. 0 1 2 3 4 5 6 7 8 9 10 11 0 x x x x x x x x 1 2 X-lines 3 4 5 6 7 0 x 1 2 DR-lines 3 4 5 6 7 x x x x x x x x x x x x x x x 3 5 0 0 0 0 0 0 0 0 0 0 0 0 4 0 0 0 0 0 0 0 0 0 0 0 0 Command bits 3 2 1 0 0 0 0 0 0 0 0 1 0 0 1 0 1 0 0 1 0 0 1 1 0 1 1 1 0 0 1 0 0 1 0 1 1 0 1 0 0 1 0 1 0 1 0 1 0 1 0 1 INA3010 Code no. 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 0 1 x x x x 2 X-lines 3 4 5 6 7 0 1 2 DR-lines 3 4 5 x x 6 7 x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x 4 5 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 4 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Command bits 3 2 1 1 1 0 1 1 0 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 0 0 1 0 1 0 0 1 0 0 1 1 0 1 1 1 0 0 1 0 0 1 0 1 1 0 1 1 1 0 1 1 0 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 0 0 1 0 1 0 0 1 0 0 1 1 0 1 1 1 0 0 1 0 0 1 0 1 1 0 1 1 1 0 1 1 0 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 0 0 1 0 1 0 0 1 0 0 1 1 0 1 1 1 0 0 1 0 0 1 0 1 1 0 1 1 1 0 1 1 0 1 1 1 1 1 1 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 INA3010 System matrix (Z-DR) Code no. 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 0 x x x x x x x x 1 2 X-lines 3 4 5 6 7 0 x 1 2 DR-lines 3 4 5 6 7 x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x 5 4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 System bits 3 2 1 0 0 0 0 0 0 0 0 1 0 0 1 0 1 0 0 1 0 0 1 1 0 1 1 1 0 0 1 0 0 1 0 1 1 0 1 1 1 0 1 1 0 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 0 0 1 0 1 0 0 1 0 0 1 1 0 1 1 1 0 0 1 0 0 1 0 1 1 0 1 1 1 0 1 1 0 1 1 1 1 1 1 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 INA3010 MAXIMUM RATINGS Symbol Parameter Value Unit VCC DC Supply Voltage (Referenced to GND) -0.5 to +8.5 V VIN DC Input Voltage (Referenced to GND)* -0.5 to VCC +0.5 V DC Output Voltage (Referenced to GND)* -0.5 to VCC +0.5 ±10 V mA VOUT IIN DC Input Current IOUT DC Output Current ±10 mA PDO PDO Maximum Power Dissipation OSC output other outputs 50 100 mW mW PD Power Dissipation in Still Air 200 mW -65 to +150 °C Tstg Storage Temperature *VCC + 0.5 must not exceeed 9.0V.. * Maximum Ratings are those values beyond which damage to the device may occur. Functional operation should be restricted to the Recommended Operating Conditions. +Derating - Plastic DIP: - 10 mW/°C from 65° to 85°C SOIC Package: : - 7 mW/°C from 65° to 85°C RECOMMENDED OPERATING CONDITIONS Symbol VCC VIH VIL VOUT IIN IOL IOH Parameter DC Supply voltage (Reference to GND) DC Input voltage (HIGH) DC Input voltage (LOW) DC Output Voltage (MDATA, DATA) DC Input Current DC Output Current (LOW) pins 7,8 pins 9-13; 15-17 DC Output Current (MDATA, DATA) TA Operating Temperature, All Package Types Min 2.0 0.7VCC 0 - Max 7.0 VCC 0.3VCC 7.0 ±10 Unit V V V V mA mA - 0.6 0.3 -0.4 -25 85 mA o C This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high-impedance circuit. For proper operation, VIN and VOUT should be constrained to the range GND≤(VIN or VOUT)≤VCC. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or VCC). Unused outputs must be left open. 6 INA3010 DC ELECTRICAL CHARACTERISTICS (Voltage Reference to GND) (VCC= 2.0 to 7.0V unless otherwise specified, TA=-25 to +70°C) Guaranteed Limits Symbol ICC Parameter Test Conditions Quiscent supply current UIL=0B; VIH=VCC IOUT=0 mA at all outputs Input current VIL=0V Min Max Unit 40 µA INPUTS IIN µA Pins 01, 03-06; 2127 ILI Pin 18 VIL=0V; VIH=VCC Input leakage current VIL=0V; VIH=VCC -10 -600 3.0 33 µA - ±10 - -20 Pins 01-06;19-27 Pin 18 OUTPUTS VOH Output voltage HIGH, pins 07-08 IOH=-0.4mA VIL=0.3 VCC VCC-0.3 - V VOL Output voltage LOW IOL=0.6mA - 0.3 V Pins 07-08 ILO VIL=0V, VHI=0.7VCC Pins 9-13; 15-17 IOL=0.3mA, VIL=0V, VIH=0.7VCC - 0.3 V Output leakage current VO=VCC, VIH=VCC, VOH=VCC - 10 µA -20 µA 10 µA Pins 07-13; 15-17 ILO Output leakage current VO=0V, VIH=VCC, VOL=0V Pins 07-08 IOH DC Output Current Pins 913; 15-17 - VIL=0V; VIH=VCC; VOH=VCC AC ELECTRICAL CHARACTERISTICS TA=-25 to +85°C; VCC=2.0 to 7.0 V unless otherwise specified Symbol Parameter Test Condition Guaranteed Limits Oscillator frequency fOSC Typ Max Unit 432 450 KHz CL=160pF operational 7 INA3010 DATA OUTPUT FORMAT. Where: debounce time + scan time = 18 bit-times repetition time = 4 ´ 16 bit-times BIPHASE TRANSMISSION TECHNIQUE. Where: 1 bit-time = 3.2 8 ´ TOSC = 1.778 ms (typ.) 8 INA3010 Combined system mode (SSM is LOW) The X and Z sense inputs have p-channel pull-up transistors, so that they are HIGH, until pulled LOW by connecting them to an output as the result of a key operation. Legal operation of a key in the X-DR or Z-DR matrix will start the debounce cycle, once key contact has been established for 18 bit-times without interruption, the oscillator enable signal is latched and the key may be released. An interruption within the 18 bit-time period resets the device. At the end of the debounce cycle the DR-outputs are switched off and two scan cycles are started, that switch on the DR-lines one by one. When a Z- or X-input senses a low level, a latch enable signal is fed to the system (Z-input) or command (X-input) latches. After latching a system number the device will generate the last command (i.e. all command bits logic 1) in the chosen system for as long as the key is operated. Latching of a command number causes the chip to generate this command together with the system number memorized in the system latch. Releasing the key will reset the device if no data is to be transmitted at the time. Once transmission has started the code will complete to the end. Single system mode (SSM is HIGH) In the single system mode, the X-inputs will be HIGH as in the combined system mode. The Z-inputs will be disabled by having their pull-up transistors switched off; a wired connection in the Z-DR matrix provides the system code. Only legal key operation in the XDR matrix will start the debounce cycle, once key contact has been established for 18 bittimes without interruption the oscillator enable signal is latched and the key may be released. An interruption within the 18 bit-time period resets the internal action. At the end of the debounce cycle the pull-up transistors in the X-lines are switched off and those in the Z-lines are switched on for the first scan cycle. The wired connection in the Z-matrix is then translated into a system number and memorized in the system latch. At the end of the first scan cycle the pull-up transistors in the Z-lines are switched off and the inputs are disabled again; the pull-up transistors in the X-lines are switched on. The second scan cycle produces the command number which, after being latched, is transmitted together with the system number. Key release detection An extra control bit is added which will be complemented after key release; this indicates to the decoder that the next code is a new command. This is important in the case where more digits need to be entered (channel numbers of Teletext or Viewdata pages). The control bit will only be complemented after the completion of at least one code transmission. The scan cycles are repeated before every code transmission, so that even with “take over” of key operation during code transmission the right system and command numbers are generated. Reset action The device will be reset immediately a key is released during: · debounce time · between two codes. When a key is released during matrix scanning, a reset will occur if: · a key is released while one of the driver outputs is in the low ohmic stage (logic 0) · a key is released before that key has been detected · there is no wired connection in the Z-DR matrix when SSM is HIGH. 9