ISSI IS34C02B-2DLI

ISSI
IS34C02B
®
2K-bit 2-WIRE SERIAL CMOS EEPROM
with Permanent and Reversible Write-Protection
ADVANCED INFORMATION
APRIL 2006
FEATURES
DESCRIPTION
2
TM
• Two-Wire Serial Interface, I C
compatible
– Bidirectional data transfer protocol
– 400 kHz (2.5V) and 100 KHz (1.7V) compatibility
• Organization:
– 256 x 8-bit
• Data Protection Features
– Write Protect Pin
– Permanent Software Protection
– Reversible Software Protection
• 16-Byte Page Write Buffer
– Partial Page-writes permitted
• Low Power CMOS Technology
– Active Current less than 3 mA (3.6V)
– Standby Current less than 1 µA (1.7V)
– Standby Current less than 2 µA (3.6V)
• Low Voltage Operation
The IS34C02B is an electrically erasable PROM device
that uses the industry-standard I2C communication
protocol. The IS34C02B contains a non-volatile memory
array of 2,048-bits (256K x 8 bytes), and is further
subdivided into 16 pages of 16 bytes each for Pagewrite mode. The device operates over the voltage range
of 1.7V to 3.6V to satisfy the voltage requirements of
DDR2, DDR1, and many other specifications. In normal
Read or Write operations, a master device communicates with the EEPROM via the two wires Serial Clock
and Serial Data. During application system boot-up, it
may be necessary to read out the contents of the
IS34C02B that pertain to the configuration of a DRAM
module. If the module manufacturer wishes to safeguard this memory content, the first half of the array can
be write-protected with either a permanent or reversible
software command, or the entire array can be writeprotected with the WP input pin. The IS34C02B has
three address pins, allowing up to eight devices (or
memory modules) to be uniquely accessible in a system. To minimize board real-estate, IS34C02B is
available in two space-saving packages: TSSOP(8), and
DFN(8). All these features make the device ideal for
use as a Serial Presence Detect (SPD) EEPROM in
various types of memory modules.
– IS34C02B-2: Vcc = 1.7V to 3.6V
• Random or Sequential Read Modes
• Filtered Inputs for Noise Suppression
• Self timed Write cycle (5ms max.)
• High Reliability
– Endurance: 1,000,000 Cycles
– Data Retention: 40 Years
• Industrial temperature range
• 8-pin TSSOP and DFN (leadless array)
• Lead-free available
Copyright © 2006 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no liability
arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on any published
information and before placing orders for products.
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
ADVANCED INFORMATION Rev. 00D
03/21/06
1
ISSI
IS34C02B
®
FUNCTIONAL BLOCK DIAGRAM
HIGH VOLTAGE
GENERATOR,
TIMING & CONTROL
Vcc
SDA
CONTROL
LOGIC
WP
SLAVE ADDRESS
REGISTER &
COMPARATOR
A0
00H-7FH
X
DECODER
SCL
ARRAY
80H-FFH
WORD ADDRESS
COUNTER
A1
Y
DECODER
A2
ACK
GND
nMOS
2
Clock
DI/O
>
DATA
REGISTER
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
ADVANCED INFORMATION Rev. 00D
03/21/06
ISSI
IS34C02B
PIN CONFIGURATION
8-Pin TSSOP
A0
A1
A2
GND
1
®
8-pad DFN
8
2
7
3
6
4
5
VCC
WP
SCL
SDA
A0 1
8 VCC
A1 2
7 WP
A2 3
6 SCL
GND 4
5 SDA
(Top View)
PIN DESCRIPTIONS
A0-A2
SDA
SCL
WP
Vcc
Address Inputs
Serial Address/Data I/O
Serial Clock Input
Write Protect Input
Power Supply
GND
Ground
WP
WP is the Write Protect pin. If the WP pin is tied to Vcc, the
entire array becomes Write Protected, and software writeprotection cannot be initiated. When WP is tied to GND or
left floating, normal read/write operations are allowed to the
device. If the device has already received a write-protection
command, the memory in the range of 00h-7Fh is read -only
regardless of the setting of the WP pin.
DEVICE OPERATION
SCL
This input clock pin is used to synchronize the data
transfer to and from the device.
The IS34C02B features a serial communication and supports
a bi-directional 2-wire bus transmission protocol called
I2CTM.
SDA
2-WIRE BUS
The SDA is a Bi-directional pin used to transfer addresses
and data into and out of the device. The SDA pin is an open
drain output and can be wire Or'ed with other open drain or
open collector outputs. The SDA bus requires a pullup
resistor to Vcc.
The two-wire bus is defined as a Serial Data line (SDA), and
a Serial Clock line (SCL). The protocol defines any device
that sends data onto the SDA bus as a transmitter, and the
receiving device as a receiver. The bus is controlled by
Master device which generates the SCL, controls the bus
access and generates the Stop and Start conditions. The
IS34C02B is the Slave device on the bus.
A0, A1, A2
The A0, A1, and A2 are the device address inputs that are
hardwired or left unconnected for hardware flexibility. When
pins are hardwired, as many as eight devices may be
addressed on a single bus system. When the pins are not
hardwired, the default values of A0, A1, and A2 are zero.
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ADVANCED INFORMATION Rev. 00D
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3
ISSI
IS34C02B
®
DEVICE ADDRESSING
The Bus Protocol:
– Data transfer may be initiated only when the bus is not
busy
– During a data transfer, the SDA line must remain stable
whenever the SCL line is high. Any changes in the SDA
line while the SCL line is high will be interpreted as a
Start or Stop condition.
The state of the SDA line represents valid data after a Start
condition. The SDA line must be stable for the duration of
the High period of the clock signal. The data on the SDA
line may be changed during the Low period of the clock
signal. There is one clock pulse per bit of data. Each data
transfer is initiated with a Start condition and terminated
with a Stop condition.
Start Condition
The Start condition precedes all commands to the device
and is defined as a High to Low transition of SDA when
SCL is High. The IS34C02B monitors the SDA and SCL
lines and will not respond until the Start condition is met.
Stop Condition
The Stop condition is defined as a Low to High transition of
SDA when SCL is High. All operations must end with a Stop
condition.
Acknowledge (ACK)
The Master begins a transmission by sending a Start
condition. The Master then sends the address of the
particular Slave devices it is requesting. The Slave device
(Fig. 5) address is 8 bits.
The four most significant bits of the Slave device address
are fixed as 1010 for normal read/write operations, and
0110 for permanent write-protection operations.
This device has three address bits (A1, A2, and A0) that
allow up to eight IS34C02B devices to share the 2-wire
bus. Upon receiving the Slave address, the device
compares the three address bits with the hardwired A2,
A1, and A0 input pins to determine if it is the appropriate
Slave. If any of the A2 - A0 pins is neither biased to High
nor Low, internal circuitry defaults the value to Low.
The last bit of the Slave address specifies whether a Read
or Write operation is to be performed. When this bit is set
to 1, a Read operation is selected, and when set to 0, a
Write operation is selected.
After the Master transmits the Start condition and
Slave address byte (Fig. 5), the appropriate 2-wire
Slave (eg. IS34C02B) will respond with ACK on the SDA
line. The Slave will pull down the SDA on the ninth clock
cycle, signaling that it received the eight bits of data. The
selected IS34C02B then prepares for a Read or Write
operation by monitoring the bus.
After a successful data transfer, each receiving device is
required to generate an ACK. The Acknowledging device
pulls down the SDA line.
Reset
The IS34C02B contains a reset function in case the 2wire bus transmission is accidentally interrupted (eg. a
power loss), or needs to be terminated mid-stream. The
reset is caused when the Master device creates a Start
condition. To do this, it may be necessary for the Master
device to monitor the SDA line while cycling the SCL up
to nine times. (For each clock signal transition to High,
the Master checks for a High level on SDA.)
Standby Mode
Power consumption is reduced in standby mode. The
IS34C02B will enter standby mode: a) At Power-up, and
remain in it until SCL or SDA toggles; b) Following the Stop
signal if no write operation is initiated; or c) Following any
internal write operation
4
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ADVANCED INFORMATION Rev. 00D
03/21/06
ISSI
IS34C02B
®
WRITE OPERATION
WRITE PROTECTION
Byte Write
Hardware Write Protection
In the Byte Write mode, the Master device sends the Start
condition and the Slave address information (with the R/W
set to Zero) to the Slave device. After the Slave generates
an ACK, the Master sends a byte address that is written into
the address pointer of the IS34C02B. After receiving another
ACK from the Slave, the Master device transmits the data
byte to be written into the address memory location. The
IS34C02B acknowledges once more and the Master
generates the Stop condition, at which time the device
begins its internal programming cycle. While this internal
cycle is in progress, the device will not respond to any
request from the Master device.
The IS34C02B has two forms of software write protection and one form of hardware write protection. The
hardware write protection is enabled when the WP input
is held High. In this case, the entire array of the
IS34C02B is read-only regardless of the status of the
software protection. The hardware protection is disabled
when the WP input is held Low or is floating. In this
case, the upper half of the array (80h-FFh) can be
modified by a valid Write command, and the lower half of
the array (00h-7Fh) can be modified only if software write
protection has not been enabled.
Page Write
Reversible Software Write Protection
The IS34C02B is capable of 16-byte Page-Write operation.
A Page-Write is initiated in the same manner as a Byte Write,
but instead of terminating the internal Write cycle after the
first data byte is transferred, the Master device can transmit
up to 15 more bytes. After the receipt of each data byte, the
IS34C02B responds immediately with an ACK on SDA line,
and the four lower order data byte address bits are internally
incremented by one, while the higher order bits of the data
byte address remain constant. If a byte address is
incremented from the last byte of a page, it returns to the first
byte of that page. If the Master device should transmit more
than 16 bytes prior to issuing the Stop condition, the address
counter will “roll over,” and the previously written data will be
overwritten. Once all 16 bytes are received and the Stop
condition has been sent by the Master, the internal
programming cycle begins. At this point, all received data is
written to the IS34C02B in a single Write cycle. All inputs are
disabled until completion of the internal Write cycle.
There is a non-volatile flag for each of the two forms of
software write protection. When the bit value for either
flag or both flags is 1, it is not possible to modify the
contents of the lower 128 bytes of the array (00h-7Fh). If
the bit value for both flags is 0, it is possible to modify
this half of the array with a valid Write command,
assuming WP is held Low or is floating. The device is
shipped with both flags cleared. One of those flags is
the Reversible Software Write Protection (RSWP) flag,
and can be changed with the Set RSWP and Clear
RSWP commands. The flag can also be verified without
being changed with a Read SWP command. In order to
set, clear or read the RSWP, the IS34C02B input pins
must be as follows: A0 must be held to an extra high
voltage of VHV (see DC Characteristics), while A2 and
A1 must be set High, Low, or left floating, depending on
the desired command (see Figure 5). Once these input
conditions are met, a command can be issued to the
device.
Acknowledge (ACK) Polling
The disabling of the inputs can be used to take advantage
of the typical Write cycle time. Once the Stop condition is
issued to indicate the end of the host's Write operation, the
IS34C02B initiates the internal Write cycle. ACK polling can
be initiated immediately. This involves issuing the Start
condition followed by the Slave address for a Write operation.
If the IS34C02B is still busy with the Write operation, no
No Acknowledge (NoACK) will be returned. If the IS34C02B
has completed the Write operation, an ACK will be returned
and the host can then proceed with the next Read or Write
operation.
The reversible software commands are initiated similarly
to a normal byte write operation; however, the slave
device address begins with the bit values 0110. The
next three bits are A2 = 0, A1 = 0 or 1, and A0 = 1, so
that they logically match the values on the input pins. If
the last bit of the slave device address (R/W) is 0, the
RSWP flag can be Cleared or Set. If R/W is 1, the flag
can be verified with the Read SWP command. Following
this bit, the device responds with either ACK or NoACK,
depending on the exact command and the flag status
(see Table 1: Reversible Instructions). To complete the
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5
ISSI
IS34C02B
®
Set RSWP or Clear RSWP command, the Master must
transmit a dummy address byte, a dummy data byte,
and a Stop signal. To actually modify the RSWP flag,
WP should be held Low or be floating during entire
command sequence. Before resuming any other
command, the internal write cycle time should be
observed. To complete the Read SWP Status or Read
CWP Status command, the Master can transmit a Stop
signal after the ACK/NoACK. The WP input is not
evaluated for the Read SWP Status or Read CSP
Status commands.
Permanent Software Write Protection
The IS34C02B contains a permanent software write
protection (PSWP) feature. If the non-volatile PSWP flag
has a bit value of 1, the array region of 00h-7Fh is
protected from modification. If the PSWP flag has a bit
value of 0, the write protection for the lower half of the
array is determined solely by the statuses of RSWP and
the WP input. After the PSWP flag is set to 1 via the
Permanent Write Protect command, the protected area
becomes irreversibly read-only despite power removal
and re-application on the device. Once enabled, the
permanent protection is independent of the status of the
WP pin.
The Permanent Software Write Protect command is
initiated similarly to a normal byte write operation;
however, the slave device address begins with the bit
values of 0110 (see Figure 5). The following three bits
are A2-A0, so that they logically match the values on
the input pins. The last bit of the slave address (R/W) is
0. The IS34C02B responds with either ACK or NoACK,
depending on the flag status (see Table 1: Permanent
Instructions). Assuming an ACK is received, Master
then must complete the sequence by transmitting a
dummy address byte, dummy data byte, and a Stop
signal (see Figure 11). The WP pin should be held Low
or left floating during the entire command. Before
resuming any other command, the internal write cycle
should be observed.
The status of the PSWP can be safely determined
without any changes by transmitting the same slave
address as above, but with the last bit (R/W) set to 1
(see Figure 12). If the PSWP has been set, the
IS34C02B will not acknowledge any slave address
starting with bits 0110 (see Figure 5). To complete the
command, the Master can transmit a Stop signal after
the ACK/NoACK.
6
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ADVANCED INFORMATION Rev. 00D
03/21/06
ISSI
IS34C02B
®
TABLE 1
Normal Instructions
Command
Read
Write
Write
Write
Write
Write
PSWP
(Permanent)
X
0
X
1
X
X
RSWP
(Reversible)
X
0
X
X
1
X
WP1
RSWP
(Reversible)
X
WP1
ACK
Command
ACK
ACK
ACK
ACK
ACK
ACK
Address
Address
X
ACK
Command
ACK
X
0
1
X
X
0
00h-FFh
00h-FFh
00h-FFh
00h-7Fh
00h-7Fh
80h-FFh
ACK
Address
ACK
ACK
ACK
ACK
ACK
ACK
Data Byte
ACK
Address
ACK
Data Byte
Data
Data
Data
Data
Data
Data
Byte
Byte
Byte
Byte
Byte
Byte
Data Byte
ACK
ACK
ACK
ACK
ACK
ACK
ACK
Write
Cycle
No
Yes
No
No
No
Yes
Data Byte
ACK
ACK
Write
Cycle
No
—
ACK
No
Yes
—
ACK
No
No
—
No
Data Byte
ACK
ACK
Write
Cycle
No
—
ACK
No
No
—
ACK
No
Yes
—
ACK
No
No
—
ACK
No
Yes
—
ACK
No
No
—
No
Permanent Instructions
Command
PSWP
(Permanent)
Read PSWP Status4
0
Read PSWP Status
Set PSWP
1
0
X
X
X
0
NoACK
ACK
Set PSWP
Set PSWP
1
0
X
X
0
1
NoACK
ACK
Set PSWP
1
X
1
NoACK
RSWP
(Reversible)
0
WP1
X
ACK
Command
ACK
Dummy
Address
—
Dummy
Address
—
Dummy
Address
—
—
ACK
—
ACK
—
Dummy
Byte
—
Dummy
Byte
—
Dummy
Byte
—
Reversible Instructions
Command
PSWP
(Permanent)
X
Read SWP Status4
Read SWP Status
Read CWP Status3,4
X
0
1
X
X
X
NoACK
ACK
Read CWP Status3
Set RSWP
1
X
X
0
X
0
NoACK
ACK
Set RSWP
Set RSWP
X
X
1
0
0
1
NoACK
ACK
Set RSWP
Clear RSWP
X
0
1
X
1
0
NoACK
ACK
Clear RSWP
Clear RSWP
1
0
X
X
0
1
NoACK
ACK
Clear RSWP
1
X
1
NoACK
Address
Dummy
Address
—
Dummy
Address
—
Dummy
Address
—
Dummy
Address
—
Dummy
Address
—
Dummy
Address
—
ACK
Address
ACK
—
ACK
—
ACK
—
ACK
—
ACK
—
ACK
—
Data Byte
Dummy
Byte
—
Dummy
Byte
—
Dummy
Byte
—
Dummy
Byte
—
Dummy
Byte
—
Dummy
Byte
—
Notes:
1. WP = 1 if input level is High. WP = 0 if input level is GND or floating.
2. X = Don’t Care.
3. Read CWP Status yields the same result as Read PSWP Status.
4. Read out Don't Care Dummy Address and Dummy Data is optional.
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7
ISSI
IS34C02B
®
READ OPERATION
Sequential Read
Read operations are initiated in the same manner as Write
operations, except that the (R/W) bit of the Slave address is
set to “1”. There are three Read operation options: current
address read, random address read and sequential read.
Sequential Reads can be initiated as either a Current
Address Read or Random Address Read. After the
IS34C02B sends the initial byte sequence, the Master
device responds with an ACK indicating it requires additional
data from the IS34C02B. The IS34C02B continues to output
data for each ACK received. The Master device terminates
the sequential Read operation by pulling SDA High (no ACK)
indicating the last data byte to be read, followed by a Stop
condition.
Current Address Read
The IS34C02B contains an internal address counter
which maintains the address of the last byte accessed,
incremented by one. For example, if the previous
operation is either a Read or Write operation addressed
to the address location n, the internal address counter
would increment to address location n+1. When the
IS34C02B receives the Device Addressing Byte with a
Read operation (R/W bit set to “1”), it will respond an ACK
and transmit the 8-bit data byte stored at address
location n+1. The Master should not acknowledge the
transfer but should generate a Stop condition so the
IS34C02B discontinues transmission. If the last byte of
the memory was the previous access, the data from
location '0' will be transmitted. (Refer to Figure 8.
Current Address Read Diagram.)
The data output is sequential, with the data from address n
followed by the data from address n+1, ... etc. The address
counter increments by one automatically, allowing the
entire memory contents to be serially read during sequential
Read operations. When the memory address boundary 255
is reached, the address counter “rolls over” to address 0, and
the IS34C02B continues to output data for each ACK
received. (Refer to Figure 10. Sequential Read Operation
Starting with a Random Address Read Diagram.)
Random Address Read
Selective Read operations allow the Master device to select
at random any memory location for a Read operation. The
Master device first performs a 'dummy' Write operation by
sending the Start condition, Slave address and word address
of the location it wishes to read. After the IS34C02B
acknowledges the word address, the Master device resends
the Start condition and the Slave address, this time with the
R/W bit set to one. The IS34C02B then responds with its
ACK and sends the data requested. The Master device
does not send an ACK but will generate a Stop
condition. (Refer to Figure 9. Random Address Read
Diagram.)
8
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ADVANCED INFORMATION Rev. 00D
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ISSI
IS34C02B
®
Figure 1. Typical System Bus Configuration
Vcc
SDA
SCL
Master
Transmitter/
Receiver
IS34C02B
Figure 2. Output Acknowledge
SCL from
Master
1
8
9
Data Output
from
Transmitter
tAA
Data Output
from
Receiver
tAA
ACK
STOP
Condition
SCL
START
Condition
Figure 3. Start and Stop Conditions
SDA
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9
ISSI
IS34C02B
®
Figure 4. Data Validity Protocol
Data Change
SCL
Data Stable
Data Stable
SDA
Figure 5. Command Configuration
Pin Connection1
A2
A1
A0
A2
A1
A2
A1
Slave Device Address
7
6
5
4
3
2
1
0
A0
1
0
1
0
A2
A1
A0
R/W
Normal
Instruction2
A0
0
1
1
0
A2
A1
A0
R/W
Permanent Write
Protection Instruction2
GND GND VHV
0
1
1
0
0
0
1
0
Set Write Protection
(SWP)
VHV
0
1
1
0
0
1
1
0
Clear Write Protection
(CWP)
GND GND VHV
0
1
1
0
0
0
1
1
VHV
0
1
1
0
0
1
1
1
GND
GND
Vcc
Vcc
BIT
Read SWP
Read CWP
Note:
1. A2-A0 input pin connections must be GND (or floating), Vcc, or VHV.
2. Bits 1, 2, and 3 of the device address will be compared with the values on the external pins.
Figure 6. Byte Write
SDA
Bus
Activity
S
T
A
R
T
Device
Address
M
S
B
W
R
I
T
E *
A
C
K
L
S
B
R/W
Word Address
*
A
C
K
Data
S
T
O
* P
A
C
K
M
S
B
* Acknowledges provided by the slave regardless of hardware or software Write Protection.
10
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ADVANCED INFORMATION Rev. 00D
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ISSI
IS34C02B
®
Figure 7. Page Write
SDA
Bus
Activity
S
T
A
R
T
W
R
I
T
E * Word Address (n) *
A
A
C
C
K
K
Device
Address
M
S
B
Data (n)
*
A
C
K
Data (n+1)
*
A
C
K
Data (n+15)
S
T
O
* P
A
C
K
L
S
B
R/W
* Acknowledges provided by the slave regardless of hardware or software Write Protection.
Figure 8. Current Address Read
S
T
A
R
T
R
E
A
D
Device
Address
SDA
Bus
Activity
S
T
O
P
Data
A
C
K
M
S
B
L
S
B
N
O
A
C
K
R/W
Figure 9. Random Address Read
S
T
A
R
T
Device
Address
SDA
Bus
Activity
W
R
I
T
E
Word
Address (n)
A
C
K
M
S
B
S
T
A
R
T
Device
Address
A
C
K
L
S
B
R/W
R
E
A
D
S
T
O
P
Data n
A
C
K
N
O
A
C
K
DUMMY WRITE
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ADVANCED INFORMATION Rev. 00D
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11
ISSI
IS34C02B
®
Figure 10. Sequential Read
Device
Address
SDA
Bus
Activity
R
E
A
D
Data Byte n
A
C
K
Data Byte n+1
A
C
K
Data Byte n+2
A
C
K
S
T
O
P
Data Byte n+X
A
C
K
N
O
A
C
K
R/W
Figure 11. SET PERMANENT WRITE PROTECTION
SDA
Bus
Activity
S
T
A
R
T
W
R
I
Device
T
Data
Address
E * Word Address
A
A
A
C # # ## # # # #C # # # ## # # # C
K
K
K
M
L
M
S
S
S
B
B
B
R/W
S
T
O
P
* The slave does not provide an acknowledgement if the permanent write protection is already enabled.
# Don't care bits are required.
Figure 12. READ PERMANENT WRITE PROTECTION
S
T
A
R
T
R S
E T
A O
D * P
A
C
K
Device
Address
SDA
Bus
Activity
M
S
B
L
S
B
R/W
* The slave does not provide an acknowledgement if the permanent write protection is already enabled.
12
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
ADVANCED INFORMATION Rev. 00D
03/21/06
ISSI
IS34C02B
®
ABSOLUTE MAXIMUM RATINGS(1)
Symbol
VS
VP
TBIAS
TSTG
IOUT
Parameter
Supply Voltage
Voltage on Any Pin
Temperature Under Bias
Storage Temperature
Output Current
Value
–0.5 to +6.5
–0.5 to Vcc + 0.5
–55 to +125
–65 to +150
5
Unit
V
V
°C
°C
mA
Notes:
1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause
permanent damage to the device. This is a stress rating only and functional operation
of the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
OPERATING RANGE
(IS34C02B-2)
Range
Industrial
Ambient Temperature
–40°C to +85°C
VCC
1.7V to 3.6V
CAPACITANCE(1,2)
Symbol
Parameter
CIN
Input Capacitance
COUT
Output Capacitance
Conditions
Max.
Unit
VIN = 0V
6
pF
VOUT = 0V
8
pF
Notes:
1. Tested initially and after any design or process changes that may affect these parameters.
2. Test conditions: TA = 25°C, f = 400 KHz, Vcc = 3.0V.
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
ADVANCED INFORMATION Rev. 00D
03/21/06
13
ISSI
IS34C02B
®
DC ELECTRICAL CHARACTERISTICS
Industrial (TA = -40oC to +85oC)
Symbol
VOL1
VOL2
VIH
V IL
VHV
I LI
ILO
Parameter
Output Low Voltage
Output Low Voltage
Input High Voltage
Input Low Voltage
A0 High Voltage
Input Leakage Current
Output Leakage Current
Test Conditions
VCC = 1.7V, IOL = 0.15 mA
VCC = 3.6V, IOL = 2.1 mA
VHV - VCC > 4.8V
VIN = VCC max.
Min.
Max.
—
0.2
—
0.4
VCC X 0.7 VCC + 0.5
–1.0
VCC X 0.3
7
10
—
3
—
3
Unit
V
V
V
V
V
µA
µA
Notes: VIL min and VIH max are reference only and are not tested.
POWER SUPPLY CHARACTERISTICS
Industrial (TA = -40oC to +85oC)
Symbol
ICC1
ICC2
ISB1
ISB2
Parameter
Vcc Operating Current
Vcc Operating Current
Standby Current
Standby Current
Test Conditions
Read at 100 KHz (Vcc = 3.6V)
Write at 100 KHz (Vcc = 3.6V)
Vcc = 1.7V
Vcc = 3.6V
Min.
—
—
—
—
Max.
1.0
3.0
1
2
Unit
mA
mA
µA
µA
AC ELECTRICAL CHARACTERISTICS
Industrial (TA = -40oC to +85oC)
1.7V ≤ Vcc < 2.2V
Symbol
fSCL
T
tLow
tHigh
tBUF
tSU:STA
tSU:STO
tHD:STA
tHD:STO
tSU:DAT
tHD:DAT
tSU:WP
tHD:WP
tDH
tAA
tR
tF
tWR
Parameter
SCL Clock Frequency
Noise Suppression Time(1)
Clock Low Period
Clock High Period
Bus Free Time Before New Transmission(1)
Start Condition Setup Time
Stop Condition Setup Time
Start Condition Hold Time
Stop Condition Hold Time
Data In Setup Time
Data In Hold Time
WP pin Setup Time
WP pin Hold Time
Data Out Hold Time (SCL Low to SDA Data Out Change)
Clock to Output (SCL Low to SDA Data Out Valid)
SCL and SDA Rise Time(1)
SCL and SDA Fall Time(1)
Write Cycle Time
Min. Max.
0
100
—
100
4.7
—
4
—
4.7
—
4
—
4
—
4
—
4
—
100
—
0
—
4
—
4.7
—
100
—
100 3500
—
1000
—
300
—
5
2.2V ≤ Vcc ≤ 3.6V
Min. Max.
0
400
—
50
1.2
—
0.6
—
1.2
—
0.6
—
0.6
—
0.6
—
0.6
—
100
—
0
—
0.6
—
1.2
—
50
—
50
900
—
300
—
300
—
5
Unit
KHz
ns
µs
µs
µs
µs
µs
µs
µs
ns
ns
µs
µs
ns
ns
ns
ns
ms
Note:
1. These parameters are characterized, but not 100% tested.
14
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
ADVANCED INFORMATION Rev. 00D
03/21/06
ISSI
IS34C02B
®
FIGURE 13. AC WAVEFORMS
tR
tF
tHIGH
tLOW
tSU:STO
SCL
tSU:STA
tBUF
tHD:DAT
tHD:STA
tSU:DAT
SDAIN
tAA
tDH
SDAOUT
tSU:WP
tHD:WP
WP
FIGURE 14. WRITE CYCLE TIMING
SCL
SDA
8th BIT
ACK
tWR
WORD n
STOP
Condition
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
ADVANCED INFORMATION Rev. 00D
03/21/06
START
Condition
15
ISSI
IS34C02B
®
ORDERING INFORMATION
Industrial Range: -40°C to +85°C, Lead-free
16
Voltage
Range
Part Number
Package
1.7V
to 3.6V
IS34C02B-2DLI
IS34C02B-2ZLI
DFN
TSSOP
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
ADVANCED INFORMATION Rev. 00D
03/21/06
ISSI
PACKAGING INFORMATION
®
Dual Flat No-Lead
Package Code: D (8-pad)
D2
E
tie bars(3)
b
(8X)
E2
A
Pad 1 ID
L (8X)
D
A2
A1
e (6X)
1.50 REF.
A3
Pad 1 index area
DFN
MILLIMETERS
Sym.
Min. Nom. Max.
N0.
Pad
8
D
2.00 BSC
E
3.00 BSC
D2
1.50
—
1.75
E2
1.60
—
1.90
A
0.70
0.75
0.80
A1
0.0
0.02
0.05
A2
—
—
0.75
A3
L
0.20 REF
0.30
e
b
Notes:
1. Refer to JEDEC Drawing MO-229.
2. This is the metallized terminal and
is measured between 0.18 mm
and 0.30 mm from the terminal tip.
The terminal may have a straight
end instead of rounded.
3. Package may have exposed tie
bars, ending flush with package
edge.
0.40
0.50
0.50 BSC
0.18
0.25
0.30
Copyright © 2006 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time
without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to
obtain the latest version of this device specification before relying on any published information and before placing orders for products.
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. B
02/13/06
ISSI
PACKAGING INFORMATION
Thin Shrink Small Outline TSSOP
Package Code: Z (8 pin, 14 pin)
N
E1
1
E
α
N/2
A1
D
A2
A
L
C
e
B
TSSOP (Z)
Ref. Std.
JEDEC MO-153
No. Leads
8
Millimeters
Inches
Symbol Min Max
Min Max
A
—
1.20
— 0.047
A1
0.05 0.15
0.002 0.006
A2
0.80 1.05
0.032 0.041
B
0.19 0.30
0.007 0.012
C
0.09 0.20
0.004 0.008
D
2.90 3.10
0.114 0.122
E1
4.30 4.50
0.169 0.177
E
6.40 BSC
0.252 BSC
e
0.65 BSC
0.026 BSC
L
0.45 0.75
0.018 0.030
α
—
8°
—
8°
TSSOP (Z)
Ref. Std.
JEDEC MO-153
No. Leads
14
Millimeters
Inches
Symbol Min Max
Min
Max
A
—
1.20
—
0.047
A1
0.05 0.15
0.002 0.006
A2
0.80 1.05
0.031 0.041
B
0.19 0.30
0.007 0.012
C
0.09 0.20
0.0035 0.008
D
4.90 5.10
0.193 0.201
E1
4.30 4.50
0.170 0.177
E
6.40 BSC
0.252 BSC
e
0.65 BSC
0.026 BSC
L
0.45 0.75
0.0177 0.0295
α
—
8°
—
8°
SSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the best possible product. We assume no responsibility for any errors which may
appear in this publication. © Copyright 2002, Integrated Silicon Solution, Inc.
Integrated Silicon Solution, Inc.
Rev B 02/01/02
®