ISSI ® IS43R16320A 32Meg x 16 512-MBIT DDR SDRAM MARCH 2006 FEATURES DEVICE OVERVIEW • • ISSI’s 512-Mbit DDR SDRAM achieves high-speed data transfer using pipeline architecture and two data word accesses per clock cycle. The 536,870,912-bit memory array is internally organized as four banks of 128M-bit to allow concurrent operations. The pipeline allows Read and Write burst accesses to be virtually continuous, with the option to concatenate or truncate the bursts. The programmable features of burst length, burst sequence and CAS latency enable further advantages. The device is available in 16-bit data word size. Input data is registered on the I/O pins on both edges of Data Strobe signal(s), while output data is referenced to both edges of Data Strobe and both edges of CK. Commands are registered on the positive edges of CK. Auto Refresh, Active Power Down, and Pre-charge Power Down modes are enabled by using clock enable (CKE) and other inputs in an industry-standard sequence. All input and output voltage levels are compatible with SSTL 2. • • • • • • • • • • • • • • • • Clock Frequency: 166 MHz Power supply (VDD and VDDQ) DDR 333: 2.5V + 0.2V SSTL 2 interface Four internal banks to hide row Pre-charge and Active operations Commands and addresses register on positive clock edges (CK) Bi-directional Data Strobe signal for data capture Differential clock inputs (CK and CK) for two data accesses per clock cycle Data Mask feature for Writes supported DLL aligns data I/O and Data Strobe transitions with clock inputs Programmable burst length for Read and Write operations Programmable CAS Latency (2 or 2.5 clocks) Programmable burst sequence: sequential or interleaved Burst concatenation and truncation supported for maximum data throughput Auto Pre-charge option for each Read or Write burst 8192 refresh cycles every 64ms Auto Refresh and Self Refresh Modes KEY TIMING PARAMETERS Parameter -6 Unit DDR333 Clock Cycle Time CAS Latency = 3 CAS Latency = 2.5 CAS Latency = 2 — 6 7.5 ns ns ns Clock Frequency CAS Latency = 3 CAS Latency = 2.5 CAS Latency = 2 — 166 133 MHz MHz MHz Pre-charge Power Down and Active Power Down Modes Lead-free package Copyright © 2006 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on any published information and before placing orders for products. Integrated Silicon Solution, Inc. — 1-800-379-4774 Rev. A 03/22/06 1 ISSI IS43R16320A ® PIN CONFIGURATIONS 66 pin TSOP - Type II for x16 VDD 1 66 VSS DQ0 2 65 DQ15 VDDQ 3 64 VSSQ DQ1 4 63 DQ14 DQ2 5 62 DQ13 VSSQ 6 61 VDDQ DQ3 7 60 DQ12 DQ4 8 59 DQ11 VDDQ 9 58 VSSQ DQ5 10 57 DQ10 DQ6 11 56 DQ9 VSSQ 12 55 VDDQ DQ7 13 54 DQ8 NC 14 53 NC VDDQ 15 52 VSSQ LDQS 16 51 UDQS NC 17 50 NC VDD 18 49 VREF DNU 19 48 VSS LDM 20 47 UDM WE 21 46 CK CAS 22 45 CK RAS 23 44 CKE CS 24 43 NC NC 25 42 A12 BA0 26 41 A11 BA1 27 40 A9 A10 28 39 A8 A0 29 38 A7 A1 30 37 A6 A2 31 36 A5 A3 32 35 A4 VDD 33 34 VSS PIN DESCRIPTIONS 2 A0-A12 Row Address Input WE Write Enable A0-A9 Column Address Input LDM, UDM x16 Input Mask BA0, BA1 Bank Select Address LDQS, UDQS Data Strobe DQ0 to DQ15 Data I/O VDD Power CK, CK System Clock Input Vss Ground CKE Clock Enable VDDQ Power Supply for I/O Pin CS Chip Select VssQ Ground for I/O Pin RAS Row Address Strobe Command VREF Input Reference Voltage CAS Column Address Strobe Command DNU Do Not Use NC No Connection Integrated Silicon Solution, Inc. — 1-800-379-4774 Rev. A 03/22/06 ISSI IS43R16320A ® Mode Register Operation BA1 BA0 0* 0* A12 A11 A10 A9 A8 A7 A6 A5 A4 CAS Latency Operating Mode A12 - A9 A8 A7 A6 - A0 Operating Mode 0 0 0 Valid Normal operation Do not reset DLL 0 1 0 Valid Normal operation in DLL Reset A3 A2 BT A1 Burst Length A3 Burst Type 0 Sequential 1 Interleave A0 Address Bus Mode Register Reserved CAS Latency Burst Length A6 A5 A4 Latency A2 A1 A0 Burst Length 0 0 0 Reserved 0 0 0 Reserved 0 0 1 Reserved 0 0 1 2 0 1 0 2 0 1 0 4 0 1 1 Reserved 0 1 1 8 1 0 0 Reserved 1 0 0 Reserved 1 0 1 Reserved 1 0 1 Reserved 1 1 0 2.5 1 1 0 Reserved 1 1 1 Reserved 1 1 1 Reserved * BA0 and BA1 must be 0, 0 to select the Mode Register (vs. the Extended Mode Register). Integrated Silicon Solution, Inc. — 1-800-379-4774 Rev. A 03/22/06 3 ISSI IS43R16320A ® Burst Definition Burst Length Starting Column Address A2 A1 A0 Type = Sequential Type = Interleaved 0 0-1 0-1 1 1-0 1-0 0 0 0-1-2-3 0-1-2-3 0 1 1-2-3-0 1-0-3-2 1 0 2-3-0-1 2-3-0-1 1 1 3-0-1-2 3-2-1-0 0 0 0 0-1-2-3-4-5-6-7 0-1-2-3-4-5-6-7 0 0 1 1-2-3-4-5-6-7-0 1-0-3-2-5-4-7-6 0 1 0 2-3-4-5-6-7-0-1 2-3-0-1-6-7-4-5 0 1 1 3-4-5-6-7-0-1-2 3-2-1-0-7-6-5-4 1 0 0 4-5-6-7-0-1-2-3 4-5-6-7-0-1-2-3 1 0 1 5-6-7-0-1-2-3-4 5-4-7-6-1-0-3-2 1 1 0 6-7-0-1-2-3-4-5 6-7-4-5-2-3-0-1 1 1 1 7-0-1-2-3-4-5-6 7-6-5-4-3-2-1-0 2 4 8 Order of Accesses Within a Burst Notes: 1. For a burst length of two, A1-A i selects the two-data-element block; A0 selects the first access within the block. 2. For a burst length of four, A2-A i selects the four-data-element block; A0-A1 selects the first access within the block. 3. For a burst length of eight, A3-A i selects the eight-data- element block; A0-A2 selects the first access within the block. 4. Whenever a boundary of the block is reached within a given sequence above, the following access wraps within the block. Burst Type Accesses within a given burst may be programmed to be either sequential or interleaved; this is referred to as the burst type and is selected via bit A3. The ordering of accesses within a burst is determined by the burst length, the burst type and the starting column address, as shown in Burst Definition. Read Latency The Read latency, or CAS latency, is the delay, in clock cycles, between the registration of a Read command and the availability of the first burst of output data. The latency can be programmed 2 or 2.5 clocks for DDR333. If a Read command is registered at clock edge n, and the latency is m clocks, the data is available nominally coincident with clock edge n + m. Reserved states should not be used as unknown operation or incompatibility with future versions may result. 4 Integrated Silicon Solution, Inc. — 1-800-379-4774 Rev. A 03/22/06 ISSI IS43R16320A ® Read Command CK CK CKE HIGH CS RAS CAS WE CA A0-A9 EN AP A10 DIS AP BA0, BA1 BA CA = column address BA = bank address EN AP = enable Auto Precharge DIS AP = disable Auto Precharge Don’t Care Integrated Silicon Solution, Inc. — 1-800-379-4774 Rev. A 03/22/06 5 ISSI IS43R16320A ® Write Command CK CK CKE HIGH CS RAS CAS WE A0-A9 CA EN AP A10 DIS AP BA0, BA1 BA CA = column address BA = bank address EN AP = enable Auto Precharge DIS AP = disable Auto Precharge Don’t Care 6 Integrated Silicon Solution, Inc. — 1-800-379-4774 Rev. A 03/22/06 ISSI IS43R16320A ® Capacitance Parameter Input Capacitance: CK, CK Symbol Min. Max. Units Notes CI1 2.0 3.0 pF 1 0.25 pF 1 3.0 pF 1 0.5 pF 1 5.0 pF 1, 2 0.5 pF 1 delta CI1 Delta Input Capacitance: CK, CK Input Capacitance: All other input-only pins (except DM) Delta Input Capacitance: All other input-only pins (except DM) Input/Output Capacitance: DQ, DQS, DM 2.0 CI2 delta CI2 4.0 CIO Delta Input/Output Capacitance: DQ, DQS, DM delta CIO 1. VDDQ = VDD = 2.5V ± 0.2V (minimum range to maximum range), f = 100MHz, TA = 25°C, VODC = VDDQ/2, VOPeak -Peak = 0.2V. 2. Although DM is an input-only pin, the input capacitance of this pin must model the input capacitance of the DQ and DQS pins. This is required to match input propagation times of DQ, DQS and DM in the system. DC Electrical Characteristics and Operating Conditions (0°C < T A < 70oC; VDDQ = VDD = + 2.5V ± 0.2V (DDR333); see AC Characteristics) Symbol Min Max Units Notes Supply Voltage DDR 333 2.3 2.7 V 1 I/O Supply Voltage DDR333 2.3 2.7 V 1 0 0 V I/O Reference Voltage 0.49 x VDDQ 0.51 x VDDQ V 1, 2 I/O Termination Voltage (System) VREF - 0.04 VREF + 0.04 V 1, 3 VIH(DC) Input High (Logic1) Voltage VREF + 0.15 VDDQ + 0.3 V 1 VIL(DC) Input Low (Logic0) Voltage -0.3 VREF - 0.15 V 1 VIN(DC) Input Voltage Level, CK and CK Inputs -0.3 VDDQ + 0.3 V 1 VID(DC) Input Differential Voltage, CK and CK Inputs 0.30 VDDQ + 0.6 V 1, 4 VIX(DC) Input Crossing Point Voltage, CK and CK Inputs 0.30 VDDQ + 0.6 V 1, 4 VIRatio V-I Matching Pullup Current to Pulldown Current Ratio 0.71 1.4 VDD VDDQ VSS, VSSQ VREF VTT II IOZ Parameter Supply Voltage I/O Supply Voltage 5 Input Leakage Curr ent Any input 0V < VIN < VDD; (All other pins not under test = 0V) -2 2 µA 1 Output Leakage Current (DQs are disabled; 0V < Vout < VDDQ -5 5 µA 1 1. Inputs are not recognized as valid until VREF stabilizes. 2. VREF is expected to be equal to 0.5 VDDQ of the transmitting device, and to track variations in the DC level of the same. Peak-to-peak noise on VREF may not exceed ± 2% of the DC value. 3. VTT is not applied directly to the device. VTT is a system supply for signal termination resistors, is expected to be set equal to VREF, and must track variations in the DC level of VREF. 4. VID is the magnitude of the difference between the input level on CK and the input level on CK. 5. The ratio of the pullup current to the pulldown current is specified for the same temperature and voltage, over the entire temperature and voltage range, for device drain to source voltages for 0.25 volts to 1.0 volts. For a given output, it represents the maximum difference between pullup and pulldown drivers due to process variation. Integrated Silicon Solution, Inc. — 1-800-379-4774 Rev. A 03/22/06 7 ISSI IS43R16320A ® DC Electrical Characteristics and Operating Conditions (0°C < T A < 70oC; VDDQ = VDD = + 2.5V ± 0.2V (DDR333); see AC Characteristics) Symbol IOH IOL IOHW IOLW Parameter Min Output Current: Nominal Strength Driver High current (VOUT= VDDQ -0.373V, min VREF, min VTT) Low current (VOUT= 0.373V, max VREF, max VTT) − 16.8 Output Current: Half- Strength Driver High current (VOUT= VDDQ -0.763V, min VREF, min VTT) Low current (VOUT= 0.763V, max VREF, max VTT) − 9.0 Max 16.8 9.0 Units Notes mA 1 mA 1 1. Inputs are not recognized as valid until VREF stabilizes. 2. VREF is expected to be equal to 0.5 VDDQ of the transmitting device, and to track variations in the DC level of the same. Peak-to-peak noise on VREF may not exceed ± 2% of the DC value. 3. VTT is not applied directly to the device. VTT is a system supply for signal termination resistors, is expected to be set equal to VREF, and must track variations in the DC level of VREF. 4. VID is the magnitude of the difference between the input level on CK and the input level on CK. 5. The ratio of the pullup current to the pulldown current is specified for the same temperature and voltage, over the entire temperature and voltage range, for device drain to source voltages for 0.25 volts to 1.0 volts. For a given output, it represents the maximum difference between pullup and pulldown drivers due to process variation. Normal Strength Driver Pulldown and Pullup Characteristics 1. The full variation in driver pulldown current from minimum to maximum process, temperature and voltage will lie within the outer bounding lines of the V-I curve. 2. It is recommended that the “typical” IBIS pulldown V-I curve lie within the shaded region of the V-I curve. Normal Strength Driver Pulldown Characteristics 140 IOUT (mA) Maximum Typical High Typical Low Minimum 0 0 VOUT (V) 2.7 3. The full variation in driver pullup current from minimum to maximum process, temperature and voltage will lie within the outer bounding lines of the V-I curve. 4. It is recommended that the “typical” IBIS pullup V-I curve lie within the shaded region of the V-I curve. 8 Integrated Silicon Solution, Inc. — 1-800-379-4774 Rev. A 03/22/06 ISSI IS43R16320A ® Normal Strength Driver Pullup Characteristics 0 Minimum IOUT (mA) Typical Low Typical High Maximum -200 0 VOUT (V) 2.7 5. The full variation in the ratio of the maximum to minimum pullup and pulldown current will not exceed 1.7, for device drain to source voltages from 0.1 to 1.0. 6. The full variation in the ratio of the “typical” IBIS pullup to “typical” IBIS pulldown current should be unity + 10%, for device drain to source voltages from 0.1 to 1.0. This specification is a design objective only. It is not guaranteed. 7. These characteristics are intended to obey the SSTL_2 class II standard. 8. This specification is intended for DDR SDRAM only. Integrated Silicon Solution, Inc. — 1-800-379-4774 Rev. A 03/22/06 9 ISSI IS43R16320A ® Normal Strength Driver Pulldown and Pullup Currents Pulldown Current (mA) Pullup Current (mA) Voltage (V) Typical Low Typical High Min Max Typical Low Typical High Min Max 0.1 6.0 6.8 4.6 9.6 -6.1 -7.6 -4.6 -10.0 0.2 12.2 13.5 9.2 18.2 -12.2 -14.5 -9.2 -20.0 0.3 18.1 20.1 13.8 26.0 -18.1 -21.2 -13.8 -29.8 0.4 24.1 26.6 18.4 33.9 -24.0 -27.7 -18.4 -38.8 0.5 29.8 33.0 23.0 41.8 -29.8 -34.1 -23.0 -46.8 0.6 34.6 39.1 27.7 49.4 -34.3 -40.5 -27.7 -54.4 0.7 39.4 44.2 32.2 56.8 -38.1 -46.9 -32.2 -61.8 0.8 43.7 49.8 36.8 63.2 -41.1 -53.1 -36.0 -69.5 0.9 47.5 55.2 39.6 69.9 -43.8 -59.4 -38.2 -77.3 1.0 51.3 60.3 42.6 76.3 -46.0 -65.5 -38.7 -85.2 1.1 54.1 65.2 44.8 82.5 -47.8 -71.6 -39.0 -93.0 1.2 56.2 69.9 46.2 88.3 -49.2 -77.6 -39.2 -100.6 1.3 57.9 74.2 47.1 93.8 -50.0 -83.6 -39.4 -108.1 1.4 59.3 78.4 47.4 99.1 -50.5 -89.7 -39.6 -115.5 1.5 60.1 82.3 47.7 103.8 -50.7 -95.5 -39.9 -123.0 1.6 60.5 85.9 48.0 108.4 -51.0 -101.3 -40.1 -130.4 1.7 61.0 89.1 48.4 112.1 -51.1 -107.1 -40.2 -136.7 1.8 61.5 92.2 48.9 115.9 -51.3 -112.4 -40.3 -144.2 1.9 62.0 95.3 49.1 119.6 -51.5 -118.7 -40.4 -150.5 2.0 62.5 97.2 49.4 123.3 -51.6 -124.0 -40.5 -156.9 2.1 62.9 99.1 49.6 126.5 -51.8 -129.3 -40.6 -163.2 2.2 63.3 100.9 49.8 129.5 -52.0 -134.6 -40.7 -169.6 2.3 63.8 101.9 49.9 132.4 -52.2 -139.9 -40.8 -176.0 2.4 64.1 102.8 50.0 135.0 -52.3 -145.2 -40.9 -181.3 2.5 64.6 103.8 50.2 137.3 -52.5 -150.5 -41.0 -187.6 2.6 64.8 104.6 50.4 139.2 -52.7 -155.3 -41.1 -192.9 2.7 65.0 105.4 50.5 140.8 -52.8 -160.1 -41.2 -198.2 Normal Strength Driver Evaluation Conditions 10 Typical Minimum Maximum Temperature (Tambient) 25 °C 70 °C 0 °C VDDQ 2.5V 2.3V 2.7V Process conditions typical process slow-slow process fast-fast process Integrated Silicon Solution, Inc. — 1-800-379-4774 Rev. A 03/22/06 ISSI IS43R16320A ® AC Characteristics (Notes 1-5 apply to the following Tables; Electrical Characteristics and DC Operating Conditions, AC Operating Conditions, IDD Specifications and Conditions, and Electrical Characteristics and AC Timing.) 1. All voltages referenced to VSS. 2. Tests for AC timing, IDD, and electrical, AC and DC characteristics, may be conducted at nominal reference/supply voltage levels, but the related specifications and device operation are guaranteed for the full voltage range specified. 3. Outputs measured with equivalent load. Refer to the AC Output Load Circuit below. 4. AC timing and IDD tests may use a VIL to VIH swing of up to 1.5V in the test environment, but input timing is still referenced to VREF (or to the crossing point for CK, CK), and parameter specifications are guaranteed for the specified AC input levels under normal use conditions. The minimum slew rate for the input signals is 1V/ns in the range between VIL(AC) and VIH(AC). 5. The AC and DC input level specifications are as defined in the SSTL_2 Standard (i.e. the receiver effectively switches as a result of the signal crossing the AC input level, and remains in that state as long as the signal does not ring back above (below) the DC input low (high) level. AC Output Load Circuit Diagrams VTT 50Ω Output Timing Reference Point (VOUT) 30pF Integrated Silicon Solution, Inc. — 1-800-379-4774 Rev. A 03/22/06 11 ISSI IS43R16320A ® AC Input Operating Conditions (0 °C < TA < 70o C VDD = VDDQ = 2.5V + 0.2V (DDR333); See AC Characteristics) Symbol Parameter/Condition VIH(AC) Input High (Logic 1) Voltage, DQ, DQS, and DM Signals VIL(AC) Input Low (Logic 0) Voltage, DQ, DQS, and DM Signals VID(AC) Input Differential Voltage, CK and CK Inputs VIX(AC) Input Crossing Point Voltage, CK and CK Inputs 1. 2. 3. 4. Min Max Unit Notes V 1, 2 VREF - 0.31 V 1, 2 0.62 VDDQ + 0.6 V 1, 2, 3 0.5*VDDQ - 0.2 0.5*VDDQ + 0.2 V 1, 2, 4 VREF + 0.31 Input slew rate = 1V/ns Inputs are not recognized as valid until VREF stabilizes. VID is the magnitude of the difference between the input level on CK and the input level on CK. The value of VIX is expected to equal 0.5*VDDQ of the transmitting device and must track variations in the DC level of the same. IDD Specifications and Conditions (0 °C < TA < 70oC V DD = VDDQ = 2.5V + 0.2V (DDR333); See AC Characteristics) Symbol Parameter/Condition DDR333 (6K) tCK=6ns IDD0 Operating Current: one bank; active / precharge; tRC = tRC (min); DQ, DM, and DQS inputs changing twice per clock cycle; address and control inputs changing once per clock cycle 96 mA 1 IDD1 Operating Current: one bank; active / read / precharge; Burst = 2; tRC = tRC (min); CL = 2.5; IOUT = 0mA; address and control inputs changing once per clock cycle 99 mA 1 IDD2P Precharge Power Down Standby Current: all banks idle; Power Down mode; CKE < VIL (max) 5 mA 1 IDD2N Idle Standby Current: CS > VIH (min); all banks idle; CKE > VIH (min); address and control inputs changing once per clock cycle 25 mA 1 IDD3P Active Power Down Standby Current: one bank active; Power Down mode; CKE < VIL (max) 11 mA 1 IDD3N Active Standby Current: one bank; active / precharge; CS > VIH (min); CKE > VIH (min); tRC = tRAS (max); DQ, DM, and DQS inputs changing twice per clock cycle; address and control inputs changing once per clock cycle 45 mA 1 IDD4R Operating Current: one bank; Burst = 2; reads; continuous burst; address and control inputs changing once per clock cycle; DQ and DQS outputs changing twice per clock cycle; CL = 2.5; IOUT = 0mA 104 mA 1 IDD4W Operating Current: one bank; Burst = 2; writes; continuous burst; address and control inputs changing once per clock cycle; DQ and DQS inputs changing twice per clock cycle; CL = 2.5 117 mA 1 IDD5 Auto-Refresh Current: tRC = tRFC (min) 193 mA 1 IDD6 Self-Refresh Current: CKE < 0.2V 5 mA 1, 2 IDD7 Operating current: four bank; four bank interleaving with BL = 4, address and control inputs randomly changing; 50% of data changing at every transfer; t RC = t RC (min); I OUT = 0mA. 307 mA 1 Unit Notes 1. IDD specifications are tested after the device is properly initialized. 2. Enables on-chip refresh and address counters. Values are averaged from high and low temp values using x16 devices. 12 Integrated Silicon Solution, Inc. — 1-800-379-4774 Rev. A 03/22/06 ISSI IS43R16320A ® Electrical Characteristics & AC Timing - Absolute Specifications (0 °C < TA < 70 oC VDD = VDDQ = 2.5V + 0.2V (DDR333); See AC Characteristics) Symbol DDR333 (6K) Parameter Min tAC DQ output access time from CK/CK tDQSCK DQS output access time from CK/CK tCH CK high-level width tCL CK low-level width Clock cycle time Notes Max -0.7 +0.7 ns 1-4 -0.6 +0.6 ns 1-4 0.45 0.55 tCK 1-4 0.45 0.55 tCK 1-4 ns 1-4 CL = 3.0 tCK Unit CL = 2.5 6 12 ns 1-4 CL = 2.0 7.5 12 ns 1-4 tDH DQ and DM input hold time 0.45 ns 1-4, 15, 16 tDS DQ and DM input setup time 0.45 ns 1-4, 15, 16 tIPW Input pulse width 2.2 ns 2-4, 12 tDIPW DQ and DM input pulse width (each input) 1.75 ns 1-4 tHZ Data-out high-impedance time from CK/CK -0.7 +0.7 ns 1-4, 5 tLZ Data-out low-impedance time from CK/CK -0.7 +0.7 ns 1-4, 5 +0.45 ns 1-4 +0.4 tDQSQ DQS-DQ skew (DQS & associated DQ signals) TSOP Package ns 1-4 tHP Minimum half clk period for any given cycle; defined by clk high (tCH) or clk low (tCL) time min (tCL, tCH) tCK 1-4 tQH Data output hold time from DQS tHP - tQHS tCK 1-4 tQHS Data hold Skew Factor tDQSS Write command to 1st DQS latching transition BGA Package TSOP Package 0.55 tCK 1-4 BGA Package 0.5 tCK 1-4 1.25 tCK 1-4 0.75 tDQSH DQS input high pulse width (write cycle) 0.35 tCK 1-4 tDQSL DQS input low pulse width (write cycle) 0.35 tCK 1-4 tDSS DQS falling edge to CK setup time (write cycle) 0.2 tCK 1-4 tDSH DQS falling edge hold time from CK (write cycle) 0.2 tCK 1-4 tMRD Mode register set command cycle time 2 tCK 1-4 0 ns 1-4, 7 tWPRES Write preamble setup time tWPST Write postamble tWPRE Write preamble tCK 1-4, 6 0.25 0.40 0.60 tCK 1-4 tIH Address and control input hold time (fast slew rate) 0.75 ns 2-4, 9, 11, 12 tIS Address and control input setup time (fast slew rate) 0.75 ns 2-4, 9, 11, 12 tIH Address and control input hold time (slow slew rate) 0.8 ns 2-4, 10-12, 14 tIS Address and control input setup time (slow slew rate) 0.8 ns 2-4, 10, 11, 12, 14 tRPRE Read preamble 0.9 1.1 tCK 1-4 tRPST Read postamble 0.40 0.60 tCK 1-4 Integrated Silicon Solution, Inc. — 1-800-379-4774 Rev. A 03/22/06 13 ISSI IS43R16320A ® Electrical Characteristics & AC Timing - Absolute Specifications (0 °C < TA < 70 oC VDD = VDDQ = 2.5V + 0.2V (DDR333); See AC Characteristics) Symbol 14 Parameter DDR333 (6K) Unit Notes ns 1-4 Min Max tRAS Active to Precharge command 42 120,000 tRC Active to Active/Auto-refresh command period 60 ns 1-4 tRFC Auto-refresh to Active/Auto-refresh command period 72 ns 1-4 tRCD Active to Read or Write delay tRAP Active to Read Command with Autoprecharge tRP Precharge command period 18 ns 1-4 min (tRCD, tRAS) ns 1-4 18 ns 1-4 tRRD Active bank A to Active bank B command 12 ns 1-4 tWR Write recovery time 15 ns 1-4 tDAL Auto precharge write recovery + precharge time (tWR/tCK) + (tRP/tCK) tCK 1-4, 13 tWTR Internal write to read command delay 1 tCK 1-4 tPDEX Power down exit time 6 ns 1-4 tXSNR Exit self-refresh to non-read command 75 ns 1-4 tXSRD Exit self-refresh to read command 200 tREFI Average Periodic Refresh Interval 7.8 tCK 1-4 us 1-4, 8 Integrated Silicon Solution, Inc. — 1-800-379-4774 Rev. A 03/22/06 IS43R16320A ISSI ® Electrical Characteristics & AC Timing - Absolute Specifications Notes 1. Input slew rate = 1V/ns. 2. The CK/CK input reference level (for timing reference to CK/CK) is the point at which CK and CK cross; the input reference level for signals other than CK/CK is VREF. 3. Inputs are not recognized as valid until VREF stabilizes. 4. The Output timing reference level, as measured at the timing reference point indicated in AC Characteristics (Note 3) is VTT. 5. tHZ and tLZ transitions occur in the same access time windows as valid data transitions. These parameters are not referred to a specific voltage level, but specify when the device is no longer driving (HZ), or begins driving (LZ). 6. The maximum limit for this parameter is not a device limit. The device operates with a greater value for this parameter, but system performance (bus turnaround) degrades accordingly. 7. The specific requirement is that DQS be valid (high, low, or some point on a valid transition) on or before this CK edge. A valid transition is defined as monotonic and meeting the input slew rate specifications of the device. When no writes were previously in progress on the bus, DQS will be transitioning from Hi-Z to logic LOW. If a previous write was in progress, DQS could be HIGH, LOW, or transitioning from high to low at this time, depending on tDQSS. 8. A maximum of eight Autorefresh commands can be posted to any given DDR SDRAM device. 9. For command/address input slew rate ≥ 1.0V/ns. Slew rate is measured between VOH (AC) and VOL (AC). 10. For command/address input slew rate ≥ 0.5V/ns and < 1.0V/ns. Slew rate is measured between VOH (AC) and VOL (AC). 11. CK/CK slew rates are ≥ 1.0V/ns. 12. These parameters guarantee device timing, but they are not necessarily tested on each device, and they may be guaranteed by design or tester characterization. 13. For each of the terms in parentheses, if not already an integer, round to the next highest integer. tCK is equal to the actual system clock cycle time. For example, for DDR333 at CL = 2.5, t DAL = (15ns/6ns) + (18ns/6ns) = 3 + 3 = 6. Integrated Silicon Solution, Inc. — 1-800-379-4774 Rev. A 03/22/06 15 ISSI IS43R16320A ® 14. An input setup and hold time derating table is used to increase tIS and tIH in the case where the input slew rate is below 0.5 V/ns. Input Slew Rate delta (tIS) delta (tIH) Unit Notes 0.5 V/ns 0 0 ps 1,2 0.4 V/ns +50 0 ps 1,2 0.3 V/ns +100 0 ps 1,2 1. Input slew rate is based on the lesser of the slew rates determined by either V IH (AC) to V IL (AC) or V IH (DC) to V IL (DC), similarly for rising transitions. 2. These derating parameters may be guaranteed by design or tester characterization and are not necessarily tested on each device. 15. An input setup and hold time derating table is used to increase tDS and tDH in the case where the I/O slew rate is below 0.5 V/ns. Input Slew Rate delta (tDS) delta (tDH) Unit Notes 0.5 V/ns 0 0 ps 1,2 0.4 V/ns +75 +75 ps 1,2 0.3 V/ns +150 +150 ps 1,2 1. I/O slew rate is based on the lesser of the slew rates determined by either V IH (AC) to V IL (AC) or V IH (DC) to V IL (DC), similarly for rising transitions. 2. These derating parameters may be guaranteed by design or tester characterization and are not necessarily tested on each device. 16. An I/O Delta Rise, Fall Derating table is used to increase tDS and tDH in the case where DQ, DM, and DQS slew rates differ. Input Slew Rate delta (tDS) delta (tDH) Unit Notes 0.0 V/ns 0 0 ps 1,2,3,4 0.25 V/ns +50 +50 ps 1,2,3,4 0.5 V/ns +100 +100 ps 1,2,3,4 1. Input slew rate is based on the lesser of the slew rates determined by either V IH (AC) to V IL (AC) or V IH (DC) to V IL (DC), similarly for rising transitions. 2. Input slew rate is based on the larger of AC to AC delta rise, fall rate and DC to DC delta rise, fall rate. 3. The delta rise, fall rate is calculated as: [1/(slew rate 1)] - [1/(slew rate 2)] For example: slew rate 1 = 0.5 V/ns; slew rate 2 = 0.4 V/ns Delta rise, fall = (1/0.5) - (1/0.4) [ns/V] = -0.5 ns/V Using the table above, this would result in an increase in t DS and t DH of 100 ps. 4. These derating parameters may be guaranteed by design or tester characterization and are not necessarily tested on each device. 16 Integrated Silicon Solution, Inc. — 1-800-379-4774 Rev. A 03/22/06 ISSI IS43R16320A ® ORDERING INFORMATION Commercial Range: 0°C to +70°C Frequency Speed (ns) 166 MHz 6 Order Part No. Package IS43R16320A-6TL 66-pin TSOP-II, Lead-free Integrated Silicon Solution, Inc. — 1-800-379-4774 Rev. A 03/22/06 17 ISSI ® PACKAGING INFORMATION Plastic TSOP 66-pin Package Code: T (Type II) N N/2+1 E1 E Notes: 1. Controlling dimension: millimieters, unless otherwise specified. 2. BSC = Basic lead spacing between centers. 3. Dimensions D and E1 do not include mold flash protrusions and should be measured from the bottom of the package. 4. Formed leads shall be planar with respect to one another within 0.004 inches at the seating plane. N/2 1 D SEATING PLANE A ZD b e A1 L α C Plastic TSOP (T - Type II) Millimeters Inches Symbol Min Max Min Max Ref. Std. No. Leads (N) 66 A A1 A2 b C D E1 E e L L1 ZD α — 1.20 0.05 0.15 — — 0.24 0.40 0.12 0.21 22.02 22.42 10.03 10.29 11.56 11.96 0.65 BSC 0.40 0.60 — — 0.71 REF 0° 8° — 0.047 0.002 0.006 — — 0.009 0.016 0.005 0.0083 0.867 0.8827 0.395 0.405 0.455 0.471 0.026 BSC 0.016 0.024 — — 0.028 REF 0° 8° Integrated Silicon Solution, Inc. — 1-800-379-4774 Rev. A 08/09/05 1