ISSI IS43R16800A-6

ISSI
®
IS43R16800A-6
8Meg x 16
128-MBIT DDR SDRAM
PRELIMINARY INFORMATION
APRIL 2006
FEATURES
DEVICE OVERVIEW
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•
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•
ISSI’s 128-Mbit DDR SDRAM achieves high-speed data
transfer using pipeline architecture and two data word
accesses per clock cycle. The 134,217,728-bit memory
array is internally organized as four banks of 32M-bit to
allow concurrent operations. The pipeline allows Read
and Write burst accesses to be virtually continuous, with
the option to concatenate or truncate the bursts. The
programmable features of burst length, burst sequence
and CAS latency enable further advantages. The device
is available in 16-bit data word size. Input data is registered on the I/O pins on both edges of Data Strobe
signal(s), while output data is referenced to both edges of
Data Strobe and both edges of CK. Commands are
registered on the positive edges of CK. Auto Refresh,
Active Power Down, and Pre-charge Power Down modes
are enabled by using clock enable (CKE) and other
inputs in an industry-standard sequence. All input and
output voltage levels are compatible with SSTL 2.
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Clock Frequency: 166, 133 MHz
Power supply (VDD and VDDQ): 2.5V
SSTL 2 interface
Four internal banks to hide row Pre-charge
and Active operations
Commands and addresses register on positive
clock edges (CK)
Bi-directional Data Strobe signal for data capture
Differential clock inputs (CK and CK) for
two data accesses per clock cycle
Data Mask feature for Writes supported
DLL aligns data I/O and Data Strobe transitions
with clock inputs
Half-strength and Matched drive strength
options
Programmable burst length for Read and Write
operations
Programmable CAS Latency (2, 2.5 clocks)
Programmable burst sequence: sequential or
interleaved
Burst concatenation and truncation supported
for maximum data throughput
Auto Pre-charge option for each Read or Write
burst
4096 refresh cycles every 64ms
Auto Refresh and Self Refresh Modes
Pre-charge Power Down and Active Power
Down Modes
Lead-free Availability
IS43R16800A-6
1M x16x8 Banks
VDD: 2.5V
VDDQ: 2.5V
66-pin TSOP-II
KEY TIMING PARAMETERS
Parameter
-6
Unit
DDR333
Clock Cycle Time
CAS Latency = 3
CAS Latency = 2.5
CAS Latency = 2
—
6
7.5
ns
ns
ns
Clock Frequency
CAS Latency = 3
CAS Latency = 2.5
CAS Latency = 2
—
166
133
MHz
MHz
MHz
Copyright © 2006 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time
without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to
obtain the latest version of this device specification before relying on any published information and before placing orders for products.
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. 00A
04/04/06
1
ISSI
IS43R16800A-6
®
FUNCTIONAL BLOCK DIAGRAM (X16)
CK
CK
CKE
CS
RAS
CAS
WE
COMMAND
DECODER
&
CLOCK
GENERATOR
LDM, UDM
16
MODE
REGISTER
SELF
MULTIPLEXER
12
12
12
COLUMN
ADDRESS LATCH
ROW
ADDRESS
BUFFER
16
2
12
ROW
ADDRESS
LATCH
VDD/VDDQ
Vss/VssQ
16
4096
4096
4096
4096
ROW DECODER
REFRESH
COUNTER
UDQS, LDQS
DATA OUT
BUFFER
CONTROLLER
14
I/O 0-15
2
REFRESH
14
16
REFRESH
CONTROLLER
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
BA0
BA1
2
DATA IN
BUFFER
MEMORY CELL
ARRAY
BANK 0
SENSE AMP I/O GATE
512
(x16)
BANK CONTROL LOGIC
9
BURST COUNTER
COLUMN
ADDRESS BUFFER
2
COLUMN DECODER
9
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. 00A
04/04/06
ISSI
IS43R16800A-6
®
PIN CONFIGURATIONS
66 pin TSOP - Type II for x16
VDD
1
66
VSS
DQ0
2
65
DQ15
VDDQ
3
64
VSSQ
DQ1
4
63
DQ14
DQ2
5
62
DQ13
VSSQ
6
61
VDDQ
DQ3
7
60
DQ12
DQ4
8
59
DQ11
VDDQ
9
58
VSSQ
DQ5
10
57
DQ10
DQ6
11
56
DQ9
VSSQ
12
55
VDDQ
DQ7
13
54
DQ8
NC
14
53
NC
VDDQ
15
52
VSSQ
LDQS
16
51
UDQS
NC
17
50
NC
VDD
18
49
VREF
NC
19
48
VSS
LDM
20
47
UDM
WE
21
46
CK
CAS
22
45
CK
RAS
23
44
CKE
CS
24
43
NC
NC
25
42
NC
BA0
26
41
A11
BA1
27
40
A9
A10
28
39
A8
A0
29
38
A7
A1
30
37
A6
A2
31
36
A5
A3
32
35
A4
VDD
33
34
VSS
PIN DESCRIPTIONS
A0-A11
Row Address Input
WE
Write Enable
A0-A8
Column Address Input
LDM, UDM
x16 Input/Output Mask
BA0, BA1
Bank Select Address
LDQS, UDQS
Data Strobe
DQ0 to DQ15
Data I/O
VDD
Power
CK
System Clock Input
Vss
Ground
CKE
Clock Enable
VDDQ
Power Supply for I/O Pin
CS
Chip Select
VssQ
Ground for I/O Pin
RAS
Row Address Strobe Command
NC
No Connection
CAS
Column Address Strobe Command
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. 00A
04/04/06
3
ISSI
IS43R16800A-6
®
PIN FUNCTIONS
4
Symbol
A0-A11
Type
Input Pin
BA0, BA1
Input Pin
CAS
Input Pin
CKE
Input Pin
CK, CK
Input Pin
CS
Input Pin
LDM, UDM
Input Pin
LDQS, UDQS
Input/Output Pin
DQ0-DQ15
Input/Output Pin
NC
—
RAS
Input Pin
WE
Input Pin
VDDQ
VDD
VREF
VSSQ
VSS
Power
Power
Power
Power
Power
Supply
Supply
Supply
Supply
Supply
Pin
Pin
Pin
Pin
Pin
Function (In Detail)
Address inputs are sampled during several commands. During an Active
command, A0-A11 select a row to open. During a Read or Write command,
A0-A8 select a starting column for a burst. During a Pre-charge command,
A10 determines whether all banks are to be pre-charged, or a single bank.
During a Load Mode Register command, the address inputs select an
operating mode.
Bank Address inputs are used to select a bank during Active, Pre-charge,
Read, or Write commands. During a Load Mode Register command, BA0
and BA1 are used to select between the Base or Extended Mode Register
CAS is Column Access Strobe, which is an input to the device command
along with RAS and WE. See “Command Truth Table” for details.
Clock Enable: CKE High activates and CKE Low de-activates internal clock
signals and input/output buffers. When CKE goes Low, it can allow Self
Refresh, Pre-charge Power Down, and Active Power Down. CKE must be
High during entire Read and Write accesses. Input buffers except CK,
CK, and CKE are disabled during Power Down. CKE uses an SSTL 2
input, but will detect a LVCMOS Low level after VDD is applied.
All address and command inputs are sampled on the rising edge of the
clock input CK and the falling edge of the differential clock input CK.
Output data is referenced from the crossings of CK and CK.
The Chip Select input enables the Command Decoding block of the device.
When CS is disabled, a NOP occurs. See “Command Truth Table” for
details. Multiple DDR SDRAM devices can be managed with CS.
These are the Data Mask inputs. During a Write operation, the Data Mask
input allows masking of the data bus. DM is sampled on each edge of DQS.
There are two Data Mask input pins for the x16 DDR SDRAM. Each input
applies to DQ0-DQ7, or DQ8-DQ15.
These are the Data Strobe inputs. The Data Strobe is used for data capture.
During a Read operation, the DQS output signal from the device is edgealigned with valid data on the data bus. During a Write operation, the DQS
input should be issued to the DDR SDRAM device when the input values on
DQ inputs are stable. There are two Data Strobe pins for the x16 DDR
SDRAM. Each of the two Data Strobe pins applies to DQ0-DQ7, or DQ8DQ15.
The pins DQ0 to DQ15 represent the data bus. For Write operations, the
data bus is sampled on Data Strobe. For Read operations, the data bus is
sampled on the crossings of CK and CK.
No Connect: This pin should be left floating. These pins could be used for
256Mbit or higher density DDR SDRAM.
RAS is Row Access Strobe, which is an input to the device command
along with CAS and WE. See “Command Truth Table” for details.
WE is Write Enable, which is an input to the device command along with
RAS and CAS. See “Command Truth Table” for details.
VDDQ is the output buffer power supply.
VDD is the device power supply.
VREF is the reference voltage for SSTL 2.
VSSQ is the output buffer ground.
VSS is the device ground.
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. 00A
04/04/06
ISSI
IS43R16800A-6
®
ABSOLUTE MAXIMUM RATINGS(1)
Symbol
Parameters
VDD MAX
VDDQ MAX
VIN, VREF
PD MAX
ICS
TOPR
TSTG
Maximum Supply Voltage
Maximum Supply Voltage for Output Buffer
Input Voltage, Reference Voltage
Allowable Power Dissipation
Output Shorted Current
Operating Temperature
Com.
Storage Temperature
Rating
Unit
–1.0 to +3.6
–1.0 to +3.6
–1.0 to +3.6
1
50
0 to +70
–55 to +125
V
V
V
W
mA
°C
°C
Notes:
1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This
is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the
operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods
may affect reliability.
2. All voltages are referenced to Vss.
RECOMMENDED DC OPERATING CONDITIONS (SSTL_2 Input/Output, TA = 0oC to +70oC)
Symbol
VDD
VDDQ(1)
VTT
VIH(2)
VIL(3)
VREF
VIN(DC)(4)
IIL
Parameter
Supply Voltage
I/O Supply Voltage
I/O Termination Voltage
Input High Voltage
Input Low Voltage
I/O Reference Voltage
Input Voltage Level for
CK and CK
Crossing Point Voltage
Level for CK and CK
Input Differential Voltage
Level for CK and CK
Input Leakage Current
IOL
Output Leakage Current
VOH
Output High Voltage
Level
Output Low Voltage
Level
VIX(DC)
VID(DC)(5,6)
VOL
Test Condition
Min
2.3
2.3
VREF - 0.04
VREF + 0.15
- 0.3
0.49 x VDDQ
-0.3
Typ.
2.5
2.5
VREF
—
—
0.5 x VDDQ
—
Max
2.7
2.7
VREF + 0.04
VDDQ + 0.3
VREF - 0.15
0.51 x VDDQ
VDDQ + 0.3
Unit
V
V
V
V
V
V
V
0.5 x VDDQ - 0.2
0.5 x VDDQ
0.5 x VDDQ + 0.2
V
0.36
—
VDDQ + 0.6
V
-2
—
2
µA
-5
—
5
µA
VTT + 0.76
—
—
V
—
—
VREF - 0.76
V
0 ≤ VIN ≤ VDD, with all inputs
at VSS, except tested input
Output disabled;
0V ≤ VOUT ≤ VDDQ
IOH = -15.2mA
IOL = +15.2mA
Note:
1. VDDQ must always be less than or equal to VDD.
2. VIH is allowed to exceed VDD up to 3.6V for the period shorter than or equal to 5ns.
3. VIL is allowed to drop to -1.0V for the period shorter than or equal to 5ns.
4. VIN(DC) specifies the allowable DC execution of each differential input.
5. VID(DC) specifies the input differential voltage required for switching.
6. VIH for CK or CK > VREF + 0.18V; VIL for CK or CK < VREF - 0.18V.
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. 00A
04/04/06
5
ISSI
IS43R16800A-6
®
CAPACITANCE CHARACTERISTICS (At TA = 0 to +25°C, VDD = VDDQ = 2.5V, f = 100 MHz)
Symbol
Parameter
CIN1
CIN2
CIN3
COUT
Input Capacitance: CK and CK
Input Capacitance: All other input pins
Data Mask Input/Output Capacitance: LDM/UDM
Data Input/Output Capacitance: DQs and LDQS/UDQS
DC ELECTRICAL CHARACTERISTICS
Symbol Parameter
Operating Current
IDD0
IDD1
Operating Current
IDD2P
Precharge Power-Down
Standby Current
Floating Idle
Standby Current
Quiet Idle
Standby Current
IDD2F
IDD2Q
IDD3P
IDD3N
IDD4R
IDD4W
IDD5
IDD6
IDD7
Active Power-Down
Standby Current
Active Standby Current
Operating Current
Burst Read
Operating Current
Burst Write
Auto Refresh Current
Self Refresh Current
Operating Current
(1,2,3,4,5)
Min.
Max.
Unit
2
2
3.8
3.8
3
3
4.8
4.8
pF
pF
pF
pF
(VDD = 2.5V +/- 0.2V, TA = 0oC to +70oC)
Test Condition
One bank operation; Active-Precharge; DQ, DM and DQS
inputs change once per clock cycle; Address and Control
inputs change once per two clock cycles; tRC = tRC (min)
One bank operation; Active-Read-Precharge; BL = 4; CL = 2.5;
Address and Control inputs change once per clock cycle;
tRCDRD = 4 x tCK; tRC = tRC (min); IOUT = 0mA;
All banks Idle; CKE ≤ VIL
Unit
110
mA
140
3
mA
mA
CKE ≥ VIH; CS ≥ VIH; DQ, DQS, DM = VREF
35
mA
All banks idle; Address and control inputs change once per
clock cycle; CKE = High; CS = High (Deselect); VIN = VREF
for DQ, DQS, and DM; tCK = tCK (min)
One bank Active; CKE = Low; tCK = tCK (min)
30
20
mA
mA
55
mA
205
mA
205
200
3
mA
mA
mA
350
mA
One bank Active; CS = High; CKE = High; Address and
Control inputs change once per clock cycle; DQ, DQS, and
DM change twice per clock cycle; tRC = tRC (max);
One bank Active; CKE ≥ VIH; BL = 2; Address and Control inputs
change once per clock cycle; tCK = tCK (min); IOUT = 0mA;
CL = 2.5
One bank Active; BL = 2; Address and Control inputs change
once per clock cycle; DQ, DQS, DM change twice per clock
cycle; CKE ≥ VIH; CL = 2.5
tRC = tRFC (min); Input ≤ VIL or ≥ VIH
Input ≥ VDD-0.2V; Input ≤ 0.2V
Four bank interleaved Reads with Auto Precharge; BL = 4;
Address and Controls inputs change per Read, Write, or
Active command; one bank with tRC = tRC (min)
Notes:
1. Operating outside the “Absolute Maximum Ratings” may lead to temporary or permanent device failure.
2. Power up sequence describe in “Initialization” section.
3. All voltages are referenced to VSS.
4. IDD tested without DQ pins connected.
5. IDD values tested with tCK = tCK (min).
6
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. 00A
04/04/06
ISSI
IS43R16800A-6
®
AC ELECTRICAL CHARACTERISTICS (VDD = 2.5V +/- 0.2V, TA = 0oC to +70oC)
Symbol
tCK
Parameter
Clock Cycle Time
Test Condition
CL = 2
CL = 2.5
tCH
tCL
tHP
tAC
tDQSCK
tDQSQ
tQH
tQHS
tHZ
tLZ
tRPRE
tRPST
tDQSS
tDSS
tDSH
tWPRES
tWPRE
tWPST
tDQSH
tDQSL
tIS
tIH
tIPW
tDS
tDH
tRC
tRFC
tRAS
tRCDRD
tRCDWR
tRP
tRAP
tRRD
tWR
tMRD
tDAL
tREF
Clock High Level Width
Clock Low Level Width
Clock Half Period
Output Access Time from CK, CK
DQS-Out Access Time from CK, CK
DQS-DQ Skew
Output DQS Valid Window
Data Hold Skew factor
Data Out High Impedance time from CK, CK
Data Out Low Impedance time from CK, CK
Read Preamble
Read Postamble
CK to Valid DQS-In
DQS falling edge to CK setup time
DQS falling edge hold time from CK
Write Preamble Setup Time
Write Preamble
Write Postamble
DQS-In High Level Pulse Width
DQS-In Low Level Pulse Width
Address and Control Input Setup Time
Address and Control Input Hold Time
Address and Control Input Pulse Width
DQ and DM Setup Time to DQS
DQ and DM Hold Time to DQS
Active to Active/ Auto Refresh Command Period
Auto Refresh to Active/ Auto Refresh Command Period
Active to Precharge Command Period
RAS to CAS Delay in Read
RAS to CAS Delay in Write
Row Pre-charge Time
Active to Auto Precharge delay
Row Active to Row Active Delay
Write Recovery Time
Mode Register Load Delay
Auto Pre-charge Write Recovery + Pre-charge
Refresh Interval Time
-6 (2.5-3-3)
Min.
Max.
7.5
12
6
12
0.45
0.55
0.45
0.55
tCH or tCL
—
-0.7
0.7
-0.6
0.6
—
0.45
tHP - tQHS
—
—
0.55
-0.7
0.7
-0.7
0.7
0.9
1.1
0.4
0.6
0.75
1.25
0.2
—
0.2
—
0
—
0.25
—
0.4
0.6
0.35
—
0.35
—
0.75
—
0.75
—
2.2
—
0.45
—
0.45
—
60
—
72
—
42
120K
18
—
18
—
18
—
tRCD min.
—
12
—
15
—
2
—
tWR/tCK + tRP/tCK —
—
15.6
Unit
ns
tCK
tCK
ns
ns
ns
ns
ns
ns
ns
ns
tCK
tCK
tCK
tCK
tCK
ns
ns
tCK
tCK
tCK
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tCK
tCK
µs
Notes:
1. Operating outside the “Absolute Maximum Ratings” may lead to temporary or permanent device failure.
2. Power up sequence describe in “Initialization” section.
3. All voltages are referenced to Vss.
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. 00A
04/04/06
7
IS43R16800A-6
ISSI
®
Notes:
1. All AC parameters measuremed with the following test conditions.
2. This parameter defines the signal transition delay from the crossing point of CK and CK. The signal transition is defined to occur
when the signal level crosses VTT.
3. The timing reference level is VTT.
4. Output valid window is defined to be the period between two successive transition of data out or DQS (read) signals. The signal
transition is defined to occur when the signal level crosses VTT.
5. tHZ is defined as the data output transition delay from Low-Z to High-Z at the end of a read burst operation. The timing reference
is the crossing point of CK and CK. This parameter is not referred to a specific voltage level, but when the device output stops
driving.
6. tLZ is defined as the data output transition delay from High-Z to Low-Z at the beginning of read operation. This parameter is referring
to a specific voltage level, but when the device output begins driving.
7. Input valid windows is defined to be the period between two successive transition of data input or DQS (write) signals. The signal
transition is defined to occur when the signal level crosses VREF.
8. The timing reference level is VREF.
9. The transition from Low-Z to High-Z is defined to occur when the device output stops driving. There is no specific reference voltage
to judge this transition.
10. tCK (max.) is determined by the locking range of the DLL. Beyond this lock range, the DLL operation is assured.
11. tCK = tCK (min) when these parameters are measured. Otherwise, absolute minimum values of these values are 10% of tCK.
12. VDD is assumed to be 2.5V ± 0.2V. VDD power supply variation per cycle expected to be less than 0.4V per 400 cycles.
13. tDAL = (tWR/tCK)+(tRP/tCK). For each of the add-ins, if not an integer already, round up to the nearest integer.
8
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. 00A
04/04/06
ISSI
IS43R16800A-6
®
AC TEST CONDITIONS
Output Load
VTT
RT = 50 Ω
DQ
CL = 30 pF
AC TEST CONDITIONS
Parameter
Input High Voltage
Input Low Voltage
Input Signal Slew Rate
Input Timing Reference Level
Termination Voltage
Symbol
VIH (AC)
VIL (AC)
SLEW
VREF
VTT
Value
VREF + 0.31
VREF - 0.31
1
VDDQ/2
VREF
Unit
V
V
V/ns
V
V
Input Differential Voltage (CK and CK)
VID (AC)
0.62
V
Input Differential Crossing Voltage
VIX (AC)
VREF
V
OPERATING FREQUENCY / LATENCY RELATIONSHIPS (tCK = 6ns, CL = 2.5)
SYMBOL
tWPD
tRPD
tWRD
tBSTW
tBSTZ
tRWD
tHZP
tWCD
tWR
tDMD
tMRD
tSNR
tSRD
tPDEN
tPDEX
PARAMETER
Write to Pre-charge command delay (same bank)
Read to Pre-charge command delay (same bank)
Write to Read command delay (to input all data)
Burst Stop command to Write command delay
Burst Stop command to DQ High-Z
Read command to Write command delay (to output all data)
Pre-charge command to High-Z
Write command to data in latency
Write Recovery
DM to Data-In latency
Mode Register Set command cycle time
Self Refresh Exit to non-read command
Self Refresh Exit to Read command
Power Down Entry
Power Down Exit to command input
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. 00A
04/04/06
4 + BL/2
BL/2
2 + BL/2
3
2.5
3 + BL/2
2.5
1
3
0
2
12
200
1
1
UNITS
Cycle
Cycle
Cycle
Cycle
Cycle
Cycle
Cycle
Cycle
Cycle
Cycle
Cycle
Cycle
Cycle
Cycle
Cycle
9
ISSI
IS43R16800A-6
®
FUNCTIONAL DESCRIPTION
INITIALIZATION
The 128Mbit DDR SDRAM is a high-speed CMOS
device with four banks that operate at 2.5V. Each
32Mbit bank is organized as 4,096 rows of 512 columns
for the x16 option. Pre-fetch architecture allows Read
and Write accesses to be double-data rate and burst
oriented. Accesses start at a selected column location
and continue every half-clock cycle for a programmed
number of times. The Read or Write operation begins
with an Active command to transmit the selected bank
and row (A0-A11 bits are sampled). This is followed by
a Read or Write command to sample the address bits
again to determine the first column to access. When
access to the memory is not necessary, the device can
be put into a Power Down mode in which current
consumption is minimized. Prior to normal operation,
the device must be initialized in a defined procedure to
function properly. The following sections describe the
steps of initialization, the mode register definitions,
command descriptions, and device operation.
The DDR SDRAM must be powered-on and initialized in
a series of defined steps for proper operation. First,
power is applied to VDD, and then to VDDQ. After
these have reached stable values, VREF and VTT are
ramped up. If this sequence is not followed, latch-up
could occur and cause damage to the device. The
input CKE must be asserted and held to a LVCMOS
Low level during this time to prevent unwanted commands from being executed. The outputs I/O and DQS
remain in high impedance until driven during a normal
operation. Once VDD, VDDQ, VTT, VREF, and CKE are
stable values, the clock inputs can begin to be applied.
For a time period of at least 200µs, valid CK and CK
cycles must be applied prior to any command being
issued to the device. CKE needs to then be raised to
SSTL 2 logic High and issue a NOP or Deselect
command to initialize the internal logic of the DRAM.
Next, a Pre-charge All command is given to the device,
followed by a NOP/Deselect command on each clock
cycle for at least tRP. The Load Extended Mode
Register should be issued to enable DLL, followed by
another series of NOP/Deselect commands for at least
tMRD. After this time, the Load Mode Register command should be issued to reset the DLL, again followed
by a series of NOP or Deselect commands for at least
tMRD. (Note: whenever the DLL is reset, 200 clock
cycles must occur prior to any Read command.) The
Pre-charge command is then issued, with NOP/
Deselect commands for at least tRP. Next, two AutoRefresh commands are issued, each followed by NOP/
Deselect commands for at least tRFC. At this point,
the JEDEC specification recommends that a DDR
SDRAM receive another Load Mode Register command
to clear the DLL, with NOP/Deselect commands for at
least tMRD. The device is now ready to receive a valid
command for normal operation.
POWER-UP SEQUENCE AFTER CKE GOES HIGH
10
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. 00A
04/04/06
ISSI
IS43R16800A-6
MODE REGISTER DEFINITION
®
loaded only if all banks are idle. After the Load
Mode Register command, a minimum time of tMRD
must pass before the subsequent command is
issued.
The mode register allows configuration of the operating mode of the DDR SDRAM. This register is loaded
as a step in the normal initialization of the device.
The Load Mode Register command samples the
values on inputs A0-A11, BA0 (Low) and BA1 (Low)
and stores them as register values M0-M13. The
values in the register determine the burst length,
burst type, CAS latency timing, and DLL Reset/Clear.
It should be noted that some bit values are reserved
and should not be loaded into the register. The data
in the mode register is retained until it is re-loaded or
the DDR SDRAM loses its power (except for bit M8,
which is cleared automatically). The register can be
CAS LATENCY
After a Read command is issued to the device, a
latency of several clock cycles is necessary prior to
the validity of data on the data bus. Also known as
CAS Latency (CL), the value can be configured as 2 or
2.5, via the bits M4-M6 loaded into the register. The
maximum frequency allowed with the CAS setting is
defined in AC Electrical Characteristics. If CL values
are not defined, the device may not function properly.
MODE REGISTER DEFINITION
BA1 BA0 A11 A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
Address Bus (Ax)
Mode Register (Mx)
Burst Length
M2
M1
M0
M3=0
M3=1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
Reserved
2
4
8
Reserved
Reserved
Reserved
Reserved
Reserved
2
4
8
Reserved
Reserved
Reserved
Reserved
Burst Type
M3
Type
0
1
Sequential
Interleaved
Latency Mode
M6 M5 M4
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
CAS Latency
Reserved
Reserved
2
Reserved
Reserved
Reserved
2.5
Reserved
Operating Mode
M8 M7
M6-M0
Mode
0
Defined
Standard Operation
1 0
— —
Defined
—
Standard Operation w/DLL Reset
All Other States Reserved
0
Operating Mode
M13 M12
M10
M9
0
0
M11
0
0
0
Mode
Standard operation
—
—
—
—
—
All Other States Reserved
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. 00A
04/04/06
11
ISSI
IS43R16800A-6
®
BURST LENGTH
BURST TYPE
The highest access throughput of this device can be
achieved by using a burst of either Read or Write
accesses. The number of accesses in each burst
would be pre-configured to be 2, 4, or 8, as shown in
Mode Register Definition (bits M0-M2). When a Read or
Write command is given to the device, the address bits
A0-A8 (x16) select the block of columns and the starting
column for the subsequent burst. The accesses in this
burst can only reference the selected block, and may
wrap-around if a boundary is reached. The Burst Definition table indicates the relationship between the least
significant address bits and the starting column. The
most significant address bits can select any unique
block of columns in the currently activated row.
Bursts can be made in either of two types: sequential or
interleaved. The burst type is programmed during a Load
Mode Register command (bit M3). During a Read or
Write burst, the order of accesses is determined by burst
length, starting column, and burst type, as indicated in
the Burst Definition table.
DLL RESET/CLEAR
To cause a DLL reset, the bit M8 is set to 1 in the
Load Mode Register command. When the DLL is
reset, 200 clock cycles are required to occur prior to
any Read operation. To clear the DLL for normal
operation, the bit M8 is set to 0. This device does not
require it, but JEDEC specifications require that any
time that the DLL is reset, it later be cleared prior for
normal operation.
BURST DEFINITION
Burst
Starting Column
Length
Address
Sequential
Interleaved
0
0-1
0-1
1
1-0
1-0
0
0
0-1-2-3
0-1-2-3
0
1
1-2-3-0
1-0-3-2
1
0
2-3-0-1
2-3-0-1
1
1
3-0-1-2
3-2-1-0
0
0
0
0-1-2-3-4-5-6-7
0-1-2-3-4-5-6-7
0
0
1
1-2-3-4-5-6-7-0
1-0-3-2-5-4-7-6
0
1
0
2-3-4-5-6-7-0-1
2-3-0-1-6-7-4-5
0
1
1
3-4-5-6-7-0-1-2
3-2-1-0-7-6-5-4
1
0
0
4-5-6-7-0-1-2-3
4-5-6-7-0-1-2-3
1
0
1
5-6-7-0-1-2-3-4
5-4-7-6-1-0-3-2
1
1
0
6-7-0-1-2-3-4-5
6-7-4-5-2-3-0-1
1
1
1
7-0-1-2-3-4-5-6
7-6-5-4-3-2-1-0
A2
A1
2
4
8
12
Order of Accesses in a Burst
A0
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. 00A
04/04/06
ISSI
IS43R16800A-6
®
EXTENDED MODE REGISTER DEFINITION
DLL Enable/Disable
The Extended Mode Register is a second register to
enable additional functions of the DDR SDRAM. This
register is loaded as a step in the normal initialization
of the device. The Load Extended Mode Register
command samples the values on inputs A0-A11, BA0
(High) and BA1 (Low) and stores them as register
values E0-E13. The additional functions are DLL
enable/disable and output drive strength. Similarly to
the Load Mode Register, the Load Extended Mode
Register has reserved bit values, a bank idle prerequisite, and a tMRD time requirement. The data in
the mode register is retained until it is reloaded or the
device loses its power.
When the Load Extended Mode Register command is
issued, DLL should be enabled (E0 = 0). Normal
operation of the device requires this, but DLL can be
disabled for debugging or evaluation, if necessary.
Output Drive Strength
Normal drive strength for the outputs is specified as
SSTL 2. However, there is an option for reduced drive
strength included.
EXTENDED MODE REGISTER DEFINITION
BA1 BA0 A11 A10
A9
A8
A7
A6
A5
A4
A3
A2
Operating Mode
E13
0
—
E12
1
—
E11
0
—
E10
0
—
E9
0
—
E8
0
—
E7
0
—
Mode
Standard Operation
All Other States Reserved
A1
A0
Address Bus (Ax)
Mode Register (Ex)
DLL
E0
0
1
Status
Enable
Disable
Drive Strength
E6
0
0
—
E5
0
0
—
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. 00A
04/04/06
E4
0
0
—
E3
0
0
—
E2
0
0
—
E1
0
1
—
Type
Full Strength
Weak
All Other States Reserved
13
ISSI
IS43R16800A-6
COMMANDS
All commands described in this section should be
issued only when the initialization sequence is
obeyed.
Deselect (DESL)
This feature blocks unwanted commands from being
executed. Chip select (CS) must be taken High to
cause Deselect. Operations that are underway are
not affected.
No Operation (NOP)
NOP is a command that prevents new commands from
being executed. CS must be Low, while RAS, CAS,
and WE must be High to issue NOP. NOP or Deselect
commands must be issued during wait states to allow
operations that are underway to continue uninterrupted.
Load Mode Register (MRS)
The Base Mode Register is loaded during a step of
initialization to configure the DDR SDRAM. Load
Mode Register is issued when BA0 and BA1 are Low,
and A0-A11 are selected according to the Mode Register
Definition.
Load Extended Mode Register (EMRS)
The Extended Mode Register is loaded during a step
of initialization to enable the DLL of the device. Load
Extended Mode Register is issued when BA0 is High,
BA1 is Low, and A0-A11 are selected according to the
Extended Mode Register Definition.
Read (READ/READA)
The Read command is used to begin a burst read
access. When the command is given to the device,
the BA0 and BA1 inputs select the bank, and address
bits A0-A8 (x16) select the block of columns and the
starting column for the subsequent burst. The crossing of the CK and CK signals will cause the output
values on the I/O pins to be valid. The Auto Precharge function is one option in the Read command. If
the Auto Pre-charge is enabled, the currently selected
row will be pre-charged following the Read burst. If
the function is not enabled, the selected row will
remain open for further accesses at the end of the
Read burst.
14
®
Write (WRIT/WRITA)
The Write command is used to begin a burst write
access. When the command is given to the device,
the BA0 and BA1 inputs select the bank, and address
bits A0-A8 (x16) select the block of columns and the
starting column for the subsequent burst. The rising
edge on the Data Strobe input(s) will cause the input
values on the Data Mask pin(s) and I/O pins to be
sampled for the write operation. The Auto Pre-charge
function is one option in the Write command. If the
Auto Pre-charge is enabled, the currently selected row
will be Pre-charged following the Write burst. If the
function is not enabled, the selected row will remain
open for further accesses at the end of the Write
burst.
Pre-charge (PRE/PALL)
A Pre-charge command will de-activate an open row in
a bank. The input A10 (x16) is sampled at this time to
determine whether Pre-charge is applied to a single
bank or all banks. After tRP, the bank has been precharged. It is de-activated, and goes into the idle
state and must be activated before any Read or Write
command can be issued to it. A Pre-charge command
is treated as a NOP if either (a) the specified bank is
already undergoing Pre-charge, or (b) the specified
bank has no open row.
Auto Pre-charge
Auto Pre-charge is a feature that can be enabled as
an option in a Read or Write command. If the input
value on A10 (x16) is High during a Read or Write
command, an automatic Pre-charge will occur just after
the memory burst is completed. If the input value on
A10 (x16) is Low, no Pre-charge will occur. With Auto
Pre-charge, a minimum time of tRP must pass before the
next command is issued to the same bank.
Active (ACT)
The Active command opens a row in preparation for a
Read or Write burst. The row stays open for accesses
until the bank receives a Pre-charge command. Other
rows in the bank cannot be opened until the bank is
de-activated with a Pre-charge command and another
Active command is issued.
Burst Terminate (BST)
The Burst Terminate command truncates the burst of
the most recently issued Read command (with Auto
Pre-charge disabled). The open row being accessed
in the Read burst remains open.
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. 00A
04/04/06
IS43R16800A-6
Auto Refresh (REF)
The DDR SDRAM is issued the Auto Refresh command during normal operation to maintain data in the
memory array. All the banks must be idle for the
command to be executed. The device has 4096
refresh cycles every 64ms.
Self Refresh (SELF)
To issue the Self Refresh command, CKE must be
Low. When the DDR SDRAM is in Self Refresh mode,
it retains the data contents without external clocking,
and ignores other input signals. The DLL is disabled
upon entering the Self Refresh mode, and is enabled
again upon leaving the mode. To exit Self Refresh, all
inputs must be stable prior to CKE going High. Next,
a NOP command command must be issued on each
clock cycle for at least tSNR to ensure that internal refresh
operations are completed. To prepare for a memory
access, the DDR SDRAM must receive a DLL reset
followed by a NOP command for 200 clock cycles.
DEVICE OPERATION
Bank and Row Activation
An Active command must be issued to the DDR
SDRAM to open a bank and row prior to an access.
The row will be available for a Read or Write command once a time tRCD has occurred. The Active
command is depicted in the figure. As CK goes High,
CS and RAS are Low, while CKE, WE, and CAS are
High. Upon issuing the Active command, the values on
the address inputs specify the row, and BA0 and BA1
specify the bank. When an Active command is issued
for a bank and row, another row in that same bank may
be activated after a time tRC. When an Active command
is issued for a bank and row, a row in a different bank
may be activated after a time tRRD. (Note: to ensure
that time requirement tRCD, tRC, or tRRD is met, NOP
commands should be issued for a whole number of clock
cycles that is greater than the time requirement (ie.
tRCD) divided by the clock period.)
Read Operation
A Read command starts a burst from an activated row.
The Read command is depicted in the figure. As CK
goes High, CS and CAS are Low, while RAS, CKE,
and WE are High. The values on the inputs BA0 and
BA1 specify the bank to access, and the address
inputs specify the starting column in the open row. If
Auto Pre-charge is enabled in the Read command, the
open row will be pre-charged after completion of the Read
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. 00A
04/04/06
ISSI
®
burst. Unless stated otherwise, all timing diagrams for
Read operations have disabled Auto Pre-charge.
The Read command causes data to be retrieved and
placed in the pipeline. The subsequent command can
be NOP, Read, or Terminate Burst. The data from the
starting column specified in the Read command
appears on I/O pins following a CAS latency of after
the Read command. On each CK and CK crossing, the
data from the next column in the burst sequence is
output from the pipeline until the burst is completed
(see Read Burst, Non-consecutive Read Burst, and
Consecutive Read Burst). There are two cases in
which a full Read burst length is not completed. The
first is when the data retrieved from a subsequent
Read burst interrupts the previous burst (see Random
Read Accesses). The second is when a subsequent
Burst Terminate command truncates the burst (see
Terminating a Read Burst and Read to Write). The
Burst Terminate and Read commands obey the same
CAS latency timing such that they should be issued x
cycles after a previous Read command, where x is the
number of pairs of columns to output. By following a
desired command sequence, continuous data can be
output with either whole Read bursts or truncated
Read bursts. Whenever a Read burst finishes and no
other commands have been initiated, the I/O returns to
High-Z.
If Auto Pre-charge is not enabled in the Read burst,
the Pre-charge command can be issued separately
following the Read command. The Pre-charge command should be received by the device x cycles after
the Read command, where x is the desired number of
pairs of columns to output during the Read burst.
After the Pre-charge command, it is necessary to wait
until both tRAS and tRP have been met before issuing
a new command to the same bank.
Data Strobe output is driven synchronously with the
output data on the I/O pins. The Low portion of the
Data Strobe just prior to the first output data is the
Read Pre-amble; and the Low portion coinciding with
the last output data is the Read Post-amble. Before
any Write command can be executed, any previous
Read burst must have been completed normally or
truncated by a Burst Terminate command. In the
diagram Read to Write, a Burst Terminate command is
issued to truncate a Read Burst early, and begin a
Write operation. After the Write command, a time
tDQSS is required prior to latching the data on the I/O.
15
ISSI
IS43R16800A-6
Write Operation
A Write command starts a burst from an activated row.
The Write command is depicted in the figure. As CK
goes High, CS, WE, and CAS are Low, while CKE and
RAS are High. The values on the inputs BA0 and BA1
specify the bank to access, and the address inputs
specify the starting column in the open row. If Auto
Pre-charge is enabled in the Write command, the
open row will be pre-charged after completion of the
Write burst and time tWR. Unless stated otherwise, all
timing diagrams for Write operations have disabled
Auto Pre-charge.
The Write command in conjunction with Data Strobe
inputs causes data to be latched and placed in the
pipeline. The Low portion of the Data Strobe between
the Write command and the first rising edge of the
strobe is the Write Pre-amble; and the Low portion
following the last input data is the Write Post-amble.
A minimum time of tDQSS after the Write, the next
command can be NOP or Write. The data that is to be
written to the starting column specified in the Write
command will be latched upon the first rising edge of
Data Strobe input(s) LDQS, UDQS (x16) after that Write
command. On each Data Strobe transition from Low-toHigh or High-to-Low, the input values on the I/O are
sampled, and enter pipeline to be written in the predetermined burst sequence (see Write Burst, Consecutive Write to Write, and Non-consecutive Write to Write).
A new Write command can be issued x cycles after a
previous Write command, where x is the number of pairs
of columns to input. By following a desired command
sequence, continuous data can be input with either whole
Write bursts or truncated Write bursts. Whenever a Write
burst finishes and no other commands have been
initiated, the I/O returns to High-Z.
®
should be obeyed before issuing the Pre-charge command (see Write to Pre-charge, Non-truncated). The
period tWR begins on the first positive clock edge after
the last data input has been latched. The Write burst
can be truncated deliberately by using the Data Mask
feature and a Pre-charge command with an earlier timing
(see Write to Pre-charge, Truncated). After the Precharge command, it is necessary to wait until tRP has
been met before issuing a new command to the same
bank.
Power Down Operation
When the DDR SDRAM enters Power Down mode,
power consumption is greatly reduced. To enter the
mode, several conditions must be met. There must be
neither a Read operation, nor a Write operation
underway in the device at CK positive edge n – 1, with
CKE stable High. Prior to CK positive edge n, CKE
should go Low. A Power Down mode is entered if the
appropriate command is issued as CK n goes High. (If
the command at CK n is Auto Refresh, the SDRAM
enters Self Refresh mode.) If the command at CK n is
NOP or Deselect, the device will enter Pre-charge Power
Down mode or Active Power Down mode. While in a
Power Down mode, CKE must be stable Low, and CK
and CK signals maintained, while other inputs are
ignored. Pre-charge Power Down mode conserves
additional power by freezing the DLL. To exit the Power
Down mode, normal voltages and clock frequency are
applied. Prior to CK positive edge n, CKE should go
High. A NOP or Deselect command at CK n, allows a
valid command to be issued at CK positive edge n + 1.
(If exiting Self Refresh mode, the DLL is automatically
enabled, and the device must be prepared according to
the section describing Self Refresh.)
Pre-charge Operation
A Write burst may be followed by Read command, with
or without truncating the Write burst. To avoid truncating the input data, the timing parameter tWTR should
be obeyed before issuing the Read command (see
Write to Read, Non-truncated). The period tWTR
begins on the first positive clock edge after the last
data input has been latched. The Write burst can be
truncated deliberately by using the Data Mask feature
and a Read command with an earlier timing (see Write
to Read, Truncated).
If Auto Pre-charge is not enabled in the Write burst,
the Pre-charge command can be issued separately
some time following the Write command. The procedure to execute it is similar to the procedure to transition from a Write burst to a Read burst. To avoid
truncating the input data, the timing parameter tWR
16
When this command is issued, either a particular
bank, or all four banks will be de-activated after a time
period of tRP. The bank(s) will be available for a row
access until that time has occurred. The Pre-charge
command is depicted in the figure. As CK goes High,
CS, RAS, and WE are Low, while CKE and CAS are
High. The values on the address inputs are Don’t Care,
except for the input A10 (x16), which determines whether
a single bank is selected for Pre-charge, or all four
banks. If A10 is Low, the inputs BA0 and BA1 select the
single bank; however, if A10 is High, BA0 and BA1 are
Don’t Care. Once any bank has been pre-charged, it
becomes idle. Before any row can have a Read or Write
access, it must be activated.
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. 00A
04/04/06
ISSI
IS43R16800A-6
®
COMMAND TRUTH TABLE
DDR SDRAM recognize the following commands specified by the CS, RAS, CAS, WE and address pins. All other
combinations than those in the table below are illegal.
CKE
Command
Ignore command
No operation
Burst stop in read command
Column address and read command
Read with auto-precharge
Column address and write command
Write with auto-precharge
Row address strobe and bank active
Symbol n – 1
DESL
H
NOP
H
BST
H
READ
H
READA
H
WRIT
H
WRITA
H
ACT
H
n
H
H
H
H
H
H
H
H
Precharge select bank
Precharge all bank
Refresh
PRE
PALL
REF
SELF
MRS
EMRS
H
H
H
L
H
H
Mode register set
H
H
H
H
H
H
CS RAS CAS
H
x
x
L
H
H
L
H
H
L
H
L
L
H
L
L
H
L
L
H
L
L
L
H
L
L
L
L
L
L
L
L
L
L
L
L
H
H
L
L
L
L
WE BA1
x
x
H
x
L
x
H
V
H
V
L
V
L
V
H
V
L
L
H
H
L
L
BA0 AP
x
x
x
x
x
x
V
L
V
H
V
L
V
H
V
V
V
x
x
x
L
L
V
x
x
x
L
H
L
H
x
x
L
L
Address
x
x
x
V
V
V
V
V
x
x
x
x
V
V
Remark: H: VIH. L: VIL. ×: VIH or VIL V: Valid address input
Note: The CKE level must be kept for 1 CK cycle at least.
CKE TRUTH TABLE
CKE
Current state
Idle
Idle
Idle
Command
Auto-refresh command (REF)
Self-refresh entry (SELF)
Power down entry (PDEN)
Self refresh
Self refresh exit (SELFX)
Power down
Power down exit (PDEX)
n–1
H
H
H
H
L
L
L
L
n
H
L
L
L
H
H
H
H
CS
L
L
L
H
L
H
L
H
RAS
L
L
H
x
H
x
H
x
CAS
L
L
H
x
H
x
H
x
WE
H
H
H
x
H
x
H
x
Address Notes
x
2
x
2
x
x
x
x
x
x
Remark: H: VIH. L: VIL. ×: VIH or VIL.
Notes:
1. All the banks must be in IDLE before executing this command.
2. The CKE level must be kept for 1 CK cycle at least.
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. 00A
04/04/06
17
ISSI
IS43R16800A-6
®
Function Truth Table
The following tables show the operations that are performed when each command is issued in each state of the
DDR SDRAM.
Current state
Precharging*
1
/CS
/RAS
/CAS
/WE
H
×
×
×
L
H
H
H
L
2
Refresh
3
(auto-refresh)*
Activating*
4
18
Next state
×
DESL
NOP
ldle
×
NOP
NOP
×
BST
ldle
ILLEGAL*
11
—
—
L
H
L
H
BA, CA, A10
READ/READA
ILLEGAL*
H
L
L
BA, CA, A10
WRIT/WRITA
ILLEGAL*
11
—
11
—
L
H
H
BA, RA
ACT
ILLEGAL*
PRE, PALL
NOP
ldle
ILLEGAL
—
NOP
ldle
L
L
H
L
BA, A10
L
L
L
×
×
H
×
×
×
×
DESL
L
H
H
H
×
NOP
NOP
L
H
H
L
×
BST
ILLEGAL*
11
—
L
H
L
H
BA, CA, A10
READ/READA
ILLEGAL*
11
—
11
ldle
L
H
L
L
BA, CA, A10
WRIT/WRITA
ILLEGAL*
L
L
H
H
BA, RA
ACT
Activating
L
L
H
L
BA, A10
PRE, PALL
NOP
—
ldle
ldle/
Self refresh
Active
L
L
L
H
×
REF, SELF
Refresh/
12
Self refresh*
L
L
L
L
MODE
MRS
Mode register set*
H
×
×
×
×
DESL
NOP
ldle
L
H
H
H
×
NOP
NOP
ldle
BST
12
ldle
L
H
H
L
×
ILLEGAL
—
L
H
L
×
×
ILLEGAL
—
L
L
×
×
×
ILLEGAL
—
H
×
×
×
×
DESL
NOP
Active
L
H
H
H
×
NOP
NOP
H
H
L
×
BST
Active
ILLEGAL*
11
—
—
L
H
L
H
BA, CA, A10
READ/READA
ILLEGAL*
11
L
H
L
L
BA, CA, A10
WRIT/WRITA
ILLEGAL*
11
—
ILLEGAL*
11
—
ILLEGAL*
11
L
5
L
Operation
L
L
Active*
H
Command
11
L
Idle*
H
Address
L
H
H
BA, RA
ACT
L
L
H
L
BA, A10
L
L
L
×
×
PRE, PALL
H
×
×
×
×
DESL
L
H
H
H
×
L
H
H
L
×
L
H
L
H
L
H
L
L
L
L
L
—
ILLEGAL
—
NOP
Active
NOP
NOP
Active
BST
ILLEGAL
Active
BA, CA, A10
READ/READA
Starting read operation Read/READA
L
BA, CA, A10
WRIT/WRITA
Write
Starting write operation recovering/
precharging
H
H
BA, RA
ACT
ILLEGAL*
L
H
L
BA, A10
PRE, PALL
Pre-charge
Idle
L
L
×
×
ILLEGAL
—
11
—
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. 00A
04/04/06
ISSI
IS43R16800A-6
Current state
Read*
6
/CS
/RAS
/CAS
/WE
Address
Command
Operation
Next state
H
×
×
×
×
DESL
NOP
Active
L
H
H
H
×
NOP
NOP
Active
L
H
H
L
×
BST
BST
Active
Active
L
H
L
H
BA, CA, A10
READ/READA
Interrupting burst read
operation to
start new read
L
H
L
L
BA, CA, A10
WRIT/WRITA
ILLEGAL*
13
—
ACT
ILLEGAL*
11
—
PRE, PALL
Interrupting burst
read operation to
start pre-charge
Precharging
ILLEGAL
—
L
L
H
H
BA, RA
L
L
H
L
BA, A10
L
L
L
×
×
Read with auto-preH
7
charge*
×
×
×
×
DESL
NOP
Precharging
L
H
H
H
×
NOP
NOP
Precharging
L
H
H
L
×
BST
ILLEGAL
L
H
L
H
BA, CA, A10
READ/READA
ILLEGAL*
14
—
L
H
L
L
BA, CA, A10
WRIT/WRITA
ILLEGAL*
14
—
—
—
Write*
8
Write recovering*
9
L
L
H
H
BA, RA
ACT
ILLEGAL*
L
L
H
L
BA, A10
PRE, PALL
ILLEGAL*
11, 14
L
L
L
×
×
H
×
×
×
×
DESL
NOP
L
H
H
H
×
NOP
NOP
L
H
H
L
×
BST
ILLEGAL
L
H
L
H
BA, CA, A10
READ/READA
L
H
L
L
BA, CA, A10
WRIT/WRITA
L
L
H
H
BA, RA
ACT
ILLEGAL*
PRE, PALL
Interrupting write
operation to start precharge.
Idle
L
H
L
BA, A10
ILLEGAL
—
Write
recovering
Write
recovering
—
Interrupting burst write
operation to
start read operation.
Interrupting burst write
operation to
start new write
operation.
11
Read/ReadA
Write/WriteA
—
L
L
L
×
×
ILLEGAL
—
H
×
×
×
×
DESL
NOP
Active
L
H
H
H
×
NOP
NOP
Active
—
L
H
H
L
×
BST
ILLEGAL
L
H
L
H
BA, CA, A10
READ/READA
Starting read operation. Read/ReadA
L
H
L
L
BA, CA, A10
WRIT/WRITA
Starting new write
operation.
L
L
H
H
BA, RA
L
L
H
L
BA, A10
L
L
L
×
×
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. 00A
04/04/06
—
11, 14
L
ACT
PRE/PALL
Write/WriteA
ILLEGAL*
11
—
ILLEGAL*
11
—
ILLEGAL
®
—
19
ISSI
IS43R16800A-6
Current state
/CS
/RAS
/CAS
/WE
Address
Command
Operation
Next state
Write with auto10
pre-charge*
H
×
×
×
×
DESL
NOP
Precharging
L
H
H
H
×
NOP
NOP
Precharging
L
H
H
L
×
BST
ILLEGAL
L
H
L
H
BA, CA, A10
READ/READA
ILLEGAL*
14
—
L
H
L
L
BA, CA, A10
WRIT/WRIT A
ILLEGAL*
14
—
—
—
—
L
L
H
H
BA, RA
ACT
ILLEGAL*
11, 14
L
L
H
L
BA, A10
PRE, PALL
ILLEGAL*
11, 14
L
L
L
×
×
ILLEGAL
®
—
H: VIH. L: VIL. ×: VIH or VIL
The DDR SDRAM is in "Precharging" state for tRP after precharge command is issued.
The DDR SDRAM reaches "IDLE" state tRP after precharge command is issued.
The DDR SDRAM is in "Refresh" state for tRFC after auto-refresh command is issued.
The DDR SDRAM is in "Activating" state for tRCD after ACT command is issued.
The DDR SDRAM is in "Active" state after "Activating" is completed.
The DDR SDRAM is in "READ" state until burst data have been output and DQ output circuits are turned
off.
7. The DDR SDRAM is in "READ with auto-precharge" from READA command until burst data has been
output and DQ output circuits are turned off.
8. The DDR SDRAM is in "WRITE" state from WRIT command to the last burst data are input.
9. The DDR SDRAM is in "Write recovering" for tWR after the last data are input.
10. The DDR SDRAM is in "Write with auto-precharge" until tWR after the last data has been input.
11. This command may be issued for other banks, depending on the state of the banks.
12. All banks must be in "IDLE".
13. Before executing a write command to stop the preceding burst read operation, BST command must be
issued.
14. The DDR SDRAM supports the concurrent auto-precharge feature, a read with auto-precharge enabled,or
a write with auto-precharge enabled, may be followed by any column command to other banks, as long as
that command does not interrupt the read or write data transfer, and all other related limitations apply.
(E.g. Conflict between READ data and WRITE data must be avoided.)
Remark:
Notes: 1.
2.
3.
4.
5.
6.
The minimum delay from a read or write command with auto precharge enabled, to a command to a
different bank, is summarized below.
From command
To command (different bank, noninterrupting command)
Minimum delay
(Concurrent AP supported)
Units
Read w/AP
Read or Read w/AP
BL/2
tCK
Write or Write w/AP
CL(rounded up)+ (BL/2)
tCK
Precharge or Activate
1
tCK
Read or Read w/AP
1 + (BL/2) + tWTR
tCK
Write w/AP
20
Write or Write w/AP
BL/2
tCK
Precharge or Activate
1
tCK
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. 00A
04/04/06
ISSI
IS43R16800A-6
®
Command Truth Table for CKE
Current State
CKE
n–1 n
Self refresh
Self refresh recovery
Power down
All banks idle
Row active
/CS
/RAS /CAS /WE Address
Operation
×
INVALID, CK (n-1) would exit self refresh
H
×
×
×
×
×
L
H
H
×
×
×
×
Self refresh recovery
L
H
L
H
H
×
×
Self refresh recovery
L
H
L
H
L
×
×
ILLEGAL
L
H
L
L
×
×
×
ILLEGAL
L
L
×
×
×
×
×
Maintain self refresh
H
H
H
×
×
×
×
Idle after tRC
H
H
L
H
H
×
×
Idle after tRC
H
H
L
H
L
×
×
ILLEGAL
H
H
L
L
×
×
×
ILLEGAL
H
L
H
×
×
×
×
ILLEGAL
H
L
L
H
H
×
×
ILLEGAL
H
L
L
H
L
×
×
ILLEGAL
H
L
L
L
×
×
×
ILLEGAL
H
×
×
×
×
×
L
H
H
×
×
×
×
L
H
L
H
H
H
×
L
L
×
×
×
×
×
H
H
H
×
×
×
Refer to operations in Function Truth Table
H
H
L
H
×
×
Refer to operations in Function Truth Table
H
H
L
L
H
×
Refer to operations in Function Truth Table
H
H
L
L
L
H
×
H
H
L
L
L
L
OPCODE Refer to operations in Function Truth Table
H
L
H
×
×
×
Refer to operations in Function Truth Table
H
L
L
H
×
×
Refer to operations in Function Truth Table
H
L
L
L
H
×
Refer to operations in Function Truth Table
H
L
L
L
L
H
Notes
INVALID, CK (n – 1) would exit power down
×
EXIT power down → Idle
Maintain power down mode
CBR (auto) refresh
Self refresh
H
L
L
L
L
L
OPCODE Refer to operations in Function Truth Table
L
×
×
×
×
×
×
Power down
H
×
×
×
×
×
×
Refer to operations in Function Truth Table
L
×
×
×
×
×
×
Power down
1
1
1
Remark: H: VIH. L: VIL. ×: VIH or VIL
Note: Self refresh can be entered only from the all banks idle state. Power down can be entered only from all
banks idle or row active state.
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. 00A
04/04/06
21
ISSI
IS43R16800A-6
®
Simplified State Diagram
SELF
REFRESH
SR ENTRY
SR EXIT
MRS
MRS
EMRS
REFRESH
IDLE
*1
AUTO
REFRESH
CKE
CKE_
IDLE
POWER
DOWN
ACTIVE
ACTIVE
POWER
DOWN
CKE_
CKE
ROW
ACTIVE
WRITE
Write
READ
WRITE
WITH
AP
WRITE
BST
READ
WITH
AP
Read
READ
READ
READ
WITH AP
WRITE
WITH AP
READ
WITH AP
PRECHARGE
WRITEA
READA
PRECHARGE
POWER
APPLIED
POWER
ON
PRECHARGE
PRECHARGE
PRECHARGE
Automatic transition after completion of command.
Transition resulting from command input.
Note: 1. After the auto-refresh operation, precharge operation is performed automatically
and enter the IDLE state.
22
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. 00A
04/04/06
; ;;
ISSI
IS43R16800A-6
®
Read/Write Operations
Bank active
A read or a write operation begins with the bank active command [ACT]. The bank active command determines a
bank address and a row address. For the bank and the row, a read or a write command can be issued tRCD after
the ACT is issued.
Read operation
The burst length (BL), the /CAS latency (CL) and the burst type (BT) of the mode register are referred when a read
command is issued. The burst length (BL) determines the length of a sequential output data by the read command
that can be set to 2, 4, or 8. The starting address of the burst read is defined by the column address, the bank select
address which are loaded via the A0 to A11 and BA0, BA1 pins in the cycle when the read command is issued. The
data output timing are characterized by CL and tAC. The read burst start CL • tCK + tAC (ns) after the clock rising
edge where the read command are latched. The DDR SDRAM output the data strobe through DQS simultaneously
with data. tRPRE prior to the first rising edge of the data strobe, the DQS are driven Low from VTT level. This low
period of DQS is referred as read preamble. The burst data are output coincidentally at both the rising and falling
edge of the data strobe. The DQ pins become High-Z in the next cycle after the burst read operation completed.
tRPST from the last falling edge of the data strobe, the DQS pins become High-Z. This low period of DQS is
referred as read postamble.
t0
CK
/CK
Command
Address
t1
t4
t5
t6
t7
t8
t9
tRCD
NOP
ACT
NOP
Row
READ
NOP
Column
tRPRE
DQS
DQ
out0 out1
BL = 2
tRPST
out0 out1 out2 out3
BL = 4
out0 out1 out2 out3 out4 out5 out6 out7
BL = 8
CL = 2
BL: Burst length
Read Operation (Burst Length)
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. 00A
04/04/06
23
;; ;;
ISSI
IS43R16800A-6
t0
t0.5
t1
t1.5
t2
t2.5
t3
t3.5
t4
t4.5
t5
®
t5.5
CK
/CK
Command
READ
NOP
tRPRE
tRPST
VTT
DQS
CL = 2
tAC,tDQSCK
out0
DQ
out1
out2
VTT
out3
tRPRE
tRPST
VTT
DQS
CL = 2.5
tAC,tDQSCK
DQ
out0
out1
out2
VTT
out3
Read Operation (/CAS Latency)
Write operation
The burst length (BL) and the burst type (BT) of the mode register are referred when a write command is issued.
The burst length (BL) determines the length of a sequential data input by the write command that can be set to 2, 4,
or 8. The latency from write command to data input is fixed to 1. The starting address of the burst read is defined by
the column address, the bank select address which are loaded via the A0 to A11, BA0 to BA1 pins in the cycle when
the write command is issued. DQS should be input as the strobe for the input-data and DM as well during burst
operation. tWPRE prior to the first rising edge of the DQS should be set to Low and tWPST after the last falling edge
of the data strobe can be set to High-Z. The leading low period of DQS is referred as write preamble. The last low
period of DQS is referred as write postamble.
t0
tn tn+0.5 tn+1
t1
tn+2
tn+3
tn+4
tn+5
CK
/CK
Command
Address
tRCD
NOP
ACT
NOP
Row
WRITE
NOP
Column
tWPRE
tWPRES
DQS
DQ
BL = 2
BL = 4
BL = 8
in0
in1
tWPST
in0
in1
in2
in3
in0
in1
in2
in3
in4
in5
in6
in7
BL: Burst length
Write Operation
24
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. 00A
04/04/06
ISSI
IS43R16800A-6
®
Burst Stop
Burst stop command during burst read
The burst stop (BST) command is used to stop data output during a burst read. The BST command stops the burst
read and sets the output buffer to High-Z. tBSTZ (= CL) cycles after a BST command issued, the DQ pins become
High-Z. The BST command is not supported for the burst write operation. Note that bank address is not referred
when this command is executed.
t0
t0.5
t1
t1.5
t2
t2.5
t3
t3.5
t4
t4.5
t5
t5.5
CK
/CK
Command
READ
BST
NOP
tBSTZ
2 cycles
DQS
CL = 2
out0
DQ
out1
tBSTZ
2.5 cycles
DQS
CL = 2.5
out0
DQ
out1
CL: /CAS latency
Burst Stop during a Read Operation
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. 00A
04/04/06
25
ISSI
IS43R16800A-6
®
Auto Precharge
Read with auto-precharge
The precharge is automatically performed after completing a read operation. The precharge starts tRPD (BL/2)
cycle after READA command input. tRAP specification for READA allows a read command with auto precharge to be
issued to a bank that has been activated (opened) but has not yet satisfied the tRAS (min) specification. A column
command to the other active bank can be issued the next cycle after the last data output. Read with auto-precharge
command does not limit row commands execution for other bank. Refer to ‘Function truth table and related
note(Notes.*14).
CK
/CK
tRAP (min) = tRCD (min)
Command
ACT
tRP (min)
tRPD
2 cycles (= BL/2)
ACT
NOP
READA
DQS
tAC,tDQSCK
DQ
out0
Note: Internal auto-precharge starts at the timing indicated by "
out1
out2
out3
".
Read with auto-precharge
Write with auto-precharge
The precharge is automatically performed after completing a burst write operation. The precharge operation is
started (BL/ 2 + 3) cycles after WRITA command issued. A column command to the other banks can be issued the
next cycle after the internal precharge command issued. Write with auto-precharge command does not limit row
commands execution for other bank. Refer to the ‘Read with Auto-Precharge Enabled, Write with Auto-Precharge
Enabled’ section. Refer to ‘Function truth table and related note(Notes.*14)‘.
CK
/CK
tRAS (min)
tRP
tRCD (min)
Command
ACT
NOP
NOP
WRITA
ACT
BL/2 + 3 cycles
DM
DQS
DQ
in1
in2
Note: Internal auto-precharge starts at the timing indicated by "
in3
in4
BL = 4
".
Burst Write (BL = 4)
26
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. 00A
04/04/06
;
;;;;
ISSI
IS43R16800A-6
®
Command Intervals
A Read command to the consecutive Read command Interval
Destination row of the
consecutive read command
Bank
address
Row address State
1.
Same
Same
ACTIVE
2.
Same
Different
—
3.
Different
Any
ACTIVE
IDLE
t0
Operation
The consecutive read can be performed after an interval of no less than 1 cycle to
interrupt the preceding read operation.
Precharge the bank to interrupt the preceding read operation. tRP after the
precharge command, issue the ACT command. tRCD after the ACT command, the
consecutive read command can be issued. See ‘A read command to the
consecutive precharge interval’ section.
The consecutive read can be performed after an interval of no less than 1 cycle to
interrupt the preceding read operation.
Precharge the bank without interrupting the preceding read operation. tRP after
the precharge command, issue the ACT command. tRCD after the ACT command,
the consecutive read command can be issued.
t3
t4
READ
READ
t5
t6
t7
t8
t9
CK
/CK
Command
ACT
Address
Row
NOP
NOP
Column A Column B
BA
out out
A0 A1
DQ
Column = A Column = B
Read
Read
out
B0
Column = A
Dout
out
B1
out
B2
out
B3
Column = B
Dout
DQS
Bank0
Active
CL = 2
BL = 4
Bank0
READ to READ Command Interval (same ROW address in the same bank)
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. 00A
04/04/06
27
ISSI
IS43R16800A-6
t0
t1
t2
t3
t4
t5
ACT
NOP
ACT
NOP
READ
READ
t6
t7
®
t9
t8
CK
/CK
Command
Address
Row0
Row1
NOP
Column A Column B
BA
DQ
Column = A Column = B
Read
Read
out out
A0 A1
Bank0
Dout
out out out out
B0 B1 B2 B3
Bank3
Dout
DQS
Bank0
Active
Bank3
Active
Bank0
Read
Bank3
Read
CL = 2
BL = 4
READ to READ Command Interval (different bank)
28
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. 00A
04/04/06
;;;;;
ISSI
IS43R16800A-6
®
A Write command to the consecutive Write command Interval
Destination row of the consecutive write
command
Bank
address
1.
Same
2.
Same
3.
Different
Row address State
Operation
Same
ACTIVE
Different
—
Any
ACTIVE
The consecutive write can be performed after an interval of no less than 1 cycle to
interrupt the preceding write operation.
Precharge the bank to interrupt the preceding write operation. tRP after the
precharge command, issue the ACT command. tRCD after the ACT command, the
consecutive write command can be issued. See ‘A write command to the
consecutive precharge interval’ section.
The consecutive write can be performed after an interval of no less than 1 cycle to
interrupt the preceding write operation.
Precharge the bank without interrupting the preceding write operation. tRP after
the precharge command, issue the ACT command. tRCD after the ACT command,
the consecutive write command can be issued.
IDLE
t0
CK
/CK
Command
Address
BA
DQ
ACT
Row
tn
NOP
WRIT
tn+1
tn+3
tn+4
tn+5
tn+6
NOP
WRIT
Column A Column B
inA0 inA1 inB0 inB1 inB2 inB3
Column = A
Write
DQS
tn+2
Column = B
Write
Bank0
Active
BL = 4
Bank0
WRITE to WRITE Command Interval (same ROW address in the same bank)
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. 00A
04/04/06
29
;;; ;;;
ISSI
IS43R16800A-6
CK
/CK
Command
Address
BA
DQ
t0
t1
t2
ACT
NOP
ACT
Row0
Row1
tn
NOP
WRIT
tn+1
tn+3
tn+4
tn+5
NOP
WRIT
Column A Column B
inA0 inA1 inB0 inB1 inB2 inB3
Bank0
Write
DQS
tn+2
®
Bank0
Active
Bank3
Write
Bank3
Active
BL = 4
Bank0, 3
WRITE to WRITE Command Interval (different bank)
30
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. 00A
04/04/06
ISSI
IS43R16800A-6
®
A Read command to the consecutive Write command interval with the BST command
Destination row of the consecutive write
command
Bank
address
Row address State
1.
Same
Same
ACTIVE
2.
Same
Different
—
3.
Different
Any
ACTIVE
IDLE
Operation
Issue the BST command. tBSTW (≥ tBSTZ) after the BST command, the
consecutive write command can be issued.
Precharge the bank to interrupt the preceding read operation. tRP after the
precharge command, issue the ACT command. tRCD after the ACT command, the
consecutive write command can be issued. See ‘A read command to the
consecutive precharge interval’ section.
Issue the BST command. tBSTW (≥ tBSTZ) after the BST command, the
consecutive write command can be issued.
Precharge the bank independently of the preceding read operation. tRP after the
precharge command, issue the ACT command. tRCD after the ACT command, the
consecutive write command can be issued.
t0
t1
t2
t3
READ
BST
NOP
WRIT
t4
t5
t6
t7
t8
CK
/CK
Command
NOP
tBSTW (≥ tBSTZ)
DM
tBSTZ (= CL)
DQ
DQS
out0 out1
in0
in1
in2
in3
High-Z
OUTPUT
INPUT
BL = 4
CL = 2
READ to WRITE Command Interval
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. 00A
04/04/06
31
ISSI
IS43R16800A-6
®
A Write command to the consecutive Read command interval: To complete the burst operation
Destination row of the consecutive read
command
Bank
address
Row address State
1.
Same
Same
ACTIVE
2.
Same
Different
—
3.
Different
Any
ACTIVE
Operation
To complete the burst operation, the consecutive read command should be
performed tWRD (= BL/ 2 + 2) after the write command.
Precharge the bank tWPD after the preceding write command. tRP after the
precharge command, issue the ACT command. tRCD after the ACT command, the
consecutive read command can be issued. See ‘A read command to the
consecutive precharge interval’ section.
To complete a burst operation, the consecutive read command should be
performed tWRD (= BL/ 2 + 2) after the write command.
Precharge the bank independently of the preceding write operation. tRP after the
precharge command, issue the ACT command. tRCD after the ACT command, the
consecutive read command can be issued.
IDLE
t0
t1
t2
t3
t4
t5
t6
CK
/CK
Command
WRIT
NOP
READ
NOP
tWRD (min)
BL/2 + 2 cycle
tWTR*
DM
DQ
in0
in1
in2
out0
in3
out1
out2
DQS
INPUT
OUTPUT
Note: tWTR is referenced from the first positive CK edge after the last desired data in pair tWTR.
BL = 4
CL = 2
WRITE to READ Command Interval
32
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. 00A
04/04/06
ISSI
IS43R16800A-6
®
A Write command to the consecutive Read command interval: To interrupt the write operation
Destination row of the consecutive read
command
Bank
address
Row address State
Operation
1.
Same
Same
ACTIVE
DM must be input 1 cycle prior to the read command input to prevent from being
written invalid data. In case, the read command is input in the next cycle of the
write command, DM is not necessary.
2.
Same
Different
—
—*
3.
Different
Any
ACTIVE
DM must be input 1 cycle prior to the read command input to prevent from being
written invalid data. In case, the read command is input in the next cycle of the
write command, DM is not necessary.
IDLE
—*
1
1
Note: 1. Precharge must be preceded to read command. Therefore read command can not interrupt the write
operation in this case.
WRITE to READ Command Interval (Same bank, same ROW address)
t0
t1
WRIT
READ
t2
t3
t4
t5
t6
t7
t8
CK
/CK
Command
1 cycle
NOP
CL=2
DM
DQ
in0
in1
in2
out0 out1 out2 out3
High-Z
High-Z
DQS
Data masked
BL = 4
CL= 2
[WRITE to READ delay = 1 clock cycle]
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. 00A
04/04/06
33
ISSI
IS43R16800A-6
t0
t1
t2
WRIT
NOP
READ
t3
t4
t5
t6
t7
®
t8
CK
/CK
Command
2 cycle
NOP
CL=2
DM
in0
DQ
in1
in2
High-Z
out0 out1 out2 out3
in3
High-Z
DQS
Data masked
BL = 4
CL= 2
[WRITE to READ delay = 2 clock cycle]
t0
t1
t2
t3
t4
t5
t6
t7
t8
CK
/CK
Command
WRIT
NOP
READ
3 cycle
NOP
CL=2
tWTR*
DM
DQ
in0
in1
in2
in3
out0 out1 out2 out3
DQS
Data masked
Note: tWTR is referenced from the first positive CK edge after the last desired data in pair tWTR.
BL = 4
CL= 2
[WRITE to READ delay = 3 clock cycle]
34
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. 00A
04/04/06
ISSI
IS43R16800A-6
®
A Read command to the consecutive Precharge command interval (same bank): To output all data
To complete a burst read operation and get a burst length of data, the consecutive precharge command must be
issued tRPD (= BL/ 2 cycles) after the read command is issued.
t0
t1
t2
t3
READ
NOP
PRE/
PALL
t4
t5
t6
t7
t8
CK
/CK
Command
NOP
DQ
NOP
out0 out1 out2 out3
DQS
tRPD = BL/2
READ to PRECHARGE Command Interval (same bank): To output all data (CL = 2, BL = 4)
t0
t1
t2
t3
NOP
READ
NOP
PRE/
PALL
t4
t5
t6
t7
t8
CK
/CK
Command
DQ
NOP
out0 out1 out2 out3
DQS
tRPD = BL/2
READ to PRECHARGE Command Interval (same bank): To output all data (CL = 2.5, BL = 4)
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. 00A
04/04/06
35
ISSI
IS43R16800A-6
®
READ to PRECHARGE Command Interval (same bank): To stop output data
A burst data output can be interrupted with a precharge command. All DQ pins and DQS pins become High-Z tHZP
(= CL) after the precharge command.
t0
t1
t2
t3
READ
PRE/PALL
t4
t5
t6
t7
t8
CK
/CK
Command
NOP
DQ
NOP
High-Z
out0 out1
High-Z
DQS
tHZP
READ to PRECHARGE Command Interval (same bank): To stop output data (CL = 2, BL = 2, 4, 8)
t0
t1
t2
t3
READ
PRE/PALL
t4
t5
t6
t7
t8
CK
/CK
Command
NOP
NOP
CL = 2.5
DQ
out0 out1
High-Z
High-Z
DQS
tHZP
READ to PRECHARGE Command Interval (same bank): To stop output data (CL = 2.5, BL = 2, 4, 8)
36
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. 00A
04/04/06
;;;;;;;
;
ISSI
IS43R16800A-6
®
A Write command to the consecutive Precharge command interval (same bank)
The minimum interval tWPD is necessary between the write command and the precharge command.
t0
t1
t2
t3
t4
t5
t6
t7
CK
/CK
Command
WRIT
PRE/PALL
NOP
NOP
tWPD
tWR
DM
DQS
DQ
in0
in1
in2
in3
Last data input
WRITE to PRECHARGE Command Interval (same bank) (BL = 4)
Precharge Termination in Write Cycles
During a burst write cycle without auto precharge, the burst write operation is terminated by a precharge command
of the same bank. In order to write the last input data, tWR (min) must be satisfied. When the precharge command
is issued, the invalid data must be masked by DM.
t0
t1
t2
t3
t4
t5
t6
t7
CK
/CK
Command
WRIT
PRE/PALL
NOP
NOP
tWR
DM
DQS
DQ
in0
in1
in2
in3
Data masked
Precharge Termination in Write Cycles (same bank) (BL = 4)
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. 00A
04/04/06
37
ISSI
IS43R16800A-6
®
Bank active command interval
Destination row of the consecutive ACT
command
Bank
address
Row address
State
1.
Same
Any
ACTIVE
2.
Different
Any
ACTIVE
IDLE
Operation
Two successive ACT commands can be issued at tRC interval. In between two
successive ACT operations, precharge command should be executed.
Precharge the bank. tRP after the precharge command, the consecutive ACT
command can be issued.
tRRD after an ACT command, the next ACT command can be issued.
CK
/CK
Command
Address
ACTV
ACT
ACT
ROW: 0
ROW: 1
PRE
NOP
NOP
ACT
NOP
ROW: 0
BA
Bank0
Active
Bank3
Active
tRRD
Bank0
Precharge
Bank0
Active
tRC
Bank Active to Bank Active
Mode register set to Bank-active command interval
The interval between setting the mode register and executing a bank-active command must be no less than tMRD.
CK
/CK
Command
MRS
Address
CODE
NOP
NOP
BS and ROW
Mode Register Set
tMRD
38
ACT
Bank3
Active
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. 00A
04/04/06
ISSI
IS43R16800A-6
®
DM Control
DM can mask input data. In ×16 products, UDM and LDM can mask the upper and lower byte of input data,
respectively. By setting DM to Low, data can be written. When DM is set to High, the corresponding data is not
written, and the previous data is held. The latency between DM input and enabling/disabling mask function is 0.
t1
t2
t3
t4
t5
t6
DQS
DQ
Mask
Mask
DM
Write mask latency = 0
DM Control
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. 00A
04/04/06
39
;;;;;;
ISSI
IS43R16800A-6
®
Timing Waveforms
Command and Addresses Input Timing Definition
CK
/CK
tIS
Command
(/RAS, /CAS,
/WE, /CS)
tIH
VREF
tIS
tIH
VREF
Address
Read Timing Definition
tCK
/CK
CK
tCL
tCH
tRPRE
DQS
tDQSCK
tDQSCK
tDQSCK
tDQSQ
tLZ
DQ
(Dout)
tAC
tDQSCK tRPST
tDQSQ
tQH
tAC
tAC
tQH
tHZ
tDQSQ
tDQSQ tQH
tQH
Write Timing Definition
tCK
/CK
CK
DQS
tDQSS
tDQSL
tWPST
tDH
tDIPW
VREF
tDS
40
tDQSH
VREF
tDS
DM
tDSS
VREF
tWPRES
tWPRE
DQ
(Din)
tDSH
tDSS
tDH
tDIPW
tDIPW
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. 00A
04/04/06
ISSI
IS43R16800A-6
®
Read Cycle
;
;
;
;;; ;
;;
tCK
tCH tCL
CK
/CK
tRC
VIH
CKE
tRAS
tRCD
tRP
tIS tIH
tIS tIH
tIS tIH
tIS tIH
tIS tIH
tIS tIH
tIS tIH
tIS tIH
tIS tIH
tIS tIH
tIS tIH
tIS tIH
tIS tIH
tIS tIH
tIS tIH
tIS tIH
tIS tIH
tIS tIH
tIS tIH
tIS tIH
tIS tIH
tIS tIH
tIS tIH
tIS tIH
/CS
/RAS
/CAS
/WE
;
;;
;;
;
;
BA
A10
tIS tIH
tIS tIH
tIS tIH
Address
DM
DQS
DQ (output)
tRPRE
High-Z
High-Z
Bank 0
Active
Bank 0
Read
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. 00A
04/04/06
tRPST
Bank 0
Precharge
CL = 2
BL = 4
Bank0 Access
= VIH or VIL
41
ISSI
;;;
;
;
;;
IS43R16800A-6
®
Write Cycle
tCK
tCH
tCL
CK
/CK
CKE
tRC
VIH
tIS tIH
tRAS
tRCD
tRP
tIS tIH
tIS tIH
tIS tIH
tIS tIH
tIS tIH
tIS tIH
tIS tIH
tIS tIH
tIS tIH
tIS tIH
tIS tIH
tIS tIH
tIS tIH
tIS tIH
tIS tIH
tIS tIH
tIS tIH
tIS tIH
tIS tIH
tIS tIH
tIS tIH
tIS tIH
tIS tIH
tIS tIH
tIS tIH
/CS
/RAS
/CAS
/WE
BA
A10
tIS tIH
Address
tDQSS
DQS
(input)
tDQSL
tWPST
tDQSH
tDS
tDS
tDH
DM
tDS
tDH
DQ (input)
tWR
tDH
Bank 0
Active
42
Bank 0
Write
Bank 0
Precharge
CL = 2
BL = 4
Bank0 Access
= VIH or VIL
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. 00A
04/04/06
ISSI
IS43R16800A-6
®
Mode Register Set Cycle
0
/CK
CK
CKE
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
VIH
/CS
/RAS
/CAS
/WE
BA
code
Address
R: b
code
valid
C: b
DM
High-Z
DQS
High-Z
b
DQ (output)
tMRD
tRP
Mode
register
set
Precharge
If needed
Bank 3
Active
Bank 3
Read
Bank 3
Precharge
CL = 2
BL = 4
= VIH or VIL
Read/Write Cycle
/CK
CK
CKE
VIH
/CS
/RAS
/CAS
/WE
BA
Address
R:a
C:a
R:b
C:b''
C:b
DM
DQS
a
DQ (output)
High-Z
DQ (input)
Bank 0
Active
b
tRWD
Bank 0 Bank 3
Read Active
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. 00A
04/04/06
b’’
tWRD
Bank 3
Write
Bank 3
Read
Read cycle
CL = 2
BL = 4
=VIH or VIL
43
ISSI
IS43R16800A-6
®
Auto Refresh Cycle
/CK
CK
CKE
VIH
/CS
/RAS
/CAS
/WE
BA
Address
A10=1
R: b
C: b
DM
DQS
b
DQ (output)
High-Z
DQ (input)
tRP
Precharge
If needed
tRFC
Auto
Refresh
Bank 0
Active
Bank 0
Read
CL = 2
BL = 4
= VIH or VIL
44
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. 00A
04/04/06
ISSI
IS43R16800A-6
®
Self Refresh Cycle
/CK
CK
tIS
tIH
CKE
CKE = low
/CS
/RAS
/CAS
/WE
BA
Address
A10=1
R: b
C: b
DM
DQS
DQ (output)
High-Z
DQ (input)
tSNR
tRP
tSRD
Precharge
If needed
Self
refresh
entry
Self refresh
exit
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. 00A
04/04/06
Bank 0
Active
Bank 0
Read
CL = 2.5
BL = 4
= VIH or VIL
45
ISSI
IS43R16800A-6
®
ORDERING INFORMATION
Commercial Range: 0°C to +70°C
Frequency
166 MHz
166 MHz
46
Speed (ns)
6
6
Order Part No.
Package
IS43R16800A-6T
IS43R16800A-6TL
66-pin TSOP-II
66-pin TSOP-II, Lead-free
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. 00A
04/04/06
ISSI
®
PACKAGING INFORMATION
Plastic TSOP 66-pin
Package Code: T (Type II)
N
N/2+1
E1
E
Notes:
1. Controlling dimension: millimieters,
unless otherwise specified.
2. BSC = Basic lead spacing between
centers.
3. Dimensions D and E1 do not include
mold flash protrusions and should be
measured from the bottom of the
package.
4. Formed leads shall be planar with
respect to one another within 0.004
inches at the seating plane.
N/2
1
D
SEATING PLANE
A
ZD
b
e
A1
L
α
C
Plastic TSOP (T - Type II)
Millimeters
Inches
Symbol Min Max
Min
Max
Ref. Std.
No. Leads (N)
66
A
A1
A2
b
C
D
E1
E
e
L
L1
ZD
α
—
1.20
0.05 0.15
—
—
0.24 0.40
0.12 0.21
22.02 22.42
10.03 10.29
11.56 11.96
0.65 BSC
0.40 0.60
—
—
0.71 REF
0°
8°
—
0.047
0.002 0.006
—
—
0.009 0.016
0.005 0.0083
0.867 0.8827
0.395 0.405
0.455 0.471
0.026 BSC
0.016 0.024
—
—
0.028 REF
0°
8°
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. A
08/09/05
1