ISSI ® IS61LV256AL 32K x 8 LOW VOLTAGE CMOS STATIC RAM MARCH 2006 FEATURES • High-speed access times: — 10 ns • Automatic power-down when chip is deselected • CMOS low power operation — 60 µW (typical) CMOS standby — 65 mW (typical) operating • TTL compatible interface levels • Single 3.3V power supply • Fully static operation: no clock or refresh required • Three-state outputs • Lead-free available DESCRIPTION The ISSI IS61LV256AL is a very high-speed, low power, 32,768-word by 8-bit static RAM. It is fabricated using ISSI's high-performance CMOS technology. This highly reliable process coupled with innovative circuit design techniques, yields access times as fast as 8 ns maximum. When CE is HIGH (deselected), the device assumes a standby mode at which the power dissipation is reduced to 150 µW (typical) with CMOS input levels. Easy memory expansion is provided by using an active LOW Chip Enable (CE). The active LOW Write Enable (WE) controls both writing and reading of the memory. The IS61LV256AL is available in the JEDEC standard 28pin, 300-mil SOJ and the 450-mil TSOP (Type I) packages. FUNCTIONAL BLOCK DIAGRAM A0-A14 DECODER 32K X 8 MEMORY ARRAY I/O DATA CIRCUIT COLUMN I/O VDD GND I/O0-I/O7 CE OE WE CONTROL CIRCUIT Copyright © 2006 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on any published information and before placing orders for products. Integrated Silicon Solution, Inc. — 1-800-379-4774 Rev. A 03/17/06 1 ISSI IS61LV256AL PIN CONFIGURATION PIN CONFIGURATION 28-Pin SOJ 28-Pin TSOP (Type I) A14 1 28 VDD A12 2 27 WE A7 3 26 A13 A6 4 25 A8 A5 5 24 A9 A4 6 23 A11 A3 7 22 OE A2 8 21 A10 A1 9 20 CE A0 10 19 I/O7 I/O0 11 18 I/O6 I/O1 12 17 I/O5 I/O2 13 16 I/O4 GND 14 15 I/O3 PIN DESCRIPTIONS OE A11 A9 A8 A13 WE VDD A14 A12 A7 A6 A5 A4 A3 21 20 19 18 17 16 15 14 13 12 11 10 9 8 22 23 24 25 26 27 28 1 2 3 4 5 6 7 ® A10 CE I/O7 I/O6 I/O5 I/O4 I/O3 GND I/O2 I/O1 I/O0 A0 A1 A2 TRUTH TABLE A0-A14 Address Inputs Mode CE Chip Enable Input OE Output Enable Input WE Write Enable Input I/O0-I/O7 Input/Output Not Selected (Power-down) Output Disabled Read Write VDD Power GND Ground WE CE OE I/O Operation VDD Current X H X High-Z ISB1, ISB2 H H L L L L H L X High-Z DOUT DIN ICC ICC ICC ABSOLUTE MAXIMUM RATINGS(1) Symbol VDD VTERM TSTG PD IOUT Parameter Power Supply Voltage Relative to GND Terminal Voltage with Respect to GND Storage Temperature Power Dissipation DC Output Current Value –0.5 to +4.6 –0.5 to +4.6 –65 to +150 1 ±20 Unit V V °C W mA Notes: 1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 2 Integrated Silicon Solution, Inc. — 1-800-379-4774 Rev. A 03/17/06 ISSI IS61LV256AL ® OPERATING RANGE Range Commercial Industrial Ambient Temperature 0°C to +70°C –40°C to +85°C Speed (ns) 10 10 VDD(1) 3.3V, +10%, –5% 3.3V + 10%, –5% Note: 1. If operated at 12ns, VDD range is 3.3V + 10%. DC ELECTRICAL CHARACTERISTICS (Over Operating Range) Symbol Parameter Test Conditions Min. Max. Unit VOH Output HIGH Voltage VDD = Min., IOH = –2.0 mA 2.4 — V VOL Output LOW Voltage VDD = Min., IOL = 4.0 mA — 0.4 V VIH Input HIGH Voltage 2.2 VDD + 0.3 V VIL Input LOW Voltage(1) –0.3 0.8 V ILI Input Leakage GND ≤ VIN ≤ VDD Com. Ind. –1 –2 1 2 µA ILO Output Leakage GND ≤ VOUT ≤ VDD, Outputs Disabled Com. Ind. –1 –2 1 2 µA Notes: 1. VIL (min.) = –0.3V (DC); VIL (min.) = –2.0V (pulse width ≤ 2.0 ns). VIH (max.) = VDD + 0.5V (DC); VIH (max.) = VDD + 2.0V (pulse width ≤ 2.0 ns). 2. Not more than one output should be shorted at one time. Duration of the short circuit should not exceed 30 seconds. Integrated Silicon Solution, Inc. — 1-800-379-4774 Rev. A 03/17/06 3 ISSI IS61LV256AL ® POWER SUPPLY CHARACTERISTICS(1) (Over Operating Range) -10 ns Sym. Parameter Test Conditions ICC1 VDD Operating Supply Current VDD = Max., CE = VIL IOUT = 0 mA, f = 1 MHz ICC2 VDD Dynamic Operating Supply Current VDD = Max., CE = VIL IOUT = 0 mA, f = fMAX Min. Max. Unit Com. Ind. — — 20 25 mA Com. Ind. typ.(2) — — 30 35 mA 20 ISB1 TTL Standby Current (TTL Inputs) VDD = Max., VIN = VIH or VIL CE ≥ VIH, f = 0 Com. Ind. — — 1 1 mA ISB2 CMOS Standby Current (CMOS Inputs) VDD = Max., CE ≤ VDD – 0.2V, VIN ≥ VDD – 0.2V, or VIN ≤ 0.2V, f = 0 Com. Ind. typ.(2) — — 40 50 µA 2 Notes: 1. At f = fMAX, address and data inputs are cycling at the maximum frequency, f = 0 means no input lines change. 2. Typical values are measured at VDD = 3.3V, TA = 25oC and not 100% tested. CAPACITANCE(1,2) Symbol Parameter CIN Input Capacitance COUT Output Capacitance Conditions Max. Unit VIN = 0V 6 pF VOUT = 0V 5 pF Notes: 1. Tested initially and after any design or process changes that may affect these parameters. 2. Test conditions: TA = 25°C, f = 1 MHz, VDD = 3.3V. 4 Integrated Silicon Solution, Inc. — 1-800-379-4774 Rev. A 03/17/06 ISSI IS61LV256AL ® READ CYCLE SWITCHING CHARACTERISTICS(1) (Over Operating Range) -10 ns Symbol Parameter -12 ns Min. Max. Min. Max. Unit tRC Read Cycle Time 10 — 12 — ns tAA Address Access Time — 10 — 12 ns tOHA Output Hold Time 2 — 2 — ns tACE CE Access Time — 10 — 12 ns OE Access Time — 5 — 5 ns OE to Low-Z Output 0 — 0 — ns tHZOE OE to High-Z Output — 5 — 5 ns tLZCE(2) CE to Low-Z Output 3 — 3 — ns tHZCE CE to High-Z Output — 5 — 6 ns tPU CE to Power-Up 0 — 0 — ns tPD CE to Power-Down — 10 — 12 ns tDOE tLZOE (2) (2) (2) (3) (3) Notes: 1. Test conditions assume signal transition times of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V and output loading specified in Figure 1. 2. Tested with the load in Figure 2. Transition is measured ±200 mV from steady-state voltage. Not 100% tested. 3. Not 100% tested. AC TEST CONDITIONS Parameter Input Pulse Level Input Rise and Fall Times Input and Output Timing and Reference Levels Output Load Unit 0V to 3.0V 3 ns 1.5V See Figures 1 and 2 AC TEST LOADS 319 Ω 319 Ω 3.3V 3.3V OUTPUT OUTPUT 30 pF Including jig and scope 353 Ω Figure 1. Integrated Silicon Solution, Inc. — 1-800-379-4774 Rev. A 03/17/06 5 pF Including jig and scope 353 Ω Figure 2. 5 ISSI IS61LV256AL ® AC WAVEFORMS READ CYCLE NO. 1(1,2) t RC ADDRESS t AA t OHA t OHA DOUT DATA VALID PREVIOUS DATA VALID READ1.eps READ CYCLE NO. 2(1,3) t RC ADDRESS t AA t OHA OE t HZOE t DOE t LZOE CE t LZCE DOUT t ACE HIGH-Z t HZCE DATA VALID CE_RD2.eps Notes: 1. WE is HIGH for a Read Cycle. 2. The device is continuously selected. OE, CE = VIL. 3. Address is valid prior to or coincident with CE LOW transitions. 6 Integrated Silicon Solution, Inc. — 1-800-379-4774 Rev. A 03/17/06 ISSI IS61LV256AL ® WRITE CYCLE SWITCHING CHARACTERISTICS(1,2) (Over Operating Range) -10 ns Symbol Parameter -12 ns Min. Max. Min. Max. Unit tWC Write Cycle Time 10 — 12 — ns tSCE CE to Write End 8 — 8 — ns tAW Address Setup Time to Write End 8 — 8 — ns tHA Address Hold from Write End 0 — 0 — ns tSA Address Setup Time 0 — 0 — ns tPWE1 WE Pulse Width (OE HIGH) 7 — 8 — ns tPWE2 WE Pulse Width (OE LOW) 10 — 12 — ns tSD Data Setup to Write End 6.5 — 7 — ns tHD Data Hold from Write End 0 — 0 — ns tHZWE(3) WE LOW to High-Z Output — 3.5 — 5 ns tLZWE WE HIGH to Low-Z Output 0 — 0 — ns (3) Notes: 1. Test conditions assume signal transition times of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V and output loading specified in Figure 1. 2. The internal write time is defined by the overlap of CE LOW and WE LOW. All signals must be in valid states to initiate a Write, but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the rising or falling edge of the signal that terminates the Write. 3. Tested with the load in Figure 2. Transition is measured ±500 mV from steady-state voltage. Not 100% tested. AC WAVEFORMS WRITE CYCLE NO. 1 (CE Controlled, OE is HIGH or LOW) (1 ) t WC VALID ADDRESS ADDRESS t SA t SCE t HA CE t AW t PWE1 t PWE2 WE t HZWE DOUT DATA UNDEFINED t LZWE HIGH-Z t SD DIN t HD DATAIN VALID CE_WR1.eps Integrated Silicon Solution, Inc. — 1-800-379-4774 Rev. A 03/17/06 7 ISSI IS61LV256AL ® WRITE CYCLE NO. 2 (WE Controlled, OE is HIGH During Write Cycle) (1,2) t WC ADDRESS VALID ADDRESS t HA OE CE LOW t AW WE t SA DOUT t PWE1 t HZWE t LZWE HIGH-Z DATA UNDEFINED t SD t HD DATAIN VALID DIN CE_WR2.eps WRITE CYCLE NO. 3 (WE Controlled, OE is LOW During Write Cycle) (1) t WC ADDRESS VALID ADDRESS OE LOW CE LOW t HA t AW WE t SA DOUT DATA UNDEFINED t PWE2 t HZWE t LZWE HIGH-Z t SD DIN t HD DATAIN VALID CE_WR3.eps Notes: 1. The internal write time is defined by the overlap of CE LOW and WE LOW. All signals must be in valid states to initiate a Write, but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the rising or falling edge of the signal that terminates the Write. 2. I/O will assume the High-Z state if OE > VIH. 8 Integrated Silicon Solution, Inc. — 1-800-379-4774 Rev. A 03/17/06 ISSI IS61LV256AL ® DATA RETENTION SWITCHING CHARACTERISTICS Symbol Parameter Test Condition Min. VDR VDD for Data Retention See Data Retention Waveform 2.0 IDR Data Retention Current VDD = 2.0V, CE ≥ VDD – 0.2V VIN ≥ VDD – 0.2V, or VIN ≤ VSS + 0.2V tSDR Data Retention Setup Time See Data Retention Waveform tRDR Recovery Time See Data Retention Waveform Com. Ind. Typ.(1) Max. Unit 3.6 V 40 50 µA 0 — ns tRC — ns — — 2 — Note: 1. Typical Values are measured at VDD = 3.3V, TA = 25oC and not 100% tested. CE Controlled) DATA RETENTION WAVEFORM (CE tSDR Data Retention Mode tRDR VDD VDR CE GND Integrated Silicon Solution, Inc. — 1-800-379-4774 Rev. A 03/17/06 CE ≥ VDD - 0.2V 9 ISSI IS61LV256AL ® ORDERING INFORMATION Commercial Range: 0°C to +70°C Speed (ns) 10 Order Part No. Package IS61LV256AL-10T IS61LV256AL-10TL IS61LV256AL-10J IS61LV256AL-10JL TSOP - Type I TSOP - Type I, Lead-free 300-mil Plastic SOJ 300-mil Plastic SOJ, Lead-free ORDERING INFORMATION Industrial Range: –40°C to +85°C Speed (ns) 10 10 Order Part No. Package IS61LV256AL-10TI IS61LV256AL-10TLI IS61LV256AL-10JI IS61LV256AL-10JLI TSOP - Type I TSOP - Type I, Lead-free 300-mil Plastic SOJ 300-mil Plastic SOJ, Lead-free Integrated Silicon Solution, Inc. — 1-800-379-4774 Rev. A 03/17/06 ISSI PACKAGING INFORMATION ® 300-mil Plastic SOJ Package Code: J N E1 E 1 SEATING PLANE D A B e A2 C b A1 E2 MILLIMETERS INCHES Sym. Min. Typ. Max. Min. Typ. Max. N0. Leads 24/26 A — — 3.56 — A1 0.64 — — 0.025 — — A2 2.41 — 2.67 0.095 — 0.105 b 0.41 — 0.51 0.016 — 0.020 B 0.66 — 0.81 0.026 — 0.032 — 0.140 C 0.20 — 0.25 0.008 — 0.010 D 17.02 — 17.27 0.670 — 0.680 E 8.26 — 8.76 0.325 — 0.345 E1 7.49 — 7.75 0.295 — 0.305 E2 6.27 — 7.29 0.247 — 0.287 e 1.27 BSC Notes: 1. Controlling dimension: inches, unless otherwise specified. 2. BSC = Basic lead spacing between centers. 3. Dimensions D and E1 do not include mold flash protrusions and should be measured from the bottom of the package. 4. Formed leads shall be planar with respect to one another within 0.004 inches at the seating plane. 0.050 BSC Copyright © 2003 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on any published information and before placing orders for products. Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 Rev. D 02/25/03 ISSI PACKAGING INFORMATION ® 300-mil Plastic SOJ Package Code: J MILLIMETERS INCHES Sym. Min. Typ. Max. Min. Typ. Max. N0. Leads 28 MILLIMETERS INCHES Sym. Min. Typ. Max. Min. Typ. Max. N0. Leads 32 A — — 3.56 — — 0.140 A — — 3.56 — — 0.140 A1 0.64 — — 0.025 — — A1 0.64 — — 0.025 — — A2 2.41 — 2.67 0.095 — 0.105 A2 2.41 — 2.67 0.095 — 0.105 b 0.41 — 0.51 0.016 — 0.020 b 0.41 — 0.51 0.016 — 0.020 B 0.66 — 0.81 0.026 — 0.032 B 0.66 — 0.81 0.026 — 0.032 C 0.20 — 0.25 0.008 — 0.010 C 0.20 — 0.25 0.008 — 0.010 D 18.29 — 18.54 0.720 — 0.730 D 20.83 — 21.08 0.820 — 0.830 E 8.26 — 8.76 0.325 — 0.345 E 8.26 — 8.76 0.325 — 0.345 E1 7.49 — 7.75 0.295 — 0.305 E1 7.49 — 7.75 0.295 — 0.305 E2 6.27 — 7.29 0.247 — 0.287 E2 6.27 — 7.29 0.247 — 0.287 e 2 1.27 BSC 0.050 BSC e 1.27 BSC 0.050 BSC Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 Rev. D 02/25/03 ISSI PACKAGING INFORMATION Plastic TSOP - 28-pins Package Code: T (Type I) 1 E H N D SEATING PLANE A S B e Symbol Ref. Std. No. Leads A A1 B C D E H e L α α C Plastic TSOP (T—Type I) Millimeters Inches Min Max Min Max 28 1.00 1.20 0.05 0.20 0.16 0.27 0.10 0.20 7.90 8.10 11.70 11.90 13.20 13.60 0.55 BSC 0.30 0.70 0° 5° Integrated Silicon Solution, Inc. PK13197T28 L A1 Rev. B 01/31/97 0.037 0.047 0.002 0.008 0.006 0.011 0.004 0.008 0.308 0.316 0.456 0.465 0.515 0.531 0.022 BSC 0.011 0.027 0° 5° Notes: 1. Controlling dimension: millimeters, unless otherwise specified. 2. BSC = Basic lead spacing between centers. 3. Dimensions D and E do not include mold flash protrusions and should be measured from the bottom of the package. 4. Formed leads shall be planar with respect to one another within 0.004 inches at the seating plane. ®