KB HE84G752B

KING BILLION ELECTRONICS CO., LTD
駿 億 電 子 股 份 有 限 公 司
HE84G752B
HE80004 Series
- Table of Contents 1.
General Description ___________________________________________________________________3
2.
Features _____________________________________________________________________________3
3.
Functional Block Diagram ______________________________________________________________4
4.
Pin Description _______________________________________________________________________4
5.
Pad Location _________________________________________________________________________6
6.
ROM Map Configurations_____________________________________________________________11
7.
LCD Display RAM Map ______________________________________________________________12
7.1.
16 Gray Scale LCD Display RAM Map ________________________________________________14
7.2.
4 Gray Scale LCD Display RAM Map _________________________________________________16
7.3.
Black and White LCD Display RAM Map______________________________________________17
8.
LCD Power Supply ___________________________________________________________________19
9.
LCDC Control register________________________________________________________________21
10.
Oscillators ________________________________________________________________________22
11.
General Purpose I/O _______________________________________________________________24
12.
Timer1 ___________________________________________________________________________26
13.
Timer2 ___________________________________________________________________________27
14.
Time Base ________________________________________________________________________28
15.
Watch Dog Timer __________________________________________________________________29
16.
Voice Output ______________________________________________________________________30
17.
Low Voltage Detection/Reset _________________________________________________________34
18.
Infrared output____________________________________________________________________35
19.
Universal Asynchronous Receiver/Transmitter__________________________________________37
19.1.
Interface Registers _________________________________________________________________38
19.2.
Baud Rate Configuration Register ____________________________________________________38
19.3.
Interrupt & Identification Register ___________________________________________________39
19.4.
Line Control Register_______________________________________________________________40
19.5.
Line Status Register ________________________________________________________________41
January 21, 2005
1
V0.93
This specification is subject to change without notice. Please contact sales person for the latest version before use.
KING BILLION ELECTRONICS CO., LTD
駿 億 電 子 股 份 有 限 公 司
HE84G752B
HE80004 Series
20.
Extension Register Access ___________________________________________________________42
21.
Summary of Registers and Mask Options ______________________________________________42
22.
Absolute Maximum Rating __________________________________________________________45
23.
Recommended Operating Conditions _________________________________________________45
24.
AC/DC Characteristics _____________________________________________________________45
25.
Application Circuit_________________________________________________________________47
26.
Important Note ____________________________________________________________________49
27.
Updated History ___________________________________________________________________49
January 21, 2005
2
V0.93
This specification is subject to change without notice. Please contact sales person for the latest version before use.
KING BILLION ELECTRONICS CO., LTD
駿 億 電 子 股 份 有 限 公 司
HE84G752B
HE80004 Series
1. General Description
HE84G752B is a member of 8-bit Micro-controller series developed by King Billion Electronics.
External address and data buses are provided to access external memory. This chip has 4096 pixel, 16
gray-scale LCD driver built-in with 4 different configurations, and up to 34-bit general purpose I/O ports.
The built-in OP comparator can be used with light, voice, temperature and humility sensor or used to
detect the battery low. The 7/8 bits current-type D/A converter and PWM driver output provides the
complete speech output solutions. The 512K bytes ROM and 3K bytes RAM can be used for the storage
of large speech data, image and text, etc. An UART is included to provide the serial communication
capability. IR output makes it suitable for remote control applications.
The instruction sets of HE80000 series is easy to learn and simple to use. There are only thirty-two
instructions and four addressing modes. Most of instructions take only 3 oscillator clocks to complete.
The performance and low power consumption make it suitable for battery-powered applications such as
translator, data bank, educational toy, digital voice recorder, etc.
2. Features
9
9
9
9
9
9
9
9
9
9
9
9
9
9
9
9
9
9
9
9
9
9
Operation Voltage:
Dual Clock System:
2.4V ~ 3.6V
Fast clock
32768 Hz ~ 8 MHz
Slow clock
32768 Hz
Four operation modes: Fast, Slow, Idle, Sleep modes.
Internal Program ROM: 256K bytes
Internal Data ROM:
256K bytes
Internal RAM:
3 K bytes (page0~page11)
24 bi-directional general-purpose I/O ports with push-pull or Open-Drain output type selectable
for each I/O pin by mask option.
Up to 2048 pixels 16, 4 gray-scale or Black/White LCD driver.
Segment extender interface with KD83 and KD80.
4 LCD configurations (COM X SEG): 32 COM x 64 SEG.
Built-in LCD power supply with regulator and 3, 4, and 5 times charge pump circuit.
One 7/8-bit current-type D/A converter.
One 7/8-bit PWM output.
One built-in OP comparator.
Built-in UART for serial communication.
IR output.
Low voltage reset: 2.2V
Low voltage detection: 2.4V, 2.6V, 2.8V and 3.0V
Two external interrupts, three internal timer interrupts and extension UART interrupt
Watch dog timer to prevent deadlock condition.
Two 16-bit timers and one time-base timer.
Instruction set: 32 instructions, 4 addressing mode.
January 21, 2005
3
V0.93
This specification is subject to change without notice. Please contact sales person for the latest version before use.
KING BILLION ELECTRONICS CO., LTD
駿 億 電 子 股 份 有 限 公 司
HE84G752B
HE80004 Series
3. Functional Block Diagram
LCD
Driver
SEG
COM
LVL[5..1], LGS1, LVREG
LCAP?A, LCAP?B
LCD Power
Supply
8 Bit CPU
512 KB ROM
Fast Clock
OSC.
Slow Clock
OSC
FXI, FXO
SXI, SXO
3 KB RAM
OLFR, OCCK
SEGA, SEGD
Segment Ext.
Interface
Ext. Memory
Interface
TC1
TC2
PWM
PWM
DAC
VO, DAO
TB
PRTC, PRTD, PRT10,
PRT17
SIN, SOUT
I/O Port
UART
WDT
LVR
LVD
OP Amp
IR
OPO,OPIN, OPIP
IRO
4. Pin Description
Pin Name
COM[31..0]
SEG[63:0]
LVL1
LVL2
January 21, 2005
Pin # I/O
15~ 46
1~14
139~188
47
48
Description
O LCD COMMON Driver Pads.
O LCD SEGMENT Driver Pads
P LCD Bias Voltage 1.
P LCD Bias Voltage 2
4
V0.93
This specification is subject to change without notice. Please contact sales person for the latest version before use.
KING BILLION ELECTRONICS CO., LTD
駿 億 電 子 股 份 有 限 公 司
Pin Name
Pin # I/O
LVL3
LVL4
LVL5
LCAP4A
LCAP2B
LCAP2A
LCAP1A
LCAP1B
LCAP3A
49
50
51
52
53
54
55
56
57
P
P
P
O
O
O
O
O
O
LVREG
58
O
LGS1
LVAG
VDD_LCD(VDDA)
GND_LCD(VSSA)
OAC
OCCK
GND
OPO
OPIP
OPIN
DAO
VO
59
60
61
62
63
64
65
66
67
68
69
70
I
O
P
P
O
O
P
O
I
I
O
O
RSTP_N
71
I
FXO,
FXI
72,
73
O,
B
TSTP_P
74
I
SXO,
SXI
75,
76
O,
I
VX
77
I
VDD
78
P
PRT10[7..0]
79~86
B
PRTD[7..2]
PRTD[1]/SIN
PRTD[0]/SOUT
87~94
B
PRTC[7:0]
95~102
B
VDD_RAM
IRO
PWM
103
104
105
P
O
O
January 21, 2005
HE84G752B
HE80004 Series
Description
LCD Bias Voltage 3
LCD Bias Voltage 4
LCD Bias Voltage 5.
Charge Pump Capacitor Pin.
Charge Pump Capacitor Pin.
Charge Pump Capacitor Pin.
Charge Pump Capacitor Pin.
Charge Pump Capacitor Pin.
Charge Pump Capacitor Pin.
Voltage Regulator Output. VDD is regulated to generate LVREG, which is in turns
pumped to LVP. Adjust resistor between LGS1 and LVREG to set LVREG voltage.
Regulator Voltage Setting
Reference Voltage Output. Fixed 0.9 Volt DC reference voltage
Power supply for LCD charge-pump.
LCD power system ground.
LCD frame signal for interfacing with LCD segment extender KD80.
LCD data load pin for interfacing with LCD segment extender KD80.
Power ground Input.
Output of OP Amp.
Non-inverting input of OP Amp.
Inverting input of OP Amp.
Alternate output of DAC.
DAC Output.
System Reset input pin. Level trigger, active low on this pin will put the chip in reset
state.
External fast clock pin. Two types of oscillator can be selected by MO_FXTAL (‘0’ for
RC type and ‘1’ for crystal type). For RC type oscillator, one resistor needs to be
connected between FXI and GND. For crystal oscillator, one crystal needs to be placed
between FXI and FXO. Please refer to application circuit for details.
Test input pin. Please bond this pad and reserve a test point on PCB for debugging. But
for improving ESD, please connect this point with zero Ohm resistor to GND.
External slow clock pins. Slow clock is clock source for LCD display, TIMER1,
Time-Base and other internal blocks. Both crystal and RC oscillator are provided. The
slow clock type can be selected by mask option MO_SXTAL. Choose ‘0’ for RC type
and ‘1’ for crystal oscillator.
Input pin for x32 PLL circuit. Connect to external resistor and capacitors as shown in
application circuit.
Positive power Input. A 0.1 µF decoupling capacitors should be placed as close to IC
VDD and GND pads as possible for best decoupling effect.
8-bit bi-directional I/O port 10. The output type of I/O pad can also be selected by mask
option MO_10PP[7..0] (‘1’ for push-pull and ‘0’ for open-drain).
As the output structure of I/O pad does not contain tri-state buffer. When using the I/O
pad as input pad, “1” must be outputted before reading.
8-bit bi-directional I/O port D. The output type of I/O pad can also be selected by mask
option MO_DPP[7..0] (‘1’ for push-pull and ‘0’ for open-drain).
As the output structure of I/O pad does not contain tri-state buffer. When using the I/O
as input, ‘1’ must be outputted before reading the pin.
PRTD[7..2] can be used as wake-up pins. PRTD[7..6] can be as external interrupt
sources.
PRTD[1] shares pad with UART Receiver SIN pin.
PRTD[0] shares pad with UART transmitter SOUT pin.
8-bit bi-directional I/O port C. The output type of I/O pad can also be selected by mask
option MO_CPP[7..0] (‘1’ for push-pull and ‘0’ for open-drain).
As the output structure of I/O pad does not contain tri-state buffer. When using the I/O
as input, ‘1’ must be outputted before reading the pin.
Dedicated power input for RAM
The Infrared output.
The PWM output can drive speaker or buzzer directly. Using VDD & PWM to drive
5
V0.93
This specification is subject to change without notice. Please contact sales person for the latest version before use.
KING BILLION ELECTRONICS CO., LTD
駿 億 電 子 股 份 有 限 公 司
Pin Name
GND_PWM
NC
Pin # I/O
106
107~138
HE84G752B
HE80004 Series
Description
output device.
P Dedicated Ground for PWM output.
I: Input, O: Output, B: Bidirectional, P: Power.
5. Pad Location
PIN
PIN
X
Y
Number
Name
Coordinate
Coordinate
-----------------------------------------------------------------------1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
January 21, 2005
SEG[13]
SEG[12]
SEG[11]
SEG[10]
SEG[9]
SEG[8]
SEG[7]
SEG[6]
SEG[5]
SEG[4]
SEG[3]
SEG[2]
SEG[1]
SEG[0]
COM[31]
COM[30]
COM[29]
COM[28]
COM[27]
COM[26]
COM[25]
COM[24]
COM[23]
COM[22]
COM[21]
COM[20]
COM[19]
COM[18]
X=
X=
X=
X=
X=
X=
X=
X=
X=
X=
X=
X=
X=
X=
X=
X=
X=
X=
X=
X=
X=
X=
X=
X=
X=
X=
X=
X=
-4123.60
-4123.60
-4123.60
-4123.60
-4123.60
-4123.60
-4123.60
-4123.60
-4123.60
-4123.60
-4123.60
-4123.60
-4123.60
-4123.60
-4123.60
-4123.60
-4123.60
-4123.60
-4123.60
-4123.60
-3930.50
-3830.50
-3730.50
-3630.50
-3530.50
-3430.50
-3330.50
-3230.50
Y=
Y=
Y=
Y=
Y=
Y=
Y=
Y=
Y=
Y=
Y=
Y=
Y=
Y=
Y=
Y=
Y=
Y=
Y=
Y=
Y=
Y=
Y=
Y=
Y=
Y=
Y=
Y=
6
934.55
834.55
734.55
634.55
534.55
434.55
334.55
234.55
134.55
34.55
-65.45
-165.45
-265.45
-365.45
-465.45
-565.45
-665.45
-765.45
-865.45
-965.45
-1354.55
-1354.55
-1354.55
-1354.55
-1354.55
-1354.55
-1354.55
-1354.55
V0.93
This specification is subject to change without notice. Please contact sales person for the latest version before use.
KING BILLION ELECTRONICS CO., LTD
駿 億 電 子 股 份 有 限 公 司
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
January 21, 2005
COM[17]
COM[16]
COM[15]
COM[14]
COM[13]
COM[12]
COM[11]
COM[10]
COM[9]
COM[8]
COM[7]
COM[6]
COM[5]
COM[4]
COM[3]
COM[2]
COM[1]
COM[0]
LVL1
LVL2
LVL3
LVL4
LVL5
LCAP4A
LCAP2B
LCAP2A
LCAP1A
LCAP1B
LCAP3A
LVREG
LGS1
LVAG
VDDA
VSSA
OAC
OCCK
GND
OPO
OPIP
X=
X=
X=
X=
X=
X=
X=
X=
X=
X=
X=
X=
X=
X=
X=
X=
X=
X=
X=
X=
X=
X=
X=
X=
X=
X=
X=
X=
X=
X=
X=
X=
X=
X=
X=
X=
X=
X=
X=
-3130.50
-3030.50
-2930.50
-2830.50
-2730.50
-2630.50
-2530.50
-2430.50
-2330.50
-2230.50
-2130.50
-2030.50
-1930.50
-1830.50
-1730.50
-1630.50
-1530.50
-1430.50
-1230.50
-1130.50
-1030.50
-930.50
-830.50
-730.50
-630.50
-530.50
-430.50
-330.50
-230.50
-130.50
-30.50
69.50
169.50
369.50
469.50
569.50
669.50
769.50
869.50
Y=
Y=
Y=
Y=
Y=
Y=
Y=
Y=
Y=
Y=
Y=
Y=
Y=
Y=
Y=
Y=
Y=
Y=
Y=
Y=
Y=
Y=
Y=
Y=
Y=
Y=
Y=
Y=
Y=
Y=
Y=
Y=
Y=
Y=
Y=
Y=
Y=
Y=
Y=
7
HE84G752B
HE80004 Series
-1354.55
-1354.55
-1354.55
-1354.55
-1354.55
-1354.55
-1354.55
-1354.55
-1354.55
-1354.55
-1354.55
-1354.55
-1354.55
-1354.55
-1354.55
-1354.55
-1354.55
-1354.55
-1354.55
-1354.55
-1354.55
-1354.55
-1354.55
-1354.55
-1354.55
-1354.55
-1354.55
-1354.55
-1354.55
-1354.55
-1354.55
-1354.55
-1354.55
-1354.55
-1354.55
-1354.55
-1354.55
-1354.55
-1354.55
V0.93
This specification is subject to change without notice. Please contact sales person for the latest version before use.
KING BILLION ELECTRONICS CO., LTD
駿 億 電 子 股 份 有 限 公 司
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
January 21, 2005
OPIN
DAO
VO
RSTP_N
FXO
FXI
TSTP_P
SXO
SXI
VX
VDD
PRT10[7]
PRT10[6]
PRT10[5]
PRT10[4]
PRT10[3]
PRT10[2]
PRT10[1]
PRT10[0]
PRTD[7]
PRTD[6]
PRTD[5]
PRTD[4]
PRTD[3]
PRTD[2]
PRTD[1]
PRTD[0]
PRTC[7]
PRTC[6]
PRTC[5]
PRTC[4]
PRTC[3]
PRTC[2]
PRTC[1]
PRTC[0]
VDD_RAM
IRO
PWM
GND_PWM
X=
X=
X=
X=
X=
X=
X=
X=
X=
X=
X=
X=
X=
X=
X=
X=
X=
X=
X=
X=
X=
X=
X=
X=
X=
X=
X=
X=
X=
X=
X=
X=
X=
X=
X=
X=
X=
X=
X=
969.50
1069.50
1169.50
1269.50
1369.50
1469.50
1569.50
1669.50
1769.50
1869.50
1969.50
2169.50
2269.50
2369.50
2469.50
2569.50
2669.50
2769.50
2869.50
2969.50
3069.50
3169.50
3269.50
3369.50
3469.50
3569.50
3669.50
3769.50
4122.00
4122.00
4122.00
4122.00
4122.00
4122.00
4122.00
4122.00
4122.00
4122.00
4122.00
Y=
Y=
Y=
Y=
Y=
Y=
Y=
Y=
Y=
Y=
Y=
Y=
Y=
Y=
Y=
Y=
Y=
Y=
Y=
Y=
Y=
Y=
Y=
Y=
Y=
Y=
Y=
Y=
Y=
Y=
Y=
Y=
Y=
Y=
Y=
Y=
Y=
Y=
Y=
8
HE84G752B
HE80004 Series
-1354.55
-1354.55
-1354.55
-1354.55
-1354.55
-1354.55
-1354.55
-1354.55
-1354.55
-1354.55
-1354.55
-1354.55
-1354.55
-1354.55
-1354.55
-1354.55
-1354.55
-1354.55
-1354.55
-1354.55
-1354.55
-1354.55
-1354.55
-1354.55
-1354.55
-1354.55
-1354.55
-1354.55
-1126.45
-1026.45
-926.45
-826.45
-726.45
-626.45
-526.45
-426.45
-326.45
-226.45
-126.45
V0.93
This specification is subject to change without notice. Please contact sales person for the latest version before use.
KING BILLION ELECTRONICS CO., LTD
駿 億 電 子 股 份 有 限 公 司
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
January 21, 2005
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
SEG[63]
SEG[62]
SEG[61]
SEG[60]
SEG[59]
SEG[58]
SEG[57]
X=
X=
X=
X=
X=
X=
X=
X=
X=
X=
X=
X=
X=
X=
X=
X=
X=
X=
X=
X=
X=
X=
X=
X=
X=
X=
X=
X=
X=
X=
X=
X=
X=
X=
X=
X=
X=
X=
X=
4122.00
4122.00
4122.00
4122.00
4122.00
4122.00
4122.00
4122.00
3668.40
3568.40
3468.40
3368.40
3268.40
3168.40
3068.40
2968.40
2868.40
2768.40
2668.40
2568.40
2468.40
2368.40
2268.40
2168.40
2068.40
1968.40
1868.40
1768.40
1568.40
1468.40
1368.40
1268.40
1168.40
1068.40
968.40
868.40
768.40
668.40
568.40
Y=
Y=
Y=
Y=
Y=
Y=
Y=
Y=
Y=
Y=
Y=
Y=
Y=
Y=
Y=
Y=
Y=
Y=
Y=
Y=
Y=
Y=
Y=
Y=
Y=
Y=
Y=
Y=
Y=
Y=
Y=
Y=
Y=
Y=
Y=
Y=
Y=
Y=
Y=
9
HE84G752B
HE80004 Series
473.55
573.55
673.55
773.55
873.55
973.55
1073.55
1173.55
1354.05
1354.05
1354.05
1354.05
1354.05
1354.05
1354.05
1354.05
1354.05
1354.05
1354.05
1354.05
1354.05
1354.05
1354.05
1354.05
1354.05
1354.05
1354.05
1354.05
1354.05
1354.05
1354.05
1354.05
1354.05
1354.05
1354.05
1354.05
1354.05
1354.05
1354.05
V0.93
This specification is subject to change without notice. Please contact sales person for the latest version before use.
KING BILLION ELECTRONICS CO., LTD
駿 億 電 子 股 份 有 限 公 司
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
January 21, 2005
SEG[56]
SEG[55]
SEG[54]
SEG[53]
SEG[52]
SEG[51]
SEG[50]
SEG[49]
SEG[48]
SEG[47]
SEG[46]
SEG[45]
SEG[44]
SEG[43]
SEG[42]
SEG[41]
SEG[40]
SEG[39]
SEG[38]
SEG[37]
SEG[36]
SEG[35]
SEG[34]
SEG[33]
SEG[32]
SEG[31]
SEG[30]
SEG[29]
SEG[28]
SEG[27]
SEG[26]
SEG[25]
SEG[24]
SEG[23]
SEG[22]
SEG[21]
SEG[20]
SEG[19]
SEG[18]
X=
X=
X=
X=
X=
X=
X=
X=
X=
X=
X=
X=
X=
X=
X=
X=
X=
X=
X=
X=
X=
X=
X=
X=
X=
X=
X=
X=
X=
X=
X=
X=
X=
X=
X=
X=
X=
X=
X=
468.40
368.40
268.40
168.40
68.40
-31.60
-131.60
-231.60
-331.60
-531.60
-631.60
-731.60
-831.60
-931.60
-1031.60
-1131.60
-1231.60
-1331.60
-1431.60
-1531.60
-1631.60
-1731.60
-1831.60
-1931.60
-2031.60
-2231.60
-2331.60
-2431.60
-2531.60
-2631.60
-2731.60
-2831.60
-2931.60
-3031.60
-3131.60
-3231.60
-3331.60
-3431.60
-3531.60
Y=
Y=
Y=
Y=
Y=
Y=
Y=
Y=
Y=
Y=
Y=
Y=
Y=
Y=
Y=
Y=
Y=
Y=
Y=
Y=
Y=
Y=
Y=
Y=
Y=
Y=
Y=
Y=
Y=
Y=
Y=
Y=
Y=
Y=
Y=
Y=
Y=
Y=
Y=
10
HE84G752B
HE80004 Series
1354.05
1354.05
1354.05
1354.05
1354.05
1354.05
1354.05
1354.05
1354.05
1354.05
1354.05
1354.05
1354.05
1354.05
1354.05
1354.05
1354.05
1354.05
1354.05
1354.05
1354.05
1354.05
1354.05
1354.05
1354.05
1354.05
1354.05
1354.05
1354.05
1354.05
1354.05
1354.05
1354.05
1354.05
1354.05
1354.05
1354.05
1354.05
1354.05
V0.93
This specification is subject to change without notice. Please contact sales person for the latest version before use.
KING BILLION ELECTRONICS CO., LTD
駿 億 電 子 股 份 有 限 公 司
185
186
187
188
SEG[17]
SEG[16]
SEG[15]
SEG[14]
X=
X=
X=
X=
-3631.60
-3731.60
-3831.60
-3931.60
Y=
Y=
Y=
Y=
HE84G752B
HE80004 Series
1354.05
1354.05
1354.05
1354.05
6. ROM Map Configurations
The chip has built-in 512K bytes internal ROM. In addition, address and data buses are provided to access
External ROM. The MCU can access up to 4M bytes program ROM and up to 16M bytes data space
through external buses. The SEG[47..40], SEG[39..16] pads are used as either data and address buses for
external ROM or LCD segment driver pads depending on the mask option MO_EXMEM. When the
external ROM mask option is selected, the MCU will retrieve the instructions and data from external
ROM through the address and data buses.
The bit 14 ~ 15 bit of 16-bit logical program address can be mapped to any one (16K bytes per page) of
256 pages through mapping registers PSA1, PSA2, PSA3. As logical page 0 can not be moved and is
always physical page 0, the PSA1 ~ PSA3 contain the physical page addresses of logical pages 1 ~ 3.
Logical Address
A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
Page Addr. A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
A[15..14]
00
01
10
11
Register Address
PSA1
0x2C
PSA2
0x2D
PSA3
0x2E
January 21, 2005
Type
R/W
R/W
R/W
Logical Page Physical Page Address
0
0
1
PSA1
2
PSA2
3
PSA3
A21
A21
A21
A20
A20
A20
A19
A19
A19
11
Physical Address
00A[13..0]
PSA1+A[13..0]
PSA2+A[13..0]
PSA3+A[13..0]
Bits Definition
A18
A17
A18
A17
A18
A17
A16
A16
A16
A15
A15
A15
A14
A14
A14
Reset
0x01
0x02
0x03
V0.93
This specification is subject to change without notice. Please contact sales person for the latest version before use.
KING BILLION ELECTRONICS CO., LTD
駿 億 電 子 股 份 有 限 公 司
Address
000000
HE84G752B
HE80004 Series
Option2
Int. PROM
(256KB)
040000
Unused
400000
Int. DROM
(256KB)
440000
FFFFFF
7. LCD Display RAM Map
The gray-scale LCD driver can be configured to be a 16 gray-scale, 4 gray-scales or black and white
display by mask option MO_GRAY_MODE.
MO_GRAY_MODE[1..0]
00
January 21, 2005
12
Gray levels
16
V0.93
This specification is subject to change without notice. Please contact sales person for the latest version before use.
HE84G752B
KING BILLION ELECTRONICS CO., LTD
駿 億 電 子 股 份 有 限 公 司
01
10
11
HE80004 Series
4
2 (B/W)
2 (B/W)
For 4 gray-scale display, 2-bit of RAM is required for each pixel and 4 bit for 16 gray-scale display, 1-bit
for black and white display. For different LCD configuration, the LCD display RAM is arranged
differently. The following figure shows one byte of RAM in different LCD configurations:
0F
xx
0E
xx
0D
xx
0C
xx
0B
xx
0A
xx
09
xx
08
xx
07
xx
Bit 7
Bit 6
Bit 5
Bit 4
SEG7
SEG6
SEG5
SEG4
SEG3
SEG2
SEG1
Black/White
4 Gray scales
16 Gray scales
06
xx
05
xx
04
xx
03
xx
02
xx
01
xx
00
xx
Bit 3
Bit 2
Bit 1
Bit 0
SEG3
SEG2
SEG1
SEG0
SEG1
SEG0
SEG0
The 16 Gray Scale register GRAY0 ~ GRAYF is the mapping register between the levels selected in
RAM and the real gray scale. In other words, if the content of GRAY0 is 0x03, when value of a certain
pixel is 0, the displayed effect will correspond to actual gray level 3. The 16 gray scale display use all 16
registers GRAY0 ~ GRAYF to select among 32 available gray levels to correspond to level 0 ~ 15, while
4 gray scale display utilizes registers GRAY0 ~ GRAY3 to select among 32 gray levels to correspond to
level 0 ~ 3. Thus user can pick the gray levels which give the best and most linear effect.
16 Gray Scale registers share a common register address GRAY16. When writing is made to the register,
it will step down to next register in order. The writing sequence can be reset by clearing bit 5 of LCDC
register.
GRAY16
Seq.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
January 21, 2005
Bit4
Bit3
Field
Bit2
GRAY0
GRAY1
GRAY2
GRAY3
GRAY4
GRAY5
GRAY6
GRAY7
GRAY8
GRAY9
GRAYA
GRAYB
GRAYC
GRAYD
GRAYE
GRAYF
13
Bit1
Bit0
Reset
0x00
0x02
0x04
0x06
0x08
0x0A
0x0C
0x0E
0x10
0x12
0x14
0x16
0x18
0x1A
0x1C
0x1E
V0.93
This specification is subject to change without notice. Please contact sales person for the latest version before use.
KING BILLION ELECTRONICS CO., LTD
駿 億 電 子 股 份 有 限 公 司
HE84G752B
HE80004 Series
7.1. 16 Gray Scale LCD Display RAM Map
Page
1
2
3
4
Cnf
Loc.
00
10
20
30
40
50
60
70
80
90
A0
B0
C0
D0
E0
F0
00
10
20
30
40
50
60
70
80
90
A0
B0
C0
D0
E0
F0
00
10
20
30
40
50
60
70
80
90
A0
B0
C0
D0
E0
F0
00
10
20
30
32 X 64
F
0
S31 ~ S00
S63 ~ S32
COM0
*
S31 ~ S00
S63 ~ S32
*
COM1
*
S31 ~ S00
S63 ~ S32
*
COM2
*
S31 ~ S00
S63 ~ S32
COM3
*
S31 ~ S00
S63 ~ S32
*
COM4
*
S31 ~ S00
S63 ~ S32
*
COM5
*
S31 ~ S00
S63 ~ S32
*
COM6
*
S31 ~ S00
S63 ~ S32
*
COM7
*
S31 ~ S00
S63 ~ S32
*
COM8
*
S31 ~ S00
S63 ~ S32
*
COM9
*
S31 ~ S00
S63 ~ S32
*
COM10
*
S31 ~ S00
S63 ~ S32
*
COM11
*
S31 ~ S00
S95 ~ S64
January 21, 2005
COM12
*
14
V0.93
This specification is subject to change without notice. Please contact sales person for the latest version before use.
KING BILLION ELECTRONICS CO., LTD
駿 億 電 子 股 份 有 限 公 司
Page
5
6
7
Cnf
Loc.
40
50
60
70
80
90
A0
B0
C0
D0
E0
F0
00
10
20
30
40
50
60
70
80
90
A0
B0
C0
D0
E0
F0
00
10
20
30
40
50
60
70
80
90
A0
B0
C0
D0
E0
F0
00
10
20
30
40
50
60
70
80
90
A0
HE84G752B
HE80004 Series
32 X 64
F
0
S31 ~ S00
S63 ~ S32
*
COM13
*
S31 ~ S00
S63 ~ S32
*
COM14
*
S31 ~ S00
S63 ~ S32
*
COM15
*
S31 ~ S00
S63 ~ S32
*
COM16
*
S31 ~ S00
S63 ~ S32
*
COM17
*
S31 ~ S00
S63 ~ S32
*
COM18
*
S31 ~ S00
S63 ~ S32
*
COM19
*
S31 ~ S00
S63 ~ S32
*
COM20
*
S31 ~ S00
S63 ~ S32
*
COM21
*
S31 ~ S00
S63 ~ S32
*
COM22
*
S31 ~ S00
S63 ~ S32
*
COM23
*
S31 ~ S00
S63 ~ S32
S95 ~ S64
COM24
*
S31 ~ S00
S63 ~ S32
*
COM25
*
S31 ~ S00
S63 ~ S32
January 21, 2005
COM26
*
15
V0.93
This specification is subject to change without notice. Please contact sales person for the latest version before use.
KING BILLION ELECTRONICS CO., LTD
駿 億 電 子 股 份 有 限 公 司
Page
8
Cnf
Loc.
B0
C0
D0
E0
F0
00
10
20
30
40
50
60
70
80
90
A0
B0
C0
D0
E0
F0
HE84G752B
HE80004 Series
32 X 64
F
0
*
S31 ~ S00
S63 ~ S32
COM27
*
*
S31 ~ S00
S63 ~ S32
COM28
*
*
S31 ~ S00
S63 ~ S32
COM29
*
*
S31 ~ S00
S63 ~ S32
COM30
*
*
S31 ~ S00
S63 ~ S32
COM31
*
*
7.2. 4 Gray Scale LCD Display RAM Map
Page
1
2
Cnf
Loc.
00
10
20
30
40
50
60
70
80
90
A0
B0
C0
D0
E0
F0
00
10
20
30
40
50
60
70
80
90
A0
B0
32x64
F
0
S63 ~ S00
*
*
S63 ~ S00
*
*
S63 ~ S00
*
*
S63 ~ S00
*
*
S63 ~ S00
*
*
S63 ~ S00
*
*
S63 ~ S00
*
*
S63 ~ S00
*
*
S63 ~ S00
*
*
S63 ~ S00
*
*
S63 ~ S00
*
*
S63 ~ S00
*
*
S63 ~ S00
*
*
S63 ~ S00
*
January 21, 2005
*
COM0
COM1
COM2
COM3
COM4
COM5
COM6
COM7
COM8
COM9
COM10
COM11
COM12
COM13
16
V0.93
This specification is subject to change without notice. Please contact sales person for the latest version before use.
KING BILLION ELECTRONICS CO., LTD
駿 億 電 子 股 份 有 限 公 司
Page
3
4
Cnf
Loc.
C0
D0
E0
F0
00
10
20
30
40
50
60
70
80
90
A0
B0
C0
D0
E0
F0
00
10
20
30
40
50
60
70
80
90
A0
B0
C0
D0
E0
F0
HE84G752B
HE80004 Series
32x64
F
0
S63 ~ S00
*
COM14
*
S63 ~ S00
*
COM15
*
S63 ~ S00
*
COM16
*
S63 ~ S00
*
COM17
*
S63 ~ S00
*
COM18
*
S63 ~ S00
*
COM19
*
S63 ~ S00
*
COM20
*
S63 ~ S00
*
COM21
*
S63 ~ S00
*
COM22
*
S63 ~ S00
*
COM23
*
S63 ~ S00
*
COM24
*
S63 ~ S00
*
COM25
*
S63 ~ S00
*
COM26
*
S63 ~ S00
*
COM27
*
S63 ~ S00
*
COM28
*
S63 ~ S00
*
COM29
*
S63 ~ S00
*
COM30
*
S63 ~ S00
*
COM31
*
7.3. Black and White LCD Display RAM Map
Page
1
Cnf
Loc.
00
10
20
30
40
50
60
70
80
90
A0
B0
C0
32x64
F
0
*
S63 ~ S00
*
S63 ~ S00
*
S63 ~ S00
*
S63 ~ S00
*
S63 ~ S00
*
S63 ~ S00
*
S63 ~ S00
*
S63 ~ S00
*
S63 ~ S00
*
S63 ~ S00
*
S63 ~ S00
*
S63 ~ S00
*
S63 ~ S00
January 21, 2005
COM0
COM1
COM2
COM3
COM4
COM5
COM6
COM7
COM8
COM9
COM10
COM11
COM12
17
V0.93
This specification is subject to change without notice. Please contact sales person for the latest version before use.
KING BILLION ELECTRONICS CO., LTD
駿 億 電 子 股 份 有 限 公 司
Page
2
Cnf
Loc.
D0
E0
F0
00
10
20
30
40
50
60
70
80
90
A0
B0
C0
D0
E0
F0
HE84G752B
HE80004 Series
32x64
F
0
*
S63 ~ S00
*
S63 ~ S00
*
S63 ~ S00
*
S63 ~ S00
*
S63 ~ S00
*
S63 ~ S00
*
S63 ~ S00
*
S63 ~ S00
*
S63 ~ S00
*
S63 ~ S00
*
S63 ~ S00
*
S63 ~ S00
*
S63 ~ S00
*
S63 ~ S00
*
S63 ~ S00
*
S63 ~ S00
*
*
S63 ~ S00
S63 ~ S00
*
S63 ~ S00
January 21, 2005
COM13
COM14
COM15
COM16
COM17
COM18
COM19
COM20
COM21
COM22
COM23
COM24
COM25
COM26
COM27
COM28
COM29
COM30
COM31
18
V0.93
This specification is subject to change without notice. Please contact sales person for the latest version before use.
KING BILLION ELECTRONICS CO., LTD
駿 億 電 子 股 份 有 限 公 司
HE84G752B
HE80004 Series
8. LCD Power Supply
The built-in LCD power supply is equipped with input voltage regulator, voltage multiplier and bias
voltage generating circuit with active buffer instead of passive resistor voltage dividing network. If the
external LCD power is provided, the internal LCD power system shall be disabled. The following table
shows the relationship of the LCD power system
LCDE(LCDC BIT0)
MO_PSMODE[1:0]
Function
Internal voltage multiplier and Bias voltage
1
00
generating circuit are enable to supply the
LCD display power.
Internal voltage multiplier is enabled, but the
1
Bias voltage generating circuit is disabled,and
01
the external power sources are applied
LV4~LV1.
Internal voltage multiplier is disabled, but the
Bias voltage generating circuit is enabled.
1
10
The single external power is applied to LV5,
and internal bias circuit will generate the
LV4~LV1 voltages.
Internal voltage multiplier and Bias voltage
1
generating circuit are disabled, and the
11
external power sources are applied to
LV5~LV1.
0
The lcd power system is disable,but the LV5~
00
LV1 is applied to VDD .
The lcd power system is disable,but the LV5
0
01
is applied to VDD and LV4~LV1 is applied to
hight impedance.
The lcd power system is disable, LV5 is
0
10
applied to hight impedance,and the LV4~LV1
Applied to LV5.
0
January 21, 2005
The lcd power system is disable, LV5~LV1 is
11
applied to hight impedance.
19
V0.93
This specification is subject to change without notice. Please contact sales person for the latest version before use.
HE84G752B
KING BILLION ELECTRONICS CO., LTD
駿 億 電 子 股 份 有 限 公 司
HE80004 Series
when the internal LCD power system is used by internal voltage multiplier . The input voltage is
regulated to LVREG using the internally by resistor between LGS1 and LVREG generated LVAG as
reference voltage. LVREG can be adjusted
LVREG adjustment guideline: First, the level of VDD must be 0.3 volt higher than LVREG even at the
end of battery life for the regulator to function properly. For example, if the VDD is expected to drop to
2.2 volts when battery is low, then the level of LVREG can only be set at 1.9 volts max. Secondly, the
higher the level of LVREG, the less multiples it requires pumping LV5 to same level. For example, to
pump the 2.25 volts to 9 volts requires 4 times multiplier; to pump the 3 volts to 9 volts requires only 3
time multiplier which consumes less power. So it is advisable not to adjust the LVREG to an unnecessary
low level.
Voltage multiplication: The LVREG is then multiplied by 3, 4, or 5 times, depending on external
capacitors configurations as shown below, to generate LV5. Please note that LV5 must be lower than 8.5
volts to prevent chip from breaking down.
x4 multiplier
x3 multiplier
x5 multiplier
4.7uF
LVL1
4.7uF
LVL1
4.7uF
LVL1
0.1uF
LVL2
0.1uF
LVL2
0.1uF
LVL2
0.1uF
LVL3
0.1uF
LVL3
0.1uF
LVL3
4.7uF
LVL4
4.7uF
LVL4
4.7uF
LVL4
4.7uF
LV5
4.7uF
LVL5
4.7uF
LVL5
LCAP4A
LCAP4A
0.1uF
LCAP4A
LCAP2B
LCAP2B
LCAP2B
0.1uF
LCAP2A
0.1uF
LCAP2A
0.1uF
LCAP2A
0.1uF
LCAP1A
0.1uF
LCAP1A
0.1uF
LCAP1A
LCAP3A
0.1uF
LCAP3A
LVREG
0.1uF
LCAP1B
0.1uF
LCAP1B
LCAP3A
0.1uF
LVREG
0.1uF
R1
R2
0.1uF
GND_LCD
January 21, 2005
LCAP1B
R1
R2
LGS1
LVAG
R2
LGS1
LVAG
0.1uF
GND_LCD
LVREG
R1
0.1uF
LGS1
LVAG
GND_LCD
20
V0.93
This specification is subject to change without notice. Please contact sales person for the latest version before use.
KING BILLION ELECTRONICS CO., LTD
駿 億 電 子 股 份 有 限 公 司
HE84G752B
HE80004 Series
Different duties require different bias settings. There is some theoretical correspondence between the
Duty and Bias Setting. However, it is better to use it as starting point and adjust it with real LCD panel
connected to it to determine the final setting. The theoretic relationship between the duty and bias setting
as following:
Duty Cycle Normal Bias Alternative Bias
32 duty
1/7
1/7.5
48 duty
1/8
1/7.5, 1/8.5
64 duty
1/9
1/8.5, 1/9.5
80 duty
1/10
1/9.5, 1/10.5
The bias setting is made by mask option MO_LBSR[2..0].
MO_LBSR[2..0]
000
001
010
011
100
101
110
111
Bias Setting
1/7
1/7.5
1/8
1/8.5
1/9
1/9.5
1/10
1/5
9. LCDC Control register
LCD Control Register LCDC controls the functions of LCD driver.
LCDC
Field
Mode
Reset
bit 7
-
Field
Value
0
1
000
CLR_GP
GRAY
.
.
.
111
January 21, 2005
bit 6
-
bit 5
CLR_GP
W
1
bit 4
bit 3
GRAY
W
xxx
bit 2
bit 1
BLANK
W
1
bit 0
LCDE
W
0
Function
Reset GRAY palette register pointer by write ‘0’ to CLR_GP bit.
No effect on GRAY palette register pointer.
LCD is darkest.
LCD display contrast adjustment.
LCD is lightest.
21
V0.93
This specification is subject to change without notice. Please contact sales person for the latest version before use.
KING BILLION ELECTRONICS CO., LTD
駿 億 電 子 股 份 有 限 公 司
Field
Value
0
BLANK
LCDE
1
0
1
HE84G752B
HE80004 Series
Function
Normal display.
LCD display blanked. The COM signals of LCD driver output inactive levels
(LVL4 and LVL1) while SEG signals output normal display patterns.
LCD driver disabled, LCD driver has no output signal and applied to VDD
LCD driver Enabled.
Please note that LCD driver must be turned off before the system goes into "sleep" mode. That means
user must clear the bit 0 of LCDC to turn off LCD driving circuit before setting bit6 of OP1 to enter sleep
mode. Large current might happen if the procedure is not followed.
Please note that LCD driver uses slow clock as clock source. The LCD display will not display normally
if it works in Fast clock only mode because the LCD refresh action is too fast.
10. Oscillators
The MCU is equipped with two clock sources with a variety of selections on the types of oscillators to
choose from. The system designer can select oscillator types based on the cost target, timing accuracy
requirements etc. Crystal, Resonator or the RC oscillator can be used as fast clock source, components
should be placed as close to the pins as possible. The type of oscillator used is selected by mask option
MO_FXTAL.
MO_FXTAL
Fast clock type
0
RC Oscillator.
1
Crystal Oscillator.
FXI
FXI
FXO
FXO
Crystal Osc.
RC Osc.
The RC oscillator has a built-in capacitor. An external resistor is needed to connect from FXI to GND to
determine the oscillation frequency. The capacitance of internal RC oscillator is selected by mask option
MO_RCAP[2..0].
MO_RCAP[2:0]
000
001
010
011
100
101
January 21, 2005
Internal RC Cap. (pF)
2
4
7
14
20
40
22
V0.93
This specification is subject to change without notice. Please contact sales person for the latest version before use.
KING BILLION ELECTRONICS CO., LTD
駿 億 電 子 股 份 有 限 公 司
110
111
HE84G752B
HE80004 Series
50
60
The following table shows the combinations of R and C, and the resulting frequency. Please note that
oscillation frequency in the table only represents oscillation frequencies of certain samples. The actual
oscillation frequency may vary up to ±15% from lot to lot due to process parameter variations. User must
take this into consideration when using this chip in applications.
Ring Oscillator Frequency Table
C (pF)
R (KΩ)
30.20
19.92
9.98
40
20
14
7
4
0.8
1.2
2.3
1.5
2.2
4.0
2.0
2.8
5.1
3.0
4.4
7.5
4.0
5.6
9.4
2
5.0 MHz
7.0 MHz
11.4 MHz
Two types of oscillator, crystal and RC, can be used as slow clock selectable by mask option
MO_SXTAL. If used time keeping function or other applications that required the accurate timing, crystal
oscillator is recommended. If the timing accuracy is not important, then RC type oscillator can be used to
reduce cost.
MO_SXTAL
Slow clock type
0
R/C oscillator
1
Crystal oscillator
SXI
SXI
SXO
SXO
Crystal Osc.
RC Osc.
With two clock sources available, the system can switch among operation modes of Normal, Slow, Idle,
and Sleep modes by the setting of OP1 and OP2 registers as shown in tables below to suit the needs of
application such as high speed or low power, etc.
OP1
Field
Mode
Reset
Bit 7
DRDY
R/W
1
Bit 6
STOP
R/W
0
Bit 5
SLOW
R/W
0
Bit 4
INTE
R/W
0
Bit 3
T2E
R/W
0
Bit 2
T1E
R/W
0
Bit 1
Z
R/W
-
Bit 0
C
R/W
-
OP2
Field
Mode
Bit 7
IDLE
R/W
Bit 6
PNWK
R
Bit 5
TCWK
R
Bit 4
TBE
R/W
Bit 3
Bit 2
Bit 1
TBS[3..0]
W
W
Bit 0
January 21, 2005
23
W
W
V0.93
This specification is subject to change without notice. Please contact sales person for the latest version before use.
KING BILLION ELECTRONICS CO., LTD
駿 億 電 子 股 份 有 限 公 司
Reset
0
-
-
0
-
HE84G752B
HE80004 Series
-
-
-
If the dual clock mode is used, the LCD display, Timer1 and Timer Base will derive its clock source from
slow clock while the other blocks will operate with the fast clock.
11. General Purpose I/O
There are three dedicated general purpose I/O port, PRTC, PRTD and PRT10, while PRT15[1..0] and
PRT17 are multiplexed with LCD segment driver pins. All the I/O Ports are bi-directional and of nontri-state output structure. The output has weak sourcing (50 µA) and stronger sinking (1 mA) capability
and each can be configured as push-pull or open-drain output structure individually by mask option.
When the I/O port is used as input, the weakly high sourcing can be used as weakly pull-up. Open drain
can be used if the pull-up is not required and let the external driver to drive the pin. Please note that a
floating pad could cause more power consumption since the noise could interfere with the circuit and
cause the input to toggle. A ‘1’ needs to be written to port first before reading the input data from the I/O
pin. If the PMOS is used as pull-up, care should be taken to avoid the constant power drain by DC path
between pull-up and external circuit.
The input port has built-in Schmidt trigger to prevent it from chattering. The hysteresis level of Schmidt
trigger is 1/3 VDD.
VDD
DOUT
VDD
Q
LATCH
Q'
MO_?PP
PAD
DIN
SCHMIDT Trigger input
As pads of PRT15 and PRT17 are shared with LCD segment driver, the function of the pad is determined
by mask options. Following table is the setting for MO_LIO?[...] and MO_?PP[...] and others related to
LCD display setting and pin assignment features.
January 21, 2005
24
V0.93
This specification is subject to change without notice. Please contact sales person for the latest version before use.
KING BILLION ELECTRONICS CO., LTD
駿 億 電 子 股 份 有 限 公 司
HE84G752B
HE80004 Series
MO_LIO?[…] MO_?PP[...]
I/O Port
LCD Pin
0
0
Open-drain output
-0
1
Push-pull output
-1
0
-xx
1
1
-LCD Display
--: Function not available.
xx: Display enable, but may have abnormal leakage current, do not use.
January 21, 2005
25
V0.93
This specification is subject to change without notice. Please contact sales person for the latest version before use.
KING BILLION ELECTRONICS CO., LTD
駿 億 電 子 股 份 有 限 公 司
HE84G752B
HE80004 Series
12. Timer1
The Timer1 consists of two 8-bit write-only preload registers T1H and T1L and 16-bit down counter. If
Timer1 is enabled, the counter will decrement by one with each incoming clock pulse. Timer1 interrupt
will be generated when the counter underflows - counts down to FFFFH. And the counter will be
automatically reloaded with the value of T1H and T1L.
The clock source of Timer1 is derived from slow clock “SCK” at dual clock or slow clock only mode.
And it comes from the fast clock “FCK” at fast clock only mode.
Please note that the interrupt is generated when counter counts from 0000H to FFFFH. If the value of
T1H and T1L is N, and count down to FFFFH, the total count is N+1. The content of counter is zero
when system resets. Once it is enabled to count at this moment, interrupt will be generated immediately
and value of T1H and T1L will be loaded since it counts to FFFFH. So the T1H and T1L value should be
set before enabling Timer1.
T1H
The contents of
T1H and T1L are
almost loaded into
Timer1 immediately
when Timer1 is
enabled after reset.
T1L
Auto reload
when Timer1
is underflow
< Timer1 Counter >
Decreases 1
No
Count To
0xFFFFh
Yes
Timer1
Interrupt
Request
T1_INT
The Timer1 related control registers are list as below:
Register Address
Field
Bit position Mode
IER
0x02
TC1_IER
2
T1L
T1H
0x03
0x04
T1L[7:0]
T1H[7:0]
7~0
7~0
OP1
0x09
TC1E
2
January 21, 2005
Description
0: TC1 interrupt is disabled. (default)
R/W
1: TC1 interrupt is enabled.
W Low byte of TC1 pre-load value
W High byte of TC1 pre-load value
0: TC1 is disabled. (default)
R/W
1: TC1 is enabled.
26
V0.93
This specification is subject to change without notice. Please contact sales person for the latest version before use.
KING BILLION ELECTRONICS CO., LTD
駿 億 電 子 股 份 有 限 公 司
HE84G752B
HE80004 Series
13. Timer2
Timer2 is similar in structure to Timer1 except that clock source of Timer2 comes from the system clock
“Fsys”/1.5. The system clock “Fsys” varies depending on the operation modes of the MCU.
The Timer2 consists of two 8-bit write-only preload registers T2H and T2L and 16-bit down counter. If
Timer2 is enabled, counter will decrement by one with each incoming clock pulse. Timer2 interrupt will
be generated when the counter underflows - counts down to FFFFH. And it will be automatically reloaded
with the value of T2H and T2L.
Please note that the interrupt signal is generated when counter counts from 0000H to FFFFH. If the value
of counter is N, and count down to FFFFH, the total count is N+1. The content of counter is zero when
system resets. Once it is enabled to count at this time, the interrupt will be generated immediately and
value of T2H and T2L will be loaded since the counter counts to FFFFH. So the T2H and T2L value
should be set before enabling Timer2.
The Timer2 related control registers are list as below:
Register Address
Field
Bit position Mode
IER
0x02
TC2_IER
1
T2L
T2H
0x05
0x06
T2L[7:0]
T2H[7:0]
7~0
7~0
OP1
0x09
TC2E
3
January 21, 2005
Description
0: TC2 interrupt is disabled. (default)
R/W
1: TC2 interrupt is enabled.
W Low byte of TC2 pre-load value
W High byte of TC2 pre-load value
0: TC2 is disabled. (default)
R/W
1: TC2 is enabled.
27
V0.93
This specification is subject to change without notice. Please contact sales person for the latest version before use.
KING BILLION ELECTRONICS CO., LTD
駿 億 電 子 股 份 有 限 公 司
T2H
The contents of
T2H and T2L are
almost loaded into
Timer2 immediately
when Timer2 is
enabled after reset.
T2L
HE84G752B
HE80004 Series
Auto reload
when Timer2
is underflow
< Timer2 Counter >
Decreases 1
No
Count To
0xFFFFh
Timer2
Interrupt
Request
Yes
T2_INT
14. Time Base
The TB timer is used to generate time-out interrupt at fixed period. The time-out frequency of TB is
determined by dividing slow clock with a factor selected in OP2[3..0]. TBE (Time Base Enable) bit
controls enable or disable of the circuit.
OP2
Field
Mode
Reset
Bit 7
IDLE
R/W
0
Bit 6
PNWK
R
-
Bit 5
TCWK
R
-
Bit 4
TBE
R/W
0
Bit 3
R/W
-
Bit 2
Bit 1
TBS[3..0]
R/W
R/W
-
Bit 0
R/W
-
TBE
Function
0
Disable Time Base
1
Enable Time Base
For example, if the slow clock is 32768 Hz, then the interrupt frequency is as shown in following table.
TBS[3..0]
0000
0001
0010
0011
0100
0101
0110
0111
1000
January 21, 2005
Interrupt Frequency
16.384 KHz
8.192 KHz
4.096 KHz
2.048 KHz
1.024 KHz
512 Hz
256 Hz
128 Hz
64 Hz
28
V0.93
This specification is subject to change without notice. Please contact sales person for the latest version before use.
KING BILLION ELECTRONICS CO., LTD
駿 億 電 子 股 份 有 限 公 司
TBS[3..0]
1001
1010
1011
1100
1101
1110
1111
HE84G752B
HE80004 Series
Interrupt Frequency
32 Hz
16 Hz
8 Hz
4 Hz
2 Hz
1 Hz
0.5 Hz
15. Watch Dog Timer
Watch Dog Timer (WDT) is designed to reset system automatically and prevents system dead lock caused
by abnormal hardware activities or program execution. The WDT needs to be enabled in Mask Option.
MO_WDTE
0
1
Function
WDT disable
WDT enable
Using the WDT function, the “CLRWDT” instruction needs to be executed in every possible program
path when the program runs normally in order to clears the WDT counter before it overflows, so that the
program can operate normally. When abnormal conditions happen to cause the MCU to divert from
normal path, the WDT counter will not be cleared and reset signal will be generated to reset the system.
The WDT clock source is the same as TC1 (Timer1 clock), and the WDT reset signal is generated when
the counter had counted 32768 clock. The WDT can function in Normal, Slow and Idle Mode. However,
WDT will not function during Sleep Mode (as the TC1 clock has stopped.)
January 21, 2005
29
V0.93
This specification is subject to change without notice. Please contact sales person for the latest version before use.
HE84G752B
KING BILLION ELECTRONICS CO., LTD
駿 億 電 子 股 份 有 限 公 司
HE80004 Series
16. Voice Output
There are 7 or 8 bits DAC/PWM voice output available for user. The 7 bits DAC/PWM output format and
configuration are the same as the previous IC of HE80000 series. The 8 bits DAC/PWM format and
configuration are new designed and controlled by the VOC and PWMC registers. The selection of 7/8 bits
DAC/PWM output is by mask option MO_8BVOC.
MO_8BVOC
0
1
Function
7-bit DAC/PWM output
8-bit DAC/PWM output
8-Bit DAC/PWM Output:
The Digital-to-Analog converter converts the 8-bit unsigned speech data which is written into PWMC
data register to proportional current output.
PWMC
Field
address
0x0E
Reset
--
bit 7
DA7
bit 6
DA6
bit 5
DA5
bit 4
DA4
bit 3
DA3
bit 2
DA2
bit 1
DA1
bit 0
DA0
There are two output paths for the DAC. Either VO or DAO can be selected as output port of DAC by
VOC register when it is enabled. The VO output is primarily intended for speech generation, although it
is not necessary so, while the DAO output path can be used in conjunction with built-in OP comparator to
function as an Analog-to-Digital Converter as required in applications such as speech recording, speech
recognition or sensor interfaces.
OPO
OP
+
-
PWMC[DATA]
DAC
OPIP
OPIN
1
DAO
0
VO
R
VOC[DAC]
VOC[OP]
The DAC is enabled by DAC bit of VOC register. When DAC is enabled, the DAC output path can be
selected to output to DAO or VO pin by OP bit of VOC register.
VOC
Field
Reset
address
0x13
January 21, 2005
Bit 7
-
Bit 6
Bit 5
Bit 4
PWM O/P driver
0
0
0
30
Bit 3
PWME
0
Bit 2
PWM
0
Bit 1
DAC
0
Bit 0
OP
0
V0.93
This specification is subject to change without notice. Please contact sales person for the latest version before use.
KING BILLION ELECTRONICS CO., LTD
駿 億 電 子 股 份 有 限 公 司
Bit
Name
Value
1
VOC[3] PWME
0
1
VOC[2] PWM
0
1
VOC[1] DAC
0
1
VOC[0]
OP
0
HE84G752B
HE80004 Series
Function description
PWM Output Driver Enable
PWM Output Driver Disable
PWM Module Enable
PWM Module Disable
Digital-to-Analog Converter Enable
Digital-to-Analog Converter Disable
DAC output to DAO pin
DAC output to VO pin
The pulse-width modulator (PWM) converts 8-bit unsigned speech data which is written into PWMC data
register to proportional duty cycle of PWM output. PWM module shares the same digital input register
PWMC with Digit-to-Analog Converter. So PWM and DA output can exist at the same time. When PWM
circuit is enabled, it generates signal with duty ratio in proportion to the value of PWMC register.
DA = 0x20
DA = 0x80
DA = 0xE0
1 subframe
PWMC
Field
VOC
address
0x0E
bit 7
DA7
bit 6
DA6
bit 5
DA5
bit 4
DA4
VOC
Field
Reset
address
0x13
Bit 7
-
Bit 6
Bit 5
Bit 4
PWM O/P driver
0
0
0
bit 3
DA3
bit 2
DA2
bit 1
DA1
bit 0
DA0
Bit 3
PWME
0
Bit 2
PWM
0
Bit 1
DAC
0
Bit 0
OP
0
The PWM bit of VOC controls the enable/disable of the PWM circuit and output driver. When PWM bit
of VOC is ‘0’, PWME bit and output drivers are both cleared. To use PWM as voice output, PWM bit has
to be set to ‘1’ first, then set PWME bit and enable output driver by setting the driver number. If PWM bit
is disabled and enabled again, the setting for driver and PWME bit will be clear.
The Fast Clock is gated through PWME bit of VOC register to provide the clock source of PWM circuit
when it is enabled. As PWM needs higher frequency to operate, it cannot generate correct PWM signal in
Slow clock only mode.
When the program enters into sleep mode or idle mode, it will automatically turn off all voice outputs by
January 21, 2005
31
V0.93
This specification is subject to change without notice. Please contact sales person for the latest version before use.
KING BILLION ELECTRONICS CO., LTD
駿 億 電 子 股 份 有 限 公 司
HE84G752B
HE80004 Series
clearing VOC[6:0] to ”0000000”. To activate voice output again when returning to normal mode, the
VOC register needs to be set again.
The PWM output volume can be adjusted by command register VOC[6..4]. The bit 6 and 5 control 2
time driver, while bit 4 controls 1 time driver, thus it has 5 levels of driver output. By turning on/off the
internal drivers, the sound level of PWM output can be turned up and down. Please note that this
adjustment apply only to PWM, but not DA output.
PWM output driver selection
VOC[6..4]
Number of Driver
000
off
001
1
010
2
011
3
100
2
101
3
110
4
111
5
7-Bit DAC/PWM Output:
The 7-bit DAC/PWM voice generator is another scenario and the definitions of PWMC and VOC
registers are different from the 8-bit DAC/PWM format. These register are described as following.
The 7-bit voice output is controlled by PWMC and VOC register, and the PWMC is a command/data
register which is determined by PWMC[7] bit.
PWMC register
DA & PWM Data
Control
Bit 7
0
1
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
DA and PWM output value
PWM O/P driver
Reserved
Bit 1
Bit 0
PWME
When users write data into the PWMC register, the PWMC[7] bit will determines the data written into
PWM command register or 7-bit data register and the data register is also sent to the DA converter shown
as the below diagram. The definitions of “PWME” bit and “PWM O/P driver” bits are the same as VOC
register definition of 8-bit output mode.
January 21, 2005
32
V0.93
This specification is subject to change without notice. Please contact sales person for the latest version before use.
HE84G752B
KING BILLION ELECTRONICS CO., LTD
駿 億 電 子 股 份 有 限 公 司
_____
reset
VOC[2]
PWMC[6..0]
Register.write.strobe
PWMC[7]
PWMC_REG[6..4]
PWM
command
register
CLK
PWMC_REG[3..1]
HE80004 Series
PWM
Driver
_____
reset
PWMC
_REG[0]
PWMP
PWMN
cp
Fast clock
PWMC[6..0]
7 bit data
register
PWM_O[6..0]
DAC
CLK
The fast clock is used to provide as PWM driver time base, and user shall set the PWMC[7]=’1’ and
VOC[2]=’1’ to enable the PWM output. When the system enters into sleep or idle mode, it will
automatically turn off the voice device by clearing VOC[2:0] to ”000”. In order to activate voice output
again when the system returns and enter into normal mode, the related bits of VOC register need to be set
again.
PWM
Data=0x40h
Data=0x10h
Data=0x70h
subframe
When the DAC is used as sound generator, the bias & filter circuit is used for bias voltage setting and
waveform filter regulation and the DAC is output to the VO (Voice Output) pin and please see application
notes for detailed calculation example and application. The driving capability of DAC is shown below.
VO/DAO
January 21, 2005
Condition
VDD=3V;VO=0~2V;Data=7Fh
33
Min.
2.5
Typ.
3
Max.
Unit
mA
V0.93
This specification is subject to change without notice. Please contact sales person for the latest version before use.
KING BILLION ELECTRONICS CO., LTD
駿 億 電 子 股 份 有 限 公 司
HE84G752B
HE80004 Series
VDD
CPU
VO(DAO)
bias &
filter
circuit
SPEAKER
The VOC is a three bit voice control register in the 7-bit mode.
VOC
address
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Field
0x13
PWM
Reset
0
PWM: ‘1’ PWM output enabled; ‘0’ PWM output disabled.
DAC: ‘1’ DAC enabled; ‘0’ DAC disabled.
OP: ‘1’ DAC uses DAO pin as output pin; ‘0’ DAC uses VO pin as output pin.
Bit 1
DAC
0
Bit 0
OP
0
17. Low Voltage Detection/Reset
The low voltage detection is used to detect low battery or low power condition. There are 4 options on the
detection level selectable by mask option MO_DLVL. The low voltage detection circuit can be turned off
by clearing LVDE bit, and the status of supply power can be read out at bit LVDO of LVDC register
(extension register 0x17h).
MO_DLVL
00
01
10
11
Detection voltage
2.4 volts
2.6 volts
2.8 volts
3.0 volts
LVDC Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Field LVDO
LVDE
Mode
R
W
Reset
0
LVDO: ‘0’ Æ Battery level low; ‘1’ Æ Battery level high
LVDE: ‘0’ Æ Disable voltage Detection; ‘1’ Æ Enable voltage Detection
Low voltage reset circuit prevents the CPU from operating below its physical limit. When the supply
voltage drops below VDET (2.2Volt), the CPU will be held in reset state until the supply voltage rises to
VRLS. Then CPU will be released from reset state. VRLS will be higher than VDET by 5% to provide
hysteresis and prevent CPU from bouncing back and forth between reset and operating state. The low
voltage reset function can be enabled or disabled by mask option MO_LVRE.
January 21, 2005
34
V0.93
This specification is subject to change without notice. Please contact sales person for the latest version before use.
KING BILLION ELECTRONICS CO., LTD
駿 億 電 子 股 份 有 限 公 司
HE84G752B
HE80004 Series
MO_LVRE
Function
0
Disable LVR
1
Enable LVR
The voltage detection circuit is temperature compensated to prevent the detection voltage from drifting
with temperature variation.
Vrst
VDD
Vdet
Vrls
18. Infrared output
To achieve an IR output with programmable frequency and duty cycle, two 7-bit registers are employed
here. The IRH register represents the period (on FCK clock number) of output high, while IRL register
represents the period of output low. With this mechanism, the output IR frequency is equal to
FCK/(IRH+IRL), and the high duty cycle ratio is equal to IRH/(IRH+IRL). To make the IRO as output
pin alone, either IRH or IRL can be set as 0. When IRH is 0, the IRO output is a DC low. On the contrary,
if IRL is 0, the output is a DC high. Special care in hardware implementation is also taken according to
the MO_IRO (mask option to determine the default state of the IRO) to avoid glitch when PWM output is
disabled.
January 21, 2005
35
V0.93
This specification is subject to change without notice. Please contact sales person for the latest version before use.
HE84G752B
KING BILLION ELECTRONICS CO., LTD
駿 億 電 子 股 份 有 限 公 司
HE80004 Series
IRO
IRO
MUX
IR
generator
Compare
Counter+1
D Counter Q
7-bit
Fck
CK
R
IRO
IRL=0?
0
IRH=0?
1
IRL
MO_IRO
IRH
Toggle signal
reset
To avoid unexpected IR output, users should firstly load the content of IRH and IRL before turn on IR by
set IROE bits to ‘1’.
The access of all the registers of IR is through the extension register. They are list as below:
Extension register
Address Name Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1
0x15h IRL* IROE
IR PWM LOW DURATION
0x16h IRH
IR PWM HIGH DURATION
* IRL[7] is read/write, and IRL[6..0] is write only.
Bit0 Mode
R/W
W
Reset value
0xxx xxxx
-xxx xxxx
IROE: ‘0’ Æ IR is disabled (default); ‘1’ Æ IR is enabled.
January 21, 2005
36
V0.93
This specification is subject to change without notice. Please contact sales person for the latest version before use.
KING BILLION ELECTRONICS CO., LTD
駿 億 電 子 股 份 有 限 公 司
19.
HE84G752B
HE80004 Series
Universal Asynchronous Receiver/Transmitter
The UART (Universal Asynchronous Receiver/Transmitter) interface provides serial communication
capabilities with other devices such as PC. Features include:
9
9
9
9
9
9
9
9
9
Full duplex Asynchronous communication
Programmable transmission rate with internal baud rate generator with selectable bit rates
Double buffered Transmitter and Receiver.
Programmable Data length (from 5 to 8 bits)
Programmable stop bits (1, 1.5 or 2-stop bit) generation and detection
Programmable parity type (odd, even or no parity)
Error (parity, overrun and framing errors) detection
Fully prioritized interrupt system control
Line break generation and detection.
Example – 8-bit UART Frame Format: (1 Start Bit, 8 Data Bits, 1 Parity Bit, 1 Stop Bit)
January 21, 2005
37
V0.93
This specification is subject to change without notice. Please contact sales person for the latest version before use.
HE84G752B
KING BILLION ELECTRONICS CO., LTD
駿 億 電 子 股 份 有 限 公 司
Trans Hoding Reg
HE80004 Series
Trans Shift Reg
SOUT
TRANSMIT
MACHINE
Data
Bus
Buffer
EX_PT[7:0]
“Transmitter
control signal"
TRANSMITTER
TIMING
AND
CONTROL
Line Control Reg
“Transmitter
status"
Div Latch (MS)
ADS_N
BAUD-RATE
GENERATOR
XRD_N
Div Latch (LS)
BrgClk
XWR_N
MCLK
MCU
I/F
“Receive status"
Line Status Reg
CTRL
LOGIC
RECEIVE
TIMING
AND
CONTROL
“Receiver
control signal"
Rec Buffer Reg
RESET
RECEIVE
MACHINE
Interrupt Id Reg
Interrupt
Arbitrator
Interrupt En Reg
INTR
Rec Shift Reg
SIN
19.1. Interface Registers
Addressable extension register used to interface with MCU
Address
00H
01H
02H
03H
04H
05H
06H
Name
RBR
THR
IEIR
LCR
BRL
BRH
LSR
0
BRGE
0
Function
UART RECEIVER BUFFER
UART TRANSMITTER HOLDING REGISTER
RLSI
THRI
RBRI
0
ID2
ID1
SB
SP
EPS
PEN
STB
WLS1
UART LSB of Baud Rate Register
UART MSB of Baud Rate Register
TEMT
THRE
BI
FE
PE
OE
ID0
WLS0
DR
Mode
R
R/W
R/W
R/W
R/W
R/W
R
RESET
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0110 0000
IEIR: Interrupt enable/disable identification register.
LCR: Line control register.
LSR: Line status register.
19.2.Baud Rate Configuration Register
The BRH and BRL registers hold the upper and lower bytes of 16 bit baud rate divisor and which are
readable/writable. The baud rate of UART is calculated as following:
January 21, 2005
38
V0.93
This specification is subject to change without notice. Please contact sales person for the latest version before use.
KING BILLION ELECTRONICS CO., LTD
駿 億 電 子 股 份 有 限 公 司
BAUD _ RATE _ DIVISOR =
HE84G752B
HE80004 Series
FCK
, (FCK: fast clock of system)
16 * BAUD _ RATE
The contents of BRH and BRL are calculated by the following two formulas:
BRL = BAUD _ RATE _ DIVISOR % 256
BRH = ( BAUD _ RATE _ DIVISOR – BRL) / 256
The “%” symbol is the modulus operation (reminder of division). For example, if the FCK is 1.8432M Hz
and the desired baud rate is 2400 baud, then
BAUD _ RATE _ DIVISOR =
1843200
= 48
16 * 2400
The BRL register shall be set to 0x30 and BRH set to 0x00. The setting of baud_rate_divisor is not
updated until the BRH register is written. Thus user is strongly recommended to write BRL first, then
BRH.
In order to obtain good communication quality, the same time base shall be used in the both sides of
transmitting and receiving. The following table shows the most common baud rate setting used in the PC
UART communication.
BRL and BRH: Baud Rate Control Registers
FCK(Hz) Baud Rate (bps) Divisor
BRL
1.8432M
50
2304
0x00
1.8432M
300
384
0x80
1.8432M
1200
96
0x60
1.8432M
2400
48
0x30
1.8432M
4800
24
0x18
1.8432M
9600
12
0x0C
1.8432M
19200
6
0x06
1.8432M
38400
3
0x03
1.8432M
57600
2
0x02
1.8432M
115200
1
0x01
BRH
0x09
0x01
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
19.3. Interrupt & Identification Register
This high nibble of IEIR register allows to enable/disable interrupt generation by the UART, the low
nibble ID[2..0] of IEIR register is used to identify the source of interrupts.
Address
0x02h
Name
IEIR
Bit 7 Bit 6 Bit 5
Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Reset Value
0
RLSI THRI RBRI
0
ID2
ID1
ID0
“0000_0000”
R/W
R/W
R/W
R
R
R
RBRI: Receiver Buffer Register Interrupt (1 = Enable, 0 = Disable), related to ID[1] bit.
THRI: Transmitter Hold Register Interrupt (1 = Enable, 0 = Disable), related to ID[0] bit.
RLSI: Receiver Line Status Interrupt (1 = Enable, 0 = Disable), related to ID[2] bit.
January 21, 2005
39
V0.93
This specification is subject to change without notice. Please contact sales person for the latest version before use.
KING BILLION ELECTRONICS CO., LTD
駿 億 電 子 股 份 有 限 公 司
HE84G752B
HE80004 Series
The following table shows the related interrupt sources, user can read the ID[2:0] to retrieve what is the
current highest priority of pending interrupts. The ID[2:0] bits will be cleared when user read the related
registers. For example, when an interrupt happened and the content of ID[2:0] is “101”, this means that
LRS error and THR empty happen; user can read the LSR register to clear the ID[2] bit and ID[0] bit can
also be cleared by reading the IEIR or writing data into THR register.
Level
None
Highest
Second
IEIR Bit [2:0]
Source of Interrupt
000
None
100
LSR error flags (OE/PE/FE/BI)
010
LSR receiver data ready flag (DR)
Third
001
LSR flag THR Empty (THRE)
Interrupt Reset Control
None
Reading LSR register to clear ID[2]
Reading RBR register to clear ID[1]
Reading IEIR register or Writing
THR register to clear ID[0]
19.4.Line Control Register
The line control register allows user to configure the asynchronous data transfer format and set the UART
function. Reading from the register is allowed to check the current settings of the communication.
Bit 7
BRGE
Bit 6
SB
Bit 5
SP
Bit 4
EPS
Bit 3
PEN
Bit 2
STB
Bit 1
WLS1
Bit 0
WLS0
Name
Description
Word Length Select
“00”: word length = 5
“01”: word length = 6
WLS[1..0]
“10”: word length = 7
“11”: word length = 8
Stop Bit Length
‘0’: Stop bit length = 1
STB
‘1’: Stop bit length = 1.5 when WLS[1..0]=”00”
‘1’ Stop bit length = 2 when WLS[1..0]=”01”,”10”,”11”
Parity Selection
“xx0”: No Parity
“001”: odd Parity
[SP, EPS, PEN]
“011”: even Parity
“101”: Stick Parity 1
“111”: Stick parity 0
Set Break
When enable the break control bit causes a break condition to be transmitted (SOUT is
forced to a logic 0 state). This condition exists until disabled by resetting this bit to
SB
logic 0.
‘0’: disable break; ‘1’: enable break
Baud Rate Generator
‘0’: disable baud rate clock generator
BRGE
‘1’: enable baud rate clock generator
January 21, 2005
40
V0.93
This specification is subject to change without notice. Please contact sales person for the latest version before use.
KING BILLION ELECTRONICS CO., LTD
駿 億 電 子 股 份 有 限 公 司
HE84G752B
HE80004 Series
19.5.Line Status Register
Bit 7
0
Bit 6
TEMT
Name
DR
OE
PE
FE
Bit 5
THRE
Bit 4
BI
Bit 3
FE
Bit 2
PE
Bit 1
OE
Bit 0
DR
Description
Receiver Data Ready
DR indicates status of RBR. It will be set to logic 1 when RBR data is valid and will
be reset to logic 0 when RBR is empty. When line errors (OE/PE/FE/BI) happen, DR
will also be set to logic 1 and RBR will be updated to reflect the Data bits portion of
the frame.
Overrun Error
This bit will be set when the next character is transferred into RBR before the
previous RBR data is read by the CPU. Even though DR will still be 1 when OE is set
to logic 1, the previous frame data stored in RBR which is not read by the CPU is
trashed and can‘t be recovered.
Parity Error
This bit will be set to logic 1 only when the Parity is enabled and the Parity bit is not
at the logic state it should be. For Even Parity, the Parity bit should be 1 if an odd
number of 1s in the Data bits is received; otherwise, the Parity bit should be 0. For
Odd Parity, the Parity bit should be 1 if an even number of 1s in the Data bits is
received; otherwise, the Parity bit should be 0. For Stick Parity '1', the Parity bit
should be 1. For Stick Parity '0', the Parity bit should be 0.
Framing Error
FE will be reset to logic 0 whenever SIN is sampled high at the center of the first
Stop bit, regardless of how many Stop bits the UART is configured to.
Break Interrupt
BI will be set to logic 1 whenever SIN is low for longer than the whole frame (the
time of Start bit + Data bits + Parity bit + Stop bits), not at the SIN rising edge where
BI
Break is negated. If SIN is still low after BI is reset to logic 0 by reading LSR, BI will
not be set to logic 1 again. Since Break is also a Framing error, FE will also be set to
1 when BI is set.
THR Empty
THRE will be set to logic 1 whenever THR is empty which indicates that the
THRE
transmitter is ready to accept new data to transmit.
Both THR and TSR are Empty
This bit will be set to logic 1 when THRE is set to 1 and the last Data bit in the TSR
TEMT
is shifted out through SOUT.
* The four error flags (OE, PE, FE and BI) of LSR will be reset to logic 0 after a LSR read.
Since the SIN and SOUT of UART pins are shared with PRTD[1..0], users can use the mask option to
enable the UART function and select PRTD[1..0] function.
MO_UART
January 21, 2005
0
1
PRTD[1:0] = I/O Pin
PRTD[1:0] = UART Pin
41
V0.93
This specification is subject to change without notice. Please contact sales person for the latest version before use.
HE84G752B
KING BILLION ELECTRONICS CO., LTD
駿 億 電 子 股 份 有 限 公 司
HE80004 Series
20. Extension Register Access
The extension registers can be accessed through the extension port control registers EXTAS and
EXTDA. User can read/write the extension register easily and the control timing is generated by
hardware automatically. The following code shows how to access the extension registers.
Read Extension Register:
LDA
#0x00h ; load #0x00h data to A Register
STA
EXTAS
; store A register data to the extension port address register.
LDA
EXTDA ; store the extension register (0x00h) data to A Register.
Write Extension Register:
LDA
#0x03h ; load #0x03h data to A Register
STA
EXTAS
; store A register data to the extension port address register.
LDA
#0x18h ; load #0x18h data to A Register
STA
EXTDA ; store A register data to the extension port data register.
21. Summary of Registers and Mask Options
All the registers and mask options used in this chip are listed in the following tables.
Address NAME
00H
TPL
01H
TPH
02H
IER
03H
T1L
04H
T1H
05H
T2L
06H
T2H
07H
SP
08H
DP
09H
DRDY
OP1
0AH
IDLE
OP2
0BH
PP
0CH
PRTC
0DH
PRTD
0EH
PWMC*
0FH
LCDC
10H
PRT10
11H
PRT11
12H
DTMF
13H
VOC*
14H
PRT14
15H
PRT15
16H
TPP
January 21, 2005
Field
Table pointer low byte
Table pointer high byte
INT_EX
TB
INT1
T1
T2
Timer 1 low byte
Timer 1 high byte
Timer 2 low byte
Timer 2 high byte
stack pointer
data RAM pointer
STOP
SLOW
INTE
T2E
T1E
Z
PNWK TCWK
TBE
TBS[3..0]
RAM page pointer
I/O port C
I/O port D
PWM data
CLR_GP
GRAY
BLANK
I/O port 10
Reserved
Reserved
PWM O/P driver
PWME
PWM
DAC
Reserved
I/O port 15
ROM table page pointer
42
INT2
C
LCDE
OP
Mode
R/W
R/W
R/W
W
W
W
W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
W
W
R/W
R/W
R/W
W
R/W
R/W
R/W
RESET
xxxx xxxx
xxxx xxxx
--00 0000
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
1111 1111
xxxx xxxx
1000 00xx
0xx- ---0000 0000
1111 1111
1111 1111
0000 0000
xx1x xx10
1111 1111
xxxx xxxx
xxxx xxxx
x000 0000
xxxx xxxx
---- --11
0000 0000
V0.93
This specification is subject to change without notice. Please contact sales person for the latest version before use.
KING BILLION ELECTRONICS CO., LTD
駿 億 電 子 股 份 有 限 公 司
Address NAME
17H
PRT17
18~1FH
20H
EXTAS
21H
EXTDA
22~2AH
2BH GRAY16
GRAY0
GRAY1
GRAY2
GRAY3
GRAY4
GRAY5
GRAY6
GRAY7
GRAY8
GRAY9
GRAYA
GRAYB
GRAYC
GRAYD
GRAYE
GRAYF
2CH
PSA1
2DH
PSA2
2EH
PSA3
2FH~3FH
Field
I/O port 17
Reserved
Extension port address register
Extension port data register
Reserved
32 to 16 Gray Level Palette Register
Gray level 0 mapping register
Gray level 1 mapping register
Gray level 2 mapping register
Gray level 3 mapping register
Gray level 4 mapping register
Gray level 5 mapping register
Gray level 6 mapping register
Gray level 7 mapping register
Gray level 8 mapping register
Gray level 9 mapping register
Gray level A mapping register
Gray level B mapping register
Gray level C mapping register
Gray level D mapping register
Gray level E mapping register
Gray level F mapping register
Physical page address mapping register for logical page 1
Physical page address mapping register for logical page 2
Physical page address mapping register for logical page 3
Reserved
HE84G752B
HE80004 Series
Mode
R/W
R/W
R/W
R/W
R/W
w
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
R/W
R/W
R/W
R/W
RESET
1111 1111
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxx0 0000
xxx0 0010
xxx0 0100
xxx0 0110
xxx0 1000
xxx0 1010
xxx0 1100
xxx0 1110
xxx1 0000
xxx1 0010
xxx1 0100
xxx1 0110
xxx1 1000
xxx1 1010
xxx1 1100
xxx1 1110
0000 0001
0000 0010
0000 0011
xxxx xxxx
* The definitions of PWMC and VOC are different for 7-bit and 8-bit voice output. Please refer to voice
output section for the detailed description.
Extension registers:
Address
00H
01H
02H
03H
04H
05H
06H
15H
16H
17H
Name
RBR
THR
IEIR
LCR
BRL
BRH
LSR
IRL
IRH
LVDC
0
BRGE
0
IROE
-
LVDO
Function
UART RECEIVER BUFFER
UART TRANSMITTER HOLDING REGISTER
RLSI
THRI
RBRI
0
ID2
ID1
SB
SP
EPS
PEN
STB
WLS1
UART LSB of Baud Rate Register
UART MSB of Baud Rate Register
TEMT
THRE
BI
FE
PE
OE
IR PWM LOW DURATION
IR PWM HIGH DURATION
-
Mode
R
R/W
ID0
R/W
WLS0 R/W
R/W
R/W
DR
R
R/W
W
LVDE R/W
RESET
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0110 0000
0xxx xxxx
-xxx xxxx
x--- ---0
Mask Options:
NAME
MO_LVRE
MO_FXTAL
MO_SXTAL
MO_FCK/SCKN
January 21, 2005
VALUE
0
1
0
1
0
1
00
01
NOTE
low voltage reset disable
low voltage reset enable
R/C oscillator For fast clock
Crystal oscillator For fast clock
R/C oscillator For 32k clock
Crystal oscillator For 32k clock
slow clock only
illegal
43
V0.93
This specification is subject to change without notice. Please contact sales person for the latest version before use.
KING BILLION ELECTRONICS CO., LTD
駿 億 電 子 股 份 有 限 公 司
NAME
MO_WDTE
MO_CPP[7:0]
MO_DPP[7:0]
MO_10PP[7:0]
MO_15PP[1:0]
MO_17PP[7:0]
MO_LIO15[1:0]
MO_LIO17[7:0]
MO_COM[1:0]
MO_LBSR[2:0]
MO_RCAP[2:0]
MO_8BVOC
MO_GRAY_MODE[1:0]
MO_EXMEM
MO_DLVL[1:0]
MO_IRO
MO_PMODE[1:0]
MO_UART
MO_PSMODE[1:0]
January 21, 2005
VALUE
10
dual clock
11
fast clock only
0
WDT disable
1
WDT enable
0
open-drain output
1
push-pull output
0
open-drain output
1
push-pull output
0
open-drain output
1
push-pull output
0
open-drain output
1
push-pull output
0
open-drain output
1
push-pull output
0
IO pin
1
LCD pin
0
IO pin
1
LCD pin
Fixed to “00”
000
1/7 bias
001
1/7.5 bias
010
1/8 bias
011
1/8.5 bias
100
1/9 bias
101
1/9.5 bias
110
1/10 bias
111
1/5 bias
000
Ring-osc internal cap. Select
001
Ring-osc internal cap. Select
010
Ring-osc internal cap. Select
011
Ring-osc internal cap. Select
100
Ring-osc internal cap. Select
101
Ring-osc internal cap. Select
110
Ring-osc internal cap. Select
111
Ring-osc internal cap. Select
0
7-bit DAC/PWM output
1
8-bit DAC/PWM output
00
16 Gray Level
01
4 Gray Level
10
2 Level(B/W)
11
2 Level(B/W)
HE84G752B
HE80004 Series
NOTE
C=2P
C=4P
C=7P
C=14P
C=20P
C=40P
C=50P
C=60P
Fixed to “0”
00
01
10
11
0
1
LVD level voltage detect is 2.4V
LVD level voltage detect is 2.6V
LVD level voltage detect is 2.8V
LVD level voltage detect is 3.0V
Default State of the IRO is ‘0’
Default State of the IRO is ‘1’
Fixed to “00”
0
1
00
01
10
PRTD[1:0] = I/O Pin
PRTD[1:0] = UART Pin
Internal Mode(
Internal CP+External R String and Opamps
External CP+Internal R String and Opamps
44
V0.93
This specification is subject to change without notice. Please contact sales person for the latest version before use.
HE84G752B
KING BILLION ELECTRONICS CO., LTD
駿 億 電 子 股 份 有 限 公 司
NAME
VALUE
11
HE80004 Series
NOTE
External CP+External R String and Opamps
22. Absolute Maximum Rating
Item
Symbol
Rating
Condition
Supply Voltage
VDD
-0.5V ~ 4.0V
Input Voltage
VIN
-0.5V ~ VDD+0.5V
Output Voltage
VO
-0.5V ~ VDD+0.5V
Operating Temperature
TOP
0°C ~ 70°C
Storage Temperature
TST
-50°C ~ 100°C
23. Recommended Operating Conditions
Item
Supply Voltage
Symbol
Rating
Condition
VDD
2.4V ~ 3.6V
VIH
0.9 VDD ~ VDD
Input Voltage
VIL
0.0V ~ 0.1VDD
8M Hz
VDD =3.0V
Operating Frequency
FMAX.
6M Hz
VDD =2.4V
°
°
Operating Temperature
TOP
0 C ~ 70 C
Storage Temperature
TST
-50°C ~ 100°C
24. AC/DC Characteristics
Testing Condition : TEMP=25℃, VDD=3V±10%
Parameters
Symbol
Power consumption
NORMAL Mode Current
SLOW Mode Current
IDLE Mode Current
Sleep Mode Current
IFAST
ISLOW
IIDLE
ISLEEP
Additional Current if LCD
ON
Min.
Typ.
Max.
Unit
Condition
1
15
10
1.5
25
20
1
220
275
330
mA
µA
µA
µA
2M external R/C fast clock
32768 Hz slow clock with LCD disabled
32768 Hz slow clock with LCD disabled
200
250
300
ILCD
µA
I/O specification
Input High Voltage
Input Low Voltage
VIH
VIL
Input Hysteresis Width
VHYS
Output Source Current
Output Sink Current
IOH
IOL1
Input Low Current
IIL1
20
µA
Input Low Current
IIL2
100
µA
0.8
0.2
1/3
VDD
VDD
VDD
50
1.0
µA
mA
LV5=3xLVREG
LV5=4xLVREG
LV5=5xLVREG
Input Pins
Input Pins
I/O, RSTP_N Threshold = 2/3 VDD
(Input from low to high), Threshold = 1/3
VDD (Input from high to low)
Output drive high*1, VOH =2.0V
Output drive low, VOL=0.4V
RSTP_N, VIL = GND, Pull high
Internally
I/O, VIL=GND, if pull high Internally by
user
PWM and DAC
January 21, 2005
45
V0.93
This specification is subject to change without notice. Please contact sales person for the latest version before use.
KING BILLION ELECTRONICS CO., LTD
駿 億 電 子 股 份 有 限 公 司
PWM Output Current
IPWM
10
6
4
DAC Output Current
IoVO
2.5
Low voltage Reset
LVR detection voltage
LVR release voltage
VDET
VRLS
14
8
5
mA
mA
mA
3
mA
2.2
2.31
Volts
Volts
HE84G752B
HE80004 Series
PWM *2 With 32Ω Loading
With 64Ω Loading
With 100Ω Loading
VO, [email protected] VDD=3V,VO=0~2V,
Data =FF
Notes:
1. The “Output Source Current” specification is applicable only to the Push-Pull I/O type.
2. This Specification indicates only one PWM driving capability, and there are totally five built-in
drivers, user can multiply the actual number of driver to get the total amount of current. (IPWM x N;
N=0, 1, 2, 3, 4, 5)
January 21, 2005
46
V0.93
This specification is subject to change without notice. Please contact sales person for the latest version before use.
KING BILLION ELECTRONICS CO., LTD
駿 億 電 子 股 份 有 限 公 司
HE84G752B
HE80004 Series
25. Application Circuit
January 21, 2005
47
V0.93
This specification is subject to change without notice. Please contact sales person for the latest version before use.
KING BILLION ELECTRONICS CO., LTD
駿 億 電 子 股 份 有 限 公 司
HE84G752B
HE80004 Series
LVL5
L1
330uH
R13
100K
R23
U4
8
180
7
6
R25
0.5
5
RV4
DRC
SWC
Ipk
SWE
VCC
TC
CII
GND
1
2
3
R14
100K
D4
4
C25
RV3
1N4148
1.5nF
MC34063
VDD
R15
300K
R27
43K
220uF/25V
100nF
J4
220uF/25V
R16
100K
1 2
variable
resistor
C36
2
C35
R29
5K1
1
1
LVL5
R17
100K
J6
1
1 2
2
J5
1
C32
RV1
LVL5
RV2
LVL2
1
2
3
4
5
6
7
OUT1
IN1IN1+
VCC+
IN2+
IN2OUT2
OUT4
IN4IN4+
VCCIN3+
IN3OUT3
14
13
12
11
10
9
8
LVL4
RV4
R18
100K
RV2
RV3
LVL3
LM324
R19
100K
RV1
EXTERNAL LCD POWER SYSTEM
January 21, 2005
2
LVL1
2
U3
48
R20
100K
V0.93
This specification is subject to change without notice. Please contact sales person for the latest version before use.
KING BILLION ELECTRONICS CO., LTD
駿 億 電 子 股 份 有 限 公 司
HE84G752B
HE80004 Series
26. Important Note
1.
2.
3.
4.
5.
6.
Please note the ICE is a superset of HE80004 series IC. Each member of the family only has parts of
all resources. Do not use any hardware resource that your target chip doesn’t have, for example,
RAM and register. KBIDS and compiler can’t prevent user from using some hardware resources that
don’t exist in your target chip.
To access “Data ROM”, users must update TPP first, TPH, and then TPL. Only follow this order, the
pre-charge circuit of ROM will work correctly. The 5µs waiting is also necessary before LDV
instruction is executed since Data ROM is a low speed ROM. User can’t emulate this accessing
process in ICE, so 5µs delay should be added by firmware.
LCD driving circuit must be turned off before the system goes into sleep mode.
Please bond the TSTP_P, RSTP_N and PRTD [7:0] with test points on PCB (can be soldered and
probed) as you can, then some testing can be performed on PCB when it’s necessary. The TSTP_P is
suggested to connect to ground by a 0 ohm resistor.
The LV5 must be lower than 8.5 volts; otherwise permanent damages to the IC might be incurred.
The LCD voltage adjustment mechanism shall be reserved for LV5 voltage fine-tunes; since it’s
possible there is some variation in LV5 voltage due to IC manufacture process variation. User can
use variable-resistor to adjust the LV5 voltage or use some tools to detect the LV5 and then select a
proper resistor. Please refer to application note AN025 for the detailed description.
27. Updated History
Version
V0.92
V0.93
Date
Update History
New Created.
2005/1/17
HE84G752 -> HE84G752B
2005/1/21 Errata Correct
January 21, 2005
49
V0.93
This specification is subject to change without notice. Please contact sales person for the latest version before use.