KODENSHI KK74ACT373

TECHNICAL DATA
KK74ACT373
Octal 3-State Noninverting
Transparent Latch
High-Speed Silicon-Gate CMOS
The KK74ACT373 is identical in pinout to the LS/ALS373,
HC/HCT373. The KK74ACT373 may be used as a level converter for
interfacing TTL or NMOS outputs to High Speed CMOS inputs.
These latches appear transparent to data (i.e., the outputs change
asynchronously) when Latch Enable is high. When Latch Enable goes
low, data meeting the setup and hold time becomes latched.
• TTL/NMOS Compatible Input Levels
• Outputs Directly Interface to CMOS, NMOS, and TTL
• Operating Voltage Range: 4.5 to 5.5 V
• Low Input Current: 1.0 µA; 0.1 µA @ 25°C
• Outputs Source/Sink 24 mA
ORDERING INFORMATION
KK74ACT373N Plastic
KK74ACT373DW SOIC
TA = -40° to 85° C for all packages
PIN ASSIGNMENT
LOGIC DIAGRAM
FUNCTION TABLE
PIN 20=VCC
PIN 10 = GND
Inputs
Output
Output
Enable
Latch
Enable
D
Q
L
H
H
H
L
H
L
L
L
L
X
No Change
H
X
X
Z
X = Don’t Care
Z = High Impedance
1
KK74ACT373
MAXIMUM RATINGS*
Symbol
Parameter
Value
Unit
-0.5 to +7.0
V
VCC
DC Supply Voltage (Referenced to GND)
VIN
DC Input Voltage (Referenced to GND)
-0.5 to VCC +0.5
V
DC Output Voltage (Referenced to GND)
-0.5 to VCC +0.5
V
DC Input Current, per Pin
±20
mA
IOUT
DC Output Sink/Source Current, per Pin
±50
mA
ICC
DC Supply Current, VCC and GND Pins
±50
mA
PD
Power Dissipation in Still Air, Plastic DIP+
SOIC Package+
750
500
mW
-65 to +150
°C
260
°C
VOUT
IIN
Tstg
TL
Storage Temperature
Lead Temperature, 1 mm from Case for 10 Seconds
(Plastic DIP or SOIC Package)
*
Maximum Ratings are those values beyond which damage to the device may occur.
Functional operation should be restricted to the Recommended Operating Conditions.
+Derating - Plastic DIP: - 10 mW/°C from 65° to 125°C
SOIC Package: : - 7 mW/°C from 65° to 125°C
RECOMMENDED OPERATING CONDITIONS
Symbol
VCC
VIN, VOUT
DC Supply Voltage (Referenced to GND)
DC Input Voltage, Output Voltage (Referenced to GND)
TJ
Junction Temperature (PDIP)
TA
Operating Temperature, All Package Types
IOH
Output Current - High
IOL
Output Current - Low
tr, tf
*
Parameter
Input Rise and Fall Time
(except Schmitt Inputs)
*
Min
Max
Unit
4.5
5.5
V
0
VCC
V
140
°C
+85
°C
-24
mA
24
mA
10
8.0
ns/V
-40
VCC =4.5 V
VCC =5.5 V
0
0
VIN from 0.8 V to 2.0 V
This device contains protection circuitry to guard against damage due to high static voltages or electric fields.
However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this
high-impedance circuit. For proper operation, VIN and VOUT should be constrained to the range GND≤(VIN or
VOUT)≤VCC.
Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or VCC). Unused
outputs must be left open.
2
KK74ACT373
DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)
VCC
Symbol
Parameter
Test Conditions
Guaranteed Limits
V
25 °C
-40°C to
85°C
Unit
VIH
Minimum HighLevel Input Voltage
VOUT=0.1 V or VCC-0.1 V
4.5
5.5
2.0
2.0
2.0
2.0
V
VIL
Maximum Low Level Input Voltage
VOUT=0.1 V or VCC-0.1 V
4.5
5.5
0.8
0.8
0.8
0.8
V
VOH
Minimum HighLevel Output Voltage
IOUT ≤ -50 µA
4.5
5.5
4.4
5.4
4.4
5.4
V
4.5
5.5
3.86
4.86
3.76
4.76
4.5
5.5
0.1
0.1
0.1
0.1
VIN= VIL or VIH
IOL=24 mA
IOL=24 mA
4.5
5.5
0.36
0.36
0.44
0.44
*
VIN= VIL or VIH
IOH=-24 mA
IOH=-24 mA
VOL
Maximum LowLevel Output Voltage
IOUT ≤ 50 µA
V
*
IIN
Maximum Input
Leakage Current
VIN=VCC or GND
5.5
±0.1
±1.0
µA
IOZ
Maximum ThreeState Leakage
Current
VIN(OE)=VIL or VIH
VIN=VCC or GND
VOUT=VCC or GND
5.5
±0.5
±5.0
µA
∆ICCT
Additional Max
ICC/Input
VIN=VCC - 2.1 V
5.5
1.5
mA
IOLD
+Minimum Dynamic
Output Current
VOLD=1.65 V Max
5.5
75
mA
IOHD
+Minimum Dynamic
Output Current
VOHD=3.85 V Min
5.5
-75
mA
ICC
Maximum Quiescent
Supply Current
(per Package)
VIN=VCC or GND
5.5
80
µA
8.0
*
All outputs loaded; thresholds on input associated with output under test.
+Maximum test duration 2.0 ms, one output loaded at a time.
3
KK74ACT373
AC ELECTRICAL CHARACTERISTICS (VCC=5.0 V ± 10%, CL=50pF,Input tr=tf=3.0 ns)
Guaranteed Limits
Symbol
Parameter
25 °C
-40°C to 85°C
Min
Max
Min
Max
Unit
tPLH
Propagation Delay, Input D to Q (Figure 1)
2.5
10
1.5
11.5
ns
tPHL
Propagation Delay, Input D to Q (Figure 1)
2.0
10
1.5
11.5
ns
tPLH
Propagation Delay, Latch Enable to Q (Figure 2)
2.5
11
2.0
11.5
ns
tPHL
Propagation Delay, Latch Enable to Q (Figure 2)
2.0
10
1.5
11.5
ns
tPZH
Propagation Delay, Output Enable to Q
(Figure 3)
2.0
9.5
1.5
10.5
ns
tPZL
Propagation Delay, Output Enable to Q
(Figure 3)
2.0
9.0
1.5
10.5
ns
tPHZ
Propagation Delay, Output Enable to Q
(Figure 3)
2.5
11
2.5
12.5
ns
tPLZ
Propagation Delay, Output Enable to Q
(Figure 3)
1.5
8.5
1.0
10
ns
CIN
Maximum Input Capacitance
4.5
4.5
pF
Typical @25°C,VCC=5.0 V
CPD
Power Dissipation Capacitance
40
pF
TIMING REQUIREMENTS (VCC=5.0 V ± 10%, CL=50pF, Input tr=tf=3.0 ns)
Guaranteed Limits
Symbol
Parameter
25 °C
-40°C to 85°C
Unit
7.0
8.0
ns
tsu
Minimum Setup Time, Input D to Latch Enable
(Figure 4)
th
Minimum Hold Time, Latch Enable to
Input D (Figure 4)
0
1.0
ns
tw
Minimum Pulse Width, Latch Enable
(Figure 2)
2.0
8.0
ns
4
KK74ACT373
Figure 1. Switching Waveforms
Figure 2. Switching Waveforms
Figure 3. Switching Waveforms
Figure 4. Switching Waveforms
EXPANDED LOGIC DIAGRAM
5
KK74ACT373
N SUFFIX PLASTIC DIP
(MS - 001AD)
A
Dimension, mm
11
20
B
1
10
Symbol
MIN
MAX
A
24.89
26.92
B
6.1
7.11
5.33
C
F
L
C
-T- SEATING
PLANE
D
0.36
0.56
F
1.14
1.78
G
2.54
H
7.62
N
G
K
M
J
H
D
0.25 (0.010) M T
NOTES:
1. Dimensions “A”, “B” do not include mold flash or protrusions.
Maximum mold flash or protrusions 0.25 mm (0.010) per side.
J
0°
10°
K
2.92
3.81
L
7.62
8.26
M
0.2
0.36
N
0.38
D SUFFIX SOIC
(MS - 013AC)
A
20
11
H
Dimension, mm
B
1
P
10
G
R x 45
C
-TK
D
SEATING
PLANE
J
0.25 (0.010) M T C M
NOTES:
1. Dimensions A and B do not include mold flash or protrusion.
2. Maximum mold flash or protrusion 0.15 mm (0.006) per side
for A; for B ‑ 0.25 mm (0.010) per side.
F
M
Symbol
MIN
MAX
A
12.6
13
B
7.4
7.6
C
2.35
2.65
D
0.33
0.51
F
0.4
1.27
G
1.27
H
9.53
J
0°
8°
K
0.1
0.3
M
0.23
0.32
P
10
10.65
R
0.25
0.75
6