TECHNICAL DATA KK74HC221A Dual Monostable Multivibrator The KK74HC221A is identical in pinout to the LS/ALS221. The device inputs are compatible with standard CMOS outputs; with pullup resistors, they are compatible with LS/ALSTTL outputs. There are two trigger inputs, A INPUT (negative edge) and B INPUT (positive edge). These inputs are valid for rising/falling signals The device may also be triggered by using the RESET input (positiveedge) because of the Schmitt-trigger input; after triggering the output maintains the MONOSTABLE state for the time period determined by the external resistor REXT and capacitor CEXT. Taking RESET low breaks this MONOSTABLE STATE. If the next trigger pulse occurs during the MONOSTABLE period it makes the MONOSTABLE period longer. • Outputs Directly Interface to CMOS, NMOS, and TTL • Operating Voltage Range: 3.0 to 6.0 V • Low Input Current: 1.0 µA • High Noise Immunity Characteristic of CMOS Devices N SUFFIX PLASTIC 16 1 D SUFFIX SOIC 16 1 ORDERING INFORMATION KK74HC221AN Plastic KK74HC221AD SOIC TA = -55° to 125° C for all packages PIN ASSIGNMENT LOGIC DIAGRAM CEXT CEXT REXT 1 16 V CC 1B 2 15 1REXT/CEXT 1RESET 3 14 1CEXT 1Q 4 13 1Q DEXT DEXT 1A 2Q 5 12 2Q 2CEXT 6 11 2RESET 2REXT/CEXT 7 10 2B GND 8 9 2A REXT FUNCTION TABLE PIN 16 =VCC PIN 8 = GND Note (1) CEXT, REXT, DEXT are external components. (2) DEXT is a clamping diode. The external capacitor is charged to VCC in the stand-by state, i.e. no trigger. When the supply voltage is turned off CX is discharged mainly through an internal parasitic diode. If CX is sufficiently large and VCC decreases rapidy, there will be some possibility of damaging the I.C. with a surge current or latch-up. If the voltage supply filter capacitor is large enough and VCC decrease slowly, the surge current is automatically limited and damage the I.C. is avoided. The maximum forward current of the parasitic diode is approximately 20 mA. A X H Inputs Outputs B RESET Q H H L H L* H* Inhibit H * * Inhibit X L Note Q Output Enable L H H L H X X Output Enable Output Enable L L H Inhibit X = don’t care * - except for monostable period 1 KK74HC221A MAXIMUM RATINGS* Symbol Parameter Value Unit -0.5 to +7.0 V VCC DC Supply Voltage (Referenced to GND) VIN DC Input Voltage (Referenced to GND) -1.5 to VCC +1.5 V DC Output Voltage (Referenced to GND) -0.5 to VCC +0.5 V ±20 ±30 mA ±25 mA ±50 mA 750 500 mW -65 to +150 °C 260 °C VOUT IIN DC Input Current, per Pin A, B, RESET CEXT, REXT IOUT DC Output Current, per Pin ICC DC Supply Current, VCC and GND Pins PD Tstg TL ** Power Dissipation in Still Air, Plastic DIP SOIC Package** Storage Temperature Lead Temperature, 1 mm from Case for 10 Seconds (Plastic DIP or SOIC Package) * Maximum Ratings are those values beyond which damage to the device may occur. Functional operation should be restricted to the Recommended Operating Conditions. ** Derating - Plastic DIP: - 10 mW/°C from 65° to 125°C SOIC Package: : - 7 mW/°C from 65° to 125°C RECOMMENDED OPERATING CONDITIONS Symbol VCC VIN, VOUT Parameter Min DC Supply Voltage (Referenced to GND) Operating Temperature, All Package Types tr, tf Input Rise and Fall Time - RESET (Figure 2) VCC =2.0 V VCC =4.5 V VCC =6.0 V A or B RX External Timing Resistor CX External Timing Capacitor Unit 6.0 V 0 VCC V -55 +125 °C 0 0 0 1000 500 400 ns - No Limit 10 2.0 1000 1000 kΩ 0 No Limit µF 3.0 DC Input Voltage, Output Voltage (Referenced to GND) TA Max VCC <4.5 V VCC ≥ 4.5 V * * The KK74HC221A will function at 2.0 V but for optimum pulse width stability, VCC should be above 3.0 V. This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high-impedance circuit. For proper operation, VIN and VOUT should be constrained to the range GND≤(VIN or VOUT)≤VCC. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or VCC). Unused outputs must be left open. 2 KK74HC221A DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND) Symbol Parameter Test Conditions VCC Unit Guaranteed Limit V -55°C to 25 °C ≤85 °C ≤125 °C VIL Maximum Low -Level Input Voltage VOUT ≤ 0.1 V or VCC=0.1 V ⎢IOUT⎢ ≤ 20 µA 2.0 4.5 6.0 0.3 0.9 1.2 0.3 0.9 1.2 0.3 0.9 1.2 V VIH Minimum High-Level Input Voltage VOUT ≤ 0.1 V or VCC=0.1 V ⎢IOUT⎢ ≤ 20 µA 2.0 4.5 6.0 1.5 3.15 4.2 1.5 3.15 4.2 1.5 3.15 4.2 V VOL Maximum Low-Level Output Voltage VIN=VIH or VIL ⎢IOUT⎢ ≤ 20 µA 2.0 4.5 6.0 0.1 0.1 0.1 0.1 0.1 0.1 0.1 0.1 0.1 V VIN=VIH or VIL ⎢IOUT⎢ ≤ 4.0 mA 4.5 0.26 0.33 0.4 VIN=VIH or VIL ⎢IOUT⎢ ≤ 5.2 mA 6.0 0.26 0.33 0.40 VIN=VIH or VIL ⎢IOUT⎢ ≤ -20 µA 2.0 4.5 6.0 1.9 4.4 5.9 1.9 4.4 5.9 1.9 4.4 5.9 VIN=VIH or VIL ⎢IOUT⎢ ≤ -4.0 mA 4.5 3.98 3.84 3.70 VIN=VIH or VIL ⎢IOUT⎢ ≤ -5.2 mA 6.0 5.48 5.34 5.2 VOH Minimum High-Level Output Voltage V IIL Maximum Low-Level Output Current VIL=GND VIH=VCC 6.0 -0.1 -1.0 -1.0 µA IIH Minimum High-Level Input Current VIL=GND VIH=VCC 6.0 0.1 1.0 1.0 µA ICC Maximum Quiescent Supply Current (per Package) Standby State VIL=GND VIН=VCC IOUT=0 µA 6.0 8.0 80 160 µA ICC1 Maximum Supply Current (per Package) Active State VIL=GND VIH=VCC IOUT=0 µA VIN = 0.5 VCC 2.0 4.5 6.0 0.08 1.0 2.0 0.11 1.3 2.6 0.13 1.6 3.2 mA 3 KK74HC221A AC ELECTRICAL CHARACTERISTICS Symbol tPHL Parameter Maximum Propagation Delay A, B - Q RESET - Q Test Conditions VCC V -55°C to 25°C ≤85 °C ≤125 °C VIL=0 V VIH=VCC tLH=tHL=6 ns CL=50 pF CEXT=0 REXT=5 kΩ 2.0 4.5 6.0 180 36 31 225 45 38 270 54 46 2.0 4.5 6.0 180 36 31 225 45 38 270 54 46 2.0 4.5 6.0 195 39 33 245 49 42 295 59 50 2.0 4.5 6.0 220 44 37 275 55 47 330 66 56 2.0 4.5 6.0 245 49 42 305 61 52 370 74 63 2.0 4.5 6.0 200 40 34 250 50 43 300 60 51 2.0 4.5 6.0 75 16 14 95 20 17 110 22 20 ns - 10 20 10 20 10 20 pF RESET - Q tPLH Maximum Propagation Delay A, B - Q RESET - Q VIL=0 V VIH=VCC tLH=tHL=6 ns CL=50 pF CEXT=0 REXT=5 kΩ RESET - Q tTLH, tTHL Maximum Output Transition Time, Any Output(Figures 2 and 3) CIN Maximum Input Capacitance CPD Power Dissipation Capacitance (Per Multivibrator) VIL=0 V VIH=VCC tLH=tHL=6 нс CL=50 pF A, B, RESET CX, RX Guaranteed Limit Unit 180* 5.0 ns ns pF PD=CPDVCC2f+ICCVCC trec Minimum Recovery Time, Inactive to A or B (Figure 2) VIL=0 V VIH=VCC tLH=tHL=6 нс CL=50 pF 2.0 4.5 6.0 100 20 17 125 25 21 150 30 26 ns tw Minimum Pulse Width VIL=0 V VIH=VCC tLH=tHL=6 ns CL=50 pF CEXT=0 REXT=5 kΩ 2.0 4.5 6.0 25 9 7 95 19 16 110 22 19 ns 2.0 4.5 6.0 30 11 9 115 23 20 135 27 23 СEXT =0 пФ REXT=5 kΩ 5.0 105* ns СEXT =1 nF REXT=10 kΩ 2.0 4.5 6.0 0.80* 0.75* 0.70* µs СEXT =1 µF REXT=10 kΩ 2.0 4.5 6.0 80* 75* 70* A, RESET B tWQ * Minimum Pulse Width (Figure 4) ТА=25±10°C 4 KK74HC221A Figure 1. Switching Waveforms RESET Figure 2. Switching Waveforms Figure 3. Test Circuit 5 KK74HC221A TIMING DIAGRAM REXT/CEXT EXPANDED LOGIC DIAGRAM REXT/CEXT CEXT 6 KK74HC221A N SUFFIX PLASTIC DIP (MS - 001BB) A Dimension, mm 9 16 B 1 8 Symbol MIN MAX A 18.67 19.69 B 6.1 7.11 5.33 C F L C -T- SEATING PLANE N G K D M H J 0.25 (0.010) M T NOTES: 1. Dimensions “A”, “B” do not include mold flash or protrusions. Maximum mold flash or protrusions 0.25 mm (0.010) per side. D 0.36 0.56 F 1.14 1.78 G 2.54 H 7.62 J 0° 10° K 2.92 3.81 L 7.62 8.26 M 0.2 0.36 N 0.38 D SUFFIX SOIC (MS - 012AC) Dimension, mm A 16 9 H B 1 G P 8 R x 45 C -TK D SEATING PLANE J 0.25 (0.010) M T C M F M Symbol MIN MAX A 9.8 10 B 3.8 4 C 1.35 1.75 D 0.33 0.51 F 0.4 1.27 G 1.27 H 5.72 J 0° 8° K 0.1 0.25 1. Dimensions A and B do not include mold flash or protrusion. M 0.19 0.25 2. Maximum mold flash or protrusion 0.15 mm (0.006) per side for A; for B ‑ 0.25 mm (0.010) per side. P 5.8 6.2 R 0.25 0.5 NOTES: 7