KODENSHI KKA8351

TECHNICAL DATA
DC-COUPLED VERTICAL DEFLECTION CIRCUIT
FEATURES
GENERAL DESCRIPTION
•
•
The KKA8351 is a power circuit for use in 90°
and 110°
colour deflection systems for field frequencies
of 50 to
120 Hz. The circuit provides a DC driven
vertical deflection output circuit, operating as a
highly efficient class G system.
•
•
•
•
•
•
Few external components
Highly efficient fully DC-coupled vertical output
bridge circuit
Vertical flyback switch
Guard circuit
Protection against:
– short-circuit of the output pins (7 and 4)
– short-circuit of the output pins to VP
Temperature (thermal) protection
High EMC immunity because of common mode
inputs
A guard signal in zoom mode.
QUICK REFERENCE DATA
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
DC supply
Vp
supply voltage
9
-
25
V
Iq
quiescent supply current
-
30
-
mA
output current
(peak-to-peak value)
differential input current (peakto-peak value)
—
—
3
A
—
600
—
µA
differential input voltage
(peak-to-peak value)
—
1.5
1.8
V
IM
peak output current
-
-
±1.5
A
Vfb
flyback supply voltage
-
-
50
V
-
-
60
V
Vertical circuit
l o(p-p)
I diff(p-p)
V diff(p-p)
Flyback switch
note 1
Thermal data (in accordance with IEC 747-1)
T stg
storage temperature
-55
-
+150
°C
lamb
operating ambient temperature
-25
-
+75
°C
Tvj
virtual junction temperature
-
-
150
°C
Note
A flyback supply voltage of >50 V up to 60 V is allowed in application. A 220 nF capacitor
in series with a 22 Ω resistor (dependent on Io and the inductance of the coil) has to be
connected between pin 7 and ground. The decoupling capacitor of VFB has to be
connected between pin 6 and pin 3. The supply voltage line must have a resistance of 33
Ω.
1
KKA8351
BLOCK DIAGRAM.
VP
VO(guard)
3
VFB
8
6
+VP
CURRENT
SOURCE
+VP
KKA8351
7
VO(A)
+VO(A)
Idrive(pos)
1
-IS
+IT
9
VI(fb)
-IT
Idrive(neg)
+vP
2
+IS
+v
4
VO(B)
-VO(B)
5
GND
2
KKA8351
PINNING
SYMBOL
I drive(pos)
PIN
1
l drive(neg)
2
Vp
VO(B)
GND
Vfb
Vo(a)
Vo(guard)
V|(fb)
3
4
5
6
7
8
9
DESCRIPTION
input power-stage (positive); includes
li(sb) signal bias
input power-stage (negative); includes
li(sb) signal bias
operating supply voltage
output voltage B
ground
input flyback supply voltage
output voltage A
guard output voltage
input feedback voltage
PIN CONFIGURATION
Idrive(pos)
1
Idrive(pos)
2
VP
3
VO(B)
4
GND
5
VFB
6
VO(A)
7
VO(guard)
8
VI(fb)
9
KKA8351
FUNCTIONAL DESCRIPTION
The vertical driver circuit is a bridge configuration. The deflection coil is connected
between the output amplifiers, which are driven in phase opposition. An external resistor
(RM) connected in series with the deflection coil provides internal feedback information.
The differential input circuit is voltage driven. An external resistor (RCON) connected
between the differential input determines the output current through the deflection coil. The
relationship between the differential input current and the output current is defined by: Idiff x
RCON = Icoil x RM. The output current is adjustable from 0.5 A (p-p) to 3 A (p-p) by varying RM.
The maximum input differential voltage is 1.8 V. In the application it is recommended that
Vdiff = 1.5 V (typ). This is recommended because of the spread of input current and the
spread in the value of RCON.
The flyback voltage is determined by an additional supply voltage VFB. The principle of
operating with two supply voltages (class G) makes it possible to fix the supply voltage Vp
optimum for the scan voltage and the second supply voltage VFB optimum for the flyback
voltage. Using this method, very high efficiency is achieved.
The supply voltage VFB is almost totally available as flyback voltage across the coil, this
being possible due to the absence of a decoupling capacitor (not necessary, due to the
bridge configuration). The output circuit is fully protected against the following:
• thermal protection
short-circuit protection of the output pins (pins 4 and 7)
• short-circuit of the output pins to Vp.
A guard circuit Vo(guard) is provided. The guard circuit is activated at the following
conditions:
• during flyback
• during short-circuit of the coil and during short-circuit of the output pins (pins 4 and 7)
to Vp or ground
• during open loop
• when the thermal protection is activated.
This signal can be used for blanking the picture tube screen.
3
KKA8351
LIMITING VALUES
In accordance with the Absolute Maximum Rating System (IRC 134).
SYMBOL
PARAMETER
CONDITIONS
MIN.
MAX.
UNIT
DC supply
Vp
VFB
supply voltage
non-operetion
flyback supply voltage
note 1
-
40
V
-
25
V
-
50
V
-
60
V
Vertical circuit
I O(A)
VO(A)
output current (peak-to-peak
l ) voltage (pin 7)
output
note 2
note 1
-
3
A
-
52
V
-
62
V
-
±1.5
A
Flyback switch
IM
peak output current
Thermal data (in accordance with IEC 747-1)
Tstg
storage temperature
-55
+150
°C
lamb
operating ambient temperature
-25
+75
°C
Tvj
virtual junction temperature
-
150
°C
Rth vj-c
resistance vj-case
-
4
K/W
Rth vj-a
resistance vj-ambient in free air
-
40
K/W
tsc
short-circuiting time
-
1
hr
note 3
Notes
1. A flyback supply voltage of >50 V up to 60 V is allowed in application. A 220 nF capacitor in series with a
22 Ω resistor (dependent on Io and the inductance of the coil) has to be connected between pin 7 and
ground. The decoupling capacitor of VFB has to be connected between pin 6 and pin 3. The supply
voltage line must have a resistance of 33 Ω.
2. IO maximum determined by current protection.
3. UP to VP = 18 V.
4
KKA8351
CHARACTERISTICS
Vp = 17.5 V; Tamb = 25 0C; VFB = 45 V; tj = 50 Hz; II(sb) = 400 µA.
SYMBOL
PARAMETER
DC supply
VP
operating supply voltage
VFB
flyback supply voltage
Iq
supply current
Vertical circuit
VO
output voltage swing (scan)
LE
linearity error
VO
output voltage swing (flyback)
VO(A) - VO(B)
forward voltage of the internal
efficiency diode (VO(A) - VFB)
output offset current
VDF
I Ios I
I Vos I
∆VosT
VO(A)
Gvo
VR
tres
Gi
∆GCT
II(sb)
IFB
PSRR
VI(DC)
VICM)
Ibias
IO(CM)
offset voltage at the input of the
feedback amplifier (VI(fb) - VO(B))
output offset voltage as a function
of temperature
DC output voltage
open-loop voltage gain (V7-4/V1-2))
open loop voltage gain(V7-4/V1-2);
V1-2 = 0)
voltage ratio V1-2/V9-4
frequency response (-3 dB)
current gain (IO/Idiff)
current gain drift as a function of
temperature
signal bias current
flyback supply current
power supply ripple rejection
DC input voltage
common mode input voltage
input bias current
common mode output current
Guard circuit
IO
output current
VO(guard)
output voltage on pin 8
allowable voltage on pin 8
CONDITIONS
note 1
no signal; no load
Idiff = 0.6 mA (p-p);
Vdiff = 1.8 V (p-p);
IO = 3 A (p-p)
IO = 3 A (p-p); note 2
IO = 50 mA (p-p); note 2
Idiff = 0.3 mA;
IO = 1.5 A (M)
IO = -1.5 A (M)
Idiff = 0.3 mA
Idiff = 0;
II(sb) = 50 to 500 µA
Idiff = 0;
II(sb) = 50 to 500 µA
Idiff = 0
Idiff = 0; note 3
notes 4 and 5
note 4
open loop; note 6
during scan
note 7
II(sb)= 0
II(sb)= 0
∆ II(sb) = 300 µA (p-p);
fi = 50 Hz; Idiff = 0
not active;
VO(guard) = 0 V
active; VO(guard) = 4.5 V
IO = 100 µA
maximum leakage
current = 10 µA;
MIN.
TYP.
MAX.
UNIT
9.0
VP
VP
-
30
25
50
60
55
V
V
V
mA
19.8
-
-
V
-
1
1
39
2
2
-
%
%
V
-
-
1.5
V
-
-
30
mA
-
-
18
mV
-
-
72
µV/K
-
8.0
80
80
-
V
dB
dB
-
0
40
5000
-
-4
10
dB
Hz
50
0
-
400
80
2.7
0.1
0.2
500
100
1.6
0.5
-
µA
µA
dB
V
V
µA
mA
-
-
50
µA
1
-
-
2.5
5.5
40
mA
V
V
K
Notes
1. A flyback supply voltage of >50 V up to 60 V is allowed in application. A 220 nF capacitor in series with
a 22 Ω resistor (dependent on Io and the inductance of the coil) has to be connected between pin 7 and
ground. The decoupling capacitor of VFB has to be connected between pin 6 and pin 3. The supply voltage
line must have a resistance of 33 Ω.
2. The linearity error is measured without S-correction and based on the same measurement principle as
performed on the screen. The measuring method is as follows:
5
KKA8351
Divide the output signal I4 - I7 (VRM) into 22 equal parts ranging from 1 to 22 inclusive. Measure the value of
two succeeding parts called one block starting with part 2 and 3 (block 1) and ending with part 20 and 21
(block 10). Thus part 1 and 22 are unused. The equations for linearity error for adjacent blocks (LEAB) and
not adjacent blocks (NAB) are given below
LEAB =
3.
4.
5.
6.
7.
a k − a ( k +1)
a avg
; NAB =
a max − a min
a avg
Referenced to VP.
V values with formulae, relate to voltages at or between relating pin numbers, i.e. V7-4/ V1-2 = voltage
value across pins 7 and 4 divided by voltage value across pins 1 and 2.
V9-4 AC short-circuited.
Frequency response V7-4/ V9-4 is equal to frequency response V7-4/ V1-2 .
At V(ripple) = 500 mV eff; measured across RM; fj = 50 Hz.
• 9-Pin Plastic Power Single-in-Line (SIL-9MPF, SOT 131-2)
24-0.21
4.4
0.15
12-0.18
19.8 0.026
16.8 0.135
3.2 0.15
1
2 0.06
9
0.4 0.05
2.54
0.65 0.05
0.25 M
6