ML12009 ML12011 MECL PLL Components Dual Modulus Prescaler Legacy Device: Motorola MC12009, MC12011 These devices are two–modulus prescalers which will divide by 5 and 6, 8 and 9, respectively. A MECL–to–MTTL translator is provided to interface directly with the Motorola MC12014 Counter Control Logic. In addition, there is a buffered clock input and MECL bias voltage source. • • • • • • • 16 1 SO 16 = -5P PLASTIC PACKAGE CASE 751B ML12009 480 MHz (÷5/6), ML12011 550 MHz (÷8/9) MECL to MTTL Translator on Chip MECL and MTTL Enable Inputs 5.0 or –5.2 V Operation* Buffered Clock Input — Series Input RC Typ, 20 Ω and 4.0 pF VBB Reference Voltage 310 mW (Typ) 16 1 P DIP 16 = EP PLASTIC PACKAGE CASE 648 CROSS REFERENCE/ORDERING INFORMATION PACKAGE MOTOROLA LANSDALE * When using a 5.0 V supply, apply 5.0 V to Pin 1 (VCCO), Pin 6 (MTTL VCC), Pin 16 (VCC), and ground Pin 8 (VEE). When using –5.2 V supply, ground Pin 1 (VCCO), Pin 6 (MTTL VCC), and Pin 16 (VCC) and apply –5.2 V to Pin 8 (VEE). If the translator is not required, Pin 6 may be left open to conserve DC power drain. P DIP 16 SOIC 16 P DIP 16 SO 16W MC12009P MC12009D MC12011P MC12011D ML12009EP ML12009-5P ML12011EP ML12011-5P Note: Lansdale lead free (Pb) product, as it becomes available, will be identified by a part number prefix change from ML to MLE. MAXIMUM RATINGS Characteristic Symbol Rating Unit PIN CONNECTIONS (Ratings above which device life may be impaired) Power Supply Voltage (VCC = 0) VEE –8.0 Vdc Input Voltage (VCC = 0) Vin 0 to VEE Vdc Output Source Current Continuous Surge IO Storage Temperature Range mAdc 50 100 Tstg –65 to 175 °C (Recommended Maximum Ratings above which performance may be degraded) Operating Temperature Range ML12009, ML12011 DC Fan–Out (Note 1) (Gates and Flip–Flops) TA –30 to 85 °C n 70 — VCCO Q 1 Q (–) 3 16 VCC 15 Clock 2 14 VBB 13 E1 MECL 12 E2 MECL 4 (+) 5 MTTL VCC 6 MTTL Output 7 11 E3 MECL 10 E4 MECL VEE 8 9 E5 MECL (Top View) NOTES: 1. AC fan–out is limited by desired system performance. Page 1 of 14 www.lansdale.com Issue A ML12009, ML12011 LANSDALE Semiconductor, Inc. Figure 1. Logic Diagrams ML12009 MTTL E5 9 D Q1 D C Q1 C Q2 D MTTL E4 10 MECL to MTTL Translator Q3 MECL E3 11 MECL E2 12 C Q3 MECL E1 13 Recommended Circuitry For ac coupled Inputs. VBB 14 15 1000 pF Clock Input 3 Q3 0.1 µF 1.0 k 2 Q3 7 MTTL Out 5 4 + – ML12011 MTTL E5 9 D Q1 D Q2 D Q4 Toggle Flip Flop C Q4 Q3 MTTL E4 10 MECL E3 11 C MECL E2 12 MECL E1 13 C C Recommended Circuitry For ac coupled Inputs. VBB 14 15 1000 pF Clock Input 1.0 k MECL to MTTL Translator 3 2 Q4 Q4 0.1 µF 5 4 + – 7 MTTL Out Figure 2. Typical Frequency Synthesizer Application fref Phase Detector MC4044/ML4044 Voltage–Controlled Oscillator MC1648/ML1648 Low–Pass Filter fout Modulus Enable Line ML12009 ML12011 ML12013 Counter Control Logic MC12014 Zero Detect Line fout Np Programmable Counter MC4016/ML4016 A Programmable Counter MC4016/ML4016 Counter Reset Line Page 2 of 14 www.lansdale.com Issue A ML12009, ML12011 LANSDALE Semiconductor, Inc. Figure 2b Generic block diagram showing prescaler connection to PLL Device Prescaler Fout ML12009/11 PLL Fin ML145146 ML145158 ML145159 MC in MC VCO Loop Filter Figure 2b shows a generic block diagram of connecting a prescaler to a PLL device that supports dual modulus controls. Applicataion not AN535 describes using a two–modulus prescaler technique. By using prescaler higher frequencies can be achieved than by a single CMOS PLL device. Page 3 of 14 www.lansdale.com Issue A ML12009, ML12011 LANSDALE Semiconductor, Inc. ELECTRICAL CHARACTERISTICS (Supply Voltage = –5.2 V, unless otherwise noted.) Test Limits Symbol Pin Under Test Min ICC1 8 –88 ICC2 6 5.2 5.2 5.2 mAdc IinH1 15 11 12 13 375 375 375 375 250 250 250 250 250 250 250 250 µAdc IinH2 4 5 1.7 1.7 6.0 6.0 2.0 2.0 6.0 6.0 2.0 2.0 6.4 6.4 mAdc IinH3 5 0.7 3.0 1.0 3.0 1.0 3.6 IinH4 9 10 IinL1 15 11 12 13 –10 –10 –10 –10 –10 –10 –10 –10 –10 –10 –10 –10 µAdc IinL2 9 10 –1.6 –1.6 –1.6 –1.6 –1.6 –1.6 mAdc VBB 14 VOH1 (Note 1) 2 3 –1.100 –1.100 VOH2 7 –2.8 VOL1 (Note 1) 2 3 –1.990 –1.990 VOL2 7 Logic ‘1’ Threshold Voltage VOHA (Note 2) 2 3 Logic ‘0’ Threshold Voltage VOLA (Note 3) 2 3 IOS 7 Characteristic Power Supply Drain Current Input Current Leakage Current Reference Voltage Logic ‘1’ Output Voltage Logic ‘0’ Output Voltage Short Circuit Current –30°C 25°C Max Min Max –80 100 100 –0.890 –0.890 –1.120 –1.120 –1.360 –1.160 –1.000 –1.000 –0.810 –0.810 –1.950 –1.950 mAdc 100 100 –0.930 –0.930 –1.650 –1.650 –1.925 –1.925 –0.700 –0.700 Vdc –1.615 –1.615 Vdc –4.48 –0.950 –0.950 –1.630 –1.630 –65 µAdc Vdc –4.40 –1.655 –1.655 Unit –2.4 –1.020 –1.020 –20 Max –80 –2.6 –1.675 –1.675 Min 100 100 –4.26 –65 85°C –20 NOTES: 1. Test outputs of the device must be tested by sequencing through the truth table. All input, power supply and ground voltages must be maintained between tests. The clock input is the waveform shown. 2. In addition to meeting the output levels specified, the device must divide by 5 or 8 during this test. The clock input is the waveform shown. 3. In addition to meeting the output levels specified, the device must divide by 6 or 9 during this test. The clock input is the waveform shown. –65 Vdc –1.595 –1.595 Vdc –20 mAdc Clock Input VIHmax VILmin Each MECL 10,000 series circuit has been designed to meet the dc specifications shown in the test table, after thermal equilibrium has been established. The circuit is in a test socket or mounted on a printed circuit board and transverse air flow greater than 500 linear fpm is maintained. Outputs are terminated through a 50 Ω resistor to –2.0 V. Test procedures are shown for only one gate. The other gates are tested in the same manner. Page 4 of 14 www.lansdale.com Issue A ML12009, ML12011 LANSDALE Semiconductor, Inc. ELECTRICAL CHARACTERISTICS (continued) (Supply Voltage = –5.2 V, unless otherwise noted.) TEST VOLTAGE/CURRENT VALUES Volts Characteristic Power Supply Drain Current Input Current Leakage Current Reference Voltage Logic ‘1’ Output Voltage @ Test Temperature VIHmax VILmin VIHAmin VILAmax VIH VILH –30°C –0.890 –1.990 –1.205 –1.500 –2.8 –4.7 25°C –0.810 –1.950 –1.105 –1.475 –2.8 –4.7 85°C –0.700 –1.925 –1.035 –1.440 –2.8 –4.7 Symbol Pin Under Test ICC1 8 ICC2 6 4 IinH1 15 11 12 13 15 11 12 13 IinH2 4 5 5 5 4 4 6 6 IinH3 5 4 5 6 IinH4 9 10 IinL1 15 11 12 13 IinL2 9 10 VBB 14 VOH1 (Note 1) 2 3 VOH2 7 Logic ‘0’ Output Voltage VOL1 (Note 1) 2 3 VOL2 7 Logic ‘1’ Threshold Voltage VOHA (Note 2) 2 3 Logic ‘0’ Threshold Voltage VOLA (Note 3) 2 3 IOS 7 Short Circuit Current TEST VOLTAGE APPLIED TO PINS LISTED BELOW VIHmax VILmin VIHAmin VILAmax VIL Gnd 1,16 5 6 1,16 1,16 1,16 1,16 9 10 1,16 1,16 1,16 1,16 1,16 1,16 9 10 1,16 1,16 1,16 11,12,13 11,12,13 5 4 9,10 9,10 1,16 1,16 9,10 9,10 1,16 1,16 4 6 11,12,13 11,12,13 5 6 11,12,13 11,12,13 1,16 1,16 11,12,13 11,12,13 5 4 NOTES: 1. Test outputs of the device must be tested by sequencing through the truth table. All input, power supply and ground voltages must be maintained between tests. The clock input is the waveform shown. 2. In addition to meeting the output levels specified, the device must divide by 5 or 8 during this test. The clock input is the waveform shown. 3. In addition to meeting the output levels specified, the device must divide by 6 or 9 during this test. The clock input is the waveform shown. Page 5 of 14 VIH www.lansdale.com 1,16 1,16 7 6 Clock Input VIHmax VILmin Issue A ML12009, ML12011 LANSDALE Semiconductor, Inc. ELECTRICAL CHARACTERISTICS (continued) (Supply Voltage = –5.2 V, unless otherwise noted.) TEST VOLTAGE/CURRENT VALUES Volts Characteristic Power Supply Drain Current Input Current Leakage Current Reference Voltage Logic ‘1’ Output Voltage mA @ Test Temperature VIHT VILT VEE IL IOL IOH –30°C –3.2 –4.4 –5.2 –0.25 16 –0.40 25°C –3.2 –4.4 –5.2 –0.25 16 –0.40 85°C –3.2 –4.4 –5.2 –0.25 16 –0.40 Symbol Pin Under Test ICC1 8 8 1,16 ICC2 6 8 6 IinH1 15 11 12 13 8 8 8 8 1,16 1,16 1,16 1,16 TEST VOLTAGE APPLIED TO PINS LISTED BELOW VIHT VILT 9,10 9,10 9,10 VEE IOH Gnd 4 5 8 8 6 6 IinH3 5 8 6 IinH4 9 10 8 8 1,16 1,16 IinL1 15 11 12 13 8,15 8,11 8,12 8,13 1,16 1,16 1,16 1,16 IinL2 9 10 8 8 1,16 1,16 VBB 14 8 VOH1 (Note 1) 2 3 8 8 VOH2 7 8 VOL1 (Note 1) 2 3 8 8 VOL2 7 Logic ‘1’ Threshold Voltage VOHA (Note 2) 2 3 Logic ‘0’ Threshold Voltage VOLA (Note 2) 2 3 IOS 7 8 9,10 9,10 9,10 9,10 www.lansdale.com 14 1,16 1,16 1,16 7 6 1,16 1,16 7 6 8 8 1,16 1,16 8 8 1,16 1,16 8 6 NOTES: 1. Test outputs of the device must be tested by sequencing through the truth table. All input, power supply and ground voltages must be maintained between tests. The clock input is the waveform shown. 2. In addition to meeting the output levels specified, the device must divide by 5 or 8 during this test. The clock input is the waveform shown. 3. In addition to meeting the output levels specified, the device must divide by 6 or 9 during this test. The clock input is the waveform shown. Page 6 of 14 IOL IinH2 Logic ‘0’ Output Voltage Short Circuit Current IL Clock Input VIHmax VILmin Issue A ML12009, ML12011 LANSDALE Semiconductor, Inc. ELECTRICAL CHARACTERISTICS (Supply Voltage = 5.0 V, unless otherwise noted.) Test Limits Symbol Pin Under Test Min Power Supply Drain Current ICC1 8 –88 ICC2 6 5.2 5.2 5.2 mAdc Input Current IinH1 15 11 12 13 375 375 375 375 250 250 250 250 250 250 250 250 µAdc IinH2 4 5 1.7 1.7 6.0 6.0 6.4 6.4 mAdc IinH3 5 0.7 3.0 IinH4 9 10 IinL1 15 11 12 13 –10 –10 –10 –10 –10 –10 –10 –10 –10 –10 –10 –10 µAdc IinL2 9 10 –1.6 –1.6 –1.6 –1.6 –1.6 –1.6 mAdc VBB 14 VOH1 (Note 1) 2 3 3.900 3.900 VOH2 7 2.4 VOL1 (Note 1) 2 3 3.070 3.070 VOL2 7 Logic ‘1’ Threshold Voltage VOHA (Note 2) 2 3 Logic ‘0’ Threshold Voltage VOLA (Note 3) 2 3 IOS 7 Characteristic Leakage Current Reference Voltage Logic ‘1’ Output Voltage Logic ‘0’ Output Voltage Short Circuit Current –30°C 25°C Max Min –80 4.110 4.110 6.0 6.0 2.0 2.0 1.0 3.0 1.0 100 100 100 100 3.67 3.87 4.000 4.000 4.190 4.190 2.6 3.385 3.385 3.880 3.880 3.110 3.110 3.6 µAdc Vdc 4.070 4.070 3.410 3.410 3.135 3.135 4.300 4.300 Vdc 3.445 3.445 Vdc 0.72 4.050 4.050 3.430 3.430 –65 Unit mAdc 100 100 0.80 3.405 3.405 Max 2.8 3.980 3.980 –20 Min –80 2.0 2.0 0.94 –65 85°C Max –20 NOTES: 1. Test outputs of the device must be tested by sequencing through the truth table. All input, power supply and ground voltages must be maintained between tests. The clock input is the waveform shown. 2. In addition to meeting the output levels specified, the device must divide by 5 or 8 during this test. The clock input is the waveform shown. 3. In addition to meeting the output levels specified, the device must divide by 6 or 9 during this test. The clock input is the waveform shown. –65 Vdc 3.465 3.465 Vdc –20 mAdc Clock Input VIHmax VILmin Each MECL 10,000 series circuit has been designed to meet the dc specifications shown in the test table, after thermal equilibrium has been established. The circuit is in a test socket or mounted on a printed circuit board and transverse air flow greater than 500 linear fpm is maintained. Outputs are terminated through a 50 Ω resistor to –2.0 V. Test procedures are shown for only one gate. The other gates are tested in the same manner. Page 7 of 14 www.lansdale.com Issue A ML12009, ML12011 LANSDALE Semiconductor, Inc. ELECTRICAL CHARACTERISTICS (continued) (Supply Voltage = 5.0 V, unless otherwise noted.) TEST VOLTAGE/CURRENT VALUES Volts @ Test Temperature VIHmax VILmin VIHAmin VILAmax VIH VILH –30°C 4.110 3.070 3.795 3.500 2.4 0.5 25°C 4.190 3.110 3.895 3.525 2.4 0.5 85°C 4.300 3.135 3.965 3.560 2.4 0.5 Symbol Pin Under Test Power Supply Drain Current ICC1 8 ICC2 6 4 Input Current IinH1 15 11 12 13 15 11 12 13 IinH2 4 5 5 5 4 4 IinH3 5 4 5 IinH4 9 10 IinL1 15 11 12 13 IinL2 9 10 VBB 14 VOH1 (Note 1) 2 3 VOH2 7 VOL1 (Note 1) 2 3 VOL2 7 Logic ‘1’ Threshold Voltage VOHA (Note 2) 2 3 Logic ‘0’ Threshold Voltage VOLA (Note 3) 2 3 IOS 7 Characteristic Leakage Current Reference Voltage Logic ‘1’ Output Voltage Logic ‘0’ Output Voltage Short Circuit Current TEST VOLTAGE APPLIED TO PINS LISTED BELOW VIHmax VILmin VIHAmin VILAmax VIL (VEE) Gnd 8 5 8 8 8 8 8 8 8 8 9 10 8 8 8,15 8,11 8,12 8,13 9 10 8 8 8 11,12,13 11,12,13 5 9,10 9,10 4 11,12,13 11,12,13 4 9,10 9,10 5 8 8 11,12,13 11,12,13 4 www.lansdale.com 8 8 8 11,12,13 11,12,13 5 8 8 8 NOTES: 1. Test outputs of the device must be tested by sequencing through the truth table. All input, power supply and ground voltages must be maintained between tests. The clock input is the waveform shown. 2. In addition to meeting the output levels specified, the device must divide by 5 or 8 during this test. The clock input is the waveform shown. 3. In addition to meeting the output levels specified, the device must divide by 6 or 9 during this test. The clock input is the waveform shown. Page 8 of 14 VIH 8 8 7 8 Clock Input VIHmax VILmin Issue A ML12009, ML12011 LANSDALE Semiconductor, Inc. ELECTRICAL CHARACTERISTICS (continued) (Supply Voltage = 5.0 V, unless otherwise noted.) TEST VOLTAGE/CURRENT VALUES Volts @ Test Temperature Characteristic Power Supply Drain Current Input Current Leakage Current Reference Voltage mA VIHT VILT VCC IL IOL IOH –30°C 2.0 0.8 5.0 –0.25 16 –0.40 25°C 2.0 0.8 5.0 –0.25 16 –0.40 85°C 2.0 0.8 5.0 –0.25 16 –0.40 Symbol Pin Under Test ICC1 8 1,16 8 ICC2 6 6 8 IinH1 15 11 12 13 1,16 1,16 1,16 1,16 8 8 8 8 TEST VOLTAGE APPLIED TO PINS LISTED BELOW VIHT VILT 9,10 9,10 9,10 VCC 8 8 IinH3 5 6 8 IinH4 9 10 1,16 1,16 8 8 IinL1 15 11 12 13 1,16 1,16 1,16 1,16 8,15 8,11 8,12 8,13 IinL2 9 10 1,16 1,16 8 8 1,16 2 3 1,16 1,16 VOH2 7 6 VOL1 (Note 1) 2 3 1,16 1,16 VOL2 7 6 Logic ‘1’ Threshold Voltage VOHA (Note 2) 2 3 Logic ‘0’ Threshold Voltage VOLA (Note 3) 2 3 IOS 7 9,10 9,10 9,10 9,10 www.lansdale.com 14 8 8 8 7 8 8 8 7 8 1,16 1,16 8 8 1,16 1,16 8 8 6 8 NOTES: 1. Test outputs of the device must be tested by sequencing through the truth table. All input, power supply and ground voltages must be maintained between tests. The clock input is the waveform shown. 2. In addition to meeting the output levels specified, the device must divide by 5 or 8 during this test. The clock input is the waveform shown. 3. In addition to meeting the output levels specified, the device must divide by 6 or 9 during this test. The clock input is the waveform shown. Page 9 of 14 (VEE) Gnd 6 6 14 Short Circuit Current IOH 4 5 VBB Logic ‘0’ Output Voltage IOL IinH2 VOH1 (Note 1) Logic ‘1’ Output Voltage IL Clock Input VIHmax VILmin Issue A ML12009, ML12011 LANSDALE Semiconductor, Inc. SWITCHING CHARACTERISTICS ML12509, ML12511, ML12513 TEST VOLTAGES/WAVEFORMS APPLIED TO PINS LISTED BELOW: Characteristic Symbol Pin Under Test Propagation Delay (See Figures 3 and 5) t15+ 2+ t15+ 2– t5+ 7+ t5– 7– 2 2 7 7 — — — — — — — — 8.1 7.5 8.4 6.5 — — — — — — — — 8.1 7.5 8.1 6.5 — — — — — — — — 8.9 82 8.9 7.1 ns 15 15 A A — — — — — — — — — — — — 11,12,13 11,12,13 — — 9,10 9,10 — — 8 8 8 8 1,6,16 1,6,16 1,6,16 1,6,16 Setup Time (See Figures 4 and 5) tsetup1 tsetup2 11 9 5.0 5.0 — — — — 5.0 5.0 — — — — 5.0 5.0 — — — — ns ns 15 15 * — — * — — * 11,12,13 9,10 * 8 8 1,6,16 1,6,16 Release Time (See Figures 4 and 5) trel1 trel2 11 9 5.0 5.0 — — — — 5.0 5.0 — — — — 5.0 5.0 — — — — ns ns 15 15 * — — * — — * 11,12,13 9.10 * 8 8 1,6,16 1,6,16 Toggle Frequency (See Figure 6) ML12509 : 5/6 ML12511 : 8/9 fmax 2 440 500 — — — — 480 550 — — — — 440 500 — — — — — — — — — — 11 11 — — — — 8 8 16 16 –30°C 25°C 85°C Min Typ Max Min Typ Max Min Typ Max Unit Pulse Gen.1 Pulse Gen.2 Pulse Gen.3 VIHmin VILmin VF –3.0 V VEE –3.0 V VCC +2.0 MHz *Test inputs sequentially, with Pulse Generator 2 or 3 as indicated connected to input under test, and the voltage indicated applied to the other input(s) of the same type ( i.e., MECL or MTTL). –30°C 25°C 85°C VIHmin 1.03 1.115 1.20 Vdc VILmin 0.175 0.200 0.235 Vdc Figure 3. AC Voltage Waveforms Pulse Generator 1 VIHmin 80% 50% 20% VILmin t++ Q (Pin 2) 50% t+ – 50% Q (Pin 3) + In 50% MTTL Out t++ t–– –1.5 V Figure 4. Setup and Release Time Waveforms Pulse 50 Generator % 1 tsetup1 Pulse Generator tsetup2 2 Pulse Generator +1.5 V 3 Q (Pin 2) Page 10 of 14 80% 20% 80% 50% VIHmin VILmin VIHmin 20% VILmin 0V 10% VEE 90% Divide by 5 — ML12509 Divide by 8 — ML12511 Di id b 10 ML12513 Pulse Generator 1 Pulse 50% Generator t rel2 2 Pulse Generator 3 –1.5 V Q (Pin 2) www.lansdale.com 80% 20% 50% trel1 80% 20% 90% 10% VIHmin VILmin VIHmin VILmin 0V VEE Divide by 6 — ML12509 Divide by 9 — ML12511 Di id b 11 ML12513 Issue A ML12009, ML12011 LANSDALE Semiconductor, Inc. Figure 5. AC Test Circuit Vin 25 µF 50 Pulse Generator #1 Vout (Scope Channel B) VCC = 2.0 V 100 Vin 50 Pulse Generator #2 100 Vin 1 6 13 E1 12 E2 11 E3 10 E4 9 E5 15 C 0.1 µF 16 Vout 2 Q 3 Vout Q VBB 14 950 Pulse Generator #3 50 5 + 4 – MECL to MTTL Trans– lator 1950 7 8 0.1 µF Vin (Scope Channel A) CT VEE = –3.0 V MC10109 or equiv. A All Pulse Generators are EH 137 or equiv. Pulse Generators 1 and 2: PRF = 10 MHz PW = 50% Duty Cycle t + = t – = 2.0 ± 0.2 ns Pulse Generator 3: PRF = 2.0 MHz PW = 50% Duty Cycle t + = t – = 5.0 ± 0.5 ns Page 11 of 14 50 VEE = –3.0 V All resistors are +1%. All input and output cables to the scope are equal lengths of 50 Ω coaxial cable. The 1950 Ω resistor at Pin 7 and the scope termination impedance constitute a 40 :1 attenuator probe. CT = 15 pF = total parasitic capacitance which includes probe, wiring, and load capacitance. Unused output connected to a 50 Ω resistor to ground. www.lansdale.com Issue A ML12009, ML12011 LANSDALE Semiconductor, Inc. Figure 6. Maximum Frequency Test Circuit Vout VCC = 2.0 V 0.1 µF 1 to Scope 5.0 µF 16 13 E1 Vin 12 VEE (To Scope) Q E2 2 11 E3 10 E4 9 E5 0.1 µF Q 15 3 C 1.0 k 14 VBB 0.1 µF 8 0.1 µF VEE = –3.0 V Unused output connected to a 50 Ω resistor to ground DIVIDE BY 6 800 mV Clock Input 850 mV typ Q (Pin 2) 3 Cycles 3 Cycles DIVIDE BY 9 800 mV Clock Input 850 mV typ Q (Pin 2) Page 12 of 14 5 Cycles 4 Cycles www.lansdale.com Issue A ML12009, ML12011 LANSDALE Semiconductor, Inc. Figure 7. State Diagram DIVIDE BY 5/6 (ML12009/ML12509) Enable = 0 Q1 1 0 0 0 1 1 Q2 1 1 0 0 0 1 Q3 1 1 1 0 0 0 111 011 001 110 100 000 0101 0010 1110 0110 010 101 1000 1100 1010 0000 0111 1111 Enable = 1 Enable = 1 DIVIDE BY 8/9 (ML12011) Enable = 0 Q1 1 0 0 1 1 0 0 1 1 Q2 1 1 0 0 1 1 0 0 1 Q3 1 1 1 0 0 1 1 0 0 Q4 1 1 1 1 1 0 0 0 0 Enable = 1 0001 1101 1001 0011 Enable = 1 1011 0100 APPLICATIONS INFORMATION The primary application of these devices is as a high–speed variable modulus prescaler in the divide by N section of a phase–locked loop synthesizer used as the local oscillator of two–way radios. Proper VHF termination techniques should be followed when the clock is separated from the prescaler by any appreciable distance. Page 13 of 14 In their basic form, these devices will divide by 5/6 or 8/9. Division by 5, or 8 occurs when any one or all of the five gate inputs E1 through E5 are high. Division by 6, or 9 occurs when all inputs E1 through E5 are low. (Unconnected MTTL inputs are normally high, unconnected MECL inputs are normally low). With the addition of extra parts, many different division configurations may be obtained. www.lansdale.com Issue A ML12009, ML12011 LANSDALE Semiconductor, Inc. OUTLINE DIMENSIONS SO 16 = -5P PLASTIC PACKAGE (ML12009-5P, ML12011-5P) CASE 751B–05 (SO–16) ISSUE J –A– 16 9 –B– 1 P NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. 8 PL 0.25 (0.010) 8 B M S G R K F X 45 C –T– SEATING PLANE J M D 16 PL 0.25 (0.010) M T B S A S P DIP 16 = EP PLASTIC PACKAGE (ML12009EP, ML12011EP) CASE 648–08 ISSUE R –A– 16 9 1 8 B F C L S –T– SEATING PLANE K H G D J 16 PL 0.25 (0.010) M T A M M DIM A B C D F G J K M P R MILLIMETERS MIN MAX 9.80 10.00 3.80 4.00 1.35 1.75 0.35 0.49 0.40 1.25 1.27 BSC 0.19 0.25 0.10 0.25 0 7 5.80 6.20 0.25 0.50 INCHES MIN MAX 0.386 0.393 0.150 0.157 0.054 0.068 0.014 0.019 0.016 0.049 0.050 BSC 0.008 0.009 0.004 0.009 0 7 0.229 0.244 0.010 0.019 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. DIMENSION L TO CENTER OF LEADS WHEN FORMED PARALLEL. 4. DIMENSION B DOES NOT INCLUDE MOLD FLASH. 5. ROUNDED CORNERS OPTIONAL. DIM A B C D F G H J K L M S INCHES MIN MAX 0.740 0.770 0.250 0.270 0.145 0.175 0.015 0.021 0.040 0.70 0.100 BSC 0.050 BSC 0.008 0.015 0.110 0.130 0.295 0.305 0 10 0.020 0.040 MILLIMETERS MIN MAX 18.80 19.55 6.35 6.85 3.69 4.44 0.39 0.53 1.02 1.77 2.54 BSC 1.27 BSC 0.21 0.38 2.80 3.30 7.50 7.74 0 10 0.51 1.01 Lansdale Semiconductor reserves the right to make changes without further notice to any products herein to improve reliability, function or design. Lansdale does not assume any liability arising out of the application or use of any product or circuit described herein; neither does it convey any license under its patent rights nor the rights of others. “Typical” parameters which may be provided in Lansdale data sheets and/or specifications can vary in different applications, and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by the customer’s technical experts. Lansdale Semiconductor is a registered trademark of Lansdale Semiconductor, Inc. Page 14 of 14 www.lansdale.com Issue A