Final Electrical Specifications LT1948 DC/DC Converter for TFT-LCD Panels NOT RECOMMENDED FOR NEW DESIGNS Contact Linear Technology for Potential Replacement August 2000 U FEATURES ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ DESCRIPTIO The LT®1948 is a highly integrated multiple output DC/DC converter designed for use in TFT-LCD panels. The device contains two independent switching regulators: the main regulator has an adjustable output voltage with an internal 1.1A switch that can generate a boosted voltage as high as 30V while the second regulator generates 23V at up to 10mA for positive bias. A simple level-shift charge pump off the main switch node generates the negative bias voltage. An external capacitor sets the delay time from AVDD reaching final value to 23V appearing at the VON pin. The 3MHz switching frequency allows the use of tiny low profile chip inductors and capacitors throughout, providing a low noise, low cost total solution with all components under 1.25mm in height. The device operates from an input range of 2.6V to 6V and is available in an 8-lead MSOP package. Complete Solution Under 1.2mm Develops Three Outputs from a 3.3V or 5V Supply Externally Programmable VON Delay Fixed Frequency Low Noise Outputs All Ceramic Capacitors Operates at 3MHz Switching Frequency Fast Transient Response Few External Components Required 2.6V to 6V Input Range Tiny 8-Lead MSOP Package U APPLICATIO S ■ ■ ■ ■ TFT-LCD Notebook Display Panels TFT-LCD Desktop Monitor Display Panels Digital Cameras Handheld Computers , LTC and LT are registered trademarks of Linear Technology Corporation. U TYPICAL APPLICATIO D3A BAT54S L1, 2.2µH L2, 2.2µH VIN 2.5V TO 6V C1 2.2µF L3 2.2µH D3B C4 0.22µF D1 MBRM120 Start-Up Waveforms AVDD 8V 260mA R1 53.6k C2 2.2µF SW1 VIN SW2 FB1 D2 CMDSH-3 R2 10k LT1948 VO2 C3 0.22µF C5 1µF VOFF –8V 15mA VON CT GND VON 23V 10mA C6 22nF C1, C2: TAIYO YUDEN LMK212BJ225 C3: TAIYO YUDEN TMK316BJ224 C4: TAIYO YUDEN EMK212BJ224 VIN 5V/DIV VON 20V/DIV AVDD 10V/DIV VOFF 10V/DIV C5: TAIYO YUDEN LMK212BJ105 L1–L3: TAIYO YUDEN LB2012-2R2 2ms/DIV 1948 TA01a 1948 F01 Figure 1. 3.3V Powered TFT-LCD Bias Generator Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights. 1 LT1948 U W W W ABSOLUTE AXI U RATI GS U W U PACKAGE/ORDER I FOR ATIO (Note 1) VIN Voltage ................................................................ 8V CT Voltage.................................................................. 6V SW1, SW2 Voltage .................................................. 36V FB Voltage ................................................................. 3V VON, VO2 Voltage..................................................... 30V Operating Temperature Range (Note 2) .. – 40°C to 85°C Lead Temperature (Soldering, 10 sec).................. 300°C ORDER PART NUMBER TOP VIEW FB1 CT SW1 GND 1 2 3 4 8 7 6 5 VON VO2 SW2 VIN LT1948EMS8 MS8 PART MARKING MS8 PACKAGE 8-LEAD PLASTIC MSOP TJMAX = 125°C, θJA = 200°C/W LTNR Consult factory for Industrial and Military grade parts. ELECTRICAL CHARACTERISTICS The ● denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. VIN = 3.3V unless otherwise specified. SYMBOL CONDITIONS Supply Current Not Switching MIN Reference Voltage Reference Line Reg 2.7V < VIN < 8V CT Source Current VFB1 = 1.3V TYP MAX 7 13 UNITS mA 1.26 V 0.01 %/V 4.5 5.5 6.5 µA CT Voltage to Turn On Q3 1.25 1.28 1.30 V FB1 Voltage to Begin CT Charge 1.17 1.20 1.23 V SW1 Current Limit (Note 3) 1.2 1.5 A SW2 Current Limit (Note 3) 0.5 0.8 A SW1 Saturation Voltage ISW1 = 800mA SW2 Saturation Voltage ISW2 = 300mA Oscillator Frequency VO2 Pin Resistance 410 mV 250 300 mV ● 2.4 3.2 3.6 MHz 70 69 67 75 90 ● ● % % % Maximum Duty Cycle 0°C ≤ TA ≤ 85°C –40°C ≤ TA ≤ 0°C 350 Measured to Ground 400 kΩ SW1, SW2 Error Amp Gain 100 V/V SW1, SW2 Error Amp Gm 50 µA/V FB1 Regulation Voltage ● FB1 Line Regulation 1.240 1.230 2.7V < VIN < 8V VO2 Regulation Voltage 22 1.260 1.280 1.285 V V 0.01 0.05 23 24 V VON Switch Drop VO2 = 25V, 7mA Load from VON, CT Voltage >1.30V 200 260 mV SW1 Leakage Current Switch Off, SW1 Voltage = 3.3V 0.01 5 µA SW2 Leakage Current Switch Off, SW2 Voltage = 3.3V 0.01 2 µA Note 1: Absolute Maximum Ratings are those values beyond which the life of a device may be impaired. Note 2: The LT1948 is guaranteed to meet performance specifications from 0°C to 70°C. Specifications over the – 40°C to 85°C operating 2 temperature range are assured by design, characterization and correlation with statistical process controls. Note 3: Current limit guaranteed by design and/or correlation to static test. LT1948 U U U PI FU CTIO S FB1 (Pin 1): Feedback Pin for First Switcher. Connect resistor divider tap here. Set AVDD according to AVDD = 1.26V(1 + R1/R2). VIN (Pin 5): Input Supply Pin. Must be bypassed with a ceramic capacitor close to the pin. SW2 (Pin 6): VO2 Switch Node. Connect inductor and D2 here. Minimize trace area at this pin to keep EMI down. CT (Pin 2): Timing Capacitor Pin. Connect a 22nF capacitor from CT to ground to program a 3ms delay from FB1 reaching 1.26V to VON turning on. VO2 (Pin 7): Sense Pin for 23V Output. Connect to VO2 output capacitor. This node is also internally connected to the emitter of Q3 (see Block Diagram), the high side switch between VO2 and VON. SW1 (Pin 3): AVDD Switch Node. Connect inductor and D1 here (see Figure 1). Minimize trace area at this pin to keep EMI down. VON (Pin 8): This is the Delayed 23V Output. VON becomes 23V after the internal timer times out. GND (Pin 4): Ground. Connect directly to local ground plane. U OPERATIO To best understand operation of the LT1948, please refer to the LT1948 Block Diagram. The device contains two switching regulators, a timer and a high side switch. Three outputs can be generated: an adjustable AVDD output, a charge-pumped inversion of the AVDD output, called VOFF, and a 23V/15mA output, called VON. Q3 keeps VON off for an externally set time interval, set by a capacitor connected to the CT pin. When the input voltage is below approximately 2.4V, an undervoltage lockout circuit disables switching. When AVDD is less than its final voltage, Q4 is turned on, holding the CT pin at ground. When AVDD reaches final value, Q4 lets go of the CT pin, allowing the 5.5µA current source to charge the external capacitor, CT. When the voltage on the CT pin reaches 1.25V, Q3 turns on, connecting VO2 to VON. Capacitor value can be calculated using the following formula: The switching frequency of both switchers is 3MHz, set internally. The switchers are current mode and are internally compensated. The main AVDD switcher is current limited at 1.5A, while the second VON switcher is limited to 800mA. They share the same 1.26V reference voltage. C = (5.5µA • tDELAY)/1.25V A 22nF capacitor results in approximately 3ms of delay. AVDD VON R1 R2 1 8 2 7 3 6 4 5 D1 C2 D2 C3 L3 L1–L2 VIN C1 GND C6 C4 D3A 1948 F02 D4B VOFF Figure 2. Recommended Component Placement 3 LT1948 W BLOCK DIAGRA VIN GND VIN OSC – FB1 – SW1 S + R Q1 Q + REF ∑ + 0.01Ω + SLOPE 1 8µA 28mV –+ CT Q4 REF REF VON 1.26V REFERENCE AND UNDERVOLTAGE LOCKOUT OSC 3MHz OSCILLATOR SLOPE 1 SLOPE 2 Q3 REF VO2 OSC – – SW2 S + R Q2 Q + REF ∑ + 0.03Ω + SLOPE 2 1948BD RELATED PARTS PART NUMBER DESCRIPTION COMMENTS LT1949 600kHz, 1A Switch PWM DC/DC Converter 10V at 175mA from 3.3V Input LT1317 2-Cell Micropower DC/DC with Low-Battery Detect 3.3V at 200mA from 2-Cell Input LT1308B 600kHz Single Cell Step-Up Regulator 5V at 1A from a 1-Cell Li-Ion Battery LT1615 Micropower Step-Up Regulator in SOT-23 20V at 12mA from 2.5V Input, 5-Lead SOT-23 Package LT1930 1.2MHz, Step-Up Regulator in SOT-23 5V at 480mA from 3.3V, 5-Lead SOT-23 Package 4 Linear Technology Corporation 1948i LT/TP 0800 4K • PRINTED IN USA 1630 McCarthy Blvd., Milpitas, CA 95035-7417 (408)432-1900 ● FAX: (408) 434-0507 ● www.linear-tech.com LINEAR TECHNOLOGY CORPORATION 2000