LF3321 Horizontal Digital Image Filter DEVICES INCORPORATED Improved Performance FEATURES Supports Interleaved Data Streams Supports Decimation up to 16:1 for Increasing Number of Filter Taps 3.3 Volt Power Supply 144 Lead PQFP 111 MHz Data Rate 12-bit Data or Coefficients (Expandable to 24-bit) 32-Tap FIR Filter, Cascadable for More Filter Taps LF Interface™ Allows All 256 Coefficient Sets to be Updated Within Vertical Blanking Over 49 K-bits of on-board Memory Various Operating Modes: Dual Filter, Single Filter, Double Wide Data or Coefficient, Matrix Multiplication, and Accumulator Access. Selectable 16-bit Data Output with User-Defined Rounding and Limiting DESCRIPTION The LF3321 is an improved version of the LF3320 Horizontal Digital Image Filter capable of operating at speeds of up to 111MHz. This improved speed increases flexibility and performance and enables the user to utilize this device in more applications. For example, four interleaved data streams of 27MHz can now be processed within one device. The part is functionally identical to the LF3320 with the exception that the filter data path is specified to operate faster than the LF Control Interface. When operating the filter at speeds in excess of 90MHz, loading of coefficients via the LF Interface must be throttled to a maximum of 90MHz by asserting the PAUSE pin as required to allow sufficient setup time for the configuration data provided to the chip via the LF Interface. Figure 1. Switching Waveforms: LF InterfaceTM CLK tPWH tS0 LDA LDB tPS PAUSEA PAUSEB CFA 11-0 CFB 11-0 tPWL tLH tCYC tPH tCFH tCFS ADDRESS CF0 CF1 Figure 1 demonstrates the switching waveforms, while the switching characteristics are given in Table 1. The LF3321 filters digital images in the horizontal dimension at real-time video rates. The input and coefficient data are both 12 bits and in two’s complement format. The output is also in two’s complement format and may be rounded to 16 bits. The LF3321 is designed to take advantage of symmetric coefficient sets. When symmetric coefficient sets are used, the device can be configured as a single 32-tap FIR filter or as two separate 16-tap FIR filters. When asymmetric coefficient sets are used, the device can be configured as a single 16-tap FIR filter or as two separate 8-tap FIR filters. Multiple LF3321s can be cascaded to create larger filters. Interleave/Decimation Registers (I/D Registers) allow interleaved data to be fed directly into the device and filtered without separating the data into individual data streams. The LF3321 can handle a maximum of sixteen data sets interleaved together. The I/D Registers and on-chip accumulators facilitate using decimation to increase the number of filter taps. Decimation of up to 16:1 is supported. The LF3321 contains enough on-board memory to store 256 coefficient sets. Two separate LF InterfacesTM allow all 256 coefficient sets to be updated within vertical blanking. LOGIC Devices Incorporated 1 Video Imaging Products Feb 5, 2003 LDS.3321-A LF3321 Horizontal Digital Image Filter DEVICES INCORPORATED Improved Performance DESCRIPTION Table 1. Switching Characteristics Commercial Operating Range (0ºC to + 70ºC) 9* (ns) speed grade Symbol Parameter MIN MAX tCYC Cycle Time 9 tPWL Clock Pulse Width Low 4 tPWH Clock Pulse Width High 4 tS0 Input Setup Time 4 tH0 Input Hold Time 0 tSCT Setup Time Control Inputs 4 tHCT Hold Time Control Inputs 0 tSCC Setup Time Coefficient Control Inputs 4 tHCC Hold Time Coefficient Control Inputs 0 tD Output Delay tDCC Cascade Output Delay 7.5 tDIS Three State Output Display Delay 10 tDIS Three State Output Enable Delay 10 8 Figure 2. LF3321 Block Diagram ROUT11-0 DIN11-0 CAA7-0 12 12 INTERLEAVE / DECIMATION REGISTERS 12 12 8 8 12 12 CENA CFA11-0 PAUSEA LDA RIN11-0 COUT11-0 CAB7-0 CENB 256 COEFFICIENT SET STORAGE 16-TAP FILTER A 16-TAP FILTER B 256 COEFFICIENT SET STORAGE CFB11-0 PAUSEB LDB ROUND SELECT LIMIT CIRCUITRY CLK OED 16 DOUT15-0 LOGIC Devices Incorporated 2 Video Imaging Products Feb 5, 2003 LDS.3321-A 3 FILTER A LF INTERFACE Coef Bank 7 Coef Bank 6 Coef Bank 5 Coef Bank 4 Coef Bank 3 CLK SHENB SHENA RSLA3-0 TXFRB TXFRA 4 B A ALU B A ALU B A ALU B B A ALU B A ALU B A ALU B A ALU B 32 27 13 13 32 13 "0" 13 27 13 13 ALU B 25 25 25 25 ACCM A 25 25 25 25 DOUT15-0 16 16 16 RSLB OUT15-0 LIMIT FILTER B FILTER A 25 LIMIT ROUND ACCM B 25 SELECT SCALE 25 ROUND 25 SELECT 32 CONFIGURATION AND CONTROL REGISTERS 25 25 25 25 12 13 A 12 32 ALU 12 "0" A 12 27 B 12 27 ALU 12 13 A 12 13 B 12 13 ALU 12 13 A 12 B 12 13 ALU 12 13 A 12 13 B 12 1-16 12 13 ALU 1-16 A 12 FILTER B LF INTERFACE Coef Bank 8 Coef Bank 9 Coef Bank 10 Coef Bank 11 Coef Bank 12 Coef Bank 13 Coef Bank 14 Coef Bank 15 8 4 CAB7-0 12 12 OED RSLB3-0 ACCB CENB COUT11-0 OEC RIN11-0 DEVICES INCORPORATED ACCA 12 CENA Coef Bank 2 ALU 1-16 1-16 Coef Bank 1 A 1-16 1-16 B 1-16 1-16 ALU 1-16 1-16 A 1-16 1-16 12 B 1-16 1-16 Coef Bank 0 ALU 1-16 13 A S E O I 8 12 DATA REVERSAL 1-16 FILTER B I/D REGISTERS 1-16 1-16 FILTER A I/D REGISTERS 1-16 1-16 RSLB OUT15-12 1-16 4 8 1-16 1-16 CAA7-0 DIN11-0 ROUT11-4 RSLB OUT11-0 OEC 1-16 1-16 CFA11-0 1-16 1-16 PAUSEA 1-16 1-16 CFB11-0 1-16 LDA R E O I LDB DATA REVERSAL PAUSEB LOGIC Devices Incorporated ROUT3-0 LF3321 Horizontal Digital Image Filter Improved Performance DESCRIPTION Figure 3. LF3321 Functional Block Diagram Video Imaging Products Feb 5, 2003 LDS.3321-A LF3321 Horizontal Digital Image Filter DEVICES INCORPORATED Improved Performance Functional Description ALU The ALUs double the number of filter taps available, when symmetric coefficient sets are used, by preadding data values which are then multiplied by a common coefficient (see Figure 4). The ALUs can perform two operations: A+B and B–A. Bit 0 of Configuration Register 0 determines the operation of the ALUs in Filter A. Bit 0 of Configuration Register 2 determines the operation of the ALUs in Filter B. A+B is used with even-symmetric coefficient sets. B–A is used with odd-symmetric coefficient sets. Also, either the A or B operand may be set to 0. Bits 1 and 2 of Configuration Register 0 and Configuration Register 2 control the ALU inputs in Filters A and B respectively. A+0 or B+0 are used with asymmetric coefficient sets. Figure 4. Symmetric Coefficient Set Examples 8 7 6 5 8 7 6 5 4 3 2 1 Even-Tap, Even-Symmetric Coefficient Set I/D Registers 7 6 5 4 3 2 1 Odd-Tap, Even-Symmetric Coefficient Set 4 3 2 1 Even-Tap, Odd-Symmetric Coefficient Set The Interleave/Decimation Registers (I/D Registers), feed the ALU inputs. They allow the device to filter up to sixteen data sets interleaved into the same data stream without having to separate the data sets. The I/D Registers should be set to a length equal to the number of data sets interleaved together. For example, if two data sets are interleaved together, the I/D Registers should be set to a length of two. Bits 1 through 4 of Configuration Register 1 and Configuration Register 3 determine the length of the I/D Registers in Filters A and B respectively. The I/D Registers also facilitate using decimation to increase the number of filter taps. Decimation by N is accomplished by reading the filter’s output once every N clock cycles. The device supports decimation up to 16:1. With no decimation, the maximum number of filter taps is sixteen. When decimating by N, the number of filter taps becomes 16N because there are N–1 clock cycles when the filter’s output is not being read. The extra clock cycles are used to calculate more filter taps. When decimating, the I/D Registers should be set to a length equal to the decimation factor. For example, when performing a 4:1 decimation, the I/D Registers should be set to a length of four. When decimation is disabled or when only one data set (non-interleaved data) is fed into the device, the I/D Registers should be set to a length of one. I/D Registers Data Path Control LOGIC Devices Incorporated The three multiplexers in the I/D Register data path control how data is routed through the forward and reverse data paths. The forward data path contains the I/D Registers in which data flows from left to right in the block diagram in Figure 1. The reverse data path contains the I/D Registers in which data flows from right to left. In Single or Dual Filter Modes, data is fed from the forward data path to the reverse data path as follows. When the filter is configured for an even number of taps, data from the last I/D Register in the forward data path is fed into the first I/D Register in the reverse data path (see Figure 5). When the filter is configured for an odd number of taps, the data which will appear at the output of the last I/D Register in the forward data path on the next clock cycle is fed into the first I/D Register in the reverse data path. Bit 5 in Configuration Register 1 and Configuration Register 3 configures Filters A and B respectively for an even or odd number of taps. 4 Video Imaging Products Feb 5, 2003 LDS.3321-A LF3321 Horizontal Digital Image Filter DEVICES INCORPORATED Improved Performance Functional Description Figure 5. I/D Register Data Paths ALU 1-16 1-16 1-16 1-16 1-16 1-16 Delay Stage N A A B DATA REVERSAL ALU B 1-16 ALU A B 1-16 A DATA REVERSAL ALU B 1-16 1-16 DATA REVERSAL 1-16 1-16 A Delay Stage N 1 ALU B A ALU B COEF 7 COEF 7 2 COEF 7 2 COEF 6 COEF 6 COEF 6 EVEN-TAP MODE ODD-TAP MODE ODD-TAP INTERLEAVE MODE When interleaved data is fed through the device and an even tap filter is desired, the filter should be configured for an even number of taps and the I/D Register length should match the number of data sets interleaved together. When interleaved data is fed through the device and an odd tap filter is desired, the filter should be set to Odd-Tap Interleave Mode. Bit 0 of Configuration Register 1 and Configuration Register 3 configures Filters A and B respectively for Odd-Tap Interleave Mode. When the filter is configured for Odd-Tap Interleave Mode, data from the next to last I/D Register in the forward data path is fed into the first I/D Register in the reverse data path. When the filter is configured for an odd number of taps (interleaved or non-interleaved modes), the filter is structured such that the center data value is aligned simultaneously at the A and B inputs of the last ALU in the forward data path. In order to achieve the correct result, the user must divide the coefficient by two. Data Reversal Data reversal circuitry is placed after the multiplexers which route data from the forward data path to the reverse data path (see Figure 6). When decimating, the data stream must be reversed in order for data to be properly aligned at the inputs of the ALUs. Figure 6. Data Reversal LOGIC Devices Incorporated 5 Video Imaging Products Feb 5, 2003 LDS.3321-A LF3321 Horizontal Digital Image Filter DEVICES INCORPORATED Improved Performance Functional Description Data Reversal Continued When data reversal is enabled, the circuitry uses a pair of LIFOs to reverse the order of the data sent to the reverse data path. TXFRA and TXFRB control the LIFOs in Filters A and B respectively. When TXFRA/TXFRB goes LOW, the LIFO sending data to the reverse data path becomes the LIFO receiving data from the forward data path, and the LIFO receiving data from the forward data path becomes the LIFO sending data to the reverse data path. The device must see a HIGH to LOW transition of TXFRA/TXFR B in order to switch LIFOs. If decimating by N, TXFRA/TXFRB should go LOW once every N clock cycles. When data reversal is disabled, the circuitry functions like an I/D Register. When feeding interleaved data through the filter, data reversal should be disabled. Bit 6 of Configuration Register 1 and Configuration Register 3 enables or disables data reversal for Filters A and B respectively. Figure 7 .Filter A and Filter B Round/Limit/Select Circuitry RSLB3-0 DATA IN 32 32 RSLA3-0 4 RB0 RA0 4 DATA IN 32 RND 32 RB15 RA15 RND 32 SELECT SELECT 16 16 SB0 SA0 32 5 LB0 LA0 SB15 SA15 5 LIMIT FILTER B RSL 16 DATA OUT LOGIC Devices Incorporated 32 LA15 LIMIT LB15 32 6 16 FILTER A RSL DATA OUT Video Imaging Products Feb 5, 2003 LDS.3321-A LF3321 Horizontal Digital Image Filter DEVICES INCORPORATED Improved Performance Functional Description Cascading Three cascade ports are provided to allow cascading of multiple devices for more filter taps (see Figure 8). COUT11-0 of one device should be connected to DIN11-0 of another device. ROUT11-0 of one device should be connected to RIN11-0 of another device. As many LF3321s as desired may be cascaded together. However, the outputs of the LF3321s must be added together with external adders. Bit 0 of Configuration Register 5 determines how the device will send data to the reverse data path when multiple LF3321s are cascaded together. If a LF3321 is the last in the cascade chain, Bit 0 of Configuration Register 5 should be set to a “0”. This will cause the data from the end of the forward data path to be routed to the beginning of the reverse data path based on how the filter is configured (even/odd number of taps or interleave mode). If a LF3321 is not the last in the cascade chain, Bit 0 of Configuration Register 5 should be set to a “1”. This will cause RIN11-0 to feed data to the reverse data path. When not cascading, Bit 0 of Configuration Register 5 should be set to a “0”. Special data routing circuitry is used to feed the COUT and ROUT output registers. The data routing circuitry is required to correctly align data in the forward and reverse data paths as data passes from one LF3321 to another. The COUT and ROUT registers are loaded with data which is two clock cycles behind the current output of the I/D Register just before the ROUT or COUT register. This correctly accounts for the extra delays added to the forward and reverse data paths by the input/output cascade registers. Output Adder The Output Adder adds the Filter A and B outputs together when the device is in Single Filter Mode. If 24-bit data and 12-bit coefficients or 12-bit data and 24-bit coefficients are desired, the LF3321 can facilitate this by scaling the Filter B output by 2-12 before adding it to the Filter A output. Bit 3 in Configuration Register 5 determines if the Filter B output is scaled before being added to the Filter A output. Figure 8. Multiple LF3321 Cascaded Together LF3320 DIN 12 I/D REGISTERS I/D REGISTERS FILTER A FILTER B LF3320 RIN COUT ROUT DIN I/D REGISTERS I/D REGISTERS FILTER A FILTER B LF3320 RIN ROUT COUT DIN I/D REGISTERS I/D REGISTERS FILTER A FILTER B LF3320 RIN COUT ROUT DIN I/D REGISTERS I/D REGISTERS FILTER A FILTER B RSL CIRCUIT RSL CIRCUIT RSL CIRCUIT RSL CIRCUIT 16 16 16 16 LF3347 25 25 RSL CIRCUIT 16 DATA OUT 128 TAP RESULT LOGIC Devices Incorporated 7 Video Imaging Products Feb 5, 2003 LDS.3321-A LF3321 Horizontal Digital Image Filter DEVICES INCORPORATED Improved Performance Functional Description Rounding The overall filter output (Single Filter Mode) or Filter A and B outputs (Dual Filter Mode) may be rounded by adding the contents of one of the sixteen Filter A or B round registers to the overall filter, Filter A, or Filter B outputs (see Figure 10). The Filter A round registers are used for the overall filter (Single Filtermode) or Filter A (Dual Filter Mode). The Filter B round registers are used for Filter B (Dual Filter Mode). Each round register is 32-bits wide and user-programmable. This allows the filter’s output to be rounded to any precision required. Since any 32-bit value may be programmed into the round registers, the device can support complex rounding algorithms as well as standard Half-LSB rounding. RSLA3-0 determines which of the sixteen Filter A round registers are used in the Filter A rounding circuitry. RSLB3-0 determines which of the sixteen Filter B round registers are used in the Filter B rounding circuitry. A value of 0 on RSLA/RSLB3-0 selects Filter A/B round register 0. A value of 1 selects Filter A/B round register 1 and so on. RSLA/RSLB3-0 may be changed every clock cycle if desired. This allows the rounding algorithm to be changed every clock cycle. This is useful when filtering interleaved data. If rounding is not desired, a round register should be loaded with 0 and selected as the register used for rounding. Round register loading is discussed in the LF InterfaceTM section. Output Select The word width of the overall filter, Filter A, and Filter B outputs is 32-bits. However, only 16-bits may be sent to DOUT15-0 (Single or Dual Filter Modes) and COUT11-0/ROUT3-0 (Dual Filter Mode). The Filter A/B select circuitry determines which 16-bits are passed (see Table 20). The Filter A/B select registers control the Filter A/B select circuitry. There are sixteen Filter A and B select registers. The Filter A select registers are used for the overall filter (Single Filter Mode) or Filter A (Dual Filter Mode). The Filter B select registers are used for Filter B (Dual Filter Mode). Each select register is 5 bits wide and user-programmable. RSLA3-0 determines which of the sixteen Filter A select registers are used in the Filter A select circuitry. RSLB3-0 determines which of the sixteen Filter B select registers are used in the Filter B select circuitry. A value of 0 on RSLA/RSLB3-0 selects Filter A/B select register 0. A value of 1 selects Filter A/B select register 1 and so on. RSLA/RSLB3-0 may be changed every clock cycle if desired. This allows the 16-bit window to be changed every clock cycle. This is useful when filtering interleaved data. Select register loading is discussed in the LF InterfaceTM section. Output Limiting An output limiting function is provided for the overall filter, Filter A, and Filter B outputs. The Filter A limiting circuitry is used to limit the overall filter output (Single Filter Mode) and the Filter A output (Dual Filter Mode). The Filter B limiting circuitry is used to limit the Filter B output (Dual Filter Mode). The Filter A and B limit registers determine the valid range of output values for the Filter A and B limiting circuitry respectively. There are sixteen 32-bit user-programmable limit registers for both Filters A and B. The Filter A limit registers are used for the overall filter (Single Filter Mode) or Filter A (Dual Filter Mode). The Filter B limit registers are used for Filter B (Dual Filter Mode). RSLA3-0 determines which of the sixteen Filter A limit registers are used in the Filter A limit circuitry. RSLB3-0 determines which of the sixteen Filter B limit registers are used in the Filter B limit circuitry. A value of 0 on RSLA/RSLB3-0 selects Filter A/B limit register 0. A value of 1 selects Filter A/B limit register 1 and so on. Each limit register contains an upper and lower limit value. If the value fed to the limiting circuitry is less than the lower limit, the lower limit value is passed as the filter output. If the value fed to the limiting circuitry is greater than the upper limit, the upper limit value is passed as the filter output. Bit 1 and 0 in Configuration Register 4 enable and disable Filter A and B limiting respectively. RSLA/RSLB3-0 may be changed every clock cycle if desired. This allows the limit range to be changed every clock cycle. This is useful when filtering interleaved data. When loading limit values into the device, the upper limit must be greater than the lower limit. Limit register loading is discussed in the LF InterfaceTM section. Coefficient Banks The coefficient banks store the coefficients which feed into the multipliers in Filters A and B. There is a separate bank for each multiplier. Each bank can hold 256 12-bit coefficients. The banks are loaded using an LF InterfaceTM. There is a separate LF InterfaceTM for the Filter A and B banks. Coefficient bank loading is discussed in the LF InterfaceTM section. LOGIC Devices Incorporated 8 Video Imaging Products Feb 5, 2003 LDS.3321-A LF3321 Horizontal Digital Image Filter DEVICES INCORPORATED Improved Performance Functional Description Configuration and Control Registers The configuration registers determine how the LF3321 operates. Tables 2 through 7 show the formats of the six configuration registers. There are three types of control registers: round, select, and limit. There are sixteen round registers for Filter A and sixteen for Filter B. Each register is 32 bits wide. RSLA3-0 and RSLB3-0 determine which Filter A and B round registers respectively are used for rounding. There are sixteen select registers for Filter A and sixteen for Filter B. Each register is 5 bits wide. RSLA3-0 and RSLB3-0 determine which Filter A and B select registers respectively are used in the select circuitry. There are sixteen limit registers for Filter A and sixteen for Filter B. Each register is 32-bits wide and stores both an upper and lower limit value. The lower limit is stored in bits 15-0 and the upper limit is stored in bits 31-16. RSLA3-0 and RSLB3-0 determine which Filter A and B limit registers respectively are used for limiting when limiting is enabled. Configuration and control register loading is discussed in the LF InterfaceTM section. Table 2. Configuration register 0 - Address 200H BITS FUNCTION DESCRIPTION 0 ALU Mode 1 Pass A 2 Pass B 0:A+B 1:B–A 0 : ALU Input A = 0 1 : ALU Input A = Forward Register Path 0 : ALU Input B = 0 1 : ALU Input B = Reverse Register Path Must be set to “0” 11-3 Reserved Table 3. Configuration Register 1 - Address 201H BITS 0 4-1 5 Filter B Tap Number 6 Filter B Data Reversal 11-7 LOGIC Devices Incorporated FUNCTION Filter B Odd-Tap Interleave Mode Filter B I/D Register Length Reserved 9 DESCRIPTION 0 : Odd-Tap Interleave Mode Disabled 1 : Odd-Tap Interleave Mode Enabled 0000 : 1 Register 0001 : 2 Registers 0010 : 3 Registers 0011 : 4 Registers 0100 : 5 Registers 0101 : 6 Registers 0110 : 7 Registers 0111 : 8 Registers 1000 : 9 Registers 1001 : 10 Registers 1010 : 11 Registers 1011 : 12 Registers 1100 : 13 Registers 1101 : 14 Registers 1110 : 15 Registers 1111 : 16 Registers 0 : Even Number of Taps 1 : Odd Number of Taps 0 : Data Reversal Enabled 1 : Data Reversal Disabled Must be set to “0” Video Imaging Products Feb 5, 2003 LDS.3321-A LF3321 Horizontal Digital Image Filter DEVICES INCORPORATED Improved Performance Functional Description Table 4. Configuration Register 2 - Address 202H BITS 0 FUNCTION ALU Mode Filter B DESCRIPTION 1 Pass A Filter B 2 Pass B Filter B 0 : ALU Input A=0 1 : ALU Input A=Forward Register Path 0 : ALU Input A=0 1 : ALU Input A=Reverse Register Path Must be set to “0“ 11-3 Reserved 0:A+B 1:B–A Table 5. Configuration Register 3 - Address 203H BITS 0 4-1 FUNCTION Filter A Odd-Tap Interleave Mode Filter A I/D Register Length 5 Filter A Tap Number 6 Filter A Data Reversal 11-7 Reserved DESCRIPTION 0 : Odd-Tap Interleave Mode Disabled 1 : Odd-Tap Interleave Mode Enabled 0000 : 1 Register 0001 : 2 Registers 0010 : 3 Registers 0011 : 4 Registers 0100 : 5 Registers 0101 : 6 Registers 0110 : 7 Registers 0111 : 8 Registers 1000 : 9 Registers 1001 : 10 Registers 1010 : 11 Registers 1011 : 12 Registers 1100 : 13 Registers 1101 : 14 Registers 1110 : 15 Registers 1111 : 16 Registers 0 : Even Number of Taps 1 : Odd Number of Taps 0 : Data Reversal Enabled 1 : Data Reversal Disabled Must be set to “0” Table 6. Configuration Register 4 - Adress 204H BITS 0 FUNCTION Filter B Limit Enable 1 Filter A Limit Enable 11-2 LOGIC Devices Incorporated Reserved 10 DESCRIPTION 0 : Limiting Disabled 1 : Limiting Enabled 0 : Limiting Disabled 1 : Limiting Enabled Must be set to “0” Video Imaging Products Feb 5, 2003 LDS.3321-A LF3321 Horizontal Digital Image Filter DEVICES INCORPORATED Improved Performance Functional Description Table 7. Configuration Register 5 - Adress 205H BITS 0 FUNCTION Vertical Limit Enable 1 Horizontal Limit Enable 11-2 Reserved DESCRIPTION 0 : Vertical Limiting Disabled 1 : Vertical Limiting Enabled 0 : Horizontal Limiting Disabled 1 : Horizontal Limiting Enabled Must be set to “0” Table 8. CFA/CFB11-9 Decode 11 0 0 0 0 1 1 1 1 LF Interface ™ 10 0 0 1 1 0 0 1 1 9 0 1 0 1 0 1 0 1 DESCRIPTION Coefficient Banks Configuration Registers Filter A Select Registers Filter B Select Registers Filter A Round Registers Filter B Round Registers Filter A Limit Registers Filter B Limit Registers The Filter A and B LF InterfacesTM are used to load data into the Filter A and B coefficient banks respectively. They are also used to load data into the configuration and control registers. The following section describes how the Filter A LF InterfaceTM works. The Filter A and B LF InterfacesTM are identical in function. If LDA and CFA11-0 are replaced with LDB and CFB11-0, the following section will describe how the Filter B LF InterfaceTM works. LDA is used to enable and disable the Filter A LF InterfaceTM. When LDA goes LOW, the Filter A LF InterfaceTM is enabled for data input. The first value fed into the interface on CFA11-0 is an address which determines what the interface is going to load. The three most significant bits (CFA11-9) determine if the LF InterfaceTM will load coefficient banks or Configuration/control registers (see Table 8). The nine least significant bits (CFA8-0) are the address for whatever is to be loaded (see Tables 9 through 14). For example, to load address 15 of the Filter A coefficient banks, the first data value into the LF InterfaceTM should be 00FH. Table 9 Fltr. A Round Regs. Table 10 Fltr. A Select Regs Table 11 Fltr. A Limit Regs. REGISTER ADDRESS (HEX) 0 800 1 801 REGISTER ADDRESS (HEX) 0 400 1 401 REGISTER ADDRESS (HEX) 0 C00 1 C01 14 15 14 15 40E 40F 14 15 C0E C0F Table 12 Fltr. B Round Regs Table 13 Fltr. B Select Regs Table 14 Fltr. B Limit Regs REGISTER ADDRESS (HEX) 0 A00 1 A01 REGISTER ADDRESS (HEX) 0 600 1 601 REGISTER ADDRESS (HEX) 0 E00 1 E01 14 15 LOGIC Devices Incorporated 80E 80F A0E A0F 14 15 11 60E 60F 14 15 E0E E0F Video Imaging Products Feb 5, 2003 LDS.3321-A LF3321 Horizontal Digital Image Filter DEVICES INCORPORATED Improved Performance Functional Description LF Interface ™ Continued To load Filter A limit register 10, the first data value should be C0AH. The first address value should be loaded into the interface on the same clock cycle that latches the HIGH to LOW transition of LDA (see Figures 9 and 10). The next value(s) loaded into the interface are the data value(s) which will be stored in the bank or register defined by the address value. When loading coefficient banks, the interface will expect eight values to be loaded into the device after the address value. The eight values are coefficients 0 through 7. When loading configuration or select registers, the interface will expect one value after the address value. When loading round or limit registers, the interface will expect four values after the address value. Figures 9 and 10 show the data loading sequences for the coefficient banks and Configuration/control registers. Both PAUSEA and PAUSEB allow the user to effectively slow the rate of data loading through the LF InterfaceTM. When PAUSEA is HIGH, the LF InterfaceTM affecting the data used for Filter A is held until PAUSEA is returned to a LOW. When PAUSEB is HIGH, the LF InterfaceTM affecting the data used for Filter B is held until PAUSEB is returned to a LOW. Figures 11 through 14 display the effects of both PAUSEA and PAUSEB while loading coefficient and control data. Table 15 shows an example of loading data into the coefficient banks. The following data values are written into address 10 of coefficient banks 0 through 7: 210H, 543H, C76H, 9E3H, 701H, 832H, F20H, 143H. Table 16 shows an example of loading data into a Configuration Register. Data value 003H is written into Configuration Register 4. Table 17 shows an example of loading data into a round register. Data value 7683F4A2H is written into Filter A round register 12. Table 18 shows an example of loading data into a select register. Data value 00FH is loaded into Filter A select register 2. Figure 9. Coefficient Bank Loading Sequence COEFFICIENT SET 1 COEFFICIENT SET 2 COEFFICIENT SET 3 CLK W1 W2 W3 LDA/LDB CFA/CFB11-0 ADDR1 COEF0 COEF7 ADDR2 COEF0 COEF7 ADDR3 COEF0 COEF7 W1: Coefficient Set 1 written to coefficient banks during this clock cycle. W2: Coefficient Set 2 written to coefficient banks during this clock cycle. W3: Coefficient Set 3 written to coefficient banks during this clock cycle. Figure 10. Configurational/Control Register Loading Sequence CONFIG REG ROUND REGISTER SELECT REG LIMIT REGISTER CLK W1 W2 W3 W4 LDA/LDB CFA/CFB11-0 ADDR1 DATA1 ADDR2 DATA1 ADDR3 DATA1 DATA2 DATA3 DATA4 ADDR4 DATA1 DATA2 DATA3 DATA4 W1: Configuration Register loaded with new data on this rising clock edge. W2: Select Register loaded with new data on this rising clock edge. W3: Round Register loaded with new data on this rising clock edge. W4: Limit Register loaded with new data on this rising clock edge. LOGIC Devices Incorporated 12 Video Imaging Products Feb 5, 2003 LDS.3321-A LF3321 Horizontal Digital Image Filter DEVICES INCORPORATED Improved Performance Functional Description Figure 11. Coefficient Bank Loading Sequence with PAUSE Implementation COEFFICIENT SET 1 CLK W1 PAUSEA/PAUSEB LDA/LDB CFA/CFB11-0 ADDR1 COEF0 COEF1 COEF7 W1: Coefficient Set 1 written to coefficient banks during this clock cycle. Figure 12. Config and Select Register Loading Sequence w/ PAUSE Implementation SELECT REGISTER CONFIGURATION REGISTER CLK W1 W2 PAUSEA/PAUSEB LDA/LDB CFA/CFB11-0 ADDR1 DATA1 ADDR2 DATA1 W1: Configuration Register loaded with new data on this rising clock edge. W2: Select Register loaded with new data on this rising clock edge. Figure 13. Round Register Loading Sequence with PAUSE Implementation ROUND REGISTER CLK W1 PAUSEA/PAUSEB LDA/LDB CFA/CFB11-0 ADDR1 DATA1 DATA2 DATA3 DATA4 W1: Round Register loaded with new data on this rising clock edge. LOGIC Devices Incorporated 13 Video Imaging Products Feb 5, 2003 LDS.3321-A LF3321 Horizontal Digital Image Filter DEVICES INCORPORATED Improved Performance Functional Description Figure 14. Limit Register Loading Sequence with PAUSE Implementation LIMIT REGISTER CLK W1 PAUSEA/PAUSEB LDA/LDB CFA/CFB11-0 ADDR1 DATA1 DATA2 DATA3 DATA4 W1: Limit Register loaded with new data on this rising clock edge. LF Interface TM Continued Table 19 shows an example of loading data into Filter B limit register 7. Data value 3B60H is loaded as the lower limit and 72A4H is loaded as the upper limit. It takes 9S clock cycles to load S coefficient sets into the device. Therefore, it takes 2304 clock cycles to load all 256 coefficient sets. Assuming an 83 MHz clock rate, all 256 coefficient sets can be updated in less than 27.7 µs, which is well within vertical blanking time. It takes 5S clock cycles to load S round or limit registers. Therefore, it takes 320 clock cycles to update all round and limit registers (both Filters A and B). Assuming an 83 MHz clock rate, all Filter A and B round/limit registers can be updated in 3.84 µs. The coefficient banks and Configuration/Control registers are not loaded with data until all data values for the specified address are loaded into the LF InterfaceTM. In other words, the coefficient banks are not written to until all eight coefficients have been loaded into the LF InterfaceTM. A round register is not written to until all four data values are loaded. After the last data value is loaded, the interface will expect a new address value on the next clock cycle. After the next address value is loaded, data loading will begin again as previously discussed. As long as data is loaded into the interface, LDA must remain LOW. After all desired coefficient banks and Configuration/Control registers are loaded with data, the LF InterfaceTM must be disabled. This is done by setting LDA HIGH on the clock cycle after the clock cycle which latches the last data value. It is important that the LF InterfaceTM remain disabled when not loading data into it. The Filter A coefficient banks may only be loaded with the Filter A LF InterfaceTM and the Filter B coefficient banks may only be loaded with the Filter B LF InterfaceTM. The Configuration and Control registers may be loaded with either the Filter A or B LF InterfacesTM. Since both LF InterfacesTM operate independently of each other, both LF InterfacesTM can load data into their respective coefficient banks at the same time. Or, one LF InterfaceTM can load the Configuration/Control registers while the other loads it’s respective coefficient banks. If both LF InterfacesTM are used to load a Configuration or Control register at the same time, the Filter B LF InterfaceTM will be given priority over the Filter A LF InterfaceTM. For example, if the Filter A LF InterfaceTM attempts to load data into a configuration register at the same time that the Filter B LF InterfaceTM attempts to load a Filter A round register, the Filter B LF InterfaceTM will be allowed to load the round register while the Filter A LF InterfaceTM will not be allowed to load the configuration register. However, the Filter A LF InterfaceTM will continue to function as if the write occurred. LOGIC Devices Incorporated 14 Video Imaging Products Feb 5, 2003 LDS.3321-A LF3321 Horizontal Digital Image Filter DEVICES INCORPORATED Improved Performance Functional Description Table 15. Coefficient Bank Loading Format 1st Word - Address 2nd Word - Bank 0 3rd Word - Bank 1 4th Word - Bank 2 5th Word - Bank 3 6th Word - Bank 4 7th Word - Bank 5 8th Word - Bank 6 9th Word - Bank 7 CFA/B11 CFA/B10 CFA/B 9 CFA/B 8 CFA/B 7 CFA/B 6 CFA/B 5 CFA/B 4 CFA/B 3 CFA/B 2 CFA/B 1 CFA/B 0 0 0 0 0 0 0 0 0 1 0 1 0 0 0 1 0 0 0 0 1 0 0 0 0 0 1 0 1 0 1 0 0 0 0 1 1 1 1 0 0 0 1 1 1 0 1 1 0 1 0 0 1 1 1 1 0 0 0 1 1 0 1 1 1 0 0 0 0 0 0 0 1 1 0 0 0 0 0 1 1 0 0 1 0 1 1 1 1 0 0 1 0 0 0 0 0 0 0 0 1 0 1 0 0 0 0 1 1 Table 16. Configuration Register Loading Format 1st Word - Address 2nd Word - Data CFA/B11 CFA/B10 CFA/B 9 CFA/B 8 CFA/B 7 CFA/B 6 CFA/B 5 CFA/B 4 CFA/B 3 CFA/B 2 CFA/B 1 CFA/B 0 0 0 1 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 1 1 Table 17. Round Register Loading Format 1st Word - Address 2nd Word - Data 3rd Word - Data 4th Word - Data 5th Word - Data CFA/B11 CFA/B10 CFA/B 9 CFA/B 8 CFA/B 7 CFA/B 6 CFA/B 5 CFA/B 4 CFA/B 3 CFA/B 2 CFA/B 1 CFA/B 0 1 0 0 0 0 0 0 0 1 1 0 0 R R R R 0 1 0 1 0 0 1 0* R R R R 1 1 1 1 0 1 0 0 R R R R 1 0 0 0 0 0 1 1 R R R R 0 ** 1 1 1 0 1 1 0 Table 18. Select Register Loading Format 1st Word - Address 2nd Word - Data CFA/B11 CFA/B10 CFA/B 9 CFA/B 8 CFA/B 7 CFA/B 6 CFA/B 5 CFA/B 4 CFA/B 3 CFA/B 2 CFA/B 1 CFA/B 0 0 1 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 1 1 1 1 Table 19. Limit Register Loading Format 1st Word - Address 2nd Word - Data 3rd Word - Data 4th Word - Data 5th Word - Data CFA/B11 CFA/B10 CFA/B 9 CFA/B 8 CFA/B 7 CFA/B 6 CFA/B 5 CFA/B 4 CFA/B 3 CFA/B 2 CFA/B 1 CFA/B 0 1 1 1 0 0 0 0 0 0 1 1 1 R R R R 0 1 1 0 0 0 0 0 R R R R 0* 0 1 1 1 0 1 1 R R R R 1 0 1 0 0 1 0 0 R R R R 0 ** 1 1 1 0 0 1 0 R = Reserved. Must be set to “0“. * This bit represents the MSB of the Lower Limit. ** This bit represents the MSB of the Upper Limit. LOGIC Devices Incorporated 15 Video Imaging Products Feb 5, 2003 LDS.3321-A LF3321 Horizontal Digital Image Filter DEVICES INCORPORATED Improved Performance Operating Modes Single Filter Mode In this mode, the device operates as a single FIR filter (see Figure 15). It can be configured to have as many as 32 taps if symmetric coefficient sets are used. If asymmetric coefficient sets are used, the device can be configured to have as many as 16 taps. Cascade ports are provided to facilitate cascading multiple devices to increase the number of filter taps. Bit 1 in Configuration Register 5 determines the filter mode. In Single Filter Mode, DIN11-0 is the data input for the filter and DOUT15-0 is the data output for the filter. Figure 15. Single Filter Mode ROUT11-0 DIN11-0 12 12 12 I/D REGISTERS I/D REGISTERS FILTER A FILTER B 12 RIN11-0 COUT11-0 RSL CIRCUIT 16 DOUT15-0 Dual Filter Mode In this mode, the device operates as two separate FIR filters (see Figure 16). Each filter can be configured to have as many as 16 taps if symmetric coefficient sets are used. If asymmetric coefficient sets are used, each filter can be configured to have as many as 8 taps. In Dual Filter Mode, DIN11-0 is the data input for Filter A. Either RIN11-0 or DIN11-0 can be the data input for Filter B. The Filter B input is determined by Bit 2 in Configuration Register 5. DOUT15-0 is the data output for Filter A. COUT11-0 and ROUT3-0 together form the data output for Filter B. COUT11-0 is the twelve least significant bits and ROUT3-0 is the four most significant bits of the 16-bit Filter B output. Figure 16. Dual Filter Mode 12 DIN11-0 12 I/D REGISTERS I/D REGISTERS FILTER A FILTER B R.S.L. CIRCUIT 16 DOUT15-0 Matrix-vector Multiply Mode RIN11-0 R.S.L. CIRCUIT 16 ROUT3-0 / COUT11-0 In this mode, the LF3321 can be configured to multiply a square matrix of maximum size N (N = 8 or 16), multiplied by a matrix-vector of maximum size [8,1] or [16,1]. The mathematical representation for this operation is in Figure 18. When configured in the dual filter mode, the LF3321 can process two matrixvector multipliers simultaneously (i.e. [8x8][8x1]). In the single filter mode, the LF3321 can process a single matrix-vector multiply (i.e. [16x16][16x1]). This mode of operation allows the user to organize data values (e.g. pixels) into an array (e.g. blocks). This function is useful for any application requiring the operation of matrix multiplication; a function that is used when generating Discrete Cosine Transform coefficients (DCT) for the purpose of further processing. When configuring the LF3321 for an [8x8][8x1] matrix-vector operation, the coefficient banks will require 8 coefficient sets to be loaded into the coefficient memory banks; each coefficient set will have 8, 12-bit coefficients. The input data, [8x1] column-vector, will be loaded through DIN11-0 for Filter A; either RIN11-0 or DIN11-0 can be the data input for Filter B. Conversely, when configured for a [16x16][16x1] matrix-vector operation, the coefficient banks will require 16 coefficient sets to be loaded into the coefficient memory banks; each coefficient set will have 16, 12-bit coefficients. The input data, [16x1] column-vector, will be loaded through DIN11-0. LOGIC Devices Incorporated 16 Video Imaging Products Feb 5, 2003 LDS.3321-A LF3321 Horizontal Digital Image Filter DEVICES INCORPORATED Improved Performance Operating Modes Matrix-vector Multiply Mode Continued To configure the LF3321 for matrix-vector multiplication, bit 4 of Configuration Register 5 must be set to 1 (Table 7). The configuration for single filter mode or dual filter mode will still apply. Writing 012H or 016H to Configuration Register 5 will configure the device for dual filter mode, [8x8][8x1] matrix-vector multiplication. Subsequently, writing 014H to Configuration Register 5 will configure the device for single filter mode, [16x16][16x1] matrix-vector multiplication. Some functions of the LF3321 must be disabled when configured for matrix-vector multiplication. This will apply to both the single filter mode and the dual filter mode; these functions are data reversal and interleave/decimation. The LF3321 can be cascaded to realize larger matrices. Figure 17. Matrix-vector Multiply Mode N DIN11-0 RIN11-0 12 0 A ALU B 0 A ALU 0 0 B A ALU B A ALU B TXFRA TXFRB COEF (N-1) N COEF 2 COEF 1 COEF 0 12 12 12 12 Dual Filter Mode, N=8 Single FIlter Mode, N=16 32 Data reversal can be disabled by setting bit 6, of Configuration Register 1 (Filter A) and Configuration Register 3 (Filter B), both to 1. The Odd-Tap, interleave mode will need to be disabled. Writing a 0 to bit 0 of Configuration Register 1 and Configuration Register 3 will disable the odd-tap interleave mode for Filter A and Filter B. When data is not being interleaved or decimated, the I/D Register length should be set to a length of one (Table 3 and Table 5). Therefore, writing 040H to Configuration Register 1 and 3 will disable the data reversal and set the corresponding inherent characteristics for the desired matrix function. The Filter A ALU and Filter B ALU are to be configured for A+B (Table 2 and Table 4); so that condition A+0 is satisfied. To accomplish this, bit 0 is to be reset to 0, bit 1 is to be set to 1, and bit 2 is to be reset to 0. Writing 002H to Configuration Register 0 (Filter A) and Configuration Register 2 (Filter B) will set the corresponding registers to satisfy the A+0 condition. The timing diagrams in Figure 19 and 20 will assume that the Configuration Registers, the coefficient sets, and the first set of data values (data set) have been loaded. Loading input data for an [8x8][8x1] matrix operation requires 9 clock cycles and loading input data for a [16x16][16x1] matrix operation requires 17 clock cycles. When configured for an [8x8][8x1] matrix-vector operation, 8 data values are required for loading. When configured for a [16x16][16x1] matrix-vector operation, 16 data values are required for loading. Each data value is fed through the I/D Registers, using the corresponding input. Once the final data value, of the data set, has been loaded TXFRA/TXFRB should be brought LOW for one clock cycle to complete the loading. Once this occurs, the data set is then bank loaded into the respective registers ready to begin the matrix-vector multiplication operation. The current data set will not change until TXFRA/TXFRB is brought LOW again. To satisfy the matrix equation (see Figure 18), the current data set is held for the duration of the required matrix dimension while cycling through each coefficient set (CENA/CENB must be held LOW). During this time new data values can be loaded serially, ready for the next activation of TXFRA/TXFRB. To insure the correct evaluation of the matrix-vector multiplication equation, it is imperative that the coefficient values are paired with their corresponding data values. For the [8x8][8x1] matrix-vector configuration (dual filter mode), the first result will appear 19 clock cycles from the first data input, DIN15-0 (Filter A) and RIN15-0 (Filter B); device latency for the first result is 10 clock cycles (10+9 = 19). LOGIC Devices Incorporated 17 Video Imaging Products Feb 5, 2003 LDS.3321-A LF3321 Horizontal Digital Image Filter DEVICES INCORPORATED Improved Performance Operating Modes Matrix-vector Multiply Mode Continued The result will appear at the corresponding filter output, DOUT15-0 (Filter A) and ROUT3-0/COUT11-0 (Filter B). For the [16x16][16x1] matrix-vector configuration (single filter mode), the first result will appear 28 clock cycles from the first data input, DIN15-0; device latency for the first result is 11 clock cycles (11+17 = 28). The result will appear at the corresponding filter output, DOUT15-0. Subsequently, for both dual and single filter mode configurations, the sum of products will continue to appear every clock cycle thereafter until the matrix dimension has been realized. The total pipeline latency for a complete [8x8][8x1] matrixvector operation is 26 clock cycles and the total pipeline latency for a complete [16x16][16x1] matrix-vector operation is 43 clock cycles. Therefore, to process two square matrices simultaneoulsy, of size N=8, a total of 73 clock cycles are all that is required. Similarly, to process a single square matrix, of size N=16, a total of 283 clock cycles are required. Figure 18. Matrix Equation C = COEFFICIENTS D = DATA INPUT R = DATA OUTPUT R0 R1 R2 Ri = C00 C01 C02 C10 C11 C12 C20 C21 C22 C0j C1j C2j D0 D1 D2 Ci0 Cij Di Ci1 Ci2 (N-1) = Ri Cij Di i=0 For j=0,1,2,...,(N-1) N=8 or 16 Figure 19. Dual Filter, Matrix Multiply Timing Sequence Data Set 1 with 8 Coefficient Sets 1 2 3 8* Data Set 2 with 8 Coefficient Sets 9 10** 11 17*** 18 CLK DIN11-0 RIN11-0 DATA SET 1 DATA SET 0 CAA7-0 CAB7-0 CF00 CF01 CF02 CF07 CF10 CF11 CF12 CF17 CF20 CF21 TXFRA/ TXFRB DOUT15-0 ROUT3-0/COUT15-0 OUT0 OUT1 OUT7 OUT0 OUT1 CENA / CENB SHENA / SHENB * ** *** 8 Clocks - End of First Data/Coefficient Set 10 Clocks - First Output of First Data/Coefficient Set 17 Clocks - Final Output of First Data/Coefficient Set Once again, the timing diagrams (see Figure 19 and 20) will assume that the Configuration Registers, the coefficient sets, and the data values have been loaded. The corresponding timing diagram loading sequence for the coefficient banks and Configuration/Control registers are included in the LF3321 data sheets (Figure 9 and Figure 10 respectively). Further reference to timing diagram loading sequence for the RSL registers are also included in the device data sheet (Figure 14, Figure 13, and Figure 12). The Filter A and Filter B LF InterfaceTM are used to load data into the Filter A and Filter B Configuration Registers and coefficient banks. The Matrix Multiplication Mode is valid in the Double Wide Data/Coefficient Mode. However, there are some special considerations when this mode is desired. The LF3321 must be configured for single filter mode only, for a maximum (8x8) matrix. The user must disable the cascaded filter mode, the accumulator access mode, and the data reversal (see Table 7). LOGIC Devices Incorporated 18 Video Imaging Products Feb 5, 2003 LDS.3321-A LF3321 Horizontal Digital Image Filter DEVICES INCORPORATED Improved Performance Operating Modes Figure 20. Single Filter, Matrix Multiply Timing Sequence 1 Data Set with 16 Coefficient Sets 1 2 11* 3 12 13 14 15 CF0D CF0E 17 16** 26*** CLK DIN11-0 RIN11-0 DATA SET 0 DATA SET 0 CAA7-0 CAB7-0 CF00 CF01 CF02 CF0A CF0B CF0C CF10 CF0F TXFRA/ TXFRB DOUT15-0 OUT0 OUT1 OUT2 OUT3 OUT4 OUT5 OUT6 OUT15 CENA / CENB SHENA / SHENB * ** *** Double Wide Data/Coefficient Mode 11 Clocks - First Output of First Data/Coefficient Set 16 Clocks - End of First Data/Coefficient Set 26 Clocks - Final Output of First Data/Coefficient Set The LF3321 is capable of supporting 24-bit data and 12-bit coefficients or 12-bit data and 24-bit coefficients. When configured for this mode of operation, the Filter B output is scaled by 2-12 before adding it to the Filter A output. This mode of operation is only valid in single filter mode. To configure the LF3321 for this mode, bit 3 of Configuration Register 5 must be set to 1; this will account for the scaling function (Table 7). For 24-bit data, DIN11-0 becomes the MSB (Filter A) and RIN11-0 becomes the LSB (Filter B), bit 2 of Configuration Register 5 must be set to 0. To insure correct results, the coefficient sets must be aligned appropriately; that is to say, the coefficient set used for the MSB must be the same for the LSB. For 24-bit coefficients, the coefficient banks for Filter A will correspond to the coefficient MSB and the coefficient banks for Filter B will correspond to the coefficient LSB; therefore, bit 2 must be set to 1. Once again, to insure correct results, the coefficient sets must be aligned appropriately; that is to say, the MSB coefficients must correspond to their LSB coefficients. The output data will appear at DOUT15-0; output appearing at ROUT3-0/COUT11-0 will not be of any value. Bit 1 is set to 0 (for single filter mode) and bit 0 is set to 0 (cascade mode must be disabled). Therefore, to realize 24-bit data/12-bit coefficients the user must write 008H to Configuration Register 5; conversely, for 12-bit data/24-bit coefficients the user must write 00CH to Configuration Register 5. The Double Wide Data/Coefficient Mode is valid in the Matrix Multiplication Mode; however, special considerations must be observed when these two modes are combined. The LF3321 must be configured for single filter mode only, for a maximum (8x8) matrix. In addition, the user must disable the cascaded filter mode, the accumulator access mode, and the data reversal (Table 7). For additional considerations, refer to the corresponding mode of operation section. LOGIC Devices Incorporated 19 Video Imaging Products Feb 5, 2003 LDS.3321-A LF3321 Horizontal Digital Image Filter DEVICES INCORPORATED Improved Performance Operating Modes Figure 21. Double Wide Data Coefficient Mode DIN11-0 RIN11-0 12 I/D REGISTERS I/D REGISTERS FILTER A FILTER B 12 SCALE R.S.L. CIRCUIT 16 DOUT15-0 Accumulator Access Mode Accumulator access allows the user to accumulate the Filter A output with the Filter B output. Therefore, this mode is only valid when the device has been configured for dual filter operation. To configure the device for this mode, bit 1 and bit 5 must be set to 1; bit 5 is the corresponding accumulator access bit (Table 7). Writing 022H to Configuration Register 5 configures the device to accumulate the Filter A output with the Filter B output. All remaining Configuration Registers, 0 through 4 inclusive, will depend on specific application requirements (see Tables 2 through 4). In this mode of operation, the accumulated output is realized at DOUT15-0. The output data at ROUT15-0/COUT15-0 is the Filter B output that is normally expected; however, the accumulated output data (DOUT15-0) will be delayed by one clock cycle, compared to the Filter B output data. This type of operation is useful when two filtered data streams (i.e. I+jQ) need to be accumulated. Such is the requirement to satisfy the equation, y(t) = cos(vt)+jsin(vt). The complex data can be streamed and filtered using a respective ‘I’ filter and ‘Q’ filter. To convert the complex result into a real result, as seen at the LF3321 output, two multiplies and one accumulation is required. The cosine and sine functions are realized through the coefficient sets; consequently, multiplied by the corresponding ‘I’ and ‘Q’ data streams. To satisfy the remainder of the equation, Filter A and Filter B must be accumulated. As previously stated, this mode of operation is only valid with the dual filter mode configuration. All modes of operation, that are valid in the dual filter mode, are valid with the accumulator access mode. For additional considerations, refer to the corresponding mode of operation section. Figure 22. Accumulator Access Mode DIN11-0 12 I/D REGISTERS I/D REGISTERS FILTER A FILTER B R.S.L. CIRCUIT R.S.L. CIRCUIT 16 DOUT15-0 LOGIC Devices Incorporated 20 12 RIN11-0 16 ROUT3-0 / COUT11-0 Video Imaging Products Feb 5, 2003 LDS.3321-A LF3321 Horizontal Digital Image Filter DEVICES INCORPORATED Improved Performance Signal Definitions Power Vcc and GND +3.3 V power supply. All pins must be connected. Clock CLK — Master Clock The rising edge of CLK strobes all enabled registers. Inputs DIN11-0 — Data Input DIN11-0 is the 12-bit data input port to Filter A. In Dual Filter Mode, DIN11-0 can also be the 12-bit input port to Filter B. Data is latched on the rising edge of clock. RIN11-0 — Reverse Cascade Input In Single Filter Mode, RIN11-0 is the 12-bit reverse cascade input port. This port is connected to ROUT11-0 of another LF3321. In Dual Filter Mode, RIN11-0 can be the 12-bit input port to Filter B. Data is latched on the rising edge of CLK. CFA11-0 — Coefficient A Input CFA11-0 is used to load data into the Filter A coefficient banks (banks 0 through 7) and the configuration/ control registers. Data present on CFA11-0 is latched into the Filter A LF InterfaceTM on the rising edge of CLK when LDA is LOW (see the LF InterfaceTM section for a full discussion). CAA7-0 — Coefficient Address A CAA7-0 determines which row of data in coefficient banks 0 through 7 is fed to the multipliers. CAA7-0 is latched into Coefficient Address Register A on the rising edge of CLK when CENA is LOW. CFB11-0 — Coefficient B Input CFB11-0 is used to load data into the Filter B coefficient banks (banks 8 through 15) and the configuration/ control registers. Data present on CFB11-0 is latched into the Filter B LF InterfaceTM on the rising edge of CLK when LDB is LOW (see the LF InterfaceTM section for a full discussion). CAB7-0 — Coefficient Address B CAB7-0 determines which row of data in coefficient banks 8 through 15 is fed to the multipliers. CAB7-0 is latched into Coefficient Address Register B on the rising edge of CLK when CENB is LOW. Figure 23. Input Formats Input Data 11 10 9 –211 210 29 (Sign) Coefficient Data 2 1 0 22 21 20 11 10 9 –20 2–1 2–2 (Sign) 2 1 0 2–9 2–10 2–11 Figure 24. Accumulator Output Formats Accumulator A Output 31 30 29 –220 219 218 (Sign) LOGIC Devices Incorporated 2 1 0 2–9 2–10 2–11 21 Accumulator B Output 31 30 29 –220 219 218 (Sign) 2 1 0 2–9 2–10 2–11 Video Imaging Products Feb 5, 2003 LDS.3321-A LF3321 Horizontal Digital Image Filter DEVICES INCORPORATED Improved Performance Signal Definitions Table 20. Output Formats SLCT4-0 00000 00001 00010 · · · 01110 01111 10000 Outputs S15 F15 F16 F17 · · · F29 F30 F31 S14 F14 F15 F16 · · · F28 F29 F30 S13 F13 F14 F15 · · · F27 F28 F29 ··· ··· ··· ··· ··· ··· ··· S8 F8 F9 F10 · · · F22 F23 F24 S7 F7 F8 F9 · · · F21 F22 F23 ··· ··· ··· ··· ··· ··· ··· S2 F2 F3 F4 · · · F16 F17 F18 S1 F1 F2 F3 · · · F15 F16 F17 S0 F0 F1 F2 · · · F14 F15 F16 DOUT15-0 — Data Output DOUT15-0 is the 16-bit registered data output port for the overall filter (Single Filter Mode) or Filter A (Dual Filter Mode). COUT11-0 — Cascade Output In Single Filter Mode, COUT11-0 is a 12-bit registered cascade output port. COUT11-0 should be connected to DIN11-0 of another LF3321. In Dual Filter Mode, COUT11-0 is a 12-bit registered output port for the lower twelve bits of the 16-bit Filter B output. ROUT11-0 — Reverse Cascade Output In Single Filter Mode, ROUT11-0 is a 12-bit registered cascade output port. ROUT11-0 on one device should be connected to RIN11-0 of another LF3321. In Dual Filter Mode, ROUT3-0 is a 4-bit registered output port for the upper four bits of the 16-bit Filter B output. In this mode, ROUT11-4 is disabled. Controls LDA — Coefficient A Load When LDA is LOW, data on CFA11-0 is latched into the Filter A LF InterfaceTM on the rising edge of CLK. When LDA is HIGH, data is not loaded into the Filter A LF InterfaceTM. When enabling the LF InterfaceTM for data input, a HIGH to LOW transition of LDA is required in order for the input circuitry to function properly. Therefore, LDA must be set HIGH immediately after power up to ensure proper operation of the input circuitry (see the LF InterfaceTM section for a full discussion). CENA — Coefficient Address Enable A When CENA is LOW, data on CAA7-0 is latched into Coefficient Address Register A on the rising edge of CLK. When CENA is HIGH, data on CAA7-0 is not latched and the register’s contents will not be changed. LDB — Coefficient B Load When LDB is LOW, data on CFB11-0 is latched into the Filter B LF InterfaceTM on the rising edge of CLK. When LDB is HIGH, data is not loaded into the Filter B LF InterfaceTM. When enabling the LF InterfaceTM for data input, a HIGH to LOW transition of LDB is required in order for the input circuitry to function properly. Therefore, LDB must be set HIGH immediately after power up to ensure proper operation of the input circuitry (see the LF InterfaceTM section for a full discussion). LOGIC Devices Incorporated 22 Video Imaging Products Feb 5, 2003 LDS.3321-A LF3321 Horizontal Digital Image Filter DEVICES INCORPORATED Improved Performance Signal Definitions Controls Cont’d CENB — Coefficient Address Enable B When CENB is LOW, data on CAB7-0 is latched into Coefficient Address Register B on the rising edge of CLK. When CENB is HIGH, data on CAB7-0 is not latched and the register’s contents will not be changed. TXFRA — Filter A LIFO Transfer Control TXFRA is used to change which LIFO in the data reversal circuitry sends data to the reverse data path and which LIFO receives data from the forward data path in Filter A. When TXFRA goes LOW, the LIFO sending data to the reverse data path becomes the LIFO receiving data from the forward data path, and the LIFO receiving data from the forward data path becomes the LIFO sending data to the reverse data path. The device must see a HIGH to LOW transition of TXFRA in order to switch LIFOs. TXFRA is latched on the rising edge of CLK. TXFRB — Filter B LIFO Transfer Control TXFRB is used to change which LIFO in the data reversal circuitry sends data to the reverse data path and which LIFO receives data from the forward data path in Filter B. When TXFRB goes LOW, the LIFO sending data to the reverse data path becomes the LIFO receiving data from the forward data path, and the LIFO receiving data from the forward data path becomes the LIFO sending data to the reverse data path. The device must see a HIGH to LOW transition of TXFRB in order to switch LIFOs. TXFRB is latched on the rising edge of CLK. ACCA — Accumulator A Control When ACCA is HIGH, Accumulator A is enabled for accumulation and the Accumulator A Output Register is disabled for loading. When ACCA is LOW, no accumulation is performed and the Accumulator A Output Register is enabled for loading. ACCA is latched on the rising edge of CLK. ACCB — Accumulator B Control When ACCB is HIGH, Accumulator B is enabled for accumulation and the Accumulator B Output Register is disabled for loading. When ACCB is LOW, no accumulation is performed and the Accumulator B Output Register is enabled for loading. ACCB is latched on the rising edge of CLK. SHENA — Filter A Shift Enable In Dual Filter Mode, SHENA enables or disables the loading of data into the Input (DIN11-0) and Filter A I/D Registers. When SHENA is LOW, data is latched into the Input/Cascade Registers and shifted through the I/D Registers on the rising edge of CLK. When SHENA is HIGH, data can not be loaded into the Input/Cascade Registers or shifted through the I/D Registers and their contents will not be changed. In Single Filter Mode, SHENA also enables or disables the loading of data into the Reverse Cascade Input (RIN11-0), Cascade Output (COUT11-0), Reverse Cascade Output (ROUT11-0) and Filter B I/D Registers. It is important to note that in Single Filter Mode, both SHENA and SHENB should be connected together. Both must be active to enable data loading in Single Filter Mode. SHENA is latched on the rising edge of CLK. LOGIC Devices Incorporated 23 Video Imaging Products Feb 5, 2003 LDS.3321-A LF3321 Horizontal Digital Image Filter DEVICES INCORPORATED Improved Performance Signal Definition Controls Cont’d SHENB — Filter B Shift Enable In Dual Filter Mode, SHENB enables or disables the loading of data into the Reverse Cascade Input (RIN11-0), Cascade Output (COUT11-0), Reverse Cascade Output (ROUT3-0) and Filter B I/D Registers. When SHENB is LOW, data is latched into the Cascade Registers and shifted through the I/D Registers on the rising edge of CLK. When SHENB is HIGH, data can not be loaded into the Cascade Registers or shifted through the I/D Registers and their contents will not be changed. In Single Filter Mode, SHENB also enables or disables the loading of data into the Input (DIN11-0), Reverse Cascade Output (ROUT11-0) and Filter A I/D Registers. It is important to note that in Single Filter Mode, both SHENA and SHENB should be connected together. Both must be active to enable data loading in Single Filter Mode. SHENB is latched on the rising edge of CLK. RSLA3-0 — Filter A Round/Select/Limit Control RSLA3-0 determines which of the sixteen user-programmable Round/Select/Limit registers (RSL registers) are used in the Filter A RSL circuitry. A value of 0 on RSLA3-0 selects RSL register 0. A value of 1 selects RSL register 1 and so on. RSLA3-0 is latched on the rising edge of CLK (see the round, select, and limit sections for a complete discussion). RSLB3-0 — Filter B Round/Select/Limit Control RSLB3-0 determines which of the sixteen user-programmable RSL registers are used in the Filter B RSL circuitry. A value of 0 on RSLB3-0 selects RSL register 0. A value of 1 selects RSL register 1 and so on. RSLB3-0 is latched on the rising edge of CLK (see the round, select, and limit sections for a complete discussion). OED — DOUT Output Enable When OED is LOW, DOUT15-0 is enabled for output. When OED is HIGH, DOUT15-0 is placed in a high-impedance state. OEC — COUT/ROUT Output Enable When OEC is LOW, COUT11-0 and ROUT3-0 are enabled for output. When OEC is HIGH, COUT11-0 and ROUT3-0 are placed in a high-impedance state. PAUSEA — LF InterfaceTM Pause When PAUSEA is HIGH, the Filter A LF InterfaceTM loading sequence is halted until PAUSEA is returned to a LOW state. This effectively allows the user to load coefficients and control registers at a slower rate than the master clock (see the LF InterfaceTM section for a full discussion). PAUSEB — LF InterfaceTM Pause When PAUSEB is HIGH, the Filter B LF InterfaceTM loading sequence is halted until PAUSEB is returned to a LOW state. This effectively allows the user to load coefficients and control registers at a slower rate than the master clock (see the LF InterfaceTM section for a full discussion). LOGIC Devices Incorporated 24 Video Imaging Products Feb 5, 2003 LDS.3321-A LF3321 Horizontal Digital Image Filter DEVICES INCORPORATED Improved Performance Specifications Maximum Ratings - Above which useful life may be impaired (Notes 1,2,3,8) Storage temperature .......................................................................................... –65°C to +150°C Operating ambient temperature ......................................................................... –55°C to +125°C VCCO supply voltage with respect to ground ........................................................ –0.5 V to +4.5 V Input signal with respect to ground ........................................................................ –0.5 V to 5.5 V Signal applied to high impedance output ............................................................... –0.5 V to 5.5 V Output current into low outputs ........................................................................................... 25 mA Latchup current .............................................................................................................. > 400 mA ESD Classification (MIL-STD-883E METHOD 3015.7) ..................................................... Class 3 Operating Conditions - To meet specified electrical and switching characteristics Mode Active Operation, Commercial Active Operation, Military Temperature Range (Ambient) 0°C to +70°C -55°C to +125°C Supply Voltage 3.00 V < VCCO < 3.60 V 3.00 V < VCCO < 3.60 V Electrical Characteristics - Over Operating Conditions (Note 4) Symbol Parameter VOH VOL VIH VIL I IX I OZ I CC1 I CC2 C IN C OUT Output High Voltage Output Low Voltage Input High Voltage Input Low Voltage Input Current Output Leakage Current VCC Current, Dynamic VCC Current, Quiescent Input Capacitance Output Capacitance Test Condition Switching Waveforms: 1 Min Typ VCC = Min., IOH = -4 mA VCC = Min., IOL = 8.0 mA Max Unit 2.4 0.4 5.5 0.8 +10 +10 250 2 10 10 2.0 0.0 (Note 3) Ground < VIN < VCC (Note 12) Ground < VOUT < VCC (Note 12) (Notes 5, 6) (Note 7) TA = 25°C, f = 1 MHz TA = 25°C, f = 1 MHz V V V V µA µA mA mA pF pF Data I/O 2 3 4 5 6 7 CLK DIN11-0 RIN11-0 ACA8-0 BCA8-0 CONTROLS (Except OED & OEC) OED OEC tS tH DIN/RINN tSCC tHCC CAA/CABN tSCT tPWH DIN/RINN+1 CAA/CABN+1 tHCT tDIS tENA HIGH IMPEDANCE DOUT15-0 tDIS 25 tD OUTPUTN-1 tENA HIGH IMPEDANCE ROUT11-0/COUT11-0 LOGIC Devices Incorporated tPWL tCYC OUTPUTN tDCC OUTPUTN-1 OUTPUTN Video Imaging Products Feb 5, 2003 LDS.3321-A LF3321 Horizontal Digital Image Filter DEVICES INCORPORATED Improved Performance Notes 1. Maximum Ratings indicate stress specifications only. Functional operation of these products at values beyond those indicated in the Operating Conditions table is not implied. Exposure to maximum rating conditions for extended periods may affect reliability. 2. The products described by this specification include internal circuitry designed to protect the chip from damaging substrate injection currents and accumulations of static charge. Nevertheless, conventional precautions should be observed during storage, handling, and use of these circuits in order to avoid exposure to excessive electrical stress values. 3. This device provides hard clamping of transient undershoot. Input levels below ground will be clamped beginning at –0.6 V. The device can withstand indefinite operation with inputs or outputs in the range of –0.5V to +5.5V. Device operation will not be adversely affected, however, input current levels will be well in excess of 100 mA. 4. Actual test conditions may vary from those designated but operation is guaranteed as specified. 5. Supply current for a given application can be accurately approximated by: where NCV2 F 4 N C V F = total number of device outputs = capacitive load per output = supply voltage = clock frequency 6. Tested with outputs changing every cycle and no load, at a 40 MHz clock rate. 7. Tested with all inputs within 0.1 V of VCC or Ground, no load. 8. These parameters are guaranteed but not 100% tested. 9. AC specifications are tested with input transition times less than 3ns, output reference levels of 1.5V (except tDIS test), and input levels of nominally 0 to 3.0V. Output loading may be a resistive divider which provides for specified IOH and IOL at an output voltage of VOH min and VOL max respectively. Alternatively, a diode bridge with upper and lower current sources of IOH and IOL respectively, and a balancing voltage of 1.5V may be used. Parasitic capacitance is 30 pF minimum, and may be distributed. This device has high-speed outputs capable of large instantaneous current pulses and fast turn-on/turn-off times. As a result, care must be exercised in the testing of this device. The following measures are recommended: a. A 0.1 µF ceramic capacitor should be installed between VCC and Ground leads as close to the Device Under Test (DUT) as possible. Similar capacitors should be installed between device VCC and the tester common, and device ground and tester common. b. Ground and VCC supply planes must be brought directly to the DUT socket or contactor fingers. c. Input voltages on a test fixture should be adjusted to compensate for inductive ground and VCC noise to maintain required DUT input levels relative to the DUT ground pin. 10. Each parameter is shown as a minimum or maximum value. Input requirements are specified from the point of view of the external system driving the chip. Setup time, for example, is specified as a minimum since the external system must supply at least that much time to meet the worst-case requirements of all parts. Responses from the internal circuitry are specified from the point of view of the device. Output delay, for example, is specified as a maximum since worst-case operation of any device always provides data within that time. LOGIC Devices Incorporated 26 Video Imaging Products Feb 5, 2003 LDS.3321-A LF3321 Horizontal Digital Image Filter DEVICES INCORPORATED Improved Performance Notes 11. For the tENA test, the transition is measured to the 1.5V crossing point with datasheet loads. For the tDIS test, the transition is measured to the ±200mV level from the measured steady-state output voltage with ±10mA loads. The balancing voltage, VTH, is set at 3.0 V for Z-to-0 and 0-to-Z tests, and set at 0 V for Z-to-1 and 1-to-Z tests. 12. These parameters are only tested at the high temperature extreme, which is the worst case for leakage current. Figure A. Output Loading Circuit Figure B. Threshold Levels tENA OE S1 DUT IOL Z 0 tDIS 1.5 V 1.5 V 1.5 V VTH CL IOH Z 1 1.5 V 3.0V Vth VOL* VOH* 0.2 V 0.2 V 0 Z 1 Z 0V Vth VOL* Measured VOL with IOH = –10mA and IOL = 10mA VOH* Measured VOH with IOH = –10mA and IOL = 10mA LOGIC Devices Incorporated 27 Video Imaging Products Feb 5, 2003 LDS.3321-A LF3321 Horizontal Digital Image Filter DEVICES INCORPORATED Improved Performance 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 Top View 144-pin 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 GND COUT11 COUT10 COUT9 COUT8 COUT7 COUT6 COUT5 COUT4 COUT3 COUT2 COUT1 COUT0 GND VCC CENB CAB7 CAB6 CAB5 CAB4 CAB3 CAB2 CAB1 CAB0 CFB11 CFB10 CFB9 CFB8 CFB7 CFB6 CFB5 CFB4 CFB3 CFB2 CFB1 CFB0 LDA PAUSEA ACCA RSLA3 RSLA2 RSLA1 RSLA0 VCC GND DOUT15 DOUT14 DOUT13 DOUT12 DOUT11 DOUT10 DOUT9 DOUT8 GND OED DOUT7 DOUT6 DOUT5 DOUT4 DOUT3 DOUT2 DOUT1 DOUT0 GND VCC RSLB0 RSLB1 RSLB2 RSLB3 ACCB PAUSEB LDB 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 VCC DIN11 DIN10 DIN9 DIN8 DIN7 DIN6 DIN5 DIN4 DIN3 DIN2 DIN1 DIN0 GND VCC CENA CAA7 CAA6 CAA5 CAA4 CAA3 CAA2 CAA1 CAA0 CFA11 CFA10 CFA9 CFA8 CFA7 CFA6 CFA5 CFA4 CFA3 CFA2 CFA1 CFA0 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 GND ROUT11 ROUT10 ROUT9 ROUT8 ROUT7 ROUT6 ROUT5 ROUT4 ROUT3 ROUT2 ROUT1 ROUT0 GND VCC SHENA TXFRA GND CLK VCC TXFRB SHENB RIN0 RIN1 RIN2 RIN3 RIN4 RIN5 RIN6 RIN7 RIN8 RIN9 RIN10 RIN11 OEC VCC Package and Ordering Information Plastic Quad Flatpack (Q5) 0°C to 70°C--Commercial Screening Speed 9 ns LOGIC Devices Incorporated LF3321QC9 28 Video Imaging Products Feb 5, 2003 LDS.3321-A