DA9188.002 23 February 2005 MAS9188 12 × 8-Bit D to A Converter • • • • 3-Pin Serial Data Interface Low Voltage Output Buffer Replaces 12 Potentiometers Individually Programmable Outputs • Fully Operational Down to 1.2 V DESCRIPTION MAS9188 is 12-channel 8-bit DAC, designed primarily for trimmer replacement. The device is controlled by a simple 3-line input. The DAC is selected with the four first bits in the serial input data (SDI-pin) and the DAC output value is set according to the last 8 bits in the serial input data. FEATURES APPLICATIONS • • • • • • • • • • Twelve 8-Bit DACs on a Single Monolithic Chip Voltage Level Output TSSOP-20 Package Single, Low +1.2 V Supply Power-On Reset Functionally and Pin Compatible with AD8802/AD8804 High Resolution Monitors Automatic Gain Control Trimmer Replacement Portable and Battery-Operated Equipment BLOCK DIAGRAM SDI CLK 12-bit Shift Register 8-bit data 8-BIT DAC O12 8-BIT DAC O10 O11 8-BIT DAC O9 8-BIT DAC 8-BIT DAC XCS O7 8-BIT DAC Address Decoder 8-BIT DAC 8-BIT DAC 8-BIT DAC VDD O4 O3 8-BIT DAC VREFHVREFL O6 O5 8-BIT DAC 8-BIT DAC O8 O2 O1 GND 1 (10) DA9188.002 23 February 2005 PIN CONFIGURATION 20 VDD VREFH 1 20 VDD O1 2 19 XRESET O1 2 19 O12 O2 3 18 O12 O2 3 18 O11 O3 4 17 O11 O3 4 17 O10 O4 5 16 O10 O4 5 16 O9 O5 6 15 O9 O5 6 15 O6 7 O8 14 O8 O6 7 14 O7 XSHDN 8 13 O7 XSHDN 8 13 SDI XCS 9 12 SDI XCS 9 12 CLK GND 10 11 CLK GND 10 11 VREFL MAS9188A2 YYWW 1 MAS9188A1 YYWW VREFH Top view YYWW = year, week PIN DESCRIPTION Pin Number MAS9188 A1 MAS9188 A2 Function 1 VREFH VREFH DAC output reference high voltage 2 O1 O1 DAC 1, address 0x0 3 O2 O2 DAC 2, address 0x1 4 O3 O3 DAC 3, address 0x2 5 O4 O4 DAC 4, address 0x3 6 O5 O5 DAC 5, address 0x4 7 O6 O6 DAC 6, address 0x5 8 XSHDN XSHDN Device analog part power-down signal (active low) 9 XCS XCS Device enable signal (rising edge loads data to DAC) 10 GND GND Device ground-pin 11 CLK VREFL Data clock / DAC output low reference voltage 12 SDI CLK Serial input data / Data clock 13 O7 SDI DAC 7, address 0x6 / Serial input data 14 O8 O7 DAC 8, address 0x7 / DAC 7, address 0x6 15 O9 O8 DAC 9, address 0x8 / DAC 8, address 0x7 16 O10 O9 DAC 10, address 0x9 / DAC 9, address 0x8 17 O11 O10 DAC 11, address 0xA / DAC 10, address 0x9 18 O12 O11 DAC 12, address 0xB / DAC 11, address 0xA 19 XRESET O12 Device Digital part reset – middle code preset pin / DAC 12, address 0xB 20 VDD VDD Device power supply pin MAS9188 has two bonding options available: • • MAS9188A1, where VREFL pin is bonded to GND pin and XRESET pin can be used MAS9188A2, where XRESET pin is bonded to VDD pin and VREFL pin can be used 2 (10) DA9188.002 23 February 2005 ABSOLUTE MAXIMUM RATINGS Parameter Symbol Min Max Unit -0.3 6.0 V Input Voltage Range (any other pin) -0.3 VDD + 0.3 V Operating Temperature Range -40 +85 °C Storage Temperature Range -65 +150 °C Min Typ Max Unit 1.2 -40 3.6 5.5 +85 V Power Supply (VDD to GND) Conditions VDD RECOMMENDED OPERATION CONDITIONS Parameter Supply Voltage Range Operating Temperature Range Symbol Conditions VDD Temp °C ELECTRICAL CHARACTERISTICS DC Parameters ◆ Digital Inputs VDD = 2.4…5.5 V, VREFH = VDD, VREFL = 0 V, -40°C ≤ TA ≤ +85°C unless otherwise noted Parameter Symbol DAC Resolution Conditions Min N Typ Max 8 Unit Bits DAC Differential Nonlinearity Error DNL -1 +1 LSB DAC Integral Nonlinearity Error INL -1 +1 LSB DAC Full-scale Error GFSE -1 +1 LSB DAC Zero Code Error BZSE -1 +1 LSB DAC Output Resistance ROUT 3 8 kΩ ◆ Reference Input 5 VDD = 2.4…5.5 V, VREFH = VDD, VREFL = 0 V, -40°C ≤ TA ≤ +85°C unless otherwise noted Parameter Symbol Conditions Min REFH Voltage Range VREFH VREFH > VREFL 0 VDD REFL Voltage Range (MAS9188A2 only) VREFL VREFH > VREFL 0 VDD REFH Input Resistance RREFH REFL Input Resistance ROUT Matching (∆ROUT/ROUT) 0.5 Typ Max Unit 1.1 kΩ RREFL 1.1 kΩ RMATCH 0.4 2 % 3 (10) DA9188.002 23 February 2005 ◆ Digital Input Parameter VDD = 2.4…5.5 V, VREFH = VDD, VREFL = 0 V, -40°C ≤ TA ≤ +85°C unless otherwise noted Symbol Conditions Min Typ Max Digital Logic High VIH Digital Logic Low VIL 0.3 × VDD Digital Input Current IIL ±1 0.7 × VDD ◆ Power Supplies Parameter Unit µA VDD = 2.4…5.5 V, VREFH = VDD, VREFL = 0 V, -40°C ≤ TA ≤ +85°C unless otherwise noted Symbol Conditions Min Typ Unit 5.5 V Power Supply Range VDD Supply Current IDD 0.01 5 µA ISHDN 0.01 5 µA Shutdown Current 1.2 Max AC Parameters ◆ AC Characteristics Dynamic Performance VDD = 2.4…5.5 V, VREFH = VDD, VREFL = 0 V, -40°C ≤ TA ≤ +85°C unless otherwise noted Parameter Symbol Conditions Power Supply Sensitivity ∆VOUT ∆VDD ∆VDD = 1.1 × VDD – 0.9 × VDD Power Supply Sensitivity (100 Hz) Min Typ Max Unit 0.12 % PSRR 65 dB Vout Settling time (±1/2 LSB error band) TS 5 µs Crosstalk between adjacent outputs CT 50 dB Switching Characteristics VDD = 3.6 V, VREFH = VDD, VREFL = 0 V, TA = +25°C unless otherwise noted Parameter Symbol Conditions Min Typ Max Unit Input Clock High Pulse Width TCH 17 ns Input Clock Low Pulse Width TCL 8 ns Data Setup Time TDS -7 ns Data Hold Time TDH 24 ns XCS Fall to First Clock Pulse Fall TCLCL 18 ns XCS High Pulse Width TCSW 10 ns CLK Rise to XCS Rise Hold Time TCSH 22 ns XCS Rise to CLOCK Rise Setup TCS1 7 ns RESET Pulse Width TRS 18 ns 4 (10) DA9188.002 23 February 2005 OPERATING MODES DAC maximum output voltage is set using VREFH and VREFL pins (= 255/256 * (VREFH-VREFL)+VREFL) (note: VREFL = GND in case of MAS9188A1). The XRESET pin is used for middle code preset: DAC registers are reset and middle code will appear at the DAC output. Serial input data is written to SDI while XCS is low. Data is read at CLK rising edge to on-chip shift register. Rising XCS-pin reads data and 12 CLK-cycles are used as the input data (4 address bits and 8 data bits). The last 12 bits before rising XCS are used as input data. ◆ Timing diagram SDI A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0 CLK XCS DAC Register Load VOUT APPLICATION AND TEST CIRCUIT INFORMATION +3.0v 20 VDD Power On/Off 1 VREFH MAS9188A2 8 XSHDN O12 Controller Clock Data In Chip Select 12 13 O11 CLK O10 O9 SDI O8 9 O7 XCS O6 16 15 14 7 O4 5 O1 10 17 6 O2 GND 18 O5 O3 100 nF 19 4 3 2 VREFL 11 5 (10) DA9188.002 23 February 2005 PACKAGE (TSSOP-20) OUTLINES e/ 2 A VIEW B-B b E E1 c1 12° REF c S R b1 INDEX AREA GAUGE PLANE e A L 0.25 12° REF L1 D A A2 b B B A1 VIEW A-A b Symbol Min Nom Max Unit A A1 A2 b b1 c c1 D E E1 e L L1 R S -0.05 0.85 0.19 0.19 0.09 0.09 6.40 --0.90 -0.22 --6.50 6.4 BSC 4.40 0.65 BSC 0.60 1.00 REF -0.20 1.10 0.15 0.95 0.30 0.25 0.20 0.16 6.60 0.75 mm mm mm mm mm mm mm mm mm mm mm mm --- mm mm 4.30 0.50 0.09 -- 4.50 Dimensions do not include mold or interlead flash, protrusions or gate burrs. Reference Standard : JEDEC MO-153 . 6 (10) DA9188.002 23 February 2005 SOLDERING INFORMATION ◆ For For Eutectic Sn/Pb TSSOP-20 Resistance to Soldering Heat Maximum Temperature Maximum Number of Reflow Cycles Reflow profile According to RSH test IEC 68-2-58/20 2*220°C 240°C 3 Thermal profile parameters stated in JESD22-A113 should not be exceeded. http://www.jedec.org max 0.08 mm Solder plate 7.62 - 25.4 µm, material Sn 85% Pb 15% Seating Plane Co-planarity Lead Finish ◆ For Green (Pb Free, RoHS Compliant) TSSOP-20 Resistance to Soldering Heat Maximum Temperature Maximum Number of Reflow Cycles Reflow profile According to RSH test IEC 68-2-58/20 260°C 3 Thermal profile parameters stated in IPC/JEDEC J-STD-020 should not be exceeded. http://www.jedec.org max 0.08 mm Solder plate 7.62 - 25.4 µm, material Matte Tin Seating Plane Co-planarity Lead Finish EMBOSSED TAPE SPECIFICATIONS PO P2 P1 DO X E F W X AO User Direction of Feed T Section X-X Pin1 BO KO 7 (10) DA9188.002 23 February 2005 Dimension Min/Max Unit Ao Bo Do E F Ko Po P1 P2 T W 6.70 ±0.10 6.90 ±0.10 1.50 +0.1/-0.0 1.75 7.50 ±0.10 1.30 ±0.10 4.0 12.0 ±0.10 2.0 ±0.05 0.3 ±0.05 16.00 +0.30/-0.10 mm mm mm mm mm mm mm mm mm mm mm 8 (10) DA9188.002 23 February 2005 REEL SPECIFICATIONS W3 W2 A D N C W1 B • • • • 2500 Components on Each Reel Reel Material: Conductive, Plastic Antistatic or Static Dissipative Carrier Tape Material: Conductive Cover Tape Material: Static Dissipative Carrier Tape Cover Tape End Start Trailer Dimension A B C D N W1 (measured at hub) W2 (measured at hub) Trailer Leader Weight Components Min 1.5 12.80 20.2 50 16.4 Leader Max Unit 330 mm mm mm mm mm mm mm mm mm 13.50 18.4 22.4 160 390, of which minimum 160 mm of empty carrier tape sealed with cover tape 1500 g 9 (10) DA9188.002 23 February 2005 ORDERING INFORMATION Product Code Product Package Comments MAS9188AUA1 MAS9188AUA2 MAS9188A1UC06 12 x 8-bit D to A Converter 12 x 8-bit D to A Converter 12 x 8-bit D to A Converter 0 V Reference Level Adjustable Reference Level 0 V Reference Level MAS9188A2UC06 12 x 8-bit D to A Converter TSSOP-20 TSSOP-20 TSSOP-20 Pb free, RoHS compliant TSSOP-20 Pb free, RoHS compliant Adjustable Reference Level LOCAL DISTRIBUTOR MICRO ANALOG SYSTEMS OY CONTACTS Micro Analog Systems Oy Kamreerintie 2, P.O.Box 51 FIN-02771 Espoo, FINLAND Tel. +358 9 80 521 Fax +358 9 805 3213 http://www.mas-oy.com NOTICE Micro Analog Systems Oy reserves the right to make changes to the products contained in this data sheet in order to improve the design or performance and to supply the best possible products. Micro Analog Systems Oy assumes no responsibility for the use of any circuits shown in this data sheet, conveys no license under any patent or other rights unless otherwise specified in this data sheet, and makes no claim that the circuits are free from patent infringement. Applications for any devices shown in this data sheet are for illustration only and Micro Analog Systems Oy makes no claim or warranty that such applications will be suitable for the use specified without further testing or modification. 10 (10)