MX23J25640 256M-BIT NAND INTERFACE XtraROMTM FEATURES • Word organization - (33,554,432 + 2,097,152Note) by 8 bits • Page size - (512 + 16Note) by 8 bits • Block size - (16,384 + 512Note) by 8 bits Note : Underlined parts are redundancy and fixed to all FFH. • Operation mode - READ mode (1), READ mode (2), READ mode (3), RESET • Operating supply voltage : VCC = 2.7~3.6V • Access Time - Memory cell array to starting address : 7 us (MAX.) - Read cycle time : 50 ns (MAX.) - RE access time : 35 ns (MAX.) • Operating supply current - During read : 30 mA (MAX.) (50 ns cycle operation) - During standby (CMOS) : 40 uA (MAX.) • Package Type - 48-pin TSOP(I) (12mmx20mm) • XtraROM TM: factory pre-programmed ROM with Macronix NBitTM technology, supporting short TAT • Process - 0.15um PIN CONFIGURATIONS PIN DESCRIPTION 48 TSOP NC NC NC NC NC GND RB RE CE NC NC VCC VSS NC NC CLE ALE WE NC NC NC NC NC NC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 MX23J25640 (Normal Type) 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 NC NC NC NC I/O7 I/O6 I/O5 I/O4 NC NC NC VCC GND NC NC NC I/O3 I/O2 I/O1 I/O0 NC NC NC NC SYMBOL PIN NAME I/O0~I/O7 Address Input/Command Inputs/ Data Outputs CLE Command Latch Enable ALE Address Latch Enable WE Write Enable RE Read Enable CE Chip Enable RB READY, /BUSY pin VCC Supply Voltage NC No Connection GND Ground ORDER INFORMATION Part No. MX23J25640TC-50G MX23J25640TC-50 MX23J25640TI-50G Package 48 pin TSOP (Pb-free, RoHS) 48 pin TSOP 48 pin TSOP (Pb-free, RoHS) P/N:PM1137 Grade Commercial Commercial Industrial REV. 1.2, OCT. 28, 2005 1 MX23J25640 BLOCK DIAGRAM Data Register Circuit I/O0 I/O3 I/O4 I/O5 I/O6 I/O7 Sense Amplifier Address Register Y-Selector Command Register CLE ALE WE Control Logic CE READ Contorol Circuit X-Decoder I/O2 Input/Output Buffer I/O1 Memory Cell Matrix RE READY/BUSY Control Circuit VCC RB (Open-drain) P/N:PM1137 REV. 1.2, OCT. 28, 2005 2 MX23J25640 MEMORY MAP 1 Page=528 Bytes 0 0 1 2 1 Block =32 Pages . . 30 31 . . . . . . . . . 65,533 65,534 65,535 . . . 255 256 . (A) . (B) 512 Bytes (Main memory) • . 511 . 527 (C) 2,048 Blocks =65,536 Pages 16 Bytes (Redundancy) The start address (SA) during read operation is specified divided into three areas using three types of read commands. - In read mode (1), start address (SA) is set in area (A). - In read mode (2), start address (SA) is set in area (B). - In read mode (3), start address (SA) is set in area (C). One page consists of a total of 528 bytes broken down into 512 bytes (main memory) and 16 bytes (redundancy). One block consists of 32 pages. Caution The data of area (C) is redundancy, which is not programmable and is fixed to all FFH. P/N:PM1137 REV. 1.2, OCT. 28, 2005 3 MX23J25640 Operation Modes Command input, address input, and serial read are all performed from I/O pins, and the respective statuses are controlled by the CLE, ALE, WE, RE, and CE signals. Command input cycle Address input cycle Serial read cycle CLE CE WE ALE RE I/O0~ I/O7 RB Busy Operation mode Mode Command input cycle Address input cycle Serial read cycle CLE H L L ALE L H L CE L L L WE H ALE L L L CE L L H WE H H H RE H H Operation mode during serial read Mode Data output Output Hi-Z Standby CLE L L L RE L H x I/O0 - I/O7 Data output Hi-Z Hi-Z Remark ´ : VIH or VIL P/N:PM1137 REV. 1.2, OCT. 28, 2005 4 MX23J25640 Operation Commands The following six operation settings are possible by inputting commands from I/O pins. Command Hex I/O7 I/O6 I/O5 I/O4 I/O3 I/O2 I/O1 I/O0 Command receivable during Busy Read mode(1) 00 L L L L L L L L 01 L L L L L L L H Read mode(3) 50 L H L H L L L L Reset Note2 FF H H H H H H H H Read mode(2) Note1 Notes: 1. The data output in read mode (3) is all FFH. 2. The only command that can be executed when the device is Busy is the reset command. Do not set any of the other commands while the device is Busy. I/O Pin Correspondence Table during Address Input Cycle (Address Setting) (1) When 00H or 01H command is set [Read mode (1), Read mode (2)] Command I/O7 I/O6 I/O5 I/O4 I/O3 I/O2 I/O1 I/O0 1st address cycle A7 A6 A5 A4 A3 A2 A1 A0 2nd address cycle A16 A15 A14 A13 A12 A11 A10 A9 3rd address cycle A24 A23 A22 A21 A20 A19 A18 A17 (2) When 50H command is set [Read mode (3)] Command I/O7 I/O6 I/O5 I/O4 I/O3 I/O2 I/O1 I/O0 1st address cycle X X X X A3 A2 A1 A0 2nd address cycle A16 A15 A14 A13 A12 A11 A10 A9 3rd address cycle A24 A23 A22 A21 A20 A19 A18 A17 Remarks 1. A0 to A24 are internal addresses. 2. Internal address A8 is set internally with command 00H or 01H. 3. When 50H command is set [read mode (3)], the I/O4, I/O5, I/O6, and I/O7 inputs of the 1st address cycle are VIH or VIL. P/N:PM1137 REV. 1.2, OCT. 28, 2005 5 MX23J25640 Electrical Specifications Absolute Maximum Ratings Parameter Symbol Supply voltage Rating Unit VCC -0.5 to +4.6 V VI -0.3 to VCC+0.3 V VI/O -0.3 to VCC+0.3 (< 4.6) V TA -40 to 85 °C Tstg -65 to +150 °C Input voltage Input / Output voltage Operating ambient temperature Storage temperature Condition Caution Exposing the device to stress above those listed in Absolute Maximum Ratings could cause permanent damage. The device is not meant to be operated under conditions outside the limits described in the operational section of this specification. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability. Capacitance (TA = 25°° C) Parameter Symbol Input capacitance CI Output capacitance CO Test condition MIN. TYP. MAX. Unit 10 pF 10 pF f = 1 MHz DC Characteristics (TA = -40 to 85°° C, VCC = 2.7~3.6V) Parameter Symbol Test conditions MIN. TYP. MAX. Unit High level input voltage VIH 2.0 VCC+0.3 V Low level input voltage VIL -0.3 +0.8 V High level output voltage VOH IOH =-400uA Low level output voltage VOL IOL = 2.1 mA 0.4 V 2.4 V Input leakage current ILI VI = 0 V to VCC ±10 uA Output leakage current ILO VO = 0 V to VCC ±10 uA CE = VIL, IOUT =0 mA, 30 mA 40 uA Power supply current in read ICCO1 tCYCLE = 50 ns Standby current (CMOS) RB pin output current ICCS2 IOL(RB) CE = VCC-0.2 V VOL = 0.4 V P/N:PM1137 8 mA REV. 1.2, OCT. 28, 2005 6 MX23J25640 AC Characteristics (TA = -40 to 85°° C, VCC = 2.7~3.6V) Parameter Symbol MIN. CLE setup time tCLS 0 ns CLE hold time tCLH 10 ns CE setup time tCS 0 ns CE hold time tCH 10 ns Write pulse width tWP 25 ns ALE setup time tALS 0 ns ALE hold time tALH 10 ns Data setup time tDS 20 ns Data hold time tDH 10 ns Write cycle time tWC 50 ns WE high hold time tWH 15 ns Ready to RE falling edge tRR 20 ns Read pulse width tRP 35 ns Read cycle time tRC 50 ns RE access time (serial data access) tREA CE high hold time for last address in serial read cycle tCEH 100 RE high to output Hi-Z tRHZ 10 CE high to output Hi-Z tCHZ RE high hold time tREH 15 ns Output Hi-Z to RE falling edge tIR 0 ns WE high to RE low tWHR 30 ns Memory cell array to starting address tR 7 us WE high to Busy tWB 200 ns ALE low to RE low (read cycle) tAR2 RE last clock rising edge to Busy (in sequential read) tRB CE high to Ready (when interrupted by CE in read mode) tCRY Device reset time tRST TYP. MAX. 35 ns ns 30 ns 20 ns 50 Note Unit ns 200 ns 1 us 6 us Note :tCRY (time from CE to Ready) depends on the pull-up resister of the RB pin. P/N:PM1137 REV. 1.2, OCT. 28, 2005 7 MX23J25640 AC Test Conditions Input Waveform (Rise/Fall Time < 5ns) 1.5V Test points 1.5V 1.5V Test points 1.5V Output Waveform Input Pulse Levels : 0.4 ~ 2.4V Output Load : 1 TTL + 100pF P/N:PM1137 REV. 1.2, OCT. 28, 2005 8 MX23J25640 READ CYCLE TIMING CHART (1) (In case of read mode (1)) CLE tCLS tCLH CE tWC tCS tCEH tR WE tCRY tALH tALH tALS tWP tWH tAR2 tCHZ ALE tRR tRC tRC RE tRP tREH tWB tDS tDH I/O0~ I/O7 00H tDS tDS tDS A0-A7 A9-A16 A17-A24 tDH tDH tRHZ tDS tDH A25 tDH tRHZ DOUT DOUT DOUT N N+1 527 tREA tRB RB Access page M Output Page M Data Remarks: 1. Start address (SA) specification when read is performed with command 00H. N: 0 to 255 2. The time (tCRY) from CE high level until Busy is cancelled depends on the pull-up register of the RB output pin. P/N:PM1137 REV. 1.2, OCT. 28, 2005 9 MX23J25640 READ CYCLE TIMING CHART (2) (In case of read mode (2)) CLE tCLS tCLH CE tWC tCS tCEH tR WE tCRY tALH tALH tALS tWP tWH tAR2 tCHZ ALE tRR tRC tRC RE tRP tREH tWB tDS tDH I/O0~ I/O7 01H tDS tDS tDS A0-A7 A9-A16 A17-A24 tDH tDH tRHZ tDS tDH A25 tDH tRHZ DOUT DOUT DOUT 256+N 256+N+1 527 tREA tRB RB Access page M Output Page M Data Remarks 1. Start address (SA) specification when read is performed with command 01H. N: 0 to 255 2. The time (tCRY) from CE high level until Busy is cancelled depends on the pull-up register of the RB output pin. P/N:PM1137 REV. 1.2, OCT. 28, 2005 10 MX23J25640 READ CYCLE TIMING CHART (3) (In case of read mode (3)) CLE tCLS tCLH CE tWC tCS tCEH tR WE tCRY tALH tALH tALS tWP tWH tAR2 tCHZ ALE tRR tRC tRC RE tRP tREH tWB tDS tDH I/O0~ I/O7 50H tDS tDS tDS A0-A3 A9-A16 A17-A24 tDH tDH tRHZ tDS tDH A25 tDH tRHZ DOUT DOUT DOUT 512+N 512+N+1 527 tREA tRB RB Access page M Output Page M Data Remarks 1. Start address (SA) specification when read is performed with command 50H. N: 0 to 15 2. The start address of area C (redundancy data) is specified with A0 tp A3 during the 1st address cycle. At this time, A4 to A7 are Don't Care. 3. The time (tCRY) from CE high level until Busy is cancelled depends on the pull-up register of the RB output pin. P/N:PM1137 REV. 1.2, OCT. 28, 2005 11 MX23J25640 Sequential Read In read modes (1), (2), and (3), when a command (00H, 01H, 50H) is input and an address specified, if it is in the block that includes the address that was specified first, the address is automatically incremented and the read operation is continuously performed until the last address in the same block, by inputting the RE# clock. At this time, a Busy period (tR) occurs after the last address is accessed in a page. Note Command Address input input Page M data output Page M+1 data output Command input Output of in last page in block 00H 00H 01H 01H 50H 50H Address input Data output Note tR tR tR tR tCRY Busy Busy Busy Busy tR RB Busy Busy In same block (Maximum of 32 pages) Note :To perform read again after reading the 527th byte of data of the last page of block, stop the read operation once, and then restart the read operation by inputting again the read command and an address. Relationship Between Command and Start Address (SA) during Sequential Read (A) 0 (B) 256 (C) 512 527 (A) (B) 256 (C) 512 (A) 527 (B) 256 (C) 512 527 SA SA SA 1block =32 pages Sequential read mode (1) (When "00H" command is input) Sequential read mode (2) (When "01H" command is input) Note Sequential read mode (3) (When "50H" command is input) Note : When the "50H" command is set, only the (C) area (redundancy data part) is continuously read. • When the "00H" command is set, the start address (SA) is set to area (A). • When the "01H" command is set, the start address (SA) is set to area (B). • When the "50H" command is set, the start address (SA) is set to area (C). P/N:PM1137 REV. 1.2, OCT. 28, 2005 12 MX23J25640 SEQUENTIAL READ CYCLE TIMING CHART(1) (In case of read mode (1)) CLE tCLS tCLH CE tWC tCS tR WE tALH tALH tALS tWP tWH tAR2 ALE tRR tRC tRC RE tRP tREH tWB tDS tDH I/O0~ I/O7 00H tDS tDS tDS A0-A7 A9-A16 A17-A24 tDH tDH tRR tRHZ tDS tDH tR A25 tDH DOUT DOUT DOUT DOUT DOUT N N+1 527 0 1 tREA tRB RB Access page M Output Page M Data Access page M+1 Output page M+1 data Remarks 1.Start address (SA) specification when read is performed with command 00H. N:0 to 255. P/N:PM1137 REV. 1.2, OCT. 28, 2005 13 MX23J25640 SEQUENTIAL READ CYCLE TIMING CHART(2) (In case of read mode (2)) CLE tCLS tCLH CE tWC tCS tR WE tALH tALH tALS tWP tWH tAR2 ALE tRR tRC tRC RE tRP tREH tWB tDS tDH I/O0~ I/O7 01H tDS tDS tDS A0-A7 A9-A16 A17-A24 tDH tDH tRR tRHZ tDS tDH tR A25 tDH DOUT DOUT DOUT DOUT DOUT 256+N 256+N+1 527 0 1 tREA tRB RB Access page M Output Page M Data Access page M+1 Output page M+1 data Remarks 1.Start address (SA) specification when read is performed with command 01H. N:0 to 255. P/N:PM1137 REV. 1.2, OCT. 28, 2005 14 MX23J25640 SEQUENTIAL READ CYCLE TIMING CHART(3) (In case of read mode (3)) CLE tCLS tCLH CE tWC tCS tR WE tALH tALH tALS tWP tWH tAR2 ALE tRR tRC tRC RE tRP tREH tWB tDS tDH I/O0~ I/O7 50H tDS tDS tDS A0-A3 A9-A16 A17-A24 tDH tDH tRR tRHZ tDS tDH tR A25 tDH DOUT DOUT DOUT DOUT DOUT 512+N 512+N+1 527 512 513 tREA tRB RB Access page M Output Page M Data Access page M+1 Output page M+1 data Remarks 1.Start address (SA) specification when read is performed with command 50H. N:0 to 15. P/N:PM1137 REV. 1.2, OCT. 28, 2005 15 MX23J25640 Reset Cycle Timing Chart CLE tCLS tCLH tCS tCH CE WE tRST tALS tWP tALH ALE tDS I/O0~ I/O7 tDH FFH tWB RB P/N:PM1137 REV. 1.2, OCT. 28, 2005 16 MX23J25640 [Usage Cautions] (1) Rated operation Operation using timing other than shown in the timing charts is not guaranteed. (2) Commands that can be input The only commands that can be input are 00H, 01H, 50H, and FFH. Do not input any other commands. If other commands are input, the subsequent operation is not guaranteed. (3) Command limitations during Busy period Do not input commands other than the reset command (FFH) during the Busy period. If a command is input during the Busy period, the subsequent operation is not guaranteed. (4) Cautions regarding RE clock • Following the last RE clock, do not input the RE clock until the RB pin changes from Busy to Ready. • Do not input the RE clock other than during data output. (5) Cautions upon power application Since the state of the device is undetermined upon power on, input high level to the CE pin and execute the reset command following power on. (6) Cautions during read mode • Perform address input immediately following command input. If address input is done without performing command input first, the correct data cannot be output because the operation mode is undetermined. • To execute the read mode after the read mode has been stopped with the reset command (FFH) and CE, input again a command and address. (7) Busy output following access of last address in page in read mode After the access to the last address in a page, if the delay (tRHCH) from RE to CE is 30 ns or less, the Ready status is maintained and Busy is not output by keeping CE high level for a set period (tCEH). tCEH CE tRHCH RE 526 527 RB P/N:PM1137 REV. 1.2, OCT. 28, 2005 17 MX23J25640 PACKAGE INFORMATION P/N:PM1137 REV. 1.2, OCT. 28, 2005 18 MX23J25640 REVISION HISTORY Revision # Description Page 1.0 1. Changed standby current from 100uA to 40uA P1,6 2. Removed "Advanced Information" P1 1.1 1. Added "Order Information" P1 1.2 1. Removed tWHC P7 2. Modified "Read cycle timing chart" and "Sequential read cycle timing P9~11 chart" P13~15 P/N:PM1137 Date AUG/16/2005 SEP/06/2005 OCT/28/2005 REV. 1.2, OCT. 28, 2005 19 MX23J25640 MACRONIX INTERNATIONAL CO., LTD. Headquarters: TEL:+886-3-578-6688 FAX:+886-3-563-2888 Europe Office : TEL:+32-2-456-8020 FAX:+32-2-456-8021 Hong Kong Office : TEL:+86-755-834-335-79 FAX:+86-755-834-380-78 Japan Office : Kawasaki Office : TEL:+81-44-246-9100 FAX:+81-44-246-9105 Osaka Office : TEL:+81-6-4807-5460 FAX:+81-6-4807-5461 Singapore Office : TEL:+65-6346-5505 FAX:+65-6348-8096 Taipei Office : TEL:+886-2-2509-3300 FAX:+886-2-2509-2200 MACRONIX AMERICA, INC. TEL:+1-408-262-8887 FAX:+1-408-262-8810 http : //www.macronix.com MACRONIX INTERNATIONAL CO., LTD. reserves the right to change product and specifications without notice.