MCNIX MX98726EC

MX98726EC
SINGLE CHIP 10/100 FAST ETHERNET
CONTROLLER WITH uP INTERFACE
1.0 Features
• Support bus size configuration:
- CPU : 8 bits, SRAM: 8 bits
- CPU : 16 bits, SRAM: 8/16 bits
• Flexible packet buffer partition and addressing space
for 32k, 64k up to 512K bytes
• NWAY autonegotiation function to automatically set
up network speed and protocol
• 3 loop back modes for system level diagnostics
• Rich on-chip register set to support a wide variety of
network management functions
• Support 64 bits hash table for multicast addressing
• Support software EEPROM interface for easy upgrade of EEPROM content
• Support 1K bits and 4K bits EEPROM interface
• 5V CMOS in 128 PQFP package for minimum board
size application
• Direct interface to 80188/186 up to 40Mhz.
• Integrated 10/100 TP tranceiver on chip to reduce
overall cost
• Optional MII interface for external tranceiver.
• Fully comply to IEEE 802.3u spec.
• Best fit in network printer and hub/switch management application
• A local DMA channel between on-chip FIFOs and
packet memory
• Shared memory architecture allow host and
MX98726EC to use only one single SRAM
• Host DMA can share packet memory with local DMA
with simple hand shake protocol for x188/186 type of
processor
• Supports proprietary local DMA channel to share
packet memory
1.1 Introduction
A intelligent built-in SRAM bus arbitor will manage all
the SRAM access requests from host, on-chip transmit
channel and on-chip receive channel. The throughput
of these network channels and MX98726EC's DMA burst
length can be easily adjusted by option bits on the chip.
These options can help system developers to "fine tune"
a best cost/performance ratio.
MX98726EC ( Generic MAC , or GMAC ) is a cost effective solution as a generic single chip 10/100 Fast Ethernet
controller. It is designed to directly interface 80188, 80186
( host ) without glue logic. Two types of memory sharing
schemes are supported, i.e. interleaved and shared mode
to support a variety of applications. Single chip solution
will help reduce system cost not only on the components but also the board size. Full NWAY function with
10/100 tranceiver will ease the field installation, simply
plug the chip in and it will connect itself with the best
protocol available.
MX98726EC is also equipped with fast back-to-back
transmit capability which allow software to "fire" as many
transmit packets as needed in a single command. Receive FIFO also allow back-to-back reception. Optional
EEPROM can be used to stored network network address and other information. In case cost is really a concern, most configuration options including network address can be programmed through uP.
The interleaved mode allow uP to access SRAM (
packet/host buffer ) through MX98726EC's local DMA
channel. This way, no extra SRAM interface logic is
needed on the host side. If high performance is desired,
then shared memory mode is another alternative which
allow host to access SRAM on its own by denying SRAM
bus grant to MX98726EC using simple hand shake protocol. Without SRAM bus grant, MX98726EC will float
its interface connected to the SRAM, therefore host can
utilize its own memory subsystem to conduct its own
SRAM access.
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MX98726EC
1.2 Internal Block Diagram
Host
Packet Buffer
(SRAM)
EPROM
SRAMIU
Serial ROM port
BIU
RX
FIFO
TX
FIFO
RX
SM
TX
SM
MII Interface
PCS
NWAY
CTRL & REGS
100 TX PHY
100TX PMD
interface
10Mbps
MCC+TP interface
Architecture and Interface overview
1.3 Typical Applications
Packet
buffer
EPROM
C46/C66
local DMA
uP with dedicate bus
Host side
MX98726EC
RJ45
Xformer
TP cable
CSB
decode
Customer Application
Interleaved memory Architecture
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MX98726EC
EPROM
C46/C66
Packet
buffer
Host Memory
Subsystem
SRAM Bus
HOLD
uP with
shared bus
RJ45
Xformer
HLDA
TP cable
MX98726EC
CSB
Decode
Customer Application
Shared memory Architecture
1.4 Combo Application
EPROM
C46/C66
Packet
buffer
Host Memory
Subsystem
Local DMA
1M 8PHY
or
10M 8PHY
Customer Application
MX98726EC
Host
RJ11 Phone Line
Xformer
or
RJ45
Xformer
CSB
TP Cable
Decode
COMBO APPLICATION
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29
30
31
32
33
34
35
36
37
38
TXON
TXOP
GNDA
CPK
RXT2EQ
RTX
VDDA
GNDA
GNDA
VDDA
19
GNDA
28
18
GNDA
VDDA
17
CKREF(X1)
27
16
X2
GNDR
15
VDDA
26
14
RDA
GNDR
13
GNDA
25
12
VDDA
VDDR
11
TXD0
24
10
TXD1
RXIP
9
TXD2
23
8
TXD3
RXIN
7
(RXD0)MA19
22
6
(RXD1)MA18
VDDR
5
(RXD2)MA17
21
4
(RXD3)MA16
GNDR
3
VDD
20
2
GND
VDDA
1
MA15
39
GNDA
GND
128
AD11
VDDA
GND
65
40
AD10
127
66
GNDA
MA14
AD9
41
67
126
AD8
UPTYPE0(MDIO)
MA13
68
42
A19(RXC)
125
69
UPTYPE1(MDC)
MA12
A18(RXDV)
43
70
124
A17(CRS)
C46/C66
MA11
71
44
A16(COL)
123
72
HOLD
MA10
RSTB
45
73
122
BHEB
HLDA
MA9
74
46
ALE
121
75
CSB
MA8
PSENB
47
76
120
WRB
MIO
VDD
77
48
RDB
119
78
AD7
MA7
SRDY
49
79
118
INTB
AD6
MA6
80
50
CLKIN
117
81
AD5
MA5
LED1(TXEN)
51
82
116
LED0(TXC)
AD4
MA4
83
52
GND
115
84
AD3
MA3
MCSB
53
85
114
MOEB
AD2
MA2(EEDO)
86
54
MWE0B
113
87
GND
MA1(EEDI)
MWE1B
55
88
112
MD0
AD1
GND
89
56
MD1
111
90
AD0
MA0(EECK)
VDD
57
91
110
GND
VDD
EECS
92
58
MD2
109
93
AD15
MD15
MD3
59
94
108
MD4
AD14
MD14
95
60
VDD
107
96
AD13
MD13
MD5
61
97
106
MD6
AD12
MD12
98
62
MD7
105
99
VDD
GND
MD8
GND
63
100
64
104
MD9
103
MD11
101
MD10
102
MX98726EC
2.0 Pin Configuration and Description
MX98726EC
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MX98726EC
2.1 Pin Description :
PIN#
82
49-54,
Pin Name
CLKIN
AD[7:0]
59-62,
AD[15:8]
76
70
ALE
A19(RXC)
Type
I, TTL
I/O, 4ma
56,57
I/O, 4ma
66-69
I,TTL
I, TTL
71
A18(RXDV)
I,TTL
72
A17(CRS)
I,TTL
73
A16(COL)
I,TTL
79
78
81
RDB
WRB
INTB
I, TTL
I, TTL
O/D, 4ma
75
BHEB
I,TTL
80
SRDY
O, 4ma
47
CSB
I, TTL
48
MIO
I, TTL
Description
Host Clock Input : 8M to 40 Mhz.
Multiplexed Address/Data Bit [7:0] : Internal pull-down
Multiplexed Address/Data Bit [15:8] : Internal pull-down
Address Latch Enable : Active high
Host Bus Address Bit19, when on-chip tranceiver is used,it is used in
A[19:16], when in MII mode, it is defined as receive clock RXC (25MHz or
2.5MHz) When this pin is used as address bit, it is internally grounded until
Reg50.6 (A19A16EN bit) is set to enable decoding of this pin as address
bit. Internal pull-up
Host Bus Address Bit18, when on-chip tranceiver is used,it is used in
A[19:16], when in MII mode, it is defined as receive data valid RXDV
signal. When this pin is used as address bit, it is internally grounded until
Reg50.6 (A19A16EN bit) is set to enable decoding of this pin as address
bit. Internal pull-up.
Host Bus Address Bit17, when on-chip tranceiver is used, it is used in
A[19:16], when in MII mode, it is defined as carrier same CRS signal.
When this pin isused as address bit, it is internally grounded until Reg50.6
(A19A16EN bit) is set to enable decoding of this pin as address bit. Internal pull-up.
Host Bus Address Bit16, when on-chip tranceiver is used, it is used in
A[19:16], when in MII mode, it is defined as collision COL signal. When
this pin is used as address bit, it is internally grounded until Reg50.6
(A19A16EN bit) is set to enable decoding of this pin as address bit. Internal pull-up.
Host Read Strobe: Active low. Internal pull-up
Host Write Strobe : Active low. Internal pull-up
Host Interrupt Output : Polarity can be programmed, default is active low.
For active Low interrupt application, external pull-up is reguired. For active
high interrupt application, external pull-down is required.
Host Byte High Enable : Internal pull-up.
BHEB A0
Function
0
0
Word Transfer
0
1
Upper Byte Transfer
1
0
Lower Byte Transfer
1
1
Lower Byte Transfer
Synchronous Host Ready Output : Active high synchronized to CLKIN to
indicate data is ready to be transferred. Initially low at the beginning of a
host cycle.
Chip Select : Active low, used to enable GMAC to decode host address.
When high, no host cycle is recognized by MAC.
Host Memory/IO cycle indicator : Set for memory access and reset for IO
access. Internal pull-up. Decode of MIO can be disable by DISMIO register bit. Default is enabled.
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MX98726EC
45
HOLD
O, 4ma
46
HLDA
I, TTL
77
PSENB
I, TTL
74
RSTB
I,TTL
Packet Memory Bus Hold Request : Active high to request Host to "float"
its interface of the packet memory. Host grants the packet buffer bus to
MX98726EC by asserting HLDA = 1.
Packet Memory Bus Hold Acknowledge: Packet buffer bus is granted to
MX98726EC. If HLDA=0 then MX98726EC will float its interface on the
packet buffer. Internal pull-up.
Host Program Strobe Enable : Active low to indicate current cycle is a
ROM access and MX98726EC will not decode this ROM cycle. PSENB
must high for packet memory access. Internal pull-up.
Host Reset Input : Active low, Schmitt trigger input, Internal pull-up.
Packet Buffer Interface :
PIN#
Pin Name
Type
Description
O,4ma
Memory Address Bit 19-0: If HLDA = 0 then all these address lines are tristated.
Memory Address Bit19, when on-chip tranceiver is used, it is defined as
MA19, while in MII mode, it is used as receive data bit RXD0 pin.
Memory Address Bit18, when on-chip tranceiver is used, it is defined as
MA18, while in MII mode, it is used as receive data bit RXD1 pin.
Memory Address Bit17, when on-chip tranceiver is used, it is defined as
MA17, while in MII mode, it is used as receive data bit RXD2 pin.
Memory Address Bit16, when on-chip tranceiver is used, it is defined as
MA16, while in MII mode, it is used as receive data bit RXD3 pin.
Memory Data Bit 15-0 : Internal pull-down.
1,
MA[19:3]
115-119
7
MA19(RXD0)
I/O, 4ma
6
MA18(RXD1)
I/O, 4ma
5
MA17(RXD2)
I/O, 4ma
4
MA16(RXD3)
I/O, 4ma
90-96,
MD[15:0]
98-104,
106-109
114
MA2(EEDO)
I/O,4ma
1/O,4ma
113
MA1(EEDI)
1/O,4ma
111
MA0(EECK)
1/O,4ma
87
86
88, 89
MOEB
MCSB
MWEB[1:0]
O,4ma
O,4ma
O,4ma
Memory Address Bit 2 or EEPROM Data Out bit: Right after host reset,
GMAC automatically load configuration information from external EEPROM.
During this period, MA2 pin acts as a EEDO pin that read in output data
stream from EEPROM. After EEPROM auto load sequence is done, this
pin becomes MA2 together with MA[19:3] forms packet buffer address
line 19 - 0. Internally pull-down.
Memory Address Bit 1 or EEPROM Data In bit: During EEPROM auto load
sequence, MA1 pin acts as EEDI pin that write data stream into EEPROM.
After EEPROM auto load sequence is done, this pin becomes MA1, together with MA[19:2] forms packet buffer address lines.
Memory Address Bit 0 or EEPROM Clock Input : During EEPROM auto
load sequence, MA0 pin acts as EECK pin that provides clock to EEPROM.
After EEPROM auto load sequence is done, this pin becomes MA0, together with MA[19:1] forms packet buffer address lines.
Memory Output Enable: Active low during packet buffer read access.
Memory Chip Select: Active low during packet buffer accesses.
Byte Write Enable: Active low during packet buffer write cycle. MWEB1 for
high byte and MWEB0 for low byte.
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MX98726EC
10/100 Tranceiver interface :
PIN#
14
17
16
23
24
29
Pin Name
RDA
CKREF(X1)
X2
RXIN
RXIP
TXON
Type
O
I, TTL
O
I
I
O
30
TXOP
O
32
33
34
CPK
RTX2EQ
RTX
O
O
O
Description
RDA external resistor to ground: 10K ohm, 5%
25Mhz , 30 PPM external osc./crystal input :
25Mhz , 30 PPM external crystal output :
Twisted pair receive differential input: support both 10/100 Mbps speed
Twisted pair receive differential input: support both 10/100 Mbps speed
Twisted pair transmit differential output: support both 10/100 Mbps speed,
meet 802.3/802.3u spec.
Twisted pair transmit differential output: support both 10/100 Mbps speed,
meet 802.3/802.3u spec.
NC pin : used in test mode only
RTX2EQ external resistor to ground: 1.4K ohm, 5%
RTX external resistor to ground: 560 ohm, 5%
Miscellaneous :
PIN#
110
44
84
Pin Name
EECS
C46/C66
LED0(TXC)
Type
O,2ma
I,TTL
I/O,16ma
83
LED1(TXEN)
O,16ma
42,43 UPTYPE0,
I,TTL
42
UPTYPE0( MDIO) I/O,TTL
43
UPTYPE1(MDC)
I/O, TTL
Description
EEPROM Chip Select Signal : Active high
EEPROM Size Select : Set for C46, reset for C66. Internal pull-up.
LED0 (TXC in MII mode) : When on-chip tranceiver is used, it is defined as
SPEED LED. When the light is on, it indicates the 100 Mbps speed. When
off, it indicates the 10 Mbps speed. When both LED0 and LED1 are flashing identically, it means the bus integrity error. (Internal pull-up). When in
MII mode, this pin is defined as transmit clock TXC (25 MHz or 2.5 MHz)
input.
LED1 (TXEN in MII mode) :When on-chip tranceiver is used, it is defined
as Link/Activity LED. When the light is stable and on, it indicates a good
link. When flashing, it indicates TX and RX activities. When off, it means
a bad link. (Internal pull-up). When in MII mode, this pin is defined as transmit enable TXEN pin.
uP type select control bit 1-0: UPTYPE1 and UPTYPE0 must be externally pull-up or down through < 4.7K ohm resistors to configure the bus
interface for different uP.
UPTYPE1
UPTYPE0
uP selected
0
0
reserved 0
0
1
80x1
1
0
80188
1
1
80186
uP type select control bit 0 ( MDIO in MII mode ): UPTYPE0 is
internally pull-down and used as uP type selection during host reset (
RSTB=0 ). After host reset sequence is completed, this pin become MDIO
pin if MII mode is selected.
uP type select control bit 1 ( MDC in MII mode ) : UPTYPE1 is internally
pull-down, after host reset sequence is completed , this pin become MDC
clock output pin if MII mode is selected.
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MX98726EC
Vdd/Gnd Pins :
PIN#
12,15,20,28,35,38,40
Pin Name
VDDA
13,18,19,31,36,37,39,41
GNDA
22,25
VDDR
21,26,27
GNDR
3,58,63,92,97,120
VDD
2,55,64,65,85,93,105,112,128
GND
Description
Analog Vdd Pins : Must be carefully isolated in a separted
vdd plane.
Analog Ground Pins : Must be carefully isolated in a
separted ground plane.
RX Vdd Pins : Must be carefully isolated in a separted
Vdd plane.
RX Ground Pins : Must be carefully isolated in a separted
ground plane.
Digital Vdd Pins : Must be carefully isolated in a separted
Vdd plane.
Digital Ground Pins : Must be carefully isolated in a
separted ground plane.
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MX98726EC
3.0 Register (Default value is defined after hardware/power-up reset)
Reset logic : All register bits are cleared by hardware reset, while register bit with an "*" in its symbol
name is also cleared by software reset.
Network Control Register A : NCRA (Reg00h),R/W, default=00h
Bit
0.0
0.1
0.2
Symbol
RESET
ST0*
ST1*
Description
Software reset.
Start Transmit Command/Status : Write to issue commands. When done, both bits are
cleared automatically.
Transmit command : ST1
IDLE state
0
TX DMA Poll
0
TX FIFO Send
1
TX DMA Poll
1
ST0
0
Read to indicate TX DMA idle state, write has no effect.
1
Start TX DMA, send packets stored in packet memory.
0
Immediately send the packet stored in the TX FIFO.
1
Start TX DMA, send packets stored in packet memory.
All transmit commands are cleared to 00 when the operation is done to indicate idle
state. When the TX DMA poll and the TX FIFO Send can not be used at the same time.
New packet can be written to the FIFO directly only when ST1, ST0=IDLE and
TXDMA[3:0]=1h. The TX DMA poll and the TX FIFO Send commands can be issued only
when ST1, ST0=IDLE and TXDMA[3:0]=1h, regardless of any error status in previous
transmission.
0.3
0.4, 0.5
0.6
0.7
SR*
LB0*,LB1*
INTMODE
CLKSEL
Start Receive: Enable the MAC receive packets. Default is disabled.
Loopback Mode:
LB1
LB0
Mode0
0
0
Normal mode
Mode1
0
1
Internal FIFO Loopback
Mode2
1
0
Internal NWAY Loopback
Mode3
1
1
Internal PMD Loopback
Mode 2 and 3 are reserved for IC test purpose. Only mode 1 can be used on bench.
External loopback for bench can be done by full duplex normal mode with real cable
hooked up from TX port to RX port.
Interrupt Mode: Set for active high interrupt, reset for active low interrupt case.
Clock Select : Set to use internal 40MHz clock for all internal DMA, default is reset to use
internal 50MHz clock for all internal DMA.
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MX98726EC
Network Control Register : NCRB (Reg01h),R/W, default=01h
Bit
1.0
Symbol
PR*
1.1
CA*
1.2
PM*
1.3
PB*
1.4
AB*
1.5
HBD*
Reserved
Description
Promiscuous mode: Set to receive any incoming valid frames received, regardless of
its destination address. Default is set.
Capture Effect Mode: Set to enable an enhanced backoff algorithm to avoid network
capture effect.
Pass Multicast: Set to accept all multicast packets including broadcast address ( 1st
bit in destination address is 1 ), default is reset
Pass Bad Frame: Enable GMAC to accept Runt frame. Default is reset.
Accept Broadcast: Default is reset. Set to accept all broadcast packets.
Reserved for test purpose. Default is 0.
Must be 00.
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MX98726EC
GMAC Test Register A : TRA (Reg02h),R/W, default=00h
Bit
2.0
Symbol
TEST
2.1-2.3
TMODE[2:0]
2.4
RWR
2.5
RWD
2.6
FC
2.7
SB
Description
Test mode enable: Set to enable test modes defined by TMODE[2:0], default is reset
for normal operation.
Test Mode Select bits[2:0]: Reserved for GMAC's internal tests, only meaningful when
the TEST bit is set, except when TMODE [2:0] = "110" which is also used as normal
mode with EEPROM interface disabled. When TMODE [2:0] = "110" & Test =0, then
MA19~MA16 are still SRAM address bit19~16, while Test = 1, MA19~MA16 are defined as test pins reserved for debug purpose.
Receive Watchdog Release : When set, the receive watchdog is released 40 to 48 bit
times from the last carrier deassertion. When reset, the receive watchdog is released
16 to 24 bits times from the last carrier deassertion.
Receive Watchdog Disable : When set, the receive watchdog is disabled. When reset,
receive carriers longer than 2560 bytes are guaranteed to cause the watchdog timeout.
Packets shorted than 2048 bytes are guaranteed to pass.
Forced Collision : Set to force collision at every transmit packet, this bit works only in
internal FIFO loopback mode, i.e. LB0=1, LB1=0, to test excessive collision. Default
is reset.
Start/Stop Backoff counter: When set, indicates internal backoff counter stops counting when any carrier is detected. Counter resumed when carrier drops. When reset,
the internal backoff counter is not affected by carrier activity. Default is reset.
GMAC Test Register : TRB (Reg03h),R/W, default=00h
Bit
3.0
Symbol
FKD*
3.1
3.2
3.3
3.4
RDNCNTCB*
RDNCNTSB*
COLCNTCB*
BFS0*(MDC)
3.5
BKCNTLB*(MDIOEN)
3.6
BFS1*(MDO)
3.7
BFSTATUS*(MDI)
Description
Flaky Oscillator Disable: When set, indicates that the internal flaky
oscillator is disabled. Pseudo random numbers are chosen instead of
fully random numbers, used for the internal diagnostic purpose. Set to
disable the normal clocking scheme in the timer's test. Reset to enable
the timer test. Default is reset.
Reserved for test
Reserved for test
Reserved for test
Normally used as BFS0 pin for test purpose, while in MII mode, it is
defined as MII management clock signal (MDC) to be used as a timing
reference of MDIO pin.
Normally used as BKCNTLB pin for test purpose, while in MII mode, it is
used to control the direction of MDIO pin. Set MDIOEN = 1 will make
MDIO pin as input pin, the value can be read from MDI bit.
Set MDIOEN = 0 will make MDIO pin as output pin, the value of MDO bit
is driven out to MDIO pin.
Normally used as BFS1 pin for test purpose, while in MII mode, it is
used as MII management write data (MDO) for MDIO pin's output data.
Normally used as BFSTATUS pin for test purpose, while in MII mode, it is
used as MII management read data (MDI) for MDIO pin's input data.
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MX98726EC
Last Transmitted Packet Status: LTPS ( Reg04h), RO, default=00h
Bit
4.0
4.1
4.2
4.3
Symbol
CC0*
CC1*
CC2*
CC3*
4.4
CRSLOST*
4.5
UF*
4.6
OWC*
4.7
TERR*
Description
Collision Count Bit 0 :
Collision Count Bit 1 :
Collision Count Bit 2 :
Collision Count Bit 3 : when CC[3:0] = 1111 and a new collision is detected, then it is
called excessive collision error which will abort the current packet, TEI interrupt bit
will be set.
Carrier Sense Lost : Set to indicate CRS was lost during the transmission, default is
reset for normal packet transmission.
TX FIFO underflow : Set to indicate a underflow problem in TX FIFO an FIFOEI
interrupt is generated for driver to resolve this problem.
Out of Window Collision : Set to indicate an collision occured after 64 bytes of data
has been transmitted, no retransmission will be issued
Transmit Error: Set to indicate packet transmitted with error, reset for normal packet
transmission.
Last Received Packet Status: LRPS ( Reg05h), RO, default=00h
Bit
5.0
5.1
Symbol
BF*
CRC*
5.2
FAE*
5.3
5.4
FO*
RW*
5.5
5.6
MF*
RF*
5.7
RERR*
Description
RX Packet Buffer Full Error : 1 indicates RX packet buffer is full.
CRC error : Calculation is based on integer multiple of bytes, set to indicate CRC error
for received packet.
Frame Alignment Error : Set to indicate extra nibble is received which is not at octet
boundary. This error is independent of CRC detection.
FIFO overrun : When set, an interrupt is generated, driver must resolve this error.
Receive Watchdog : Set to indicate the frame length exceeds 2048 bytes. An interrupt
will be generated to driver.
Multicast address : Set to indicate current frame has multicast address.
Runt Frame : Set to indicate a frame length less than 64 bytes, only meaningful when
Reg01h.3 PB bit =1 is set.
Receive Error : Set to indicate a packet received with errors including CRC, FAE, FO,
RW, ( RF and PB=1 ).
Notes : This LRPS register contains the same status byte as in the description field of the last received packet
in the packet memory.
Missed Packet Counter: MPC (Reg07/06h), R/W, default=0000h
Bit
6.7-0
7.7-0
Symbol
MISSCNT[7:0]*
MISSCNT[15:8]*
Description
Miss Packet Counter Bit [7:0]: Lower byte of Miss packet counter
Miss Packet Counter Bit [15:8]: Upper byte of Miss packet counter
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MX98726EC
Interrupt Mask Register: IMR (Reg08h), R/W, default=00h
Bit
8.0
Symbol
CNTOFIM
8.1
RIM
8.2
TIM
8.3
RXEIM
8.4
TXEIM
8.5
FIFOEIM
8.6
BUSEIM
8.7
RBFIM
Description
Miss Counter Over Flow Interrupt Mask : Set to enable Miss counter overflow interrupt,
default is reset. When Overflow condition of the miss packet counter occures, counter is
halt and driver need to resolve this condition in order to reset the counter if counter is
ever used.
Received Interrupt Mask: Set to enable Packet Received Interrupt, default is reset which
disable RI interrupt.
Transmit Interrupt Mask: Set to enable Packet transmit OK interrupt, default is reset
which disable TI interrupt.
Receive Error Mask: Set to enable Receive Error interrupt, default is reset which disable
RXEI interrupt.
Transmit Error Mask: Set to enable transmit error interrupt, default is reset which disable
TXEI interrupt.
FIFO Error Interrupt Mask: Set to enable FIFO Error interrupt, default is reset which
disable FIFOEI interrupt.
Bus Error Interrupt Mask: Set to enable Bus Error interrupt, default is reset which disable BUSEI interrupt.
RX Buffer Full Interrupt Mask: Set to enable RX Buffer full interrupt, default is reset
which disable BFI interrupt.
Interrupt Register: IR (Reg09h), R/W, default=00h
Bit
9.0
Symbol
CNTOFI*
9.1
RI*
9.2
TI*
9.3
REI*
9.4
TEI*
9.5
FIFOEI*
9.6
BUSEI*
9.7
RBFI*
Description
Miss Counter Over Flow Interrupt : Set to assert interrupt when Miss packet counter is
overflow, write 1 to this bit will clear the bit and interrupt, write 0 has no effect.
Receive OK interrupt : Set to assert interrupt, write 1 to this bit will clear the bit and
interrupt, write 0 has no effect
Transmit OK interrupt: Set to assert interrupt, write 1 to this bit will clear the bit and
interrupt, write 0 has no effect
Receive Error Interrupt: Set to assert interrupt when packet is received with error , write
1 to this bit will clear the bit and interrupt, write 0 has no effect
Transmit Error Interrupt : Set to assert interrupt when packet is transmitted with error,
write 1 to this bit will clear the bit and interrupt, write 0 has no effect
FIFO Error Interrupt: Set to assert interrupt when either TX FIFO is overrun or RX FIFO
is overrun, write 1 to this bit will clear the bit and interrupt, write 0 has no effect
Bus Error Interrupt: Set to assert interrupt when Bus integrity check is enabled and
failed. Write 1 to this bit will clear the bit and interrupt, write 0 has no effect
RX Buffer Full Interrupt: Set to assert interrupt when RX buffer area is being overwritten
by new received packets, write 1 to this bit will clear the bit and interrupt, write 0 has no
effect
Note : All page pointer bit [11:0] are mapped to MA[19:8] in the same bit ordering.
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Boundary Page Pointer Register: BP (Reg0Bh/0Ah), R/W, default=x000h
Bit
0A.7-0,
0B.3-0
Symbol
BP[11:0]
Description
Boundary Page Pointer between tx/rx buffer: page TLBP[11:0] to page BP[11:0]
is tx buffer. page BP[11:0] to RHBP[11:0] is rx buffer. BP[11:0] is mapped to
MA[19:8]. MSB bit is Reg0BH.3 bit. LSB is Reg0AH.0 bit.
TX Low Boundary Page Pointer Register: TLBP (Reg0Dh/0Ch), R/W, default=x000h
Bit
0C.7-0,
0D.3-0
Symbol
TLBP[11:0]
Description
TX Low Boundary Page Pointer : Points to the first page of transmit buffer ring.
It's a static pointer that is used by GmAC to link to the last page pointed by
boundary pointer. TLBP[11:0] MSB bit is Reg0Fh.3 bit. LSB is Reg0Ch.0 bit.
Transmit Buffer Write Page Pointer : TWP (Reg.0Fh/0Eh), R/W, default=x000h
Bit
0E.7-0,
0F.3-0
Symbol
TWP[11:0]
Description
Transmit Buffer Write Page Pointer: TWP[11:0] are mapped to MA[19:8] with
the same bit ordering. The MSB is the Reg0Fh.3 bit. The LSB is the
Reg0Eh.0 bit. TWP is normally controlled by the device driver. An internal Byte
Counter (TWPBC) is associated with this page register.
IO Base Page Register: IOB (Reg11h/10h), R/W, default=x000h
Bit
10.7-0,
11.3-0
Symbol
IOB[11:0]
Description
IO Base Address Register: On-chip register IO base address register. This
page address register defines the base page address of all on-chip registers
in a IO address space.(00h-FFh). MIO=0 and CSB=0 will force GMAC to
decode IO address for on chip register access. if MIO=1 and CSB=0, then all
on chip registers are localed in memory page 0. IOB register is mapped to
physical address [19:8] during decoding. IOB is 0000h after Reset, software
can assign new base address by writing new page number to this register.
Transmit Buffer Read Page Pointer Register: TRP (Reg13h/12h), R/W, default=x000h
Bit
12.7-0,
13.0-3
Symbol
TRP[11:0]
Description
The Page Index of transmit buffer read pointer: Current transmit read page pointer.
MSB bit is Reg13h.3 bit. LSB is Reg12h.0 bit. TRP is controlled by GMAC only.
An internal Byte Counter (TRPBC) is associated with this page register.
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MX98726EC
Receive Interrupt Timer: RXINTT (Reg15h/14h), R/W
Bit
14.7-0,
15.7-0,
Symbol
RXINTT[7:0],
RXINTT[15:8]
Description
Receive Interrupt Timer: Default is 0000h "not used".
Receive Buffer Write Page Pointer Register: RWP (Reg17h/16h), R/W, default=x000h
Bit
16.7-0,
17.0-3
Symbol
RWP[11:0]
Description
Receive Buffer Write Page Pointer: Current receive write page pointer. MSB
bit is Reg17h.3 bit. LSB is Reg16h.0 bit. This register is controlled by GMAC only.
An internal Byte Counter (RWPBC) is associated with this page register.
Receive Buffer Read Page Pointer Register: RRP ( Reg19h/18h), R/W, default=000h
Bit
18.7-0,
19.0-3
Symbol
RRP[11:0]
Description
Receive Buffer Read Page Pointer: MAC current receive read page pointer.
RRP[11:0] is mapped to MA[19:8]. MSB bit is Reg19h.3 bit. LSB is Reg18h.0 bit.
This register is normally controlled by device driver. An internal byte Counter
(RRPBC) is associated with this page register.
64K Memory Bank Address : Reg19h (R/W), default=0h
Bit
19.7-4
Symbol
BANK[3:0]
Description
Reserved : Default is 0000
RX High Boundary Page Pointer Register: RHBP ( Reg1Bh/1Ah), R/W, default=x000h
Bit
1A.7-0.
1B.0-3
Symbol
Description
RHBP[11:0] Receive High Boundary Page Pointer : RX packet buffer is defined as between
RHBP [11:0] and BP[11:0]. MSB bit is Reg1Bh.3 bit. LSB is Reg1Ah.0 bit.
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MX98726EC
EEPROM Interface Register: Reg1Ch, R/W, default=00h
Bit
1C.0
1C.1
1C.2
1C.3
1C.4
1C.5
Symbol
EECS*
EECK*
EEDI*
EEDO*
EESEL*
EELD*
1C.6
HOLDREQ
1C.7
HLDAACK
Description
Chip select output to external EEPROM clock device
Serial clock output to external EEPROM clock device, <1MHz
Serial data input to external EEPROM clock device
Serial data output from external EEPROM clock device
Set to enable external EEPROM write operation, default 0 is read.
Set to enable reloading the entire content of EEPROM just like power-on reset or
hardware reset. When loading is done, this bit will be set by GMAC automatically.
Reserved, default = 0, set to hold host access to SRAM in order to access
EEPROM by software.
Reserved, Read only, set to indicate that request to hold host is granted, GMAC
can access EEPROM through Reg. IC by software.
Reserved ( Reg 1Dh ), default=00h
Bit
Symbol
Reserved
Description
Must be 00h
Reserved (Reg1Fh/1Eh), R/W, default=0000h
Bit
1E.7-0,
1F.7-0
Symbol
Description
reserved
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MX98726EC
Network Address Registers : Reg20h~25h (R/W), 26h~2Dh (R/W), default=00h
Bit
20.[7:0]
21.[7:0]
22.[7:0]
23.[7:0]
24.[7:0]
25.[7:0]
26.[7:0]
27.[7:0]
28.[7:0]
29.[7:0]
2A.[7:0]
2B.[7:0]
2C.[7:0]
2D.[7:0]
Symbol
PAR0
PAR1
PAR2
PAR3
PAR4
PAR5
MAR0
MAR1
MAR2
MAR3
MAR4
MAR5
MAR6
MAR7
Description
Physical Address Byte 0: PAR[7:0]
Physical Address Byte 1: PAR[15:8]
Physical Address Byte 2 : PAR[23:16]
Physical Address Byte 3 : PAR[31:24]
Physical Address Byte 4 : PAR[39:32]
Physical Address Byte 5 : PAR[47:40]
Hash Table Register Byte 0 : MAR[7:0]
Hash Table Register Byte 1 : MAR[15:8]
Hash Table Register Byte 2 : MAR[23:16]
Hash Table Register Byte 3 : MAR[31:24]
Hash Table Register Byte 4 : MAR[39:32]
Hash Table Register Byte 5 : MAR[47:40]
Hash Table Register Byte 6 : MAR[56:48]
Hash Table Register Byte 7 : MAR[63:57]
Transceiver Control Register : ANALOG (Reg 2Eh), R/W, default=07h
Bit
2E.0
2E.1
2E.2
Symbol
DS120
DS130
PWD10B
2E.3
PWD100
2E.4
RSQ
2E.5
RST100
2E.6-7
Reserved
Description
Must be 1 for NORMAL mode with auto-compensation.
Must be 1 for NORMAL mode with auto-compensation
Set for NORMAL mode, write 0 followed by write 1 will power down 10 Base-T
analog circuit.
Reset for NORMAL mode, write 1 followed by write 0 will power down 100 BaseT analog circuit.
Reduced SQuelch Enable : Set to enable the reduced squelch circuit in the 10
Base-T mode for the receive channel. This can help the reception in a long cable
application. Default is reset, meaning the normal CAT-5 cable is used.
Reset for NORMAL mode, write 1 followed by write 0 will reset 100 Bare-T analog
circuit.
must be zero.
Reserved, default=00h
Bit
2F.7-0
Symbol
Reserved
Description
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NWAY Configuration Register : NWAYC (Reg 30h), R/W, default=84h
Bit
30.0
Symbol
FD
30.1
30.2
PS100/10
ANE
30.[5:3]
ANS[2:0]
30.6
30.7
NTTEST
LTE
Description
Full Duplex Mode: Set 1 to force the full duplex mode. The default is 0, meaning
the half duplex mode. This bit is meaningful only if ANE = 0
Port Select 100/10 bit : Default is 0, meaning the 10 Base-T mode.
Autonegotiation Enable: Set to enable the NWAY function. Default is set. ANS[2:0]
should be written 001 to restart the autonegotiation sequence after ANE is set.
Autonegotiation status bits: Read only for the NWAY status, except when write
001 will restart the autonegotiation sequence. The MSB is the Reg30h.5 bit when
Nway settles down in one network mode, one bit of Reg31.4~Reg 31.7 will be set
to indicate the chosen network mode.
Autonegotiation Arbitration State, arbitration states are defined
000 = Autonegotiation disable
001 = Transmit disable
010 = ability detect
011 = Acknowledge detect
100 = Complete acknowledge detect
101 = FLP link good; autonegotiation complete
110 = Link check
Reserved
Link Test Enable : Default is high, meaning the link check is always enabled.
Reset forces a good link in the 10 Base-T mode for the testing purpose.
NWAY Status Register : NWAYS (Reg 31h), RO, default=00h
Bit
31.0
31.1
31.2
Symbol
LS10
LS100
LPNWAY
31.3
ANCLPT
31.4
100TXF
31.5
100TXH
31.6
10TXF
31.7
10TXH
Description
Physical Link Status of 10 Mbps TP : Set for good link in 10 Base-T.
Physical Link Status of 100 Mbps TP : Set for good link in 100 Base-TX.
Link Partner Status : 1 to indicate link partner is capable of NWAY support, reset
for non-NWAY link partner.
Autonegotiation Completion : Set to indicate that a normal NWAY state machine
completion. Reset for incomplete.
NWAY 100 TX Full_duplex Mode : Set to indicate NWAY is settle down in 100 TX
full duplex mode.
NWAY 100 TX Half_dulpex Mode : Set to indicate NWAY is settle down in 100
Base-T half duplex mode.
NWAY 10 TX Full_duplex Mode : Set to indicate NWAY is settle down in 10 BaseT full duplex mode.
NWAY 10 TX Half_duplex Mode : Set to indicate NWAY is settle down in 10
Base-T half duplex mode.
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GMAC Configuration A Register: GCA (Reg32h), R/W, default=00h
Bit
32.0
Symbol
BPSCRM
32.1
PBW
32.2
SLOWSRAM
32.3
ARXERRB
32.4
MIISEL
32.5
AUTOPUB
32.6
TXFIFOCNTEN
32.7
reserved
Description
Bypass 100TX Scrambler: Default is 0, meaning enable scrambler during 100TX
mode, set to disable scrambler.
Packet Buffer Data Width : Default is 0. Meaning packet buffer data width is byte
wide. Set for word (16 bit) wide packet buffer. For 8 bit system bus, the packet
buffer bus width must be byte wide.
Slow SRAM select bit: Default is 0 meaning fast SRAM must be used ( Taa <= 20ns
), if set , then Taa<= 70ns can be used. Slow SRAM will reduce packet through put,
therefore, if high speed host is intended, then SRAM should be fast otherwise, FIFO
underrun or overrun can happen.
Accept RX packet with error : Default is reset to receive packets with error, set to
reject packets with error, packet memory will not contain packet with RW, FO, CRC
errors.
Default = 0 after reset, on-chip tranceiver is used. Set by software to enable MII
interface.
Auto Page Update option :
Set to disable the automatic host page update during the host DMAs. Reset to
enable the host page update for the RRP, TWP registers. Default is reset.
Default=0, after rest which means Reg 3E & 3F (TXFIFOCNT) are not used. This
option is only good for a byte-base host transfer. For host which do word/double
word transfer, this bit must be set to 1 to force TXFIFO use actual packet length
for transmission.
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GMAC Configuration B Register: GCB (Reg33h), R/W
Bit
33.1-0
Symbol
TTHD[1:0]
33.3-2
RTHD[1:0]
33.4
33.5
33.6
33.7
SRAMELEN
X4ELEN
DREQB2EN
reserved
Description
Transmit FIFO Threshold : Default is 00
TTHD1
TTHD0
FIFO depth
aggressiveness
0
0
1/2
medium
0
1
1/4
least
1
0
3/4
most
1
1
reserved
reserved
Receive FIFO Threshold : Default is 00
RTHD1
RTHD0
FIFO depth
aggressiveness
0
0
1/2
medium
0
1
1/4
most
1
0
3/4
least
1
1
reserved
reserved
SRAM Early Latch Enable : Default = 0. Set to enable.
X4 FIFO Early Latch Enable : Defautl = 0. Set to enable.
DREQB NEW Timing Enable : Default = 0. Set to enable.
Reserved (Reg34h/35h/36h/37h), R/W
Bit
34.7-0
35,7-0
36.7-0
38.8-0
34.7-0
35,7-0
36.7-0
37.7-0
Symbol
Reserved
Description
Reserved
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Reserved (Reg39h/38h), R/W, default=0000h
Bit
38.7-0
39.7-0
Symbol
Reserved
Reserved
Description
Reserved (Reg3Ah), default=00h
Bit
3A.7-0
Symbol
Reserved
Description
Link Partner Link Code Register : LPC, Reg3Bh, RO
Bit
3B.0
3B.1
3B.2
3B.3
3B.4
3B.5
3B.6
3B.7
Symbol
LPC[0]
LPC[1]
LPC[2]
LPC[3]
LPC[4]
LPC[5]
LPC[6]
LPC[7]
Description
Link Partner Link Code A0 : 10 Base-T half duplex ability
Link Partner Link Code A1 : 10 Base-T full duplex ability
Link Partner Link Code A2 : 100 Base-TX half duplex ability
Link Partner Link Code A3 : 100 Base-TX full duplex ability
Link Partner Link Code A4 : 100 Base-T4 ability
Link Partner Link Code RF bit : Remote Fault bit
Link Partner Link Code Ack bit : Acknowledge bit
Link Partner Link Code NP bit : Next Page bit
TX/RX DMA Status Register: Reg3Ch, R/W, default=00h
Bit
3C.7-4
Symbol
TXDMA[3:0]*
3C.3-0
RXDMA[3:0]*
TXDMA[1:0]
00
01
10
11
Description
TX DMA State Indicators : For internal diagnostic purpose indicating TX DMA's
current status.
TXDMA3 is TX status error bit, set to indicate error during transmission.
TXDMA2 is TX FIFO underflow error.
RX DMA State Indicators : For internal diagnostic purpose indicating RX DMA's
current status.
RXDMA3 is RX status error bit, set to indicate error during receive.
RXDMA2 is RX FIFO overflow error.
State Description
Idle
Read TX Description
Transmit Current Packet
Write TX Description
RXDMA[1:0]
00
01
10
11
P/N:PM0729
State Description
Idle
Receive Current Packet
Write TX Description
Run Frame/Reset RX FIFO
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MISC Control Register : MISC1, Reg3Dh, R/W, default=3Ch
Bit
3D.0
3D.1
Symbol
BURSTDMA
DISLDMA*
3D.2
TPF
3D.3
TPH
3D.4
TXF
3D.5
TXH
3D.6
TXFIFORST
3D.7
RXFIFORST
Description
reserved for internal DMA burst control, default = 0 after reset.
Disable Local DMA arbitration : Default is 0 after reset, meaning local DMAs are
enabled in the SRAM bus arbitration. Set to disable the local DMA arbitration only
when the Reg02h.0 TEST bit is also set. It is used to force the overrun or the
underrun error for the test purpose.
10 Base-T Port Full Duplex capability bit in the linkcode word : Default is set to
enable advertising the 10 Base-T Full duplex capability. Reset to disable advertising this capability in the outgoing NWAY's linkcode word.
10 Base-T Port Half Duplex capability bit in the linkcode word : Default is set to
enable advertising the 10 Base-T Half duplex capability. Reset to disable advertising this capability in the outgoing NWAY's linkcode word.
100 Base-TX Full Duplex capability bit in the linkcode word : Default is set to enable
advertising the 100 Base-TX Full duplex capability. Reset to disable advertising
this capability in the outgoing NWAY's linkcode word.
100 Base-TX Half Duplex capability bit in the linkcode word ; Default is set to
enable advertising the 100 Base-TX Half duplex capability. Reset to disable advertising this capability in the outgoing NWAY's linkcode word.
TX FIFO Reset control : Writing a 1 to this bit will clear the TX FIFO, reset all the
current TX FIFO's internal pointers and related byte counters and bring the TX DMA
back to the idle state. After reset this bit to 0, GMAC starts normal operation. If
current transmission takes too long due to collisions, the software can use this bit
to abort "current transmission" and bring GMAC's TX DMA back to idle state for a
fresh new transmission.
RX FIFO Reset control : Writing a 1 to this bit will clear the RX FIFO, reset all the
current RX FIFO's internal pointers and related byte counters and bring the RX
DMA back to the idle state. After reset this bit to 0, GMAC starts normal operation.
TX FIFO Byte Counter (Direct FIFO Mode) : TXFIFOCNT, Reg3F/3Eh, R/W
Bit
3E.7-0
3F.3-0
Symbol
TXFIFOCNT[7:0]
Description
TX FIFO Send Byte Count bit [7:0]: Together with TXFIFOCNT[11:8] forms a 12
bits TX FIFO byte count for direct FIFO mode.
TXFIFOCNT[11:8] TX FIFO Send Byte Count bit [11:8]: Together with TXFIFOCNT[7:0] forms a 12
bits TX FIFO byte count for direct FIFO mode.
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MX98726EC
Reser ved ( Reg 40h-43h ), RO
Bit
Reserved
Symbol
Description
Register 40h[7:0] to register43h[7:0] are all reserved.
ID1 (Reg45h/44h), RO, default="MX"
Bit
44.7-0,
45.7-0
Symbol
Description
ID1[15:0]
ID1 16 bit code : Reg45h is MSB byte is set to "M", Reg44h is LSB byte is
set to "X".
ID2 (Reg46h/47h), RO, default="0001"
Bit
46.7-0,
47.7-0
Symbol
ID2[15:0]
Description
ID2 16 bit code : Reg47h is MSB byte is set to 00h, Reg46h is LSB byte is
set to 01h.
Write TX FIFO Data Port: WRTXFIFOD (Reg48h), WO
Bit
48.7-0,
Symbol
WRTXFIFOD[7:0]
49.7-0,
4A.7-0
4B.7-0
Reserved
Reserved
Reserved
Description
Write TX FIFO Data Port: Data written to this port is directly forward to TX
FIFO, GMAC will keep track of total bytes written to FIFO. ST1,ST0 should
be in IDLE state when a packet is started to be written through this port.
Don't mix the write to this port with TX DMA start command, this may intermix data coming from this port and TX local DMA from packet memory.
IO Read Data Port: Register : Reserved, RO
Bit
4C.7-0,
4D.7-0
4E.7-0
4F.7-0
Symbol
Reserved
Reserved
Reserved
Reserved
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MX98726EC
MISC Control Register 2 : MISC2, Reg50h, R/W, default=00h.
Bit
50.0
50.1
50.2
Symbol
Reserved
Reserved
RUNTSIZE
50.3
50.4
50.5
50.6
Reserved
Reserved
ITPSEL
A19A16EN
50.7
AUTORCVR
Description
Runt Frame Size Select bit : Default is 0, meaning the runt frame is defined
as less than 64 bytes. Set to define the runt frame as less than 60 bytes.
reserved for internal test probing select.
Default=0, A19 to A16 are internally grounded. Set this bit to enable A19 to
A16 decoding. This bit is ignored if MIISEL = 1 in MII mode.
Auto RX Full Recovery: Default is reset meaning when RX buffer full and
RX FIFO overflow happen at the same time, GMAC will stop receiving until
host clear up RX FIFO and RX full condition. Set to enable GMAC to recover from such error automatically , the last packet with such error will be
discarded in the packet memory and RX FIFO will be cleared at the end of
current receiving, and then receiving is resumed for next packet.
Host Receive Packet Counter : Reserved, RO
Bit
52.7-0
53.7-0
Symbol
Reserved
Reserved
Host DMA Fragment Counter : Reserved, RW
Bit
54.7-0
55.7-0
56.7-0
Symbol
Reserved
Reserved
Reserved
P/N:PM0729
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MX98726EC
4.0 Host Communication
ON CHIP REGISTERS ADDRESSING SCHEME
The transmit and receive buffers must be contiguous
and separated by the BP ( Boundary Page pointer ) defined in registers 0Ah and 0Bh. TLBP ( Transmit Low
Boundary Pointer ) defines the start page of the transmit
buffer. BP- 1 defines the end page of the transmit buffer.
If the current transmit process exceeds the end of BP- 1
page then it will be set to the start page pointed by TLBP,
thus forms a "ring buffer" that logically links the end
page back to the start page of transmit buffer.
MIO=1 and CSB=0, memory space page0 (from
00000h00 to 000ffh) is used for GMAC's on chip register. Therefore, page0 of memory mapped scheme is always recerved for GMAC's on chip registers and can
not be used as part of packet buffer. So that usable free
packet buffer of a 64K SRAM is actually 64K bytes 256 bytes if GMAC's on chip registers occupied memory
page0.
Receive buffer has a similar structure as transmit buffer.
The start page of receive buffer is pointed to by BP
while the end page is pointed to by RHBP ( Receive
High Boundary Page Pointer ). If current receive process exceeds the end of the end page pointed by RHBP,
then it will be set to the start page pointed by BP, thus
forms a "ring buffer" that logically links the end page
and the start page of receive buffer.
if MIO=0 and CSB=0, then I/O space is used to decode
GMAC's on chip register access. IOB page register is
initially 0 force GMAC to use page 0 of I/O space as
GMAC's on chip register's page.
After changing IOB to a desirable page address, GMAC's
on chip registers address can be relocated to other page
for system integration. Such IO addressing scheme for
GMAC on chip register can avoid the waste of SRAM's
page 0 issue described above.
MORE RECEIVE BANDWIDTH WITHOUT USING TX
RING BUFFER
GMAC and the device driver communicate through three
data structures :
* On chip registers described in Chapter 3.
* Descriptor and data buffer resides in packet memory.
* Direct IO port to on chip TX FIFO for direct packet
transmission.
A 1.6K bytes TX FIFO can also be used to send out a
packet directly from FIFO. Register port 48h can be used
by host to write packet data directly into TX FIFO. After
moving the last byte into the TX FIFO of a packet, host
can issue a command (called TX FIFO send command)
to send out the packet stored in the TX FIFO. This function can be used alternately with the other transmission
that uses TX buffer ring.
TX RING BUFFER AND RX RING BUFFER
All incoming and outgoing packets are stored in these
buffers. Long packet may occupy multiple pages that
are logically contiguous. The descriptor is located at the
beginning of the first page of this multiple-page packet.
Normally there might be some free space left in the last
page of this multiple-page packet which is called fragment. These fragment will not affect network packet's
data integrity.
GMAC moves received data frames to the receive buffer
in the local packet memory and transmits data from the
transmit buffers in the local packet memory. All the page
pointers in the registers together with the descriptors
acts as pointers to these buffers in the packet memory.
Figure 4.0 depict the general data structure of packet
memory and page pointers.
There are two data buffers inside the packet memory,
i.e. transmit buffer and receive buffer. Packet memory
is partitioned into pages, each page contains exactly
256 bytes. A page pointer defined by registers acts as
the base address of the corresponding page. By programming these page pointers, size and area of transmit buffer and receive buffer can be individually set to
desirable size and area.
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Descriptor structure
7
Byte 0
4
Next Packet Pointer
Host Useable Area
0
TLBP
Byte 1
Descriptor
(Header) Page 0
Page 1
Byte 2
Packet Length
Byte 3
Status
TWP
Tx ring
TRP
One packet
Page 0 (Data)
Page 1 (Data)
BP
Page N (Data)
Rx Buffer
RWP
Next packet
RRP
RHBP
uP usable area
Figure 4.0 Packet Buffer Data Structures
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4.1 Packet Transmission
GMAC supports two ways to prepare packet(s) for transmission, one way is the host can write a packet directly
into TX FIFO through an IO port and send the packet
directly from FIFO, this way is called direct FIFO mode.
The other way is to write packet(s) into TX buffer ring in
the packet memory and activate TX local DMA to send
out packet(s). Using direct FIFO mode can eliminate
TX local DMA completely which will leave packet
memory's total bandwidth to RX local DMA and host.
Therefore, receiving at the full line speed is more achievable in this way. The disadvantage is that only one packet
is prepared and sent out at a time, next packet must
wait until current packet is sent out and FIFO is empty
before it can be moved into TX FIFO. In another word,
you can not issue multiple packet transmission with a
single command. But you still can prepare new packet(s)
in TX buffer ring while a packet in direct FIFO mode is
still active, so once the packet in direct FIFO mode is
finished, you can active TX DMA right away.
been finished for current packet's transmission. Register 00h.ST1 and ST0 bits are both command and status, before host issues any packet send command. Always read these two bits and make sure they are both 0
which indicate a transmit cnahhel IDLE ( FIFO is also
empty ). The rule of the mixed modes is always activate
one mode at a time, ST1 and ST0 must be both 0 before the other mode is used.
Prior to transmission in direct FIFO mode
When ST1 and ST0 bits are both 0, host can write a
packet no longer than 1518 bytes through IO port register 48h. GMAC will record the byte count. Since register
48h is write only port, it can not be read. Before the
entire packet is completely inside FIFO, host can do
other operations except activating TX local DMA. Issuing TX local DMA before current direct FIFO write operations or TX FIFO send completion will "corrupt" current packet inside TX FIFO. When the entire packet is in
the FIFO, host can issue ST1=1 and ST0=0 ( TX FIFO
send command ). When this packet is sent out completely, transmit status will be recorded in register 04h
and both ST1 and ST0 are cleared to 0 to indicate IDLE
state.
The TX local DMA mode is used between GMAC and
packet memory during transmission of packet. TRP (
Transmit Read Page pointer ) is used by local DMA to
fetch the first page of the desired packet in the packet
memory. When GMAC receive a TX DMA send command ( register 00h.ST1=0, ST0=1 ), data in the packet
memory will be moved into GMAC's transmit FIFO.
GMAC will append preamble, sync and CRC field during the actual tranmission. The advantage of this mode
is multiple packets can be processed with a single
comannd, also new packet(s) can be prepared while
TX local DMA is active. Therefore, potential higher
through-put of TX channel can be achieved. The disadvantage is packet memory bandwidth is now shared by
host, TX channel and RX channel. This means bandwidth might not be enough for all three to run at their full
speed which may result in TX FIFO underrun, or RX
FIFO overrun and slow host accesses, especially in a
system where you only have a 8 bit packet memory.
Prior to transmission in TX local DMA mode
The transmit descriptor located at the beginning of the
first page of the desired packet in the packet memory
must be properly set by device driver prior to a transmit
command. By using TWP ( Transmit Write Page Pointer
), device driver can fill up packet(s) in the transmit buffer
ring. For single packet transmission, the Next Packet
Page Pointer field should be equal to TRP page pointer
which links to the current packet itself. If multiple packets are to be transmitted, then Next Packet Page Pointer
field of transmit descriptor should be set to the start
page of next packet. Current Packet Length ( in byte ) is
set to indicate the size of current packet. Transmit Status bit 7 ( OWN bit ) of the descriptor needed to be set
to 1 to indicate that device driver has finished preparing
the current packet. Then the packet can be transferred
to GMAC for transmission. At this point, transmit command can be issued by setting Reg00h.ST1=0, ST0=1
( TX DMA poll command ) to activate transmit operation. ST1 and ST0 bits will be cleared to 0 when transmission is done.
It may be desireable to mix both direct FIFO mode anf
TX local DMA mode so that bandwidth of packet memory
and convenience of concurrent processing of mutiple
packets can be compromised for the best interest of the
system's performance. Some cautions should be taken
when you using mixed mode. Do not write to FIFO while
TX local DMA is active, because such write will corrupt
whatever packet being transmitted in the FIFO. Do not
activate TX local DMA while direct FIFO send has not
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During the process of filling up packet(s) in the transmit
buffer ring, current write address to TX buffer ring is
mapped directly from uP's address lines during uP write
to packet buffer. TWP is updated by driver only and TWP
is used to be checked against TRP,BP,TLBP by both
GMAC and driver to maintain TX buffer ring's integrity.
Collision recovery
During transmission, if a collision is detected before the
first 64 bytes of packet has been transmitted, the FIFO
will restore the necessary FIFO pointers to retransmit
the same packet without fetching the transmitted data
from packet memory. An out-of-window collision is a
collision occured after 64 bytes of data transmitted. If
out-of-window collision occurred, packet will be aborted
with interrupt asserted. OWC bit of transmit descriptor
is set and device driver needs to resolve such situation
and reissue a transmit command so that GMAC can
fetch the entire packet from packet memory again for
retransmission.
Packets between TRP and TWP will be transmitted by
GMAC if TX DMA poll command is issued. TWP serves
as the start page of non-ready packet(s) which is still
being prepared by driver.
Condition required to begin transmission
1. Register 00h.ST1=0 and Reg00h.ST0=1 for TX local
DMA mode or register 00h.ST1=1 and ST0=0 in direct FIFO mode
2. The interframe gap timer has timed out.
3. TX FIFO is filled with a complete packet or is full.
4. If a collision has been detected and backoff timer
has expired.
Collision count will be recorded for the current packet in
register 04h.CC[3:0] bits. If 15 retransmission each result in a collision, the transmission is aborted and collision count CC[3:0]=1111 and an interrupt will be asserted and TEI interrupt bit is set to indicate such a excessive collision error. If TI interrupt bit is set, then packet
is successfully transmitted with collision count=CC[3:0].
After packet is started to go out to network, TTHD[1:0]
will begin to affect packet memory's arbitration if FIFO
needs more data from packet memory. ( TTHD is not
used in duirect FIFO mode ) In the TX local DMA mode,
the advantage of smaller threshold is to reduce the risk
of a potential transmit FIFO underrun error. Such
underrun error occurres when data in FIFO is exhausted
by transmit while local DMA still has not filled in more
data to be transmitted. Since TX FIFO is large enough
for the largest normal packet ( 1518 bytes ), therefore,
the TTHD and FIFO underrun applied to packets larger
than 1518 bytes in the TX local DMA mode. The larger
the TTHD, the less aggressive the TX DMA in packet
memory arbitration, therefore host and RX DMA may
have more bandwidth in packet memory.
After single packet transmission
When a packet(s) transmission is completed, register
00h.ST1 and ST0 are both cleared to 0 automatically
by GMAC. Whenever the first packet is sent out, interrupt is asserted for host's attention. Device driver can
process this packet's status. In TX local DMA mode,
first thing to check is making sure the OWN in the status field bit 7 is 0 which indicates that GMAC has completed the transmission of this packet and the status is
valid. Or in direct FIFO mode, check ST1 and ST0 for
both 0 which indicates completion of previous transmission. At this point, device driver can proceed with transmit status and other book keeping tasks.
For successful transmission, interrupt is caused by interrupt register bit TI ( bit 2 of register 09h ) of interrupt
register IR, provided that the corresponding enable bit
TIM ( bit 2 of register 08h ) of interrupt enable register
IMR is set. In case that an error occured during the transmission, Interrupt register bit TEI will be set instead of
TI. Register 09h bit 4 ( TEIM ) is the interrupt enable bit
for TEI. Set TEIM will enable TEI interrupt.Transmission
error can be read from register 04h ( LTPS register )
which records the transmit status of the last packet transmitted. If bit 7 ( TERR ) of register 04h is set then TEI
will be set as well. TERR is a logical OR of underrun
error( UF bit ). out-of-window collision error ( OWC bit ),
carrier lost error ( CRSLOST bit ) and excessive collision error ( CC[3:0]=1111 and TEI = 1).
When this underrun occurres, packet will be aborted
and interrupt will be asserted to get host's attention.
FIFOEI ( register 09h bit 5 ) interrupt bit will be set when
underrun occures and interrupt to host is asserted if
FIFOEIM bit (register 08h bit 5 ) is also set.
So TTHD can be tuned to improve the target system for
best through put in TX local DMA mode.
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Multiple packets transmission ( TX local DMA
mode only )
Transmit packet assembly format in packet
memory
If more packets are prepared in the packet memory and
all transmit descriptors are set properly ( i.e. next packet
page pointer, packet length, OWN bit = 1) then a transmit command can send out all these packets in a row.
As soon as the first packet transmission is done, interrupt will be asserted to get host's attention. Device driver
can serve this interrupt call by processing all the packets that have OWN bit equals to zero in this multiple
packets list in packet memory. Device driver can "peek"
the OWN bit of next packet's descriptor to see if there
are more packet(s) transmitted completely at that point.
If OWN bit of next packet's descriptor is zero, then device driver can proceed to next packet after finishing
the current packet. When all packets are transmitted
successfully or aborted, register 00h. ST1 and ST0 bits
are internally reset. This way, packets can be send out
in a burst with single transmit command.
For 16 bit SRAM interface :
D15
D8
D7
D0
Descriptor Byte 1
Descriptor Byte 0
Descriptor Byte 3
Descriptor Byte 2
Destination Address Byte 1
Destination Address Byte 0
Destination Address Byte 3
Destination Address Byte 2
Destination Address Byte 5
Destination Address Byte 4
Source Address Byte 1
Source Address Byte 0
Source Address Byte 3
Source Address Byte 2
Source Address Byte 5
Source Address Byte 4
Type/Length byte 1
Type/Length byte 0
Data byte 1
Data byte 0
For 8 bit SRAM interface :
D7
D0
Descriptor Byte 0
Descriptor Byte 1
Descriptor Byte 2
Descriptor Byte 3
Destination Address Byte 0
Destination Address Byte 1
Destination Address Byte 2
Destination Address Byte 3
Destination Address Byte 4
Destination Address Byte 5
Source Address Byte 0
Source Address Byte 1
Source Address Byte 2
Source Address Byte 3
Source Address Byte 4
Source Address Byte 5
Type/Length byte 0
Type/Length byte 1
Data byte 0
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Transmit descriptor format
Bit
0
1
2
3
Symbol
CC0
CC1
CC2
CC3
4
CRSLOST
5
UF
6
OWC
7
OWN
Description
Collision Count Bit 0 :
Collision Count Bit 1 :
Collision Count Bit 2 :
Collision Count Bit 3 : when CC[3:0] = 1111 and TEI interrupt bit is set, , then it is called
excessive collision error which will abort the current packet. If TI interrupt bit is set, then
CC[3:0] is the collision count and packet is transmitted successfully.
Carrier Sense Lost : Network carrier signal was lost at some point during the transmission or lost during entire duration or transmission.
TX FIFO underflow : TX FIFO is exhausted before TX DMA fill in more data for transmission.
Out of Window Collision : A collision occured after 64 bytes of data had been transmitted. This packet will be aborted.
Packet Buffer ownership indicator:
1: indicate GMAC has access right to current packet's buffer
0: indicate host has access right to current packet's buffer
There are 4 bytes in a descriptor structure for both transmit and receive packet. Transmit descriptor is prepared by
device driver before transmitting the packet. The transmit descriptor format is defined as follows :
bit 7
Next Packet Page Pointer ( bit 7-4 )
Packet Length ( bit 3-0 )
Packet Length ( bit 11-8 )
Transmit Status ( bit 7-4 )
bit 0
Next Packet Page Pointer ( bit 3-0 )
Next Packet Page Pointer( bit 11-8 )
Packet Length ( bit 7-4 )
Transmit Status ( bit 3-0 )
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4.2 Packet Reception
The local DMA receive channel uses a receive buffer
ring structure comprised of a series of contiguous fixed
length 256-byte ( 128 word ) buffers for storage of received packets. The location of this receive buffer ring is
programmed in two page pointers, a Boundary Page
pointer and a Receive High Boundary Page pointer.
Ethernet packets consist of a distribution of shorter link
control packets and longer data packets, the 256-bytes
buffer length provides a good compromise between different packet sizes to best utilizing the memory. Receive
buffer ring provides storage for back-to-back packets in
a loaded networks. The assignment of buffers for storing packets in managed by GMAC's receive DMA logic.
Three basic functions are provided by the receive DMA
logic : linking receive buffers for long packets, recovery
of buffers when a packet is rejected and recirculation of
buffer pages that has been read by the host.
Packet Memory
BP
4
BUFFER 1
BUFFER 2
3
BUFFER 3
n-2
RHBP
PAGE
n-1
2
n
1
256 BYTES
Figure 4.2.1 GMAC Receive Buffer Ring
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Initialization of receive buffer ring
Beginning of reception
Two static page pointer and two working page pointers
control the operation of the receive buffer ring . These
are Boundary Page ( BP ) pointer, Receive High Boundary Page ( RHBP ) pointer, the Receive Read Page (
RRP ) pointer and Receive Write Page ( RWP ) pointer.
BP register points to the first buffer ( page ) of the receive buffer ring. RHBP points to the last page of receive buffer ring. RWP register points to the page in
which receive DMA logic is storing incoming network
data. RRP register points to the page from which host
will read next network data. A receive descriptor structure is located at the beginning of the start page of a
received packet. If GMAC ever reach the page pointed
by RHBP register, it will link the page pointed by BP
register as next page, thus forms a “ ring” buffer structure.
After all four page pointers are properly set by device
driver ( host ), register bit NCRA.SR bit can be set to
enable reception of packets. When the first packet begins arriving the GMAC begins storing packet at the location pointed to by the RWP register. An offset of 4
bytes ( descriptor ) is saved in this first page to store
receive status corresponding to this packet. Whenever
internal byte counter reaches FFh indicating end of a
page, RWP will be incremented by 1 automatically if
more data is arriving for this packet.
The incoming network address is examined by GMAC
to determine whether to accept or reject. If GMAC decided to reject the packet, then receive FIFO will be restored and so is the buffer used. If packet should be
accepted and FIFO contains data up to a threshold level
which can be programmed by RTHD[1:0] ( register 33h
bit [3:2] ). The smaller the threshold, the earlier the receive DMA logic removing data from FIFO, thus may
has lower risk in running into a FIFO overflow situation.
The disadvantage of a smaller threshold is that host
and transmit channel may be less efficient. So threshold should be chosen to tune for best network throughput. Default value of receive FIFO threshold is 00 meaning 50% of the FIFO is filled up before any receive local
DMA can start removing data out of FIFO.
The size of receive buffer ring is the total buffer space
between BP and RHBP register. An internal 8 bit byte
counter accounts for MA[7:0] will be used with RWP
register to form a physical memory address during receive DMA write operation. This internal 8 bit counter
will tracks the actual location within a page. After GMAC
is initialized, BP, RWP and RRP should all points to the
same page. These registers must be properly initialized
before setting NCRA's ( register 00h ) SR ( bit 3 ) bit to
one which enables the receive channel for DMA function.
Linking receive buffer pages
If packet length exhausts the first 256-bytes buffer, receive DMA logic will performs a forward link to the next
buffer to store the remainder of the packet. A maximum
length packet , up to 6 buffers can be linked together.
Buffers can not be skipped when linking, therefore a
packet will always be stored in contiguous buffers. Before the next page can be linked, receive DMA logic
does two comparisons.
4
3
n-2
Receive Write
Page Pointer
Receive High
Boundary
Page Pointer
Boundary
Page Pointer
The first comparison tests the equality between content
of RWP register + 1 and content of RRP register. If equal,
the reception is aborted. This is called receive buffer full
error. Second comparison tests the equality between
RWP register and RHBP register. If equal, the receive
DMA will restore RWP to the first buffer in the receive
buffer ring pointed by BP register if receive buffer ring is
not full.
Receive Read
Page Pointer
2
n-1
n
1
256 BYTES
Figure 4.2.2 GMAC Receive Buffer Ring at Initialization
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The following procedure is required for device driver to
recover from such error situation.
1. Issue the SR=0 ( NCRA register bit 3 ) which will stop
RX channel to prevent new data from coming into RX
FIFO.
4
3
n-2
2. Issue RX FIFORST to clean RX FIFO.
Receive Write
3. Remove all the received packets in the packet memory.
When buffer ring is empty, RRP=RWP.
Begin Storing
Packet
Page Pointer
n-1
2
4. Clear all receive related interrupt flags and then set
the SR bit=1 to resume the receive operation.
1
n
Successful reception
Begin Data
Reception
Based on the network address filtering modes set up by
the device driver, GMAC will determine whether to receive a packet or to reject it. It either branches to a
routine to store the packet or to another routine to reclaim the buffers used to store packet. If a packet is
successfully received, GMAC will store the receive status, packet length and next packet pointer in the receive
descriptor located at the beginning of the first page of
the packet and status in LRPS ( register 05h ) register.
Note that the remaining bytes in the last page are discarded and reception of the next packet begins on the
next empty 256-byte page boundary. The RWP is then
set by GMAC to the next available page in the buffer
ring.
4 Byte Offset For
Packet Descriptor
Figure 4.2.3 Received Packet Enters the Receive Buffer Pages
Receive buffer ring full
In a heavily loaded network which may cause overflow
of the receive buffer ring, when the last available page
is exhausted and more data needs to be stored for the
current packet then the receive buffer ring is full but
GMAC will continue receiving until RX FIFO is also overflow. At this point, GMAC will do the following actions :
Rejected packets
1. Close current received packet with the FO bit ( bit 3 )
and the BF bit ( bit 0 ) of the receive descriptor being
set if a minimum of one page is used by this packet.
If the packet is a runt packet and PB bit ( Pass Bad
option, register 01h, bit 3 ) is reset then it is rejected.
The buffer previously used by this rejected packet is
reclaimed by resetting the internal byte counter to zero
automatically by GMAC. Packet with at least 64 bytes
are always received and stored regardless of CRC error
status.
2. An interrupt may be asserted if the RBFI ( register
09h bit 7 ) interrupt bit is set and the RBFIM bit (
register 08h bit 7 ) is also set.
3. If AUTORCVR is reset, then GMAC can not receive
any more packet. All following packets will be lost
and MPC ( Missed Packet Counter ), registers 07h
and 06h, will be increment automatically. MPC can
be reset by the device driver.
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Host page registers RRP and TWP are maintained by
driver only. It is recommended that only when a packet
has been removed from RX buffer ring, RRP is then
incremented by driver so that GMAC will not overwrite a
page which belongs to an unprocessed packet. The following is a suggested method for maintaining the receive buffer ring pointer :
Receive Write
Page Pointer
Packet
Ends
4
3
n-2
,,
,,
1. At initialization, set up BP= RRP=RWP and RHBP to
a higher memory page. At the point, receive buffer is
empty.
Next Package Page Pointer
Packet Length
Receive Status
n-1
n
2. Set a software address counter and byte counter, byte
counter's LSB byte is reset. The MSB bits [19:8] of
the address counter will start from current RRP register, and keeping track of current page, once a packet
is removed, then RRP register is updated to next page
location.
2
1
Packet Status
3. After a packet is stored in the receive buffer ring,
GMAC issue interrupt. Device driver will start moving
data beginning from the page pointed by RRP register. Reads the packet length and advanced the address counter as the host DMA goes along. Care
should be taken if manual page pointer update is used
when RHBP page is exhausted or buffer is full.
Receive Read
Page Pointer
Figure 4.2.4 Termination Of Received Packet-Packet Accepted
Removing packets from the buffer ring
Packets are removed from the ring by the host using the
direct host DMA. The actual packet memory address
during host DMA is mapped directly from uP address
lines. i.e. Host has to control all the addresses during
the packet buffer accesses directly. By reading the descriptor device driver will know the size of packet and it
can move data up to the last page without updating RRP
register. The RRP register will be updated by driver only
whenever a packet has been removed. Driver must properly update RRP to next available page, especially if
RHBP page is exhausted. in this case, next page should
be wrapped around to the beginning ( pointed by BP register ) of RX buffer ring.
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Receive packet assembly format in packet
memory
For 8 bit SRAM interface :
D7
D0
Descriptor Byte 0
Descriptor Byte 1
Descriptor Byte 2
Descriptor Byte 3
Destination Address Byte 0
Destination Address Byte 1
Destination Address Byte 2
Destination Address Byte 3
Destination Address Byte 4
Destination Address Byte 5
Source Address Byte 0
Source Address Byte 1
Source Address Byte 2
Source Address Byte 3
Source Address Byte 4
Source Address Byte 5
Type/Length byte 0
Type/Length byte 1
Data byte 0
For 16 bit SRAM interface :
D15
D8
D7
D0
Descriptor Byte 1
Descriptor Byte 0
Descriptor Byte 3
Descriptor Byte 2
Destination Address Byte 1
Destination Address Byte 0
Destination Address Byte 3
Destination Address Byte 2
Destination Address Byte 5
Destination Address Byte 4
Source Address Byte 1
Source Address Byte 0
Source Address Byte 3
Source Address Byte 2
Source Address Byte 5
Source Address Byte 4
Type/Length byte 1
Type/Length byte 0
Data byte 1
Data byte 0
Receive status in descriptior
PIN#
0
1
2
Symbol
BF
CRC
FAE
3
4
5
6
FO
RW
MF
RF
7
RERR
Description
RX Packet Buffer Full Error : 1 indicates RX packet buffer is full.
CRC error : caused by corrupted data or dribble byte (s).
Frame Alignment Error : Dribble nibble (s), FAE error might not cause CRC error (e.g.
only a dribble nibble is detected by GMAC). FAE error will not set RERR bit.
FIFO overrun
Receive Watchdog : Set to indicate the frame length exceeds 2048 bytes.
Multicast address : Set to indicate current frame has multicast address.
Runt Frame : Set to indicate a frame length less than 64 bytes, only meaningful when
Reg00h.4 (PB bit)=1 is set.
Receive Error : a logical OR of CRC, FO, BF, RW, RF bit.
There are 4 bytes in a descriptor structure for both transmit and receive packet. Transmit descriptor is prepared by
device driver before transmitting the packet. The transmit descriptor format is defined as follows :
bit 7
Next Packet Page Pointer ( bit 7-4 )
Packet Length ( bit 3-0 )
Packet Length ( bit 11-8 )
Transmit Status ( bit 7-4 )
bit 0
Next Packet Page Pointer ( bit 3-0 )
Next Packet Page Pointer( bit 11-8 )
Packet Length ( bit 7-4 )
Transmit Status ( bit 3-0 )
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4.3 Packet Structure and 802.3 conformance
Network speed may be 10 MBPS or 100 MBPS mode. Further more, GMAC supports full duplex mode where
transmit and receive process are running independently. A typical Ethernet frame structure is shown below.
Ethernet and IEEE 802.3 Frames
An Ethernet frame format consists of the following:
Field
Description
Preamble
A 7-byte field of 56 alternating 1s and 0s, beginning with a 0.
SFD
A 1-byte field that contains the value 10101011; the MSB is transmitted and received first.
Destination
A 6-byte field that contains the specific station address, the broadcast
address. or a multicast address where this frame is directed.
Source
A 6-byte field that contains the specific station address where this frame was sent.
Type/Length
A 2-byte field that indicates whether the frame is in IEEE 802.3 format or Ethernet format. A
field greater than 1500 is interpreted as a type field, which defines the type of protocol of
the frame. A field smaller than or equal to 1500 isinterpreted as a length field, which indi
-cates the No. of data bytes in the frame.
Data
A data field consists of 46 to 1500 bytes that is fully transparent. A data field
shorter than 46 bytes is allowed, unless padding is disabled (TDES1<23>).
CRC
A frame check sequence is a 32-bit cyclic redundancy check (CRC) value that is computed
as a function of the destination address field, source address field, type field and data field.
The FCS is appended to each transmitted frame, and used at reception to determine if the
receive frame is valid.The figure shows the Ethernet frame format.
Ethernet Frame Format
Preamble
SFD
Destination
Address
(7)
(1)
(6)
Source
Address
(6)
Type/
Length
(2)
Data
(46...1500)
CRC
(4)
*Numbers in parentheses indicate field length in bytes.
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The CRC polynomial, as specified in the Ethernet specification, is as follows:
FCS(X) = X31 + X26 + X23 + X22 + X16 + X12 + X11 + X10 + X8 + X7 + X5 + X4 + X2 + X1 + 1
The 32 bits of the CRC value are placed in the FCS field so that the X31 term is the right-most bit of the first octet, and
the X0 term is the left-most bit of the last octet. The bits of the CRC are thus transmitted in the order X31,X30,....X1,X0.
4.4 Network Address Filtering
The first bit of the destination address signifies whether it is a physical address or a multicast address. The receive
MAC filters the frame based on the address filtering option described below. Register 01h ( NCRB ) bit 0 is PR (
Promiscuous mode ) and bit 2 is PM ( Pass Multicast ) are used to control the desired address filtering options.
Possible Address Filtering Options ( all independent of each other options )
option
1
2
3
4
Description
One physical address perfect filtering , always enabled
Unlimited multicast addresses imperfect filtering using hash table.
Pass all multicast address
Promiscuous Ethernet reception, when set, all valid frames are reecived
If the frame address passes the network address filter, the receive MAC removes the preamble and delivers the
frame to the host processor memory. However, if the address does not pass the filter when mismatch is recognized,
the receive MAC terminates this reception.
GMAC Network Address Filtering
Index
Hash Table Array
MAR0-MAR7
(NOTE1)
31
26
47
0
32 Bit CRC
1
0
Destination Address
0
incoming
MAC ID
PAR0-PAR5
MAC ID
ID Compare
NCRB.AB
NCRB.PB
Address
NCRB.PM
Match
Logic
NCRB.PR
RX address match
Selected Bit
"0"=reject,"1"=accept
(NOTE1) Broadcast packet Is not filtered by hash table array.
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37
MX98726EC
GMAC's Network Address Filtering Flow Chart
LLC input
NO
Unicast
YES
(Multicast Packet)
NO
Broadcast
YES
Compare DA and
PAR(0x20-0x25)
NO
NO
Accept Broadcast
Reg0x1[4]=0
YES
YES
YES
Pass Multicast
0x1[2]=1
NO
A
B
Hash Filter
MART(0x26-0x2D)
NO
YES
A
Packet Accept
B
Packet Drop
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REV. 1.1, MAY. 28, 2001
38
MX98726EC
5.0 Host/Local DMAs and packet memory bus arbitration
If no one is critical, then round-robin
scheme is used in prioritization.
Host is critical
Host Access
(1st priority)
Host is critical
RX is critical & Host is not critical
Host is critical
TX is critical & No one else is critical
TX is critical & No one else is critical
TX DMA
(3rd priority)
RX is critical & Host is not critical
RX DMA
(2nd priority)
RX is critical & Host is not critical
TX is critical & No one else is critical
Packet Memory Bus Arbitration State Diagram
Rules of packet memory access prioritization
rule 1: TX local DMA is said to be "critical" if TX FIFO counter fall below TTHD level.
If TX packet is in "stored and forward" mode (TTHD[1:0]=11), then TX local
DMA is never critical.
rule 2 : RX local DMA is said to be "critical" if RX FIFO counter rise above RTHD level.
rule 3 : Host access is said to be "critical" if DINTVAL timer is time out.
rule 4 : If all three accesses are critical, then Host has 1st priority, RX local DMA has 2nd priority and TX local DMA
has last priority. If no one is critical, then round-robin is used.
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REV. 1.1, MAY. 28, 2001
39
MX98726EC
5.1 Host DMA
cal" then receive DMA will have higher priority over transmit DMA (regardless of whether transmit FIFO is critical or not). If FIFO is not over RTHD level, it is not
critical, then transmit DMA may have equal priority as
receive DMA or higher priority over receive DMA if transmit FIFO is critical. The larger the receive threshold,
the less aggressive the receive DMA because it takes
more time for receive DMA to become critical but it also
presents a higher risk to become FIFO full or overrun
the FIFO space. The smaller the RTHD, the more aggressive the receive DMA is and less risk in running
into a FIFO full condition, but it also blocks other access
from host and transmit DMA. Since packet memory
bandwidth is shared by host, transmit DmA and receive
DMA, "tuning" RTHD threshold may be necessary for a
best network/system throughput.
The Host DMA channel is used to both assemble packets for transmission, and to remove received packets
from the receive buffer ring . Two registers RRP and
TWP are used to control host DMA. The physical address of these DMA are formed by the following rules
For 188/186 modes, HLDA must be 0 during host DMA
cycles ( HLDA=0 will disable local DMA temporarily ).
Two Page pointers ( RRP, TWP ) are to be maintained by
host for all host DMA ( packets accesses ).
Host write
Host write to packet memory is used to prepare a packet
for transmission. TWP register is used for addressing
the page address of the physical buffer. Update of TWP
can only be done by driver. HLDA must be low whenever the host DMA is running. SRDY is used to insert
wait states so that local DMA will finish at least one onchip FIFO burst transfer before host can complete current access cycle to packet buffer.
Receive FIFO burst length of Receive DMA
Receive FIFO burst length is defined by register 33h bit
[7:6] (RBLEN [1:0]) which control the number of data
transfers within each and every receive DMA cycle. e.g.
dufault receive burst length is 4 which means there will
be exactly 4 bytes (or 4 words) transferred in each receive DMA cycle. The larger the RBLEN, the more efficient the receive DMA transfer but it also cause transmit DMA and host DMA to wait more time for packet
memory bus release for new access. Tuning receive
FIFO burst length may be necessary for a best network/
system throughput.
Host Read
Host read to packet memory is used to remove a packet
for receive buffer ring. RRP register is used for addressing the page address of the physical buffer. Update of
RRP can only be done by driver. Again, HLDA must be
low whenever the host DMA is running. SRDY is used to
insert wait states so that local DMA will finish at least
one on-chip FIFO burst transfer before host can complete current access cycle to packet buffer.
Receive DMA
5.2 Local DMA
Receive DMA normally has higher priority over host and
transmit DMA. This is due to the receive data can not be
reproduced locally, therefore it is more urgent than others. Once receive DMA is granted an access to packet
memory, receive DMA conducts a burst write whose
length is defined by register 33h bit [7:6] (PBLEN [1:0]).
Only when current receive burst transfer is done, arbitrator will release the packet memory bus to next requester.
Receive FIFO threshold of Receive DMA
Receive FIFO threshold is defined by register 33h bit
[3:2] (RTHD[1:0]) is used to control the aggressiveness
of receive DMA request in packet memory bus arbitration operation. e.g. default value of RTHD=1/2 the depth
of receive FIFO which means whenever the content of
FIFO is over 1/2 of FIFO space (it is "critical" since FIFO
may soon be full or overrun), when receive FIFO is "criti-
P/N:PM0729
REV. 1.1, MAY. 28, 2001
40
MX98726EC
Transmit DMA
The physical address of receive DMA is formed by cascading a page address RWP register and an internal
byte counter for receive DMA. RWP [11:0] is mapped to
MA[19:8] while the internal byte counter is mapped to
MA[7:0]. Thus a 20 bit MA is derived. RWP will be automatically updated by GMAC whenever a page is exhausted. If RHBP is exhausted, GMAC will link BP as
the next available page into RWP if the BP page is free,
otherwise a receive buffer full error occures.
Transmit DMA normally has higher priority over host but
lower than receive DMA. Once a transmit DMA is granted
the access to packet memory, transmit DMA conducts
a burst read which is defined by TBLEN [1:0]. Only when
current burst transfer is done, arbitrator will release the
packet memory bus to next requester.
The physical address of transmit DMA is formed by cascading a page address TRP register and an internal
byte counter for receive DMA. RWP [11:0] is mapped
to MA[19:8] while the internal byte counter is mapped
to MA[7:0]. Thus a 20 bit MA bus is derived. TRP will be
automatically updated by GMAC whenever a page is
exhausted. If RHBP page is exhausted, GMAC will link
BP page as the next available page into TRP if the BP
page is free.
Transmit FIFO threshold of transmit DMA
Transmit FIFO threshold is defined by Register 33h bit
[1:0] (TTHD [1:0]). TTHD is used to control the aggressiveness of transmit DMA request in packet memory
bus arbitration. e.g. default value of TTHD=1/2 the depth
of transmit FIFO which means whenever the content of
FIFO falls below 1/2 of FIFO space, the transmit DMA
will have higher prority over receive DMA (if receive FIFO
is not critical). If transmit FIFO is over TTHD level, then
transmit may have equal priority as receive DMA or lower
priority to receive DMA (if receive FIFO is critical). The
larger the TTHD threshold, the less aggressive the transmit DMA because it takes more time for transmit DMA
to become critical of running empty. The small TTHD
will result in more aggressive transmit DMA but then it it
also more critical, i.e. it takes less time to run transmit
FIFO to empty ("underrun error). Since packet memory
bandwidth is shared by host, transmit DMA and receive
DMA, "tuning" TTHD may be necessary for a best network/system throughput.
Transmit FIFO burst length of transmit DMA
Transmit FIFO burst length is defined by register 33h bit
[5:4] (TBLEN [1:0]) which control the number of data
transfers within each transmit DMA cycle. e.g. default
transmit burst length is 4 which means there will be exactly 4 bytes (or 4 words) transferred in each transmit
DMA cycle. The larger the TBLEN, the more efficient
the transmit DMA cycle but it also cause transmit DMA
and host DMA to wait more time for a packet memory
bus release for new access. "Tuning" TBLEN may be
necessary for a best network/system throughput.
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REV. 1.1, MAY. 28, 2001
41
MX98726EC
6.0 Serial ROM ( EEPROM ) Interface
Serial ROM Connection
EESC
Serial ROM
(Micro Wire)
SK
EECK
CS
EEDI
DIN
GMAC
EEDO
DOUT
EEDI - Serial ROM (EEPROM) Data In = register 1Ch, bit2
EECK - Serial ROM (EEPROM) Serial Clock = register 1Ch,
bit 1
EECS - Serial ROM (EEPROM) Chip Select = register 1Ch,
bit 0
EESEL - must be set to enable EEPROM access by register
1Ch, bit 4
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REV. 1.1, MAY. 28, 2001
42
MX98726EC
EEDI
(from eeprom)
EEDO
Register 1Ch
EECS
EECK
MUX
EEDI
(to eeprom)
Auto Load
EEPROM Logic
Serial ROM Interface Block Diagram
EECS
EECK
EEDI
A5/A7
A0
EEDO
0
D15
D0
EEPROM Read Cycle
EECS
EECK
EEDI
A5/A7
A0
D15
EEDO
D14
D0
Busy
Ready
twp
EEPROM Write Cycle
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REV. 1.1, MAY. 28, 2001
43
MX98726EC
Autoload Function
The Autoload Function is executed only once after hardware reset (pin RSTB from low to high). At that time the
Serial ROM interface is controller by GMAC to load the
data from Serial ROM into GMAC.
EEPROM Content ( suggested )
Location
00H
01H
02H
Content
Physical Address Byte 0 : PAR[7:0] ( MSB )
Physical Address Byte 1: PAR[15:8]
Physical Address Byte 2 : PAR[23:16]
03H
04H
05H
06H
Physical Address Byte 3 : PAR[31:24]
Physical Address Byte 4 : PAR[39:32]
Physical Address Byte 5 : PAR[47:40]
GMAC Configuration A Register : GCA[7:0]
bit 0 : BPSCRM
bit 1 : PBW
bit 2 : SLOWSRAM
bit 3 : ARXERRB
bit 4 : MIISEL
bit 5 : AUTOPUB
bit 6 : TXFIFOCNTEN
bit 7 : reserved
reserved
Reserved for Software application
07H
08H-END
6.1 On-Chip Transceiver vs MII Interface
After system reset, GMAC enter its normal mode in which on chip 10/100 fast Ethernet tranceiver is used and
immediately Nway auto negotiation will start setting up link in the network. The option of using a 3rd party
tranceiver, such as 10/100 fast Ethernet tranceiver or HomePNA tranceiver is possible through the MII (Media
Independent Interface) interface. Even if both fast Ethernet connection and HomePNA connection are desired,
GMAC can allow user to switch between these two connection through register setup.
When MII mode is chosen, both Nway and on chip tranceiver are isolated from the internal MAC logic, so all data
are from and to through the MII interface.
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REV. 1.1, MAY. 28, 2001
44
MX98726EC
7.0 Timing Diagram and AC specification
SYMBOL
PARAMETER
12MHZ
16MHZ
24MHZ
40MHZ
MIN.
MAX.
MIN.
MAX.
MIN.
MAX. MIN.
MAX.
UNIT
tlp
Ale pulse duration
25
-
25
-
25
-
25
-
ns
tas
Address set-up time to ale
3
-
3
-
3
-
3
-
ns
tah
Address hold time after ale
5
-
5
-
5
-
5
-
ns
trp
RD pulse duration
38
-
38
-
38
-
38
-
ns
twp
WR pulse duration
38
-
38
-
38
-
38
-
ns
trd
RD to valid data input
-
20
-
20
-
20
-
20
ns
tdhr
Data hold time after RD
0
-
0
-
0
-
0
-
ns
tlrw
Time from ale to RD or WR
50
-
50
-
50
-
50
-
ns
trwl
Time from RD or WR high to ale high
10
-
10
-
10
-
10
-
ns
tdw
Data valid to WR transition
5
-
5
-
5
-
5
-
ns
tdhw
Data hold time after WR
0
-
0
-
0
-
0
-
ns
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REV. 1.1, MAY. 28, 2001
45
MX98726EC
ALE
tlp
trwl
PSEN
trp
RD
tas
tah
tdhr
trd
AD[7:0]
A0-A7
A0-A7
D0-D7
AD[15:8]
A8-A15
A0-A15
MX98726EC MEMORY READ CYCLE IN 80x1 MODE
ALE
trwl
PSEN
twp
tlrw
WR
tas
tah
tdw
tdhw
AD[7:0]
AD[15:8]
A0-A7
D0-D7
A0-A7
A8-A15
A0-A15
MX98726EC MEMORY WRITE CYCLE IN 80x1 MODE
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REV. 1.1, MAY. 28, 2001
46
MX98726EC
tsap
80x1 cycle
SRAM bus
owner
80x1 cycle N+1
80x1 cycle N
80x1 cycle N
GMAC cycle
80x1 cycle N+1
trls
tgnt
HLDA
SYMBOL
tgap
tgnt
tris
GMAC cycle
HLDA=VIH to enable all access to SRAM
PARAMETER
80x1 cycle recovery time
GMAC grant valid delay
GMAC grant release delay
MIN.
300
MAX.
8
4
UNIT
ns
TCLK
TCLK
TCLK=Internal clock running at 50MHz
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REV. 1.1, MAY. 28, 2001
47
MX98726EC
trc
MA[19:1]
or
MA[19:0]*
tcw
MCSB
toew
MOEB
tdh
tds
MD[15:0]
or
MD[7:0]*
Data Valid
16/8 BIT PACKET MEMORY READ CYCLE
* 8-bit packet memory
READ CYCLE
PARAMETER
Read Cycle Time
Chip Select Pulse Width
Output Enable Pulse Width
Data Hold from Address Change
Data Valid Delay From Address Change
SYMBOL
trc
tcw
toew
tdh
tds
MIN.
35
35
35
-0
-
MAX.
40
40
40
25
UNIT
ns
ns
ns
ns
ns
Note : MA[19:0], MOEB, MCSB are asserted at the same internal clock edge.
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REV. 1.1, MAY. 28, 2001
48
MX98726EC
twc
MA[19:0]
MOEB
tcw
MCSB
twp
tas
*MW0B
tdh
tds
High-Z
MD[7:0]
* In byte mode, only MWE0B is used.
8 BIT PACKET MEMORY WRITE CYCLE
WRITE CYCLE
PARAMETER
Write Cycle Time
Chip Select Pulse Wdith
Address Set-up Time
Write Pulse Width (OE-High)
Data Setup To Write Rising Edge
Data Hold from MWEB Deassertion
SYMBOL
twc
tcw
tas
twp
tds
tdh
MIN.
35
35
5
18
25
10
MAX.
40
40
28
-
UNIT
ns
ns
ns
ns
ns
ns
Note : MA[19:0], MOEB, MCSB are asserted at the same internal clock edge.
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REV. 1.1, MAY. 28, 2001
49
MX98726EC
twc
MA[19:0]
MOEB
tcw
MCSB
twp
tas
*MWE1B
or MWE0B
tdh
tds
High-Z
MD[15:0]
16 BIT PACKET MEMORY WRITE CYCLE
WRITE CYCLE
PARAMETER
Write Cycle Time
Chip Select Pulse Wdith
Address Set-up Time
Write Pulse Width (OE-High)
Data Setup To Write Rising Edge
Data Hold from MWEB Deassertion
SYMBOL
twc
tcw
tas
twp
tds
tdh
MIN.
35
35
5
18
25
10
MAX.
40
40
28
-
UNIT
ns
ns
ns
ns
ns
ns
Note : MA[19:0], MOEB, MCSB are asserted at the same internal clock edge.
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REV. 1.1, MAY. 28, 2001
50
MX98726EC
MII management signal MDIO timing :
tmdch
tmdcl
MDC
tmdhd
tmdsu
MDIO
Symbol
tmdch
tmdcl
tmdsu
tmdhd
Parameter
MDC high time
MDC low time
MDIO to MDC high setup time
MDIO to MDC high hold time
Min
200
200
10
10
Max
Units
ns
ns
ns
ns
Min
5
3
45
25
Max
Units
ns
ns
ns
ns
Host Interface timing in 8018X mode :
AD[15:0]
ADD
DATA
tas tah
ALE
WRB
talew
RDB
SRDY
tsrdy
Symbol
tas
tah
tsrdy
talew
Parameter
Address setup time for ALE
Address hold time for ALE
SRDY valid delay
ALE pulse width
P/N:PM0729
65
REV. 1.1, MAY. 28, 2001
51
MX98726EC
8.0 DC CHARACTERISTICS
Symbol
Parameter
TTL/PCI Input/Output
Voh
Minimum High Level Output Voltage
Vol
Maximum Low Level Output Voltage
Vih
Minimum High Level Input Voltage
Vil
Maximum Low Level Input Voltage
Vsih
Schmitt Trigger Input high Voltage
Vsil
Schmitt Trigger Input Low Voltage
lin
Input leakage current (No pull-up or pull-down)
lin(pull-up)
Input leakage current with Internal pull-up
lin(pull-down) Input leakage cruuent with Internal pull-down
loz
Minimum Tri-state Output Leakage Current
Ioz(pull-up) Minimum Tri-state Output Leakage Current with
internal pull-up
Ioz(pull-down)Minimum Tri-state Output Leakage Current with
internal pull down
LED Output Driver
Vlol
LED turn on Output Voltage
Idd
Average Supply Current
Ianalog
Average Analog Current
Irx
Average RX Current
Itx
Average TX Current
Vdd
Average Supply Voltage
Clock
25MHz±30ppm
Conditions
Min.
loh=-4mA
lol=+4mA
2.4
Max.
0.4
2.0
0.8
VCC = 5V
VCC = 5V
Vin=VCC or GND
Vin=VCC or GND
Vin=VCC or GND
Vout=VCC or GND
Vout=VCC or GND
0.7VCC
-2.0
-20uA
+20uA
-10
-20uA
0.3VCC
+2.0
-70uA
+70uA
+10
-70uA
Vout=VCC or GND +20uA
+70uA
lol=16mA
CKREF=25MHz
Full duplex
Full duplex
Full duplex
0.4
300
190
80
110
5.25V
160
120
50
70
4.75V
Units
V
V
V
V
V
V
uA
uA
V
mA
mA
mA
mA
V
8.1 ABSOLUTE OPERATION CONDITION
Supply Voltage (VCC)
Storage Temperature Range (Tstg)
Operating free-air Temperature Range
-0.5V to +7.0V
-55°C to +150°C
0°C to 70°C
P/N:PM0729
REV. 1.1, MAY. 28, 2001
52
MX98726EC
9.0 PACKAGE INFORMATION
128-Pin Plastic Quad Flat Pack
ITEM
MILLIMETERS
a
14.00±.05
5.512±.002
b
.20 [Typ.]
.08 [Typ.]
c
20.00±.05
7.87±.002
d
1.346
.530
e
.50 [Typ.]
.20 [Typ.]
L1
1.60±.1
.63±.04
L
.80±.1
.31±.04
ZE
.75 [Typ.]
.30 [Typ.]
E3
12.50 [Typ.]
4.92 [Typ.]
E
17.20±.2
6.77±.08
ZD
.75 [Typ.]
.30 [Typ.]
D3
18.50 [Typ.]
7.28 [Typ.]
D
23.20±.2
9.13±.08
A1
.25±.1 min.
.01±.04 min.
A
3.40±.1 max.
1.34±.04 max.
Note
Short Lead
Short Lead
D
c
D3
INCHES
NOTE: Each lead centerline is located within .25 mm[.01
inch] of its true position [TP] at maximum material condition.
ZD
102
103
65
64
E3
128
a
E
39
ZE
38
1
L1
d
A
A1
b
e
L
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REV. 1.1, MAY. 28, 2001
53
MX98726EC
REVISION HISTORY
REVISION
0.9.6
0.9.6
0.9.6
0.9.6
0.9.6
0.9.6
0.9.6
0.9.6
0.9.6
0.9.6
0.9.6
0.9.7
0.9.7
0.9.7
0.9.7
0.9.7
0.9.7
0.9.8
0.9.9
1.0
DESCRIPTION
PAGE
Changed to V 0.9.6 added revision history
P53
added register 30h description
P17
added register 30h description
P18
add register 40h-43h as reserved.
P21
LRPS register , add "notes".
P12
add MAC address filtering flow chart
P35
12K changed to 10K. 1.5K changed to 1.4K
P7
RLBP changed to RHBP
P14
add "RHBP" short hand to register 1A, 1B h
P15
rename network address filtering registers ( MAR)
P17
change 12K to 10K
P48
modify MISC Control Register
P21
add Write TX FIFO Data Port register
P22
add Read Data register
P22
add MISC Control Register 2
P22
add Host Receive Packet Counter
P23
add Host DMA Fragment Counter
P23
contents modify
P10,31
MX98726A --> MX98726EC
add features
P1
modify internal block diagram
P2
add combo application
P3
modify pin configuration and description
P4
modify pin description (pin 70~73)
P5
modify packet buffer interface (pin 4~7)
P6
modify miscellaneous (pin 83, 84)
P7
modify network control register (bit 1.5)
P10
modify GMAC test register
P11
modify receive interrupt timer
P15
modify NWY configuration register (bit 30.2, 30.[5:3]
P18
modify GMAC configuration a register (bit 32.4)
P18
modify GMAC configuration b register (bit 33.5-4, 33.7-6)
P19
modify MISC control register (bit 3D.0, 3D.6, 3D.7)
P22
modify receive buffer ring full
P32
modify GMAC network address filtering
P36
add 6.1 On-Chip Transceiver vs MII Interface
P44
add Management Signal timing MDIO source
P50
add Management Signal timing MDIO source
P51
IOB description modified
P14
add "on chip registers addressing scheme" paragraph and
P24,25
add "more receive bandwidth without using TX Ring Buffer" paragraph
modify miscellaneous description (pin 42,43)
P7
change Reg 0.1, 0.2 descriptions
P9
add Reg 1C.6 and 1C.7 descriptions
P16
change Reg 30.0 FD bit description
P18
add Reg 33.4, 33.5 and 33.6 descriptions
P20
enhance Reg 3D.6 description
P22
0.3 SR*Start Transmit-->Receive
P09
P/N:PM0729
DATE
July/28/1999
Dec/28/1999
Apr/06/2000
May/31/2000
Jun/05/2000
Jul/03/2000
Jul/13/2000
Nov/15/2000
REV. 1.1, MAY. 28, 2001
54
MX98726EC
REVISION HISTORY
REVISION
1.1
DESCRIPTION
add 8.1 ABSOLUTE OPERATION CONDITION
update internal pull-up & pull-down information
enhance TWP description
modify RXINTT register description
enhance Figure 4.0
remove TBLEN description
remove RBLEN description
add pull-up & pull-down DC current remore software programming
interface section (application note has such info)
add memory read&write cycle in 80x1 mode picture
add host interface timing in 8018x mode
modify DC CHARACTERISTICS & ABSOLUTE MAXIMUM RATING
P/N:PM0729
PAGE
P51
P5,6,7
P14
P15
P25
P27
P31
P41
P46,47
P51
P52
DATE
JAN/15/2001
FEB/28/2001
MAY/28/2001
REV. 1.1, MAY. 28, 2001
55
MX98726EC
TOP SIDE MARKING
MX98726EC
line 1 : MX98726 is MXIC parts No.
"E" :PQFP
"C" : commercial grade
line 2 : Assembly Date Code.
line 3 : Wafer Lot No.
line 4 : "38B" : revision code,
"A" : bonding option
"X" : no used
line 5 : State
C9930
TA777001
38BAX
TAIWAN
MACRONIX INTERNATIONAL CO., LTD.
HEADQUARTERS:
TEL:+886-3-578-6688
FAX:+886-3-563-2888
EUROPE OFFICE:
TEL:+32-2-456-8020
FAX:+32-2-456-8021
JAPAN OFFICE:
TEL:+81-44-246-9100
FAX:+81-44-246-9105
SINGAPORE OFFICE:
TEL:+65-348-8385
FAX:+65-348-8096
TAIPEI OFFICE:
TEL:+886-2-2509-3300
FAX:+886-2-2509-2200
MACRONIX AMERICA, INC.
TEL:+1-408-453-8088
FAX:+1-408-453-8488
CHICAGO OFFICE:
TEL:+1-847-963-1900
FAX:+1-847-963-1909
http : //www.macronix.com
MACRONIX INTERNATIONAL CO., LTD. reserves the right to change product and specifications without notice.