MICRON MT49H8M36

288Mb: x9, x18, x36 2.5V VEXT, 1.8V VDD, HSTL, CIO, RLDRAM II
Features
CIO RLDRAM® II
MT49H32M9 – 32 Meg x 9 x 8 Banks
MT49H16M18 – 16 Meg x 18 x 8 Banks
MT49H8M36 – 8 Meg x 36 x 8 Banks
Features
Figure 1:
• 400 MHz DDR operation (800 Mb/s/pin data rate)
• 28.8 Gb/s peak bandwidth (x36 at 400 MHz
clock frequency)
• Organization
– 32 Meg x 9, 16 Meg x 18, and 8 Meg x 36
• 8 internal banks for concurrent operation and
maximum bandwidth
• Reduced cycle time (20ns at 400 MHz)
• Nonmultiplexed addresses (address multiplexing
option available)
• SRAM-type interface
• Programmable READ latency (RL), row cycle time,
and burst sequence length
• Balanced READ and WRITE latencies in order to
optimize data bus utilization
• Data mask for WRITE commands
• Differential input clocks (CK, CK#)
• Differential input data clocks (DKx, DKx#)
• On-die DLL generates CK edge-aligned data and
output data clock signals
• Data valid signal (QVLD)
• 32ms refresh (8K refresh for each bank; 64K refresh
command must be issued in total each 32ms)
• 144-ball µBGA package
• HSTL I/O (1.5V or 1.8V nominal)
• 25–60Ω matched impedance outputs
• 2.5V VEXT, 1.8V VDD, 1.5V or 1.8V VDDQ I/O
• On-die termination (ODT) RTT
Options
144-Ball µBGA
Marking
• Clock cycle timing
– 2.5ns (400 MHz)
-25
– 3.3ns (300 MHz)
-33
– 5ns (200 MHz)
-5
• Configuration
– 32 Meg x 9
32M9
– 16 Meg x 18
16M18
– 8 Meg x 36
8M36
• Operating temperature
– Commercial (0° to +95°C)
– Industrial (TC = –40°C to +95°C;
TA = –40°C to +85°C)
None
IT1
• Package
– 144-ball µBGA
FM1
– 144-ball µBGA (Pb-free)
BM2
– 144-ball FBGA
HU3
– 144-ball FBGA (Pb-free)
HT2, 3
Notes: 1. Contact Micron for availability of industrial
temperature products.
2. Contact Micron for availability of Pb-free
products.
3. The FBGA package is being phased out.
PDF: 09005aef80a41b46/Source: 09005aef809f284b
288Mb_RLDRAM_II_CIO_D1.fm - Rev M 9/07 EN
1
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2003 Micron Technology, Inc. All rights reserved.
Products and specifications discussed herein are subject to change by Micron without notice.
288Mb: x9, x18, x36 2.5V VEXT, 1.8V VDD, HSTL, CIO, RLDRAM II
Features
Figure 2:
288Mb RLDRAM II CIO Part Numbers
Example Part Number: MT 4 9 H 1 6 M1 8 FM-2 5
Configuration I/O Package
MT49H
I/O
Temperature
Common None
Commercial
Separate
Industrial
C
Package
Configuration
Notes:
Speed Temp
None
IT
Speed Grade
144-ball µBGA
FM
-25
tCK = 2.5ns
16M18
144-ball µBGA (Pb-free)
-33
tCK = 3.3ns
8M36
144-ball FBGA
BM
HU1
-5
tCK = 5ns
144-ball FBGA (Pb-free)
HT1
32 Meg x 9
32M9
16 Meg x 18
8 Meg x 36
1. The FBGA package is being phased out.
BGA Part Marking Decoder
Due to space limitations, BGA-packaged components have an abbreviated part marking
that is different from the part number. Micron’s BGA Part Marking Decoder is available
on Micron’s Web site at micron.com.
PDF: 09005aef80a41b46/Source: 09005aef809f284b
288Mb_RLDRAM_II_CIO_D1.fm - Rev M 9/07 EN
2
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2003 Micron Technology, Inc. All rights reserved.
288Mb: x9, x18, x36 2.5V VEXT, 1.8V VDD, HSTL, CIO, RLDRAM II
Table of Contents
Table of Contents
BGA Part Marking Decoder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2
General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6
State Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
Ball Assignments and Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
Package Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
Electrical Specifications – IDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
Electrical Specifications – AC and DC. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
AC and DC Operating Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
Input Slew Rate Derating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
Notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
Temperature and Thermal Impedance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
MODE REGISTER SET (MRS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31
WRITE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37
READ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38
AUTO REFRESH (AREF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39
Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40
INITIALIZATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40
WRITE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43
READ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48
AUTO REFRESH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54
On-Die Termination . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55
Multiplexed Address Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57
IEEE 1149.1 Serial Boundary Scan (JTAG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .66
Disabling the JTAG Feature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .66
Test Access Port (TAP). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .66
TAP Controller. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67
Performing a TAP RESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .69
TAP Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .69
TAP Instruction Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .70
PDF: 09005aef80a41b46/Source: 09005aef809f284b
288Mb_RLDRAM_CIOTOC.fm - Rev M 9/07 EN
3
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2003 Micron Technology, Inc. All rights reserved.
288Mb: x9, x18, x36 2.5V VEXT, 1.8V VDD, HSTL, CIO, RLDRAM II
List of Figures
List of Figures
Figure 1:
Figure 2:
Figure 3:
Figure 7:
Figure 8:
Figure 9:
Figure 10:
Figure 12:
Figure 13:
Figure 14:
Figure 15:
Figure 16:
Figure 17:
Figure 18:
Figure 19:
Figure 20:
Figure 24:
Figure 25:
Figure 26:
Figure 27:
Figure 28:
Figure 29:
Figure 30:
Figure 31:
Figure 32:
Figure 33:
Figure 35:
Figure 37:
Figure 38:
Figure 39:
Figure 43:
Figure 44:
Figure 45:
Figure 46:
144-Ball FBGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1
288Mb RLDRAM II CIO Part Numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2
Simplified State Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
144-Ball FBGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
Clock Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
Nominal tAS/tCS/tDS and tAH/tCH/tDH Slew Rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
Example Temperature Test Point Location . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29
Read Burst Lengths . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34
On-Die Termination-Equivalent Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36
WRITE Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37
READ Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38
AUTO REFRESH Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39
Power-Up/Initialization Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41
Power-Up/Initialization Flow Chart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42
WRITE Burst . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43
Consecutive WRITE-to-WRITE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44
Basic READ Burst Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48
Consecutive READ Bursts (BL = 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49
Consecutive READ Bursts (BL = 4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49
READ-to-WRITE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50
Read Data Valid Window for x9 Device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51
Read Data Valid Window for x18 Device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52
Read Data Valid Window for x36 Device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53
AUTO REFRESH Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54
READ Burst with ODT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55
READ-NOP-READ with ODT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56
Command Description in Multiplexed Address Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57
Mode Register Definition in Multiplexed Address Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59
BURST REFRESH Operation with Multiplexed Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61
Consecutive WRITE Bursts with Multiplexed Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .62
TAP Controller State Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .68
TAP Controller Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .68
JTAG Operation – Loading Instruction Code and Shifting Out Data . . . . . . . . . . . . . . . . . . . . . . . . . . .71
TAP Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .72
PDF: 09005aef80a41b46/Source: 09005aef809f284b
288Mb_RLDRAM_CIOLOF.fm - Rev M 9/07 EN
4
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2003 Micron Technology, Inc. All rights reserved.
288Mb: x9, x18, x36 2.5V VEXT, 1.8V VDD, HSTL, CIO, RLDRAM II
Lisf of Tables
Lisf of Tables
Table 1:
Table 2:
Table 3:
Table 4:
Table 5:
Table 6:
Table 7:
Table 8:
Table 9:
Table 10:
Table 11:
Table 12:
Table 13:
Table 14:
Table 15:
Table 16:
Table 17:
Table 18:
Table 19:
Table 20:
Table 21:
Table 22:
Table 23:
Table 24:
Table 25:
Table 26:
Table 27:
Table 28:
Table 29:
64 Meg x 9 Ball Assignments (Top View) 144-Ball FBGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
32 Meg x 18 Ball Assignments (Top View) 144-Ball FBGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
16 Meg x 36 Ball Assignments (Top View) 144-Ball FBGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
Ball Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
IDD Operating Conditions and Maximum Limits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
DC Electrical Characteristics and Operating Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
Input AC Logic Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
Differential Input Clock Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
Address and Command Setup and Hold Derating Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
Data Setup and Hold Derating Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
AC Electrical Characteristics: -18, -25E, -25, -33 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
Temperature Limits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
Thermal Impedance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
Description of Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
Command Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
Cycle Time and READ/WRITE Latency Configuration Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33
Address Widths at Different Burst Lengths . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34
On-Die Termination DC Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36
576Mb Address Mapping in Multiplexed Address Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60
Cycle Time and READ/WRITE Latency Configuration Table in Multiplexed Mode . . . . . . . . . . . . . .61
TAP Input AC Logic Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .72
TAP AC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .72
TAP DC Electrical Characteristics and Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .73
Identification Register Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .73
Scan Register Sizes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .73
Instruction Codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .74
Boundary Scan (Exit) Order . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .74
PDF: 09005aef80a41b46/Source: 09005aef809f284b
288Mb_RLDRAM_CIOLOT.fm - Rev M 9/07 EN
5
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2003 Micron Technology, Inc. All rights reserved.
288Mb: x9, x18, x36 2.5V VEXT, 1.8V VDD, HSTL, CIO, RLDRAM II
General Description
General Description
The Micron® reduced latency DRAM (RLDRAM®) II is a high-speed memory device
designed for high bandwidth data storage—telecommunications, networking, and
cache applications, etc. The chip’s 8-bank architecture is optimized for sustainable high
speed operation.
The DDR I/O interface transfers two data words per clock cycle at the I/O balls. Output
data is referenced to the free-running output data clock.
Commands, addresses, and control signals are registered at every positive edge of the
differential input clock, while input data is registered at both positive and negative edges
of the input data clock(s).
Read and write accesses to the RLDRAM are burst-oriented. The burst length (BL) is
programmable from 2, 4, or 8 by setting the mode register.
The device is supplied with 2.5V and 1.8V for the core and 1.5V or 1.8V for the output
drivers.
Bank-scheduled refresh is supported with the row address generated internally.
The µBGA 144-ball package is used to enable ultra high-speed data transfer rates and a
simple upgrade path from early generation devices.
PDF: 09005aef80a41b46/Source: 09005aef809f284b
288Mb_RLDRAM_II_CIO_D2.fm - Rev M 9/07 EN
6
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2003 Micron Technology, Inc. All rights reserved.
288Mb: x9, x18, x36 2.5V VEXT, 1.8V VDD, HSTL, CIO, RLDRAM II
State Diagram
State Diagram
Figure 3:
Simplified State Diagram
Initialization
sequence
DSEL/NOP
WRITE
READ
MRS
AREF
Automatic sequence
Command sequence
PDF: 09005aef80a41b46/Source: 09005aef809f284b
288Mb_RLDRAM_II_CIO_D2.fm - Rev M 9/07 EN
7
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2003 Micron Technology, Inc. All rights reserved.
PDF: 09005aef80a41b46/Source: 09005aef809f284b
288Mb_RLDRAM_II_CIO_D2.fm - Rev M EN
Functional Block Diagrams
Figure 4: 32 Meg x 9 Functional Block Diagram
ZQ
ZQ CAL
Output drivers
ODT control
CK
CK#
Control
logic
WE#
VTT
Mode register
Refresh
counter
Bank 7
Bank 6
Bank 5
Bank 4
Bank 3
Bank 2
Bank 1
Bank 0
13
Rowaddress
MUX
18
13
13
Bank 0
rowaddress
latch
and
decoder
RTT
ODT control
CK/CK#
8,192
Bank 0
memory
array
(8,192 x 32 x 16 x 9)2
DLL
ZQ CAL
144
8
SENSEamplifiers
AMPLIFIERS
Sense
READ n
logic
n
9
9
(0 ....8)
9
Drivers
DQ
latch
QVLD
QK0/QK0#
2
QK/QK#
generator
8,192
144
DQ0–DQ8
BA0–BA2
24
Address
register
Bank
control
logic
3
31
I/O gating
DQM mask logic
8
8
32
144
5
8
81
Columnaddress
counter/
latch
Column
decoder
WRITE
FIFO n
and
drivers n
DK/DK#
2
9
Input
logic
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2003 Micron Technology, Inc. All rights reserved.
A0–A201
9
RCVRS
9
CLK
in
VTT
81
RTT
31
ODT control
DM
Notes:
1. Examples for BL = 2; column address will be reduced with an increase in burst length.
2. The “16” = (length of burst) x 2^(number of column addresses to WRITE FIFO and READ logic).
288Mb: x9, x18, x36 2.5V VEXT, 1.8V VDD, HSTL, CIO, RLDRAM II
State Diagram
Command
decode
CS#
REF#
ZQ
ZQ CAL
Output drivers
ODT control
CK
CK#
CS#
Command
decode
PDF: 09005aef80a41b46/Source: 09005aef809f284b
288Mb_RLDRAM_II_CIO_D2.fm - Rev M EN
Figure 5: 16 Meg x 18 Functional Block Diagram
REF#
WE#
Control
logic
VTT
13
Rowaddress
MUX
18
13
13
Bank 0
rowaddress
latch
and
decoder
RTT
ODT control
CK/CK#
8,192
Bank 0
memory
array
(8,192 x 32 x 8 x 18)2
(0 ....17)
DLL
ZQ CAL
18
144
Sense
SENSEamplifiers
AMPLIFIERS
READ n
logic
n
18
18
Drivers
DQ
latch
4
QVLD
QK0–QK1/
QK0#–QK1#
QK/QK#
generator
8,192
144
9
DQ0–DQ17
23
Bank
control
logic
Address
register
3
8
8
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2003 Micron Technology, Inc. All rights reserved.
144
5
8
71
Columnaddress
counter/
latch
DK/DK#
2
32
Column
decoder
WRITE
FIFO
and
drivers
n
n
18
Input
logic
A0–A191
BA0–BA2
21
I/O gating
DQM mask logic
18
18
RCVRS
VTT
CLK
in
71
RTT
21
ODT control
DM
Notes:
1. Examples for BL = 2; column address will be reduced with an increase in burst length.
2. The “8” = (length of burst) x 2^(number of column addresses to WRITE FIFO and READ logic).
288Mb: x9, x18, x36 2.5V VEXT, 1.8V VDD, HSTL, CIO, RLDRAM II
State Diagram
Mode register
Refresh
counter
Bank 7
Bank 6
Bank 5
Bank 4
Bank 3
Bank 2
Bank 1
Bank 0
ZQ
ZQ CAL
Output drivers
ODT control
CK
CK#
CS#
Control
logic
Command
decode
PDF: 09005aef80a41b46/Source: 09005aef809f284b
288Mb_RLDRAM_II_CIO_D2.fm - Rev M EN
Figure 6: 8 Meg x 36 Functional Block Diagram
REF#
WE#
VTT
18
13
Rowaddress
MUX
13
13
Bank 0
rowaddress
latch
and
decoder
RTT
ODT control
CK/CK#
8,192
Bank 0
memory
array
(8,192 x 32 x 4 x 36)2
DLL
ZQ CAL
144
READ n
logic
n
36
36
DQ
latch
(0 ....35)
36
Drivers
SENSE
AMPLIFIERS
Sense amplifiers
4
QVLD
QK0–QK1/
QK0#–QK1#
QK/QK#
generator
8,192
10
144
DQ0–DQ35
22
Address
register
Bank
control
logic
3
8
8
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2003 Micron Technology, Inc. All rights reserved.
32
144
5
8
61
Columnaddress
counter/
latch
WRITE
FIFO
and
drivers
CLK
in
Column
decoder
DK0–DK1/
DK0#–DK1#
4
n
n
36
36
Input
logic
A0–A181
BA0–BA2
11
I/O gating
DQM mask logic
36
RCVRS
VTT
61
RTT
11
ODT control
DM
Notes:
1. Examples for BL = 2; column address will be reduced with an increase in burst length.
2. The “4” = (length of burst) x 2^(number of column addresses to WRITE FIFO and READ logic).
288Mb: x9, x18, x36 2.5V VEXT, 1.8V VDD, HSTL, CIO, RLDRAM II
State Diagram
Mode register
Refresh
counter
Bank 7
Bank 6
Bank 5
Bank 4
Bank 3
Bank 2
Bank 1
Bank 0
288Mb: x9, x18, x36 2.5V VEXT, 1.8V VDD, HSTL, CIO, RLDRAM II
Ball Assignments and Descriptions
Ball Assignments and Descriptions
Table 1:
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
V
32 Meg x 9 Ball Assignments (Top View) 144-Ball µBGA
1
2
3
4
VREF
VDD
VTT
A221
A212
A5
A8
B2
NF3
DK
REF#
WE#
A18
A15
VSS
VTT
VDD
VREF
VSS
DNU4
DNU4
DNU4
DNU4
DNU4
A6
A9
NF3
DK#
CS#
A16
DNU4
DNU4
DNU4
DNU4
DNU4
ZQ
VEXT
DNU4
DNU4
DNU4
DNU4
DNU4
A7
VSS
VDD
VDD
VSS
A17
DNU4
DNU4
DNU4
DNU4
DNU4
VEXT
VSS
VSSQ
VDDQ
VSSQ
VDDQ
VSSQ
VDD
VSS
VDD
VDD
VSS
VDD
VSSQ
VDDQ
VSSQ
VDDQ
VSSQ
VSS
Notes:
PDF: 09005aef80a41b46/Source: 09005aef809f284b
288Mb_RLDRAM_II_CIO_D2.fm - Rev M 9/07 EN
5
6
7
8
9
10
11
12
VSS
VSSQ
VDDQ
VSSQ
VDDQ
VSSQ
VDD
VSS
VDD
VDD
VSS
VDD
VSSQ
VDDQ
VSSQ
VDDQ
VSSQ
VSS
VEXT
DQ0
DQ1
QK0#
DQ2
DQ3
A2
VSS
VDD
VDD
VSS
A12
DQ4
DQ5
DQ6
DQ7
DQ8
VEXT
TMS
DNU4
DNU4
QK0
DNU4
DNU4
A1
A4
B0
B1
A14
A11
DNU4
DNU4
DNU4
DNU4
DNU4
TDO
TCK
VDD
VTT
VSS
A20
QVLD
A0
A3
CK
CK#
A13
A10
A19
DM
VSS
VTT
VDD
TDI
1. Reserved for future use. This signal is not connected.
2. Reserved for future use. This signal is internally connected and has parasitic characteristics
of an address input signal.
3. No function. This signal is internally connected and has parasitic characteristics of a clock
input signal. This may optionally be connected to GND.
4. Do not use. This signal is internally connected and has parasitic characteristics of a I/O. This
may optionally be connected to GND. Note that if ODT is enabled, these pins will be connected to VTT.
11
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2003 Micron Technology, Inc. All rights reserved.
288Mb: x9, x18, x36 2.5V VEXT, 1.8V VDD, HSTL, CIO, RLDRAM II
Ball Assignments and Descriptions
Table 2:
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
V
16 Meg x 18 Ball Assignments (Top View) 144-Ball µBGA
1
2
3
4
VREF
VDD
VTT
A221
A212
A5
A8
B2
NF3
DK
REF#
WE#
A18
A15
VSS
VTT
VDD
VREF
VSS
DNU4
DNU4
DNU4
DNU4
DNU4
A6
A9
NF3
DK#
CS#
A16
DNU4
DNU4
QK1
DNU4
DNU4
ZQ
VEXT
DQ4
DQ5
DQ6
DQ7
DQ8
A7
VSS
VDD
VDD
VSS
A17
DQ14
DQ15
QK1#
DQ16
DQ17
VEXT
VSS
VSSQ
VDDQ
VSSQ
VDDQ
VSSQ
VDD
VSS
VDD
VDD
VSS
VDD
VSSQ
VDDQ
VSSQ
VDDQ
VSSQ
VSS
Notes:
PDF: 09005aef80a41b46/Source: 09005aef809f284b
288Mb_RLDRAM_II_CIO_D2.fm - Rev M 9/07 EN
5
6
7
8
9
10
11
12
VSS
VSSQ
VDDQ
VSSQ
VDDQ
VSSQ
VDD
VSS
VDD
VDD
VSS
VDD
VSSQ
VDDQ
VSSQ
VDDQ
VSSQ
VSS
VEXT
DQ0
DQ1
QK0#
DQ2
DQ3
A2
VSS
VDD
VDD
VSS
A12
DQ9
DQ10
DQ11
DQ12
DQ13
VEXT
TMS
DNU4
DNU4
QK0
DNU4
DNU4
A1
A4
B0
B1
A14
A11
DNU4
DNU4
DNU4
DNU4
DNU4
TDO
TCK
VDD
VTT
VSS
A202
QVLD
A0
A3
CK
CK#
A13
A10
A19
DM
VSS
VTT
VDD
TDI
1. Reserved for future use. This may optionally be connected to GND.
2. Reserved for future use. This signal is internally connected and has parasitic characteristics
of an address input signal. This may optionally be connected to GND.
3. No function. This signal is internally connected and has parasitic characteristics of a clock
input signal. This may optionally be connected to GND.
4. Do not use. This signal is internally connected and has parasitic characteristics of a I/O. This
may optionally be connected to GND. Note that if ODT is enabled, these pins will be connected to VTT.
12
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2003 Micron Technology, Inc. All rights reserved.
288Mb: x9, x18, x36 2.5V VEXT, 1.8V VDD, HSTL, CIO, RLDRAM II
Ball Assignments and Descriptions
Table 3:
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
V
8 Meg x 36 Ball Assignments (Top View) 144-Ball µBGA
1
2
3
4
VREF
VDD
VTT
A22
A212
A5
A8
B2
DK0
DK1
REF#
WE#
A18
A15
VSS
VTT
VDD
VREF
VSS
DQ8
DQ10
DQ12
DQ14
DQ16
A6
A9
DK0#
DK1#
CS#
A16
DQ24
DQ22
QK1
DQ20
DQ18
ZQ
VEXT
DQ9
DQ11
DQ13
DQ15
DQ17
A7
VSS
VDD
VDD
VSS
A17
DQ25
DQ23
QK1#
DQ21
DQ19
VEXT
VSS
VSSQ
VDDQ
VSSQ
VDDQ
VSSQ
VDD
VSS
VDD
VDD
VSS
VDD
VSSQ
VDDQ
VSSQ
VDDQ
VSSQ
VSS
Notes:
PDF: 09005aef80a41b46/Source: 09005aef809f284b
288Mb_RLDRAM_II_CIO_D2.fm - Rev M 9/07 EN
5
6
7
8
9
10
11
12
VSS
VSSQ
VDDQ
VSSQ
VDDQ
VSSQ
VDD
VSS
VDD
VDD
VSS
VDD
VSSQ
VDDQ
VSSQ
VDDQ
VSSQ
VSS
VEXT
DQ1
DQ3
QK0#
DQ5
DQ7
A2
VSS
VDD
VDD
VSS
A12
DQ35
DQ33
DQ31
DQ29
DQ27
VEXT
TMS
DQ0
DQ2
QK0
DQ4
DQ6
A1
A4
B0
B1
A14
A11
DQ34
DQ32
DQ30
DQ28
DQ26
TDO
TCK
VDD
VTT
VSS
A202
QVLD
A0
A3
CK
CK#
A13
A10
A192
DM
VSS
VTT
VDD
TDI
1. Reserved for future use. This may optionally be connected to GND.
2. Reserved for future use. This signal is internally connected and has parasitic characteristics
of an address input signal. This may optionally be connected to GND.
13
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2003 Micron Technology, Inc. All rights reserved.
288Mb: x9, x18, x36 2.5V VEXT, 1.8V VDD, HSTL, CIO, RLDRAM II
Ball Assignments and Descriptions
Table 4:
Ball Descriptions
Symbol
Type
Description
A0–A20
Input
BA0–BA2
CK, CK#
Input
Input
CS#
Input
DQ0–DQ35
Input
DK, DK#
Input
DM
Input
TCK
TMS, TDI
WE#, REF#
Input
Input
Input
VREF
ZQ
Input
I/O
QKx, QKx#
Output
QVLD
TDO
Output
Output
VDD
VDDQ
Supply
Supply
VEXT
VSS
VSSQ
VTT
Supply
Supply
Supply
Supply
A21
–
A22
–
Address inputs: A0–A20 define the row and column addresses for READ and WRITE operations.
During a MODE REGISTER SET, the address inputs define the register settings. They are sampled
at the rising edge of CK.
Bank address inputs: Select to which internal bank a command is being applied.
Input clock: CK and CK# are differential input clocks. Addresses and commands are latched on
the rising edge of CK. CK# is ideally 180 degrees out of phase with CK.
Chip select: CS# enables the command decoder when LOW and disables it when HIGH. When
the command decoder is disabled, new commands are ignored, but internal operations continue.
Data input: The DQ signals form the 36-bit data bus. During READ commands, the data is
referenced to both edges of QKx. During WRITE commands, the data is sampled at both edges of
DK.
Input data clock: DK and DK# are the differential input data clocks. All input data is referenced
to both edges of DK. DK# is ideally 180 degrees out of phase with DK. For the x36 device, DQ0–
DQ17 are referenced to DK0 and DK0# and DQ18–DQ35 are referenced to DK1 and DK1#. For the
x9 and x18 devices, all DQs are referenced to DK and DK#. All DKx and DKx# pins must always be
supplied to the device.
Input data mask: The DM signal is the input mask signal for WRITE data. Input data is masked
when DM is sampled HIGH. DM is sampled on both edges of DK (DK1 for the x36 configuration).
Tie signal to ground if not used.
IEEE 1149.1 clock input: This ball must be tied to VSS if the JTAG function is not used.
IEEE 1149.1 test inputs: These balls may be left as no connects if the JTAG function is not used.
Command inputs: Sampled at the positive edge of CK, WE# and REF# define (together with
CS#) the command to be executed.
Input reference voltage: Nominally VDDQ/2. Provides a reference voltage for the input buffers.
External impedance (25–60Ω): This signal is used to tune the device outputs to the system data
bus impedance. DQ output impedance is set to 0.2 × RQ, where RQ is a resistor from this signal to
ground. Connecting ZQ to GND invokes the minimum impedance mode. Connecting ZQ to VDD
invokes the maximum impedance mode. Refer to Figure 16 on page 44 to activate this function.
Output data clocks: QKx and QKx# are opposite polarity, output data clocks. They are freerunning, and during READs, are edge-aligned with data output from the RLDRAM. QKx# is
ideally 180 degrees out of phase with QKx. For the x36 device, QK0 and QK0# are aligned with
DQ0–DQ17, and QK1 and QK1# are aligned with DQ18–DQ35. For the x18 device, QK0 and QK0#
are aligned with DQ0–DQ8, while QK1 and QK1# are aligned with Q9–Q17. For the x9 device, all
DQs are aligned with QK0 and QK0#.
Data valid: The QVLD pin indicates valid output data. QVLD is edge-aligned with QKx and QKx#.
IEEE 1149.1 test output: JTAG output. This ball may be left as no connect if the JTAG function
is not used.
Power supply: Nominally, 1.8V. See Table 12 on page 29 for range.
DQ power supply: Nominally, 1.5V or 1.8V. Isolated on the device for improved noise immunity.
See Table 12 on page 29 for range.
Power supply: Nominally, 2.5V. See Table 12 on page 29 for range.
Ground.
DQ ground: Isolated on the device for improved noise immunity.
Power supply: Isolated termination supply. Nominally, VDDQ/2. See Table 12 on page 29 for
range.
Reserved for future use: This signal is internally connected and can be treated as an address
input.
Reserved for future use: This signal is not connected and can be connected to ground.
PDF: 09005aef80a41b46/Source: 09005aef809f284b
288Mb_RLDRAM_II_CIO_D2.fm - Rev M 9/07 EN
14
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2003 Micron Technology, Inc. All rights reserved.
288Mb: x9, x18, x36 2.5V VEXT, 1.8V VDD, HSTL, CIO, RLDRAM II
Ball Assignments and Descriptions
Table 4:
Ball Descriptions (continued)
Symbol
Type
Description
DNU
–
NF
–
Do not use: These balls may be connected to ground. Note that if ODT is enabled, these pins will
be connected to VTT.
No function: These balls can be connected to ground.
PDF: 09005aef80a41b46/Source: 09005aef809f284b
288Mb_RLDRAM_II_CIO_D2.fm - Rev M 9/07 EN
15
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2003 Micron Technology, Inc. All rights reserved.
288Mb: x9, x18, x36 2.5V VEXT, 1.8V VDD, HSTL, CIO, RLDRAM II
Package Dimensions
Package Dimensions
Figure 7:
144-Ball µBGA
10.70 CTR
10º TYP
SEATING PLANE
2.41 CTR
A
0.08 A
0.08 MAX
SOLDER BALL MATERIAL:
62% Sn, 36% Pb, 2%Ag OR
96.5% Sn, 3%Ag, 0.5% Cu
SUBSTRATE MATERIAL:
PLASTIC LAMINATE
144X Ø 0.45
DIMENSIONS APPLY
TO SOLDER BALLS
POST REFLOW. THE
PRE-REFLOW BALL
DIAMETER IS 0.50 ON A
0.40 SMD BALL PAD.
8.80
BALL A12
MOLD
COMPOUND
0.80 TYP
BALL A1
MOLD COMPOUND:
EPOXY NOVOLAC
BALL A1 ID
BALL A1 ID
1.00 TYP
17.00
18.50 ±0.10
15.40
8.50
17.90 CTR
9.25 ±0.05
4.40
0.44 ±0.05
0.39 ±0.05
5.50 ±0.05
11.00 ±0.10
Notes:
PDF: 09005aef80a41b46/Source: 09005aef809f284b
288Mb_RLDRAM_II_CIO_D2.fm - Rev M 9/07 EN
1. All dimensions are in millimeters.
16
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©2003 Micron Technology, Inc. All rights reserved.
288Mb: x9, x18, x36 2.5V VEXT, 1.8V VDD, HSTL, CIO, RLDRAM II
Package Dimensions
Figure 8:
144-Ball FBGA
0.75 ±0.05
0.155 ±0.013
SEATING
PLANE
0.10 A
A
144X Ø 0.55
DIMENSIONS APPLY TO
SOLDER BALLS POST
REFLOW. THE PRE-REFLOW
BALL IS Ø0.50 ON A Ø0.40
NSMD BALL PAD.
2.20 ±0.025
CTR
SOLDER BALL MATERIAL:
62% Sn, 36% Pb, 2%Ag OR
96.5% Sn, 3%Ag, 0.5%Cu
SUBSTRATE MATERIAL: PLASTIC LAMINATE
8.80
0.80 TYP
MOLD COMPOUND: EPOXY NOVOLAC
BALL A1
MOLD
COMPOUND
BALL A1 ID
BALL A1 ID
BALL A12
9.25 ±0.05
CL
17.00
18.50 ±0.10
8.50
1.00 TYP
4.40
CL
5.50 ±0.05
1.20 MAX
11.00 ±0.10
Notes:
PDF: 09005aef80a41b46/Source: 09005aef809f284b
288Mb_RLDRAM_II_CIO_D2.fm - Rev M 9/07 EN
1. All dimensions are in millimeters.
2. The FBGA package is being phased out.
17
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©2003 Micron Technology, Inc. All rights reserved.
288Mb: x9, x18, x36 2.5V VEXT, 1.8V VDD, HSTL, CIO, RLDRAM II
Electrical Specifications – IDD
Electrical Specifications – IDD
Table 5:
IDD Operating Conditions and Maximum Limits
Description
Condition
Standby current
t
Active standby
current
CS# = 1; No commands; Bank address
incremented and half address/data change
once every 4 clock cycles
Operational
current
BL = 2; Sequential bank access; Bank transitions
once every tRC; Half address transitions once
every tRC; Read followed by write sequence;
continuous data during WRITE commands
BL = 4; Sequential bank access; Bank transitions
once every tRC; Half address transitions once
every tRC; Read followed by write sequence;
Continuous data during WRITE commands
BL = 8; Sequential bank access; Bank transitions
once every tRC; half address transitions once
every tRC; Read followed by write sequence;
continuous data during WRITE commands
Eight-bank cyclic refresh; Continuous address/
data; Command bus remains in refresh for all
eight banks
Operational
current
Operational
current
Burst refresh
current
Distributed
refresh current
Operating burst
write current
example
Operating burst
write current
example
Operating burst
write current
example
Operating burst
read current
example
Operating burst
read current
example
Operating burst
read current
example
CK = idle; All banks idle; No inputs toggling
Symbol
-25
-33
-5
Units
ISB1 (VDD) x9/x18
ISB1 (VDD) x36
ISB1 (VEXT)
ISB2 (VDD) x9/x18
ISB2 (VDD) x36
ISB2 (VEXT)
IDD1 (VDD) x9/x18
IDD1 (VDD) x36
IDD1 (VEXT)
48
48
26
288
288
26
348
374
41
48
48
26
233
233
26
305
343
36
48
48
26
189
189
26
255
292
36
mA
IDD2 (VDD) x9/x18
IDD2 (VDD) x36
IDD2 (VEXT)
362
418
48
319
389
42
269
339
42
mA
IDD3 (VDD) x9/x18
IDD3 (VDD) x36
IDD3 (VEXT)
408
n/a
55
368
n/a
48
286
n/a
48
mA
785
785
133
325
326
48
970
615
615
111
267
281
42
819
430
430
105
221
227
42
597
mA
mA
990
100
779
914
90
609
676
69
439
mA
882
88
668
790
77
525
567
63
364
mA
n/a
60
860
880
100
680
730
88
570
n/a
60
n/a
51
735
795
90
525
660
77
450
n/a
51
n/a
40
525
565
69
380
455
63
310
n/a
40
IREF1 (VDD) x9/x18
IREF1 (VDD) x36
IREF1 (VEXT)
IREF2 (VDD) x9/x18
Single-bank refresh; Sequential bank access;
Half address transitions once every tRC,
IREF2 (VDD) x36
continuous data
IREF2 (VEXT)
IDD2W (VDD)
BL = 2; Cyclic bank access; Half of address bits
x9/x18
change every clock cycle; Continuous data;
measurement is taken during continuous
IDD2W (VDD) x36
WRITE
IDD2W (VEXT)
IDD4W (VDD)
BL = 4; Cyclic bank access; Half of address bits
x9/x18
change every 2 clock cycles; Continuous data;
Measurement is taken during continuous
IDD4W (VDD) X36
WRITE
IDD4W (VEXT)
IDD8W (VDD)
BL = 8; Cyclic bank access; Half of address bits
x9/x18
change every 4 clock cycles; continuous data;
Measurement is taken during continuous
IDD8W (VDD) x36
WRITE
IDD8W (VEXT)
IDD2R (VDD) x9/x18
BL = 2; Cyclic bank access; Half of address bits
change every clock cycle; Measurement is taken
IDD2R (VDD) x36
during continuous READ
IDD2R (VEXT)
IDD4R (VDD) x9/x18
BL = 4; Cyclic bank access; Half of address bits
change every 2 clock cycles; Measurement is
IDD4R (VDD) x36
taken during continuous READ
IDD4R (VEXT)
IDD8R (VDD) x9/x18
BL = 8; Cyclic bank access; Half of address bits
change every 4 clock cycles; Measurement is
IDD8R (VDD) x36
taken during continuous READ
IDD8R (VEXT)
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288Mb_RLDRAM_II_CIO_D2.fm - Rev M 9/07 EN
18
mA
mA
mA
mA
mA
mA
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©2003 Micron Technology, Inc. All rights reserved.
288Mb: x9, x18, x36 2.5V VEXT, 1.8V VDD, HSTL, CIO, RLDRAM II
Electrical Specifications – IDD
Notes:
PDF: 09005aef80a41b46/Source: 09005aef809f284b
288Mb_RLDRAM_II_CIO_D2.fm - Rev M 9/07 EN
1. IDD specifications are tested after the device is properly initialized. +0°C ≤ TC ≤ +95°C; +1.7V
≤ VDD ≤ +1.9V, +2.38V ≤ VEXT ≤ +2.63V, +1.4V ≤ VDDQ ≤ VDD, VREF = VDDQ/2.
2. tCK = tDK = MIN, tRC = MIN.
3. Input slew rate is specified in Table 8 on page 19.
4. Definitions for IDD conditions:
4a. LOW is defined as VIN ≤ VIL(AC) MAX.
4b. HIGH is defined as VIN ≥ VIH(AC) MIN.
4c. Stable is defined as inputs remaining at a HIGH or LOW level.
4d. Floating is defined as inputs at VREF = VDDQ/2.
4e. Continuous data is defined as half the DQ signals changing between HIGH and LOW
every half clock cycle (twice per clock).
4f. Continuous address is defined as half the address signals changing between HIGH and
LOW every clock cycle (once per clock).
4g. Sequential bank access is defined as the bank address incrementing by one every tRC.
4h. Cyclic bank access is defined as the bank address incrementing by one for each command access. For BL = 2 this is every clock, for BL = 4 this is every other clock, and for
BL = 8 this is every fourth clock.
5. CS# is HIGH unless a READ, WRITE, AREF, or MRS command is registered. CS# never transitions more than once per clock cycle.
6. IDD parameters are specified with ODT disabled.
7. Tests for AC timing, IDD, and electrical AC and DC characteristics may be conducted at nominal reference/supply voltage levels, but the related specifications and device operations are
tested for the full voltage range specified.
8. IDD tests may use a VIL-to-VIH swing of up to 1.5V in the test environment, but input timing
is still referenced to VREF (or to the crossing point for CK/CK#), and parameter specifications
are tested for the specified AC input levels under normal use conditions. The minimum slew
rate for the input signals used to test the device is 2 V/ns in the range between VIL(AC) and
VIH(AC).
19
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Electrical Specifications – AC and DC
Electrical Specifications – AC and DC
Absolute Maximum Ratings
Stresses greater than those listed in Table 6 may cause permanent damage to the device.
This is a stress rating only, and functional operation of the device at these or any other
conditions outside those indicated in the operational sections of this specification is not
implied. Exposure to absolute maximum rating conditions for extended periods may
affect reliability.
Table 6:
Absolute Maximum Ratings
Parameter
Min
Max
Units
I/O voltage
Voltage on VEXT supply relative to VSS
Voltage on VDD supply relative to VSS
Voltage on VDDQ supply relative to VSS
–0.3
–0.3
–0.3
–0.3
VDDQ + 0.3
+2.8
+2.1
+2.1
V
V
V
V
AC and DC Operating Conditions
Table 7:
DC Electrical Characteristics and Operating Conditions
Note 1 applies to the entire table; Unless otherwise noted: +0°C ≤ TC ≤ +95°C; +1.7V ≤ VDD ≤ +1.9V
Description
Conditions
Symbol
Supply voltage
Supply voltage
Isolated output buffer supply
Reference voltage
Termination voltage
Input high (logic 1) voltage
Input low (logic 0) voltage
Output high current
–
–
–
–
–
–
–
VOH = VDDQ/2
VEXT
VDD
VDDQ
VREF
VTT
VIH
VIL
IOH
Output low current
VOL = VDDQ/2
IOL
0V ≤ VIN ≤ VDD
0V ≤ VIN ≤ VDD
0V ≤ VIN ≤ VDDQ
–
ILC
ILI
ILO
IREF
Clock input leakage current
Input leakage current
Output leakage current
Reference voltage current
Notes:
PDF: 09005aef80a41b46/Source: 09005aef809f284b
288Mb_RLDRAM_II_CIO_D2.fm - Rev M 9/07 EN
Min
Max
2.38
2.63
1.7
1.9
1.4
VDD
0.49 × VDDQ 0.51 × VDDQ
0.95 × VREF
1.05 × VREF
VREF + 0.1
VDDQ + 0.3
VSSQ - 0.3
VREF - 0.1
(VDDQ/2)/
(VDDQ/2)/
(1.15 × RQ/5) (0.85 × RQ/5)
(VDDQ/2)/
(VDDQ/2)/
(1.15 × RQ/5) (0.85 × RQ/5)
–5
5
–5
5
–5
5
–5
5
Units
Notes
V
V
V
V
V
V
V
A
2
2, 3
4, 5, 6
7, 8
2
2
9, 10, 11
A
9, 10, 11
µA
µA
µA
µA
1. All voltages referenced to VSS (GND).
2. Overshoot: VIH(AC) ≤ VDD + 0.7V for t ≤ tCK/2. Undershoot: VIL(AC) ≥ –0.5V for t ≤ tCK/2. During normal operation, VDDQ must not exceed VDD. Control input signals may not have pulse
widths less than tCK/2 or operate at frequencies exceeding tCK (MAX).
3. VDDQ can be set to a nominal 1.5V ± 0.1V or 1.8V ± 0.1V supply.
4. Typically the value of VREF is expected to be 0.5 x VDDQ of the transmitting device. VREF is
expected to track variations in VDDQ.
5. Peak-to-peak AC noise on VREF must not exceed ±2 percent VREF(DC).
6. VREF is expected to equal VDDQ/2 of the transmitting device and to track variations in the
DC level of the same. Peak-to-peak noise (non-common mode) on VREF may not exceed ±2
percent of the DC value. Thus, from VDDQ/2, VREF is allowed ±2 percent VDDQ/2 for DC error
and an additional ±2 percent VDDQ/2 for AC noise. This measurement is to be taken at the
nearest VREF bypass capacitor.
20
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©2003 Micron Technology, Inc. All rights reserved.
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Electrical Specifications – AC and DC
7. VTT is expected to be set equal to VREF and must track variations in the DC level of VREF.
8. On-die termination may be selected using mode register bit 9 (see Figure 11 on page 32). A
resistance RTT from each data input signal to the nearest VTT can be enabled.
RTT = 125–185Ω at 95°C TC.
9. IOH and IOL are defined as absolute values and are measured at VDDQ/2. IOH flows from the
device, IOL flows into the device.
10. If MRS bit A8 is 0, use RQ = 250Ω in the equation in lieu of presence of an external impedance matched resistor.
11. For VOL and VOH, refer to the RLDRAM II HSPICE or IBIS driver models.
Table 8:
Input AC Logic Levels
Notes 1–3 apply to entire table; Unless otherwise noted: +0°C ≤ TC ≤ +95°C; +1.7V ≤ VDD ≤ +1.9V
Description
Input high (logic 1) voltage
Input low (logic 0) voltage
Notes:
Symbol
Min
Max
Units
VIH
VIL
VREF + 0.2
–
–
VREF - 0.2
V
V
1. All voltages referenced to VSS (GND).
2. The AC and DC input level specifications are as defined in the HSTL standard (that is, the
receiver will effectively switch as a result of the signal crossing the AC input level, and will
remain in that state as long as the signal does not ring back above [below] the DC input
LOW [HIGH] level).
3. The minimum slew rate for the input signals used to test the device is 2 V/ns in the range
between VIL(AC) and VIH(AC). See illustration below:
VDDQ
VIH(AC) MIN
VSWING
VIL(AC) MAX
GND
Rise time:
2 V/ns
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288Mb_RLDRAM_II_CIO_D2.fm - Rev M 9/07 EN
Fall time:
2 V/ns
21
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©2003 Micron Technology, Inc. All rights reserved.
288Mb: x9, x18, x36 2.5V VEXT, 1.8V VDD, HSTL, CIO, RLDRAM II
Electrical Specifications – AC and DC
Table 9:
Differential Input Clock Operating Conditions
Notes 1–4 apply to the entire table; Unless otherwise noted: +0°C ≤ TC ≤ +95°C; +1.7V ≤ VDD ≤ +1.9V
Parameter/Condition
Clock input voltage level: CK and CK#
Clock input differential voltage: CK and CK#
Clock input differential voltage: CK and CK#
Clock input crossing point voltage: CK and CK#
Notes:
Figure 9:
Symbol
Min
Max
Units
Notes
VIN(DC)
VID(DC)
VID(AC)
VIX(AC)
–0.3
0.2
0.4
VDDQ/2 - 0.15
VDDQ + 0.3
VDDQ + 0.6
VDDQ + 0.6
VDDQ/2 + 0.15
V
V
V
V
5
5
6
1. DKx and DKx# have the same requirements as CK and CK#.
2. All voltages referenced to VSS (GND).
3. The CK/CK# input reference level (for timing referenced to CK/CK#) is the point at which CK
and CK# cross. The input reference level for signals other than CK/CK# is VREF.
4. CK and CK# input slew rate must be ≥2 V/ns (≥4 V/ns if measured differentially).
5. VID is the magnitude of the difference between the input level on CK and the input level on
CK#.
6. The value of VIX is expected to equal VDDQ/2 of the transmitting device and must track variations in the DC level of the same.
Clock Input
VIN(DC) MAX
Maximum clock level
CK#
X
VDDQ/2 + 0.15
VIX(AC) MAX
VID(DC)2
VDDQ/2
VDDQ/2 - 0.15
1
X
VID(AC)3
VIX(AC) MIN
CK
Minimum clock level
VIN(DC) MIN
Notes:
PDF: 09005aef80a41b46/Source: 09005aef809f284b
288Mb_RLDRAM_II_CIO_D2.fm - Rev M 9/07 EN
1.
2.
3.
4.
CK and CK# must cross within this region.
CK and CK# must meet at least VID(DC) MIN when static and centered around VDDQ/2.
Minimum peak-to-peak swing.
It is a violation to tristate CK and CK# after the part is initialized.
22
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©2003 Micron Technology, Inc. All rights reserved.
288Mb: x9, x18, x36 2.5V VEXT, 1.8V VDD, HSTL, CIO, RLDRAM II
Electrical Specifications – AC and DC
Input Slew Rate Derating
Table 10 on page 22 and Table 11 on page 23 define the address, command, and data
setup and hold derating values. These values are added to the default tAS/tCS/tDS and
tAH/tCH/tDH specifications when the slew rate of any of these input signals is less than
the 2 V/ns the nominal setup and hold specifications are based upon.
To determine the setup and hold time needed for a given slew rate, add the tAS/tCS
default specification to the “tAS/tCS VREF to CK/CK# Crossing” and the tAH/tCH default
specification to the "tAH/tCH CK/CK# Crossing to VREF" derated values on Table 10. The
derated data setup and hold values can be determined in a like manner using the “tDS
VREF to CK/CK# Crossing” and “tDH to CK/CK# Crossing to VREF ” values on Table 11. The
derating values on Table 10 and Table 11 apply to all speed grades.
The setup times on Table 10 and Table 11 represent a rising signal. In this case, the time
from which the rising signal crosses VIH(AC) MIN to the CK/CK# cross point is static and
must be maintained across all slew rates. The derated setup timing represents the point
at which the rising signal crosses VREF(DC) to the CK/CK# cross point. This derated value
is calculated by determining the time needed to maintain the given slew rate and the
delta between VIH(AC) MIN and the CK/CK# cross point. The setup values in Table 10
and Table 11 are also valid for falling signals (with respect to VIL[AC] MAX and the CK/
CK# cross point).
The hold times in Table 10 and Table 11 represent falling signals. In this case, the time
from the CK/CK# cross point to when the signal crosses VIH(DC) MIN is static and must
be maintained across all slew rates. The derated hold timing represents the delta
between the CK/CK# cross point to when the falling signal crosses VREF(DC). This
derated value is calculated by determining the time needed to maintain the given slew
rate and the delta between the CK/CK# cross point and VIH(DC). The hold values in
Table 10 and Table 11 are also valid for rising signals (with respect to VIL[DC] MAX and
the CK and CK# cross point).
Note:
PDF: 09005aef80a41b46/Source: 09005aef809f284b
288Mb_RLDRAM_II_CIO_D2.fm - Rev M 9/07 EN
The above descriptions also pertain to data setup and hold derating when CK/CK# are
replaced with DK/DK#.
23
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©2003 Micron Technology, Inc. All rights reserved.
288Mb: x9, x18, x36 2.5V VEXT, 1.8V VDD, HSTL, CIO, RLDRAM II
Electrical Specifications – AC and DC
Table 10:
Address and Command Setup and Hold Derating Values
t
Command/
Address Slew
Rate (V/ns)
AS/ CS VREF to
CK/CK# Crossing
2.0
1.9
1.8
1.7
1.6
1.5
1.4
1.3
1.2
1.1
1.0
0
5
11
18
25
33
43
54
67
82
100
2.0
1.9
1.8
1.7
1.6
1.5
1.4
1.3
1.2
1.1
1.0
30
35
41
48
55
63
73
84
97
112
130
2.0
1.9
1.8
1.7
1.6
1.5
1.4
1.3
1.2
1.1
1.0
60
65
71
78
85
93
103
114
127
142
160
t
t
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288Mb_RLDRAM_II_CIO_D2.fm - Rev M 9/07 EN
AS/tCS VIH(AC)
MIN to CK/CK#
Crossing
t
t
t
AH/ CH CK/CK#
Crossing to VREF
CK, CK# Differential Slew Rate: 2.0 V/ns
–100
0
–100
3
–100
6
–100
9
–100
13
–100
17
–100
22
–100
27
–100
34
–100
41
–100
50
CK, CK# Differential Slew Rate: 1.5 V/ns
–70
30
–70
33
–70
36
–70
39
–70
43
–70
47
–70
52
–70
57
–70
64
–70
71
–70
80
CK, CK# Differential Slew Rate: 1.0 V/ns
–40
60
–40
63
–40
66
–40
69
–40
73
–40
77
–40
82
–40
87
–40
94
–40
101
–40
110
24
AH/tCH CK/CK#
Crossing to
VIH(DC) MIN
Units
–50
–50
–50
–50
–50
–50
–50
–50
–50
–50
–50
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
–20
–20
–20
–20
–20
–20
–20
–20
–20
–20
–20
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
10
10
10
10
10
10
10
10
10
10
10
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2003 Micron Technology, Inc. All rights reserved.
288Mb: x9, x18, x36 2.5V VEXT, 1.8V VDD, HSTL, CIO, RLDRAM II
Electrical Specifications – AC and DC
Table 11:
Data Setup and Hold Derating Values
t
t
Data Slew Rate
(V/ns)
DS VREF to
CK/CK# Crossing
2.0
1.9
1.8
1.7
1.6
1.5
1.4
1.3
1.2
1.1
1.0
0
5
11
18
25
33
43
54
67
82
100
2.0
1.9
1.8
1.7
1.6
1.5
1.4
1.3
1.2
1.1
1.0
30
35
41
48
55
63
73
84
97
112
130
2.0
1.9
1.8
1.7
1.6
1.5
1.4
1.3
1.2
1.1
1.0
60
65
71
78
85
93
103
114
127
142
160
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288Mb_RLDRAM_II_CIO_D2.fm - Rev M 9/07 EN
t
DS VIH(AC) MIN to
CK/CK# Crossing
t
DH CK/CK#
Crossing to VREF
DK, DK# Differential Slew Rate: 2.0 V/ns
–100
0
–100
3
–100
6
–100
9
–100
13
–100
17
–100
22
–100
27
–100
34
–100
41
–100
50
DK, DK# Differential Slew Rate: 1.5 V/ns
–70
30
–70
33
–70
36
–70
39
–70
43
–70
47
–70
52
–70
57
–70
64
–70
71
–70
80
DK, DK# Differential Slew Rate: 1.0 V/ns
–40
60
–40
63
–40
66
–40
69
–40
73
–40
77
–40
82
–40
87
–40
94
–40
101
–40
110
25
DH CK/CK#
Crossing to
VIH(DC) MIN
Units
–50
–50
–50
–50
–50
–50
–50
–50
–50
–50
–50
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
–20
–20
–20
–20
–20
–20
–20
–20
–20
–20
–20
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
10
10
10
10
10
10
10
10
10
10
10
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
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Electrical Specifications – AC and DC
Figure 10:
Nominal tAS/tCS/tDS and tAH/tCH/tDH Slew Rate
VIH(AC) MIN
VREF to DC VREF to DC
region
region
VSWING (MAX)
VREF to AC
region
VREF to AC
region
VDDQ
VIH(DC) MIN
VREF(DC)
VIL(DC) MAX
VIL(AC) MAX
VSSQ
Table 12:
Capacitance
Notes 1–2 apply to entire table
Description
Address/control input capacitance
Input/output capacitance (DQ, DM, and QK/QK#)
Clock capacitance (CK/CK#, and DK/DK#)
JTAG pins
Notes:
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Symbol
Conditions
Min
Max
Units
CI
CO
CCK
CJTAG
TA = 25°C; f = 100 MHz
VDD = VDDQ = 1.8V
1.5
3.5
2.0
2.0
2.5
5.0
3.0
5.0
pF
pF
pF
pF
1. Capacitance is not tested on ZQ pin.
2. JTAG pins are tested at 50 MHz.
26
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Electrical Specifications – AC and DC
Table 13:
AC Electrical Characteristics: -25, -33, -5
Notes 1–4 (page 39) apply to the entire table
-25
Description
Symbol
Min
-33
Max
Min
5.7
3.3
-5
Max
Min
5.7
5.0
Max
Units Notes
Clock
Input clock cycle time
Input data clock cycle time
Clock jitter: period
Clock jitter: cycle-to-cycle
Clock HIGH time
Clock LOW time
Clock to input data clock
Mode register set cycle time
to any command
t
CK
DK
t
JITPER
t
JITCC
tCKH,
tDKH
tCKL,
t
DKL
tCKDK
tMRSC
2.5
0.45
250
500
0.55
ns
ns
ps
ps
tCK
0.55
0.45
0.55
tCK
–0.3
6
1.0
–
–0.3
6
1.5
–
tCK
–
0.5
–
0.8
–
ns
0.25
–
0.3
–
0.4
–
ns
tAH/tCH
0.4
–
0.5
–
0.8
–
ns
tDH
0.25
–
0.3
–
0.4
–
ns
tQKH
0.9
0.9
MIN (tQKH,
t
QKL)
–0.25
–0.2
1.1
1.1
–
1.1
1.1
–
tCKH
0.3
0.25
0.9
0.9
MIN (tQKH,
t
QKL)
–0.5
–0.3
1.1
1.1
–
0.25
0.2
0.9
0.9
MIN (tQKH,
t
QKL)
–0.3
–0.25
0.5
0.3
ns
ns
7
tQKQ
–0.3
0.3
–0.35
0.35
–0.4
0.4
ns
8
tQKVLD
–0.3
QHP (tQKQx
[MAX] +
|tQKQx
[MIN]|)
0.3
–
–0.35
QHP (tQKQx
[MAX] +
|tQKQx
[MIN]|)
0.35
–
–0.4
QHP (tQKQx
[MAX] +
|tQKQx
[MIN]|)
0.4
–
ns
–
0.49
–
0.49
–
0.49
µs
t
t
t
CK
–150
–200
0.45
150
300
0.55
0.45
5.7
t
CK
–250
0.45
200
400
0.55
0.55
0.45
–0.3
6
0.5
–
tAS/tCS
0.4
tDS
CK
5, 6
ns
Setup Times
Address/command and input
setup time
Data-in and data mask to DK
setup time
Hold Times
Address/command and input
hold time
Data-in and data mask to DK
hold time
Data and Data Strobe
Output data clock HIGH time
Output data clock LOW time
Half-clock period
QK edge to clock edge skew
QK edge to output data edge
QK edge to any output data
edge
QK edge to QVLD
Data valid window
tQKL
t
QHP
t
CKQK
tQKQ0,
tCKL
tQKQ1
t
DVW
t
t
t
Refresh
Average periodic refresh
interval
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tREFI
27
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Electrical Specifications – AC and DC
Notes
1. All timing parameters are measured relative to the crossing point of CK/CK#, DK/DK#
and to the crossing point with VREF of the command, address, and data signals.
2. Outputs measured with equivalent load:
VTT
50Ω
DQ
Test point
10pF
3. Tests for AC timing, IDD, and electrical AC and DC characteristics may be conducted
at nominal reference/supply voltage levels, but the related specifications and device
operations are tested for the full voltage range specified.
4. AC timing may use a VIL-to-VIH swing of up to 1.5V in the test environment, but input
timing is still referenced to VREF (or to the crossing point for CK/CK#), and parameter
specifications are tested for the specified AC input levels under normal use conditions. The minimum slew rate for the input signals used to test the device is 2 V/ns in
the range between VIL(AC) and VIH(AC).
5. Clock phase jitter is the variance from clock rising edge to the next expected clock rising edge.
6. Frequency drift is not allowed.
7. tQKQ0 is referenced to DQ0–DQ17 for the x36 configuration and DQ0–DQ8 for the x18
configuration. tQKQ1 is referenced to DQ18–DQ35 for the x36 configuration and
DQ9–DQ17 for the x18 configuration.
8. tQKQ takes into account the skew between any QKx and any Q.
9. To improve efficiency, eight AREF commands (one for each bank) can be posted to the
RLDRAM on consecutive cycles at periodic intervals of 3.90µs.
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Temperature and Thermal Impedance
Temperature and Thermal Impedance
It is imperative that the RLDRAM device’s temperature specifications, shown in Table 14,
be maintained in order to ensure the junction temperature is in the proper operating
range to meet data sheet specifications. An important step in maintaining the proper
junction temperature is using the device’s thermal impedances correctly. The thermal
impedances are listed for the packages available.
Incorrectly using thermal impedances can produce significant errors. Read Micron technical note TN-00-08, “Thermal Applications” prior to using the thermal impedances
listed in Table 14. For designs that are expected to last several years and require the flexibility to use several DRAM die shrinks, consider using final target theta values (rather
than existing values) to account for increased thermal impedances from the die size
reduction.
The RLDRAM device’s safe junction temperature range can be maintained when the TC
specification is not exceeded. In applications where the device’s ambient temperature is
too high, use of forced air and/or heat sinks may be required in order to satisfy the case
temperature specifications.
Table 14:
Temperature Limits
Parameter
Storage temperature
Reliability junction temperature
Operating junction temperature
Operating case temperature
Notes:
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Commercial
Industrial
Commercial
Industrial
Commercial
Industrial
Symbol
Min
Max
Units
Notes
TSTG
TJ
–55
–
–
0
–40
0
–40
+150
+110
+110
+100
+100
+95
+95
°C
°C
°C
°C
°C
°C
°C
1
2
2
3
3
4, 5
4, 5, 6
TJ
TC
1. MAX storage case temperature; TSTG is measured in the center of the package, as shown in
Figure 10 on page 29. This case temperature limit is allowed to be exceeded briefly during
package reflow, as noted in Micron technical note TN-00-15.
2. Temperatures greater than 110°C may cause permanent damage to the device. This is a
stress rating only and functional operation of the device at or above this is not implied.
Exposure to absolute maximum rating conditions for extended periods may affect reliability
of the part.
3. Junction temperature depends upon package type, cycle time, loading, ambient temperature, and airflow.
4. MAX operating case temperature; TC is measured in the center of the package, as shown in
Figure 10 on page 29.
5. Device functionality is not guaranteed if the device exceeds maximum TC during operation.
6. Both temperature specifications must be satisfied.
29
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Temperature and Thermal Impedance
Table 15:
Thermal Impedance
Package
Substrate
θ JA (°C/W)
Airflow = 0m/s
θ JA (°C/W)
Airflow = 1m/s
θ JA (°C/W)
Airflow = 2m/s
θ JB (°C/W)
θ JC (°C/W)
µBGA
2-layer
4-layer
2-layer
4-layer
41.2
28.2
42.2
28.5
29.1
21.9
29.3
22.0
25.3
19.9
25.3
19.9
14.3
13.6
16.4
13.4
2.27
FBGA
2.6
Notes: Thermal impedance data is based on a number of samples from multiple lots and should be
viewed as a typical number.
Figure 11:
Example Temperature Test Point Location
Test point
18.50
9.25
5.50
11.00
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Commands
Commands
The following table provides descriptions of the valid commands of the RLDRAM. All
input states or sequences not shown are illegal or reserved. All command and address
inputs must meet setup and hold times around the rising edge of CK.
Table 16:
Description of Commands
Command
DSEL/NOP
MRS
READ
WRITE
AREF
Description
Notes
The NOP command is used to perform a no operation to the RLDRAM, which essentially
deselects the chip. Use the NOP command to prevent unwanted commands from being
registered during idle or wait states. Operations already in progress are not affected. Output
values depend on command history.
The mode register is set via the address inputs A0–A17. See Figure 11 on page 32 for further
information. The MRS command can only be issued when all banks are idle and no bursts are
in progress.
The READ command is used to initiate a burst read access to a bank. The value on the BA0–
BA2 inputs selects the bank, and the address provided on inputs A0–An selects the data
location within the bank.
The WRITE command is used to initiate a burst write access to a bank. The value on the BA0–
BA2 inputs selects the bank, and the address provided on inputs A0–An selects the data
location within the bank. Input data appearing on the DQ is written to the memory array
subject to the DM input logic level appearing coincident with the data. If the DM signal is
registered LOW, the corresponding data will be written to memory. If the DM signal is
registered HIGH, the corresponding data inputs will be ignored (that is, this part of the data
word will not be written).
The AREF command is used during normal operation of the RLDRAM to refresh the memory
content of a bank. The command is nonpersistent, so it must be issued each time a refresh is
required. The value on the BA0–BA2 inputs selects the bank. The refresh address is
generated by an internal refresh controller, effectively making each address bit a “Don’t
Care” during the AREF command. See “AUTO REFRESH (AREF)” on page 39 for more details.
1
Notes:
Table 17:
2
2
1. When the chip is deselected, internal NOP commands are generated and no commands are
accepted.
2. n = 20.
Command Table
Notes 1–2 apply to the entire table
Operation
Device DESELECT/no operation
MRS
READ
WRITE
AUTO REFRESH
Notes:
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1.
2.
3.
4.
Code
CS#
WE#
REF#
A0–An2
BA0–BA2
Notes
DSEL/NOP
MRS
READ
WRITE
AREF
H
L
L
L
L
X
L
H
L
H
X
L
H
H
L
X
OPCODE
A
A
X
X
X
BA
BA
BA
3
4
4
X = “Don’t Care;” H = logic HIGH; L = logic LOW; A = valid address; BA = valid bank address.
n = 20.
Only A0–A17 are used for the MRS command.
Address width varies with burst length; see Table 19 on page 35 for details.
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Commands
MODE REGISTER SET (MRS)
The mode register set stores the data for controlling the operating modes of the memory.
It programs the RLDRAM configuration, burst length, test mode, and I/O options.
During an MRS command, the address inputs A0–A17 are sampled and stored in the
mode register. After issuing a valid MRS command, tMRSC must be met before any
command can be issued to the RLDRAM. This statement does not apply to the consecutive MRS commands needed for internal logic reset during the initialization routine. The
MRS command can only be issued when all banks are idle and no bursts are in progress.
Note:
The data written by the prior burst length is not guaranteed to be accurate when the
burst length of the device is changed.
CK#
CK
CS#
WE#
REF#
ADDRESS
OPCODE
BANK
ADDRESS
DON’T CARE
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Commands
Figure 11:
Mode Register Definition in Nonmultiplexed Address Mode
A17
...
A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
17–10
9 8 7 6 5
Reserved1 ODT IM DLL NA2 AM
4 3
BL
Off (default)
1
On
M7
0
Drive Impedance
Internal 50Ω6 (default)
0
DLL Reset
DLL reset4 (default)
1
External (ZQ)
1
DLL enabled
M8
M5
Notes:
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1.
2.
3.
4.
5.
6.
Address MUX
2 1 0
Config
Mode Register (Mx)
M2 M1 M0 Configuration
0 0 0 13 (default)
M9 On-Die Termination
0
Address Bus
0
0
1
13
0
1
0
2
0
1
1
3
1
0
0
1
0
1
43,5
55
1
1
0
Reserved
1
1
1
Reserved
M4 M3
Burst Length
0
Nonmultiplexed (default)
0
1
Multiplexed
0
1
1
0
8
1
1
Reserved
0
2 (default)
4
A10–A17 must be set to zero; A18–An = “Don’t Care.”
A6 not used in MRS.
BL = 8 is not available.
DLL RESET turns the DLL off.
Available in 576Mb part only.
±30 percent temperature variation.
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Commands
Configuration Tables
Table 18 shows the different configurations that can be programmed into the mode
register. The WRITE latency is equal to the READ latency plus one in each configuration
in order to maximize data bus utilization. Bits M0, M1, and M2 are used to select the
configuration during the MRS command.
Table 18:
Cycle Time and READ/WRITE Latency Configuration Table
Configuration
Parameter
t
RC
t
RL
t
WL
Valid frequency range
Notes:
11
2
3
4
4
5
200–175
6
6
7
300–175
8
8
9
400–175
Units
t
CK
CK
t
CK
MHz
t
1. BL = 8 is not available.
Burst Length (BL)
Burst length is defined by M3 and M4 of the mode register. Read and write accesses to
the RLDRAM are burst-oriented, with the burst length being programmable to 2, 4, or 8.
Figure 12 on page 34 illustrates the different burst lengths with respect to a READ
command. Changes in the burst length affect the width of the address bus (see Table 19
on page 35 for details).
Note:
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The data written by the prior burst length is not guaranteed to be accurate when the
burst length of the device is changed.
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Commands
Figure 12:
CK#
Read Burst Lengths
T0
T1
T2
T3
T4
T4n
READ
NOP
NOP
NOP
NOP
T5
T5n
T6
T6n
T7
T7n
CK
COMMAND
ADDRESS
NOP
NOP
NOP
NOP
Bank a,
Col n
RL = 4
QK#
BL = 2
QK
QVLD
DO
an
DQ
QK#
BL = 4
QK
QVLD
DO
an
DQ
QK#
BL = 8
QK
QVLD
DO
an
DQ
TRANSITIONING DATA
Notes:
Table 19:
DON’T CARE
1. DO an = data-out from bank a and address an.
2. Subsequent elements of data-out appear after DO n.
3. Shown with nominal tCKQK.
Address Widths at Different Burst Lengths
Burst Length
x9
x18
x36
2
4
8
A0–A20
A0–A19
A0–A18
A0–A19
A0–A18
A0–A17
A0–A18
A0–A17
n/a
Address Multiplexing
Although the RLDRAM has the ability to operate with an SRAM interface by accepting
the entire address in one clock, an option in the mode register can be set so that it functions with multiplexed addresses, similar to a traditional DRAM. In multiplexed address
mode, the address can be provided to the RLDRAM in two parts that are latched into the
memory with two consecutive rising clock edges. This provides the advantage of only
needing a maximum of 11 address balls to control the RLDRAM, reducing the number of
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Commands
signals on the controller side. The data bus efficiency in continuous burst mode is only
affected when using the BL = 2 setting since the device requires two clocks to read and
write the data. The bank addresses are delivered to the RLDRAM at the same time as the
WRITE and READ command and the first address part, Ax. Table 21 on page 61 and
Table 22 on page 62 show the addresses needed for both the first and second rising clock
edges (Ax and Ay, respectively). The AREF command does not require an address on the
second rising clock edge, as only the bank address is needed during this command.
Because of this, AREF commands may be issued on consecutive clocks.
The multiplexed address option is available by setting bit M5 to “1” in the mode register.
Once this bit is set, the READ, WRITE, and MRS commands follow the format described
in Figure 35 on page 57. Further information on operation with multiplexed addresses
can be seen in “Multiplexed Address Mode” on page 57.
DLL RESET
DLL RESET is selected with bit M7 of the mode register as is shown in Figure 11 on
page 32. The default setting for this option is LOW, whereby the DLL is disabled. Once
M7 is set HIGH, 1,024 cycles (5µs at 200 MHz) are needed before a READ command can
be issued. This time allows the internal clock to be synchronized with the external clock.
Failing to wait for synchronization to occur may result in a violation of the tCKQK
parameter. A reset of the DLL is necessary if tCK or VDD is changed after the DLL has
already been enabled. To reset the DLL, an MRS command must be issued where M7 is
set LOW. After waiting tMRSC, a subsequent MRS command should be issued whereby
M7 goes HIGH. 1,024 clock cycles are then needed before a READ command is issued.
Drive Impedance Matching
The RLDRAM II is equipped with programmable impedance output buffers. This option
is selected by setting bit M8 HIGH during the MRS command. The purpose of the
programmable impedance output buffers is to allow the user to match the driver impedance to the system. To adjust the impedance, an external precision resistor (RQ) is
connected between the ZQ ball and VSS. The value of the resistor must be five times the
desired impedance. For example, a 300Ω resistor is required for an output impedance of
60Ω. The range of RQ is 125–300Ω, which guarantees output impedance in the range of
25–60Ω (within 15 percent).
Output impedance updates may be required because over time variations may occur in
supply voltage and temperature. When the external drive impedance is enabled in the
MRS, the device will periodically sample the value of RQ. An impedance update is transparent to the system and does not affect device operation. All data sheet timing and
current specifications are met during an update.
When bit M8 is set LOW during the MRS command, the RLDRAM provides an internal
impedance at the output buffer of 50Ω (±30 percent with temperature variation). This
impedance is also periodically sampled and adjusted to compensate for variation in
supply voltage and temperature.
On-Die Termination (ODT)
ODT is enabled by setting M9 to “1” during an MRS command. With ODT on, the DQs
and DM are terminated to VTT with a resistance RTT. The command, address, QVLD, and
clock signals are not terminated. Figure 13 on page 36 shows the equivalent circuit of a
DQ receiver with ODT. The ODT function is dynamically switched off when a DQ begins
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Commands
to drive after a READ command is issued. Similarly, ODT is designed to switch on at the
DQs after the RLDRAM has issued the last piece of data. The DM pin will always be
terminated. See section entitled “Operations” on page 40 for relevant timing diagrams.
Table 20:
On-Die Termination DC Parameters
Description
Termination voltage
On-die termination
Notes:
Figure 13:
Symbol
Min
Max
Units
Notes
VTT
RTT
0.95 × VREF
125
1.05 × VREF
185
V
Ω
1, 2
3
1. All voltages referenced to VSS (GND).
2. VTT is expected to be set equal to VREF and must track variations in the DC level of VREF.
3. The RTT value is measured at 95°C TC.
On-Die Termination-Equivalent Circuit
VTT
SW
RTT
Receiver
DQ
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Commands
WRITE
Write accesses are initiated with a WRITE command, as shown in Figure 14. The address
needs to be provided during the WRITE command.
During WRITE commands, data will be registered at both edges of DK according to the
programmed burst length (BL). The RLDRAM operates with a WRITE latency (WL) that
is one cycle longer than the programmed READ latency (RL + 1), with the first valid data
registered at the first rising DK edge WL cycles after the WRITE command.
Any WRITE burst may be followed by a subsequent READ command (assuming tRC is
met). To avoid external data bus contention, at least one NOP command is needed
between the WRITE and READ commands. Figure 21 on page 45 and Figure 22 on
page 46 illustrate the timing requirements for a WRITE followed by a READ where one
and two intermediary NOPs are required, respectively.
Setup and hold times for incoming DQ relative to the DK edges are specified as tDS and
tDH. The input data is masked if the corresponding DM signal is HIGH. The setup and
hold times for the DM signal are also tDS and tDH.
Figure 14:
WRITE Command
CK#
CK
CS#
WE#
REF#
ADDRESS
A
BANK
ADDRESS
BA
DON’T CARE
PDF: 09005aef80a41b46/Source: 09005aef809f284b
288Mb_RLDRAM_II_CIO.Core.fm - Rev A 9/07 EN
37
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©2003 Micron Technology, Inc. All rights reserved.
288Mb: x9, x18, x36 2.5V VEXT, 1.8V VDD, HSTL, CIO, RLDRAM II
Commands
READ
Read accesses are initiated with a READ command, as shown in Figure 15. Addresses are
provided with the READ command.
During READ bursts, the memory device drives the read data so it is edge-aligned with
the QKx signals. After a programmable READ latency, data is available at the outputs.
One half clock cycle prior to valid data on the read bus, the data valid signal, QVLD, transitions from LOW to HIGH. QVLD is also edge-aligned with the QKx signals.
The skew between QK and the crossing point of CK is specified as tCKQK. tQKQ0 is the
skew between QK0 and the last valid data edge generated at the DQ signals associated
with QK0 (tQKQ0 is referenced to DQ0–DQ17 for the x36 configuration and DQ0–DQ8
for the x18 configuration). tQKQ1 is the skew between QK1 and the last valid data edge
generated at the DQ signals associated with QK1 (tQKQ1 is referenced to DQ18–DQ35 for
the x36 and DQ9–DQ17 for the x18 configuration). tQKQx is derived at each QKx clock
edge and is not cumulative over time. tQKQ is defined as the skew between either QK
differential pair and any output data edge.
After completion of a burst, assuming no other commands have been initiated, output
data (DQ) will go High-Z. The QVLD signal transitions LOW on the last bit of the READ
burst. Note that if CK/CK# violates the VID(DC) specification while a READ burst is occurring, QVLD will remain HIGH until a dummy READ command is issued. The QK clocks
are free-running and will continue to cycle after the read burst is complete. Back-toback READ commands are possible, producing a continuous flow of output data.
The data valid window is derived from each QK transition and is defined as:
tQHP - (tQKQ [MAX] + |tQKQ [MIN]|). See Figures 28–30 for illustration.
Any READ burst may be followed by a subsequent WRITE command. Figure 27 on
page 50 illustrate the timing requirements for a READ followed by a WRITE. Some
systems having long line lengths or severe skews may need additional idle cycles
inserted between READ and WRITE commands to prevent data bus contention.
Figure 15:
READ Command
CK#
CK
CS#
WE#
REF#
ADDRESS
A
BANK
ADDRESS
BA
DON’T CARE
PDF: 09005aef80a41b46/Source: 09005aef809f284b
288Mb_RLDRAM_II_CIO.Core.fm - Rev A 9/07 EN
38
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©2003 Micron Technology, Inc. All rights reserved.
288Mb: x9, x18, x36 2.5V VEXT, 1.8V VDD, HSTL, CIO, RLDRAM II
Commands
AUTO REFRESH (AREF)
AREF is used to perform a REFRESH cycle on one row in a specific bank. Because the row
addresses are generated by an internal refresh counter for each bank, the external
address balls are “Don’t Care.” The bank addresses must be provided during the AREF
command. The bank address is needed during the AREF command so refreshing of the
part can effectively be hidden behind commands to other banks. The delay between the
AREF command and a subsequent command to the same bank must be at least tRC.
Within a period of 32ms (tREF), the entire device must be refreshed. For the 288Mb
device, the RLDRAM requires 64K cycles at an average periodic interval of 0.49µs MAX
(actual periodic refresh interval is 32ms/8K rows/8 banks = 0.488µs). To improve efficiency, eight AREF commands (one for each bank) can be posted to the RLDRAM at periodic intervals of 3.9µs (32ms/8K rows = 3.90µs). Figure 31 on page 54 illustrates an
example of a refresh sequence.
Figure 16:
AUTO REFRESH Command
CK#
CK
CS#
WE#
REF#
ADDRESS
BANK
ADDRESS
BA
DON’T CARE
PDF: 09005aef80a41b46/Source: 09005aef809f284b
288Mb_RLDRAM_II_CIO.Core.fm - Rev A 9/07 EN
39
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2003 Micron Technology, Inc. All rights reserved.
288Mb: x9, x18, x36 2.5V VEXT, 1.8V VDD, HSTL, CIO, RLDRAM II
Operations
Operations
INITIALIZATION
The RLDRAM must be powered up and initialized in a predefined manner. Operational
procedures other than those specified may result in undefined operations or permanent
damage to the device.
The following sequence is used for power-up:
1. Apply power (VEXT, VDD, VDDQ, VREF, VTT) and start clock as soon as the supply voltages are stable. Apply VDD and VEXT before or at the same time as VDDQ.1 Apply VDDQ
before or at the same time as VREF and VTT. Although there is no timing relation
between VEXT and VDD, the chip starts the power-up sequence only after both voltages approach their nominal levels. CK/CK# must meet VID(DC) prior to being
applied.2 Apply NOP conditions to command pins. Ensuring CK/CK# meet VID(DC)
while applying NOP conditions to the command pins guarantees that the RLDRAM
will not receive unwanted commands during initialization.
2. Maintain stable conditions for 200µs (MIN).
3. Issue at least three consecutive MRS commands: two or more dummies plus one valid
MRS. The purpose of these consecutive MRS commands is to internally reset the logic
of the RLDRAM. Note that tMRSC does not need to be met between these consecutive
commands. It is recommended that all address pins are held LOW during the dummy
MRS commands.
4. tMRSC after the valid MRS, an AUTO REFRESH command to all 8 banks (along with
1,024 NOP commands) must be issued prior to normal operation. The sequence of
the eight AUTO REFRESH commands (with respect to the 1,024 NOP commands)
does not matter. As is required for any operation, tRC must be met between an AUTO
REFRESH command and a subsequent VALID command to the same bank. Note that
older versions of the data sheet required each of these AUTO REFRESH commands be
separated by 2,048 NOP commands. This properly initializes the RLDRAM but is no
longer required.
Notes:
PDF: 09005aef80a41b46/Source: 09005aef809f284b
288Mb_RLDRAM_II_CIO.Core.fm - Rev A 9/07 EN
1. It is possible to apply VDDQ before VDD. However, when doing this, the DQs, DM, and
all other pins with an output driver, will go HIGH instead of tri-stating. These pins will
remain HIGH until VDD is at the same level as VDDQ. Care should be taken to avoid
bus conflicts during this period.
2. If VID(DC) on CK/CK# can not be met prior to being applied to the RLDRAM, placing a
large external resistor from CS# to VDD is a viable option for ensuring the command
bus does not receive unwanted commands during this unspecified state.
40
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©2003 Micron Technology, Inc. All rights reserved.
288Mb: x9, x18, x36 2.5V VEXT, 1.8V VDD, HSTL, CIO, RLDRAM II
Operations
Figure 17:
Power-Up/Initialization Sequence
VEXT
VDD
VDDQ
VREF
VTT
T0
T1
tCK
CK#
CK
tCKH
T3
T2
tCKL
T4
T5
T6
T8
T7
T9
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
tDK
DK#
DK
tDKH
COMMAND
tDKL
NOP
NOP
NOP
((
))
((
))
NOP
MRS
MRS
MRS
((
))
((
))
REF
((
))
((
))
REF
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
VALID
((
))
((
))
VALID
DM
((
))
((
))
ADDRESS
((
))
((
))
BANK ADDRESS
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
DQ
RTT
High-Z
1,2
CODE
T = 200µs (MIN)
PDF: 09005aef80a41b46/Source: 09005aef809f284b
288Mb_RLDRAM_II_CIO.Core.fm - Rev A 9/07 EN
1.
2.
3.
4.
5.
2
CODE
tMRSC
Power-up:
VDD and stable
clock (CK, CK#)
Notes:
1,2
CODE
VALID
Bank 0
((
))
((
))
Refresh
all banks5
Bank 7
1,024 NOP
commands
Indicates a break in
time scale
DON’T CARE
Recommend all address pins held LOW during dummy MRS commands.
A10–A17 must be LOW.
DLL must be reset if tCK or VDD are changed.
CK and CK# must be separated at all times to prevent bogus commands from being issued.
The sequence of the eight AUTO REFRESH commands (with respect to the 1,024 NOP commands) does not matter. As is required for any operation, tRC must be met between an
AUTO REFRESH command and a subsequent VALID command to the same bank.
41
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©2003 Micron Technology, Inc. All rights reserved.
288Mb: x9, x18, x36 2.5V VEXT, 1.8V VDD, HSTL, CIO, RLDRAM II
Operations
Figure 18:
Power-Up/Initialization Flow Chart
Step
Notes:
PDF: 09005aef80a41b46/Source: 09005aef809f284b
288Mb_RLDRAM_II_CIO.Core.fm - Rev A 9/07 EN
1
VDD, and VEXT ramp
2
VDDQ ramp
3
Apply VREF and VTT
4
Apply stable CK/CK# and DK/DK#
5
Wait at least 200µs
6
Issue MRS command—A10–A17 must be LOW
7
Issue MRS command—A10–A17 must be LOW
8
Desired load mode register with A10–A17 LOW
9
Assert NOP for tMRSC
10
Issue AUTO REFRESH to bank 0
11
Issue AUTO REFRESH to bank 1
12
Issue AUTO REFRESH to bank 2
13
Issue AUTO REFRESH to bank 3
14
Issue AUTO REFRESH to bank 4
15
Issue AUTO REFRESH to bank 5
16
Issue AUTO REFRESH to bank 6
17
Issue AUTO REFRESH to bank 7
18
Wait 1,024 NOP commands1
19
Valid command
Voltage rails
can be applied
simultaneously
MRS commands
must be on
consecutive clock
cycles
1. The sequence of the eight AUTO REFRESH commands (with respect to the 1,024 NOP commands) does not matter. As is required for any operation, tRC must be met between an
AUTO REFRESH command and a subsequent VALID command to the same bank.
42
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©2003 Micron Technology, Inc. All rights reserved.
288Mb: x9, x18, x36 2.5V VEXT, 1.8V VDD, HSTL, CIO, RLDRAM II
Operations
WRITE
Figure 19:
WRITE Burst
T0
T1
T2
T3
T4
T5
T5n
COMMAND
WRITE
NOP
NOP
NOP
NOP
NOP
ADDRESS
Bank a,
Add n
T6
T6n
T7
CK#
CK
tCKDK (NOM)
NOP
NOP
WL = 5
DK#
DK
DI
an
DQ
DM
tCKDK (MIN)
WL - tCKDK
DK#
DK
DI
an
DQ
DM
tCKDK (MAX)
WL + tCKDK
DK#
DK
DI
an
DQ
DM
TRANSITIONING DATA
Notes:
PDF: 09005aef80a41b46/Source: 09005aef809f284b
288Mb_RLDRAM_II_CIO.Core.fm - Rev A 9/07 EN
DON’T CARE
1. DI an = data-in for bank a and address n; subsequent elements of burst are applied following DI an.
2. BL = 4.
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288Mb: x9, x18, x36 2.5V VEXT, 1.8V VDD, HSTL, CIO, RLDRAM II
Operations
Figure 20:
Consecutive WRITE-to-WRITE
T0
T1
T2
T3
WRITE
NOP
WRITE
NOP
T4
T5
T5n
T6
T6n
T7
T7n
T8
T8n
T9
CK#
CK
COMMAND
ADDRESS
Bank a,
Add n
Bank b,
Add n
WRITE
NOP
NOP
NOP
NOP
NOP
Bank a,
Add n
DK#
DK
t
RC = 4
WL = 5
WL = 5
DI
an
DQ
DI
bn
DI
an
DM
TRANSITIONING DATA
Notes:
PDF: 09005aef80a41b46/Source: 09005aef809f284b
288Mb_RLDRAM_II_CIO.Core.fm - Rev A 9/07 EN
DON’T CARE
1.
2.
3.
4.
DI an (or bn) = data-in for bank a (or b) and address n.
Three subsequent elements of the burst are applied following DI for each bank.
BL = 4.
Each WRITE command may be to any bank; if the second WRITE is to the same bank,
tRC must be met.
5. Nominal conditions are assumed for specifications not defined.
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©2003 Micron Technology, Inc. All rights reserved.
288Mb: x9, x18, x36 2.5V VEXT, 1.8V VDD, HSTL, CIO, RLDRAM II
Operations
Figure 21:
WRITE-to-READ
T0
T1
T2
T3
T4
T5
COMMAND
WRITE
NOP
READ
NOP
NOP
NOP
ADDRESS
Bank a,
Add n
T5n
T6
T6n
T7
CK#
CK
NOP
NOP
Bank b,
Add n
WL = 5
RL = 4
QK#
QK
DK#
DK
QVLD
DI
an
DQ
DO
bn
DM
DON’T CARE
Notes:
PDF: 09005aef80a41b46/Source: 09005aef809f284b
288Mb_RLDRAM_II_CIO.Core.fm - Rev A 9/07 EN
1.
2.
3.
4.
5.
TRANSITIONING DATA
DI an = data-in for bank a and address n.
DO bn = data-out from bank b and address n.
Two subsequent elements of each burst follow DI an and DO bn.
BL = 2.
Nominal conditions are assumed for specifications not defined.
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©2003 Micron Technology, Inc. All rights reserved.
288Mb: x9, x18, x36 2.5V VEXT, 1.8V VDD, HSTL, CIO, RLDRAM II
Operations
Figure 22:
WRITE-to-READ (Separated by Two NOPs)
T0
T1
T2
T3
T4
T5
T5n
COMMAND
WRITE
NOP
NOP
READ
NOP
NOP
ADDRESS
Bank a,
Add n
T6
T7
NOP
NOP
T7n
T8
CK#
CK
NOP
Bank b,
Add n
WL = 5
tCKQK (MIN)
RL = 4
QK#
QK
DK#
DK
tCKDK (MAX)
QVLD
DI
an
DQ
DO
bn
DM
tDH
tQKQ (MIN)
TRANSITIONING DATA
Notes:
PDF: 09005aef80a41b46/Source: 09005aef809f284b
288Mb_RLDRAM_II_CIO.Core.fm - Rev A 9/07 EN
DON’T CARE
1.
2.
3.
4.
5.
DI an = data-in for bank a and address n.
DO bn = data-out from bank b and address n.
One subsequent element of each burst follow both DI an and DO bn.
BL = 2.
Only one NOP separating the WRITE and READ would have led to contention on the data
bus because of the input and output data timing conditions being used.
6. Nominal conditions are assumed for specifications not defined.
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©2003 Micron Technology, Inc. All rights reserved.
288Mb: x9, x18, x36 2.5V VEXT, 1.8V VDD, HSTL, CIO, RLDRAM II
Operations
Figure 23:
WRITE – DM Operation
T1
T0
T2
T3
T4
NOP
NOP
T5
T6
T6n
T7
T7n
T8
CK#
CK
tCK
COMMAND
NOP
WRITE
tCH
NOP
tCL
NOP
NOP
NOP
NOP
Bank a,
Add n
ADDRESS
DK#
DK
tDKL
WL = 5
tDKH
DI
an
DQ
DM
tDS
tDH
TRANSITIONING DATA
Notes:
PDF: 09005aef80a41b46/Source: 09005aef809f284b
288Mb_RLDRAM_II_CIO.Core.fm - Rev A 9/07 EN
1.
2.
3.
4.
DON’T CARE
DI an = data-in for bank a and address n.
Subsequent elements of burst are provided on following clock edges.
BL = 4.
Nominal conditions are assumed for specifications not defined.
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288Mb: x9, x18, x36 2.5V VEXT, 1.8V VDD, HSTL, CIO, RLDRAM II
Operations
READ
Figure 24:
Basic READ Burst Timing
T1
T0
T2
T3
T4
T5
NOP
NOP
T5n
T6
T6n
T7
CK#
CK
tCK
COMMAND
READ
NOP
tCH
tCL
NOP
READ
Bank a
Add n
ADDRESS
NOP
NOP
Bank a
Add n
RL = 4
tRC = 4
DM
tCKQK (MIN)
tCKQK (MIN)
QK#
QK
tQK
tQKH
tQKVLD
tQKL
tQKVLD
QVLD
DO
an
DQ
tCKQK (MAX)
tCKQK (MAX)
QK#
QK
tQK
tQKH
tQKL
QVLD
DO
an
DQ
TRANSITIONING DATA
Notes:
PDF: 09005aef80a41b46/Source: 09005aef809f284b
288Mb_RLDRAM_II_CIO.Core.fm - Rev A 9/07 EN
1.
2.
3.
4.
DON’T CARE
DO an = data-out from bank a and address an.
Three subsequent elements of the burst are applied following DO an.
BL = 4.
Nominal conditions are assumed for specifications not defined.
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288Mb: x9, x18, x36 2.5V VEXT, 1.8V VDD, HSTL, CIO, RLDRAM II
Operations
Figure 25:
Consecutive READ Bursts (BL = 2)
T5n
T6n
T0
T1
T2
T3
T4
COMMAND
READ
READ
READ
READ
READ
READ
READ
ADDRESS
Bank a
Add n
Bank b
Add n
Bank c
Add n
Bank d
Add n
Bank e
Add n
Bank f
Add n
Bank g
Add n
CK#
T4n
T5
T6
CK
RL = 4
QVLD
QK#
QK
DO
an
DQ
DO
bn
DO
cn
TRANSITIONING DATA
Notes:
Figure 26:
DON’T CARE
1.
2.
3.
4.
5.
DO an (or bn or cn) = data-out from bank a (or bank b or bank c) and address n.
One subsequent element of the burst from each bank appears after each DO x.
Nominal conditions are assumed for specifications not defined.
Example applies only when READ commands are issued to same device.
Bank address can be to any bank, but the subsequent READ can only be to the same bank if
tRC has been met.
6. Data from the READ commands to bank d through bank g will appear on subsequent clock
cycles that are not shown.
Consecutive READ Bursts (BL = 4)
T0
T1
T2
T3
T4
COMMAND
READ
NOP
READ
NOP
READ
ADDRESS
Bank a
Add n
CK#
T4n
T5
T5n
T6n
T6
CK
Bank b
Add n
NOP
Bank c
Add n
READ
Bank d
Add n
RL = 4
QVLD
QK#
QK
DO
an
DQ
TRANSITIONING DATA
Notes:
PDF: 09005aef80a41b46/Source: 09005aef809f284b
288Mb_RLDRAM_II_CIO.Core.fm - Rev A 9/07 EN
DO
bn
DON’T CARE
1.
2.
3.
4.
5.
DO an (or bn) = data-out from bank a (or bank b) and address n.
Three subsequent elements of the burst from each bank appears after each DO x.
Nominal conditions are assumed for specifications not defined.
Example applies only when READ commands are issued to same device.
Bank address can be to any bank, but the subsequent READ can only be to the same bank if
tRC has been met.
6. Data from the READ commands to banks c and d will appear on subsequent clock cycles
that are not shown.
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288Mb: x9, x18, x36 2.5V VEXT, 1.8V VDD, HSTL, CIO, RLDRAM II
Operations
Figure 27:
READ-to-WRITE
T0
T1
T2
T3
T4
T5
T6
T7
T8
COMMAND
READ
NOP
WRITE
NOP
NOP
NOP
NOP
NOP
NOP
NOP
ADDRESS
Bank a,
Add n
CK#
CK
Bank b,
Add n
DM
QK#
QK
DK#
DK
RL = 4
WL = RL + 1 = 5
QVLD
DO
an
DQ
DI
bn
TRANSITIONING DATA
Notes:
PDF: 09005aef80a41b46/Source: 09005aef809f284b
288Mb_RLDRAM_II_CIO.Core.fm - Rev A 9/07 EN
1.
2.
3.
4.
5.
DON’T CARE
DO an = data-out from bank a and address n.
DI bn = data-in for bank b and address n.
Three subsequent elements of each burst follow DI bn and each DO an.
BL = 4.
Nominal conditions are assumed for specifications not defined.
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288Mb: x9, x18, x36 2.5V VEXT, 1.8V VDD, HSTL, CIO, RLDRAM II
Operations
Figure 28:
Read Data Valid Window for x9 Device
QK0#
QK0
tQKQ0 (MAX)2
tQHP1
tQKQ0 (MAX)2
tQKQ0 (MIN)2
tQHP1
tQKQ0 (MAX)2
tQKQ0 (MIN)2
tQHP1
tQKQ0 (MAX)2
tQKQ0 (MIN)2
tQHP1
tQKQ0 (MIN)2
tDVW3
tDVW3
tDVW3
tDVW3
DQ0
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
DQ8
DQ (last valid data)
DQ (first valid data)
All DQs and QKs collectively
Notes:
PDF: 09005aef80a41b46/Source: 09005aef809f284b
288Mb_RLDRAM_II_CIO.Core.fm - Rev A 9/07 EN
1.
2.
3.
tQHP
is defined as the lesser of tQKH or tQKL.
is referenced to DQ0–DQ8.
Minimum data valid window (tDVW) can be expressed as
tQHP - (tQKQx [MAX] + |tQKQx [MIN]|).
tQKQ0
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288Mb: x9, x18, x36 2.5V VEXT, 1.8V VDD, HSTL, CIO, RLDRAM II
Operations
Figure 29:
Read Data Valid Window for x18 Device
QK0#
QK0
tQKQ0 (MAX)2
tQHP1
tQKQ0 (MAX)2
tQKQ0 (MIN)2
tQHP1
tQKQ0 (MAX)2
tQKQ0 (MIN)2
tQHP1
tQKQ0 (MAX)2
tQKQ0 (MIN)2
tQHP1
tQKQ0 (MIN)2
DQ0
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
DQ8
DQ (last valid data)
DQ (first valid data)
All DQs and QKs collectively
tDVW3
tDVW3
tDVW3
tDVW3
QK1#
QK1
tQKQ1 (MAX)4
tQHP1
tQKQ1 (MAX)4
tQKQ1 (MIN)4
tQHP1
tQKQ1 (MAX)4
tQKQ1 (MIN)4
tQHP1
tQKQ1 (MAX)4
tQKQ1 (MIN)4
tQHP1
tQKQ1 (MIN)4
DQ9
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
DQ17
DQ (last valid data)
DQ (first valid data)
All DQs and QKs collectively
tDVW3
Notes:
PDF: 09005aef80a41b46/Source: 09005aef809f284b
288Mb_RLDRAM_II_CIO.Core.fm - Rev A 9/07 EN
tDVW3
t
t
tDVW3
tDVW3
t
1. QHP is defined as the lesser of QKH or QKL.
2. tQKQ0 is referenced to DQ0–DQ8.
3. Minimum data valid window (tDVW) can be expressed as
t
QHP - (tQKQx [MAX] + |tQKQx [MIN]|).
4. tQKQ1 is referenced to DQ9–DQ17.
5. tQKQ takes into account the skew between any QKx and any DQ.
52
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288Mb: x9, x18, x36 2.5V VEXT, 1.8V VDD, HSTL, CIO, RLDRAM II
Operations
Figure 30:
Read Data Valid Window for x36 Device
QK0#
QK0
tQKQ0 (MAX)2
tQHP1
tQKQ0 (MAX)2
tQKQ0 (MIN)2
tQHP1
tQKQ0 (MAX)2
tQKQ0 (MIN)2
tQHP1
tQKQ0 (MAX)2
tQKQ0 (MIN)2
tQHP1
tQKQ0 (MIN)2
Lower word
DQ0
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
DQ17
DQ (last valid data)
DQ (first valid data)
All DQs and QKs collectively
tDVW3
tDVW3
tDVW3
tDVW3
tQHP1
tQKQ1(MAX)4
tQKQ1(MIN)4
tQKQ1 (MIN)4
tDVW3
tDVW3
QK1#
QK1
tQKQ1 (MAX)4
tQHP1
tQKQ1 (MAX)4
tQKQ1 (MIN)4
tQHP1
tQKQ1 (MAX)4
tQKQ1 (MIN)4
tQHP1
Upper word
DQ18
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
DQ35
DQ (last valid data)
DQ (first valid data)
All DQs and QKs collectively
tDVW3
Notes:
PDF: 09005aef80a41b46/Source: 09005aef809f284b
288Mb_RLDRAM_II_CIO.Core.fm - Rev A 9/07 EN
tDVW3
1. tQHP is defined as the lesser of tQKH or tQKL.
2. tQKQ0 is referenced to DQ0–DQ17.
3. Minimum data valid window, tDVW, can be expressed as
tQHP - (tQKQx [MAX] + |tQKQx [MIN]|).
4. tQKQ1 is referenced to DQ18–DQ35.
5. tQKQ takes into account the skew between any QKx and any DQ.
53
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288Mb: x9, x18, x36 2.5V VEXT, 1.8V VDD, HSTL, CIO, RLDRAM II
Operations
AUTO REFRESH
Figure 31:
AUTO REFRESH Cycle
T0
T1
CK
tCK
COMMAND
AREFx
AREFy
ADDRESS
BANK
BAx
T2
((
))
CK#
BAy
((
))
T3
tCH
ACx
DQ
DM
tRC
((
))
((
))
((
))
Indicates a break in
time scale
PDF: 09005aef80a41b46/Source: 09005aef809f284b
288Mb_RLDRAM_II_CIO.Core.fm - Rev A 9/07 EN
ACy
((
))
((
))
DK, DK#
Notes:
tCL
DON’T CARE
1. AREFx = AUTO REFRESH command to bank x.
2. ACx = any command to bank x; ACy = any command to bank y.
3. BAx = bank address to bank x; BAy = bank address to bank y.
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Operations
On-Die Termination
Figure 32:
CK#
READ Burst with ODT
T0
T1
T2
T3
T4
T4n
READ
NOP
NOP
NOP
NOP
T5
T5n
T6
T6n
T7
T7n
CK
COMMAND
ADDRESS
NOP
NOP
NOP
NOP
Bank a,
Col n
RL = 4
QK#
BL = 2
QK
QVLD
DO
an
DQ
DQ ODT
DQ ODT on
DQ ODT on
DQ ODT off
QK#
BL = 4
QK
QVLD
DO
an
DQ
DQ ODT
DQ ODT on
DQ ODT off
DQ ODT on
QK#
BL = 8
QK
QVLD
DO
an
DQ
DQ ODT off
DQ ODT on
DQ ODT
TRANSITIONING DATA
Notes:
PDF: 09005aef80a41b46/Source: 09005aef809f284b
288Mb_RLDRAM_II_CIO.Core.fm - Rev A 9/07 EN
on
DON’T CARE
1. DO an = data out from bank a and address n.
2. DO an is followed by the remaining bits of the burst.
3. Nominal conditions are assumed for specifications not defined.
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288Mb: x9, x18, x36 2.5V VEXT, 1.8V VDD, HSTL, CIO, RLDRAM II
Operations
Figure 33:
READ-NOP-READ with ODT
CK#
T0
T1
T2
T3
T4
T4n
READ
NOP
READ
NOP
NOP
T5
T6
T6n
NOP
NOP
T7
CK
COMMAND
Bank a,
Col n
ADDRESS
NOP
NOP
Bank b,
Col n
RL = 4
QK#
QK
QVLD
DO
an
DQ
DQ ODT on
DQ ODT
DO
bn
DQ ODT on
DQ ODT off
DQ ODT on
DQ ODT off
TRANSITIONING DATA
Notes:
Figure 34:
1.
2.
3.
4.
DON’T CARE
DO an (or bn) = data-out from bank a (or bank b) and address n.
BL = 2.
One subsequent element of the burst appear after DO an and DO bn.
Nominal conditions are assumed for specifications not defined.
READ-to-WRITE with ODT
T0
T1
T2
T3
T4
COMMAND
READ
WRITE
NOP
NOP
NOP
ADDRESS
Bank a
Add n
Bank b
Add n
T4n
T5
T6
NOP
NOP
T6n
T7
T8
NOP
NOP
T9
CK#
CK
RL = 4
WL = 5
DKx#
DKx
DO
an
DQ
DI
bn
QKx
QKx#
ODT
ODT on
ODT off
ODT on
UNDEFINED
Notes:
PDF: 09005aef80a41b46/Source: 09005aef809f284b
288Mb_RLDRAM_II_CIO.Core.fm - Rev A 9/07 EN
1.
2.
3.
4.
DON’T CARE
DO an = data-out from bank a and address n; DI bn = data-in for bank b and address n.
BL = 2.
One subsequent element of each burst appears after each DO an and DI bn.
Nominal conditions are assumed for specifications not defined.
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288Mb: x9, x18, x36 2.5V VEXT, 1.8V VDD, HSTL, CIO, RLDRAM II
Operations
Multiplexed Address Mode
Figure 35:
Command Description in Multiplexed Address Mode
READ
WRITE
MRS
REF
CK#
CK
CS#
WE#
REF#
ADDRESS
Ax
BANK
ADDRESS
BA
Ay
Ax
Ay
Ax
BA
BA
Ay
BA
DON’T CARE
Notes:
PDF: 09005aef80a41b46/Source: 09005aef809f284b
288Mb_RLDRAM_II_CIO.Core.fm - Rev A 9/07 EN
1. The minimum setup and hold times of the two address parts are defined tAS and tAH.
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288Mb: x9, x18, x36 2.5V VEXT, 1.8V VDD, HSTL, CIO, RLDRAM II
Operations
Figure 36:
Power-Up/Initialization Sequence in Multiplexed Address Mode
VEXT
VDD
VDDQ
VREF
VTT
T0
T1
tCK
CK#
CK
tCKL
tCKH
T3
T2
T4
T5
T6
T7
T8
T9
T10
T11
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
tDK
DK#
DK
tDKH
COMMAND
NOP
tDKL
NOP
NOP
((
))
((
))
NOP
MRS
MRS
MRS
((
))
((
))
MRS
NOP
((
))
((
))
((
))
((
))
REF
((
))
((
))
((
))
((
))
REF
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
5
VALID
((
))
((
))
VALID
DM
((
))
((
))
ADDRESS
((
))
((
))
BANK
ADDRESS
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
tMRSC
tMRSC
Refresh
all banks9
1,024 NOP
commands
DQ
RTT
High-Z
1,2
CODE
1,2
CODE
T = 200µs (MIN)
2,3
CODE
((
))
((
))
Ax
2,4
Ay
2
5
VALID
Bank 0
((
))
((
))
Bank 7
5
Power-up:
VDD and stable
clock (CK, CK#)
Indicates a break in
time scale
Notes:
PDF: 09005aef80a41b46/Source: 09005aef809f284b
288Mb_RLDRAM_II_CIO.Core.fm - Rev A 9/07 EN
DON’T CARE
1. Recommended that all address pins held LOW during dummy MRS commands.
2. A10–A18 must be LOW.
3. Set address A5 HIGH. This enbles the part to enter multiplexed address mode when in nonmultiplexed mode operation. Multiplexed address mode can also be entered at some later
time by issuing an MRS command with A5 HIGH. Once address bit A5 is set HIGH, tMRSC
must be satisfied before the two-cycle multiplexed mode MRS command is issued.
4. Address A5 must be set HIGH. This and the following step set the desired mode register
once the RLDRAM is in multiplexed address mode.
5. Any command or address.
6. The above sequence must be followed in order to power up the RLDRAM in the multiplexed
address mode.
7. DLL must be reset if tCK or VDD are changed.
8. CK and CK# must separated at all times to prevent bogus commands from being issued.
9. The sequence of the eight AUTO REFRESH commands (with respect to the 1,024 NOP commands) does not matter. As is required for any operation, tRC must be met between an
AUTO REFRESH command and a subsequent VALID command to the same bank.
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288Mb: x9, x18, x36 2.5V VEXT, 1.8V VDD, HSTL, CIO, RLDRAM II
Operations
Figure 37:
Mode Register Definition in Multiplexed Address Mode
A5 A4 A3
A0
Ax A18 . . . A10 A9 A8
Ay A18 . . . A10
A9 A8
A4 A3
18–10
9 8 7 6 5
Reserved1 ODT IM DLL NA5 AM
4
3
2
BL
1
0
Mode Register (Mx)
Config
M2
M1
M0
0
Off (default)
0
0
0
Configuration
12 (default)
1
On
0
0
1
12
0
1
0
2
0
1
1
3
0
0
M9 On-Die Termination
M8
Drive Impedance
M7
DLL Reset
1
0
Internal 50Ω3 (default)
0
DLL reset4 (default)
1
0
1
42,6
56
External (ZQ)
1
DLL enabled
1
1
0
Reserved
1
1
1
Reserved
1
PDF: 09005aef80a41b46/Source: 09005aef809f284b
288Mb_RLDRAM_II_CIO.Core.fm - Rev A 9/07 EN
1.
2.
3.
4.
5.
6.
7.
8.
Burst Length
Address MUX
0
Nonmultiplexed (default)
0
0
2 (default)
Multiplexed
0
1
4
1
0
8
1
1
Reserved
1
Notes:
M4 M3
M5
Bits A10–A18 must be set to zero.
BL = 8 is not available.
±30 percent temperature variation.
DLL RESET turns the DLL off.
Ay8 not used in MRS.
Available only in 576Mb device.
BA0–BA2 are “Don’t Care.”
Addresses A0, A3, A4, A5, A8, and A9 must be set as shown in order to activate the mode
register in the multiplexed address mode.
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288Mb: x9, x18, x36 2.5V VEXT, 1.8V VDD, HSTL, CIO, RLDRAM II
Operations
Address Mapping in Multiplexed Address Mode
Table 21:
288Mb Address Mapping in Multiplexed Address Mode
Data
Width
Burst
Length
x36
2
4
x18
2
4
8
x9
2
4
8
Address
Ball
A0
A3
A4
A5
A8
A9
A10
A13
A14
A17
A18
Ax
Ay
Ax
Ay
Ax
Ay
Ax
Ay
Ax
Ay
Ax
Ay
Ax
Ay
Ax
Ay
A0
X
A0
X
A0
X
A0
X
A0
X
A0
A20
A0
X
A0
X
A3
A1
A3
A1
A3
A1
A3
A1
A3
A1
A3
A1
A3
A1
A3
A1
A4
A2
A4
A2
A4
A2
A4
A2
A4
A2
A4
A2
A4
A2
A4
A2
A5
X
A5
X
A5
X
A5
X
A5
X
A5
X
A5
X
A5
X
A8
A6
A8
A6
A8
A6
A8
A6
A8
A6
A8
A6
A8
A6
A8
A6
A9
A7
A9
A7
A9
A7
A9
A7
A9
A7
A9
A7
A9
A7
A9
A7
A10
X
A10
X
A10
A19
A10
X
A10
X
A10
A19
A10
A19
A10
X
A13
A11
A13
A11
A13
A11
A13
A11
A13
A11
A13
A11
A13
A11
A13
A11
A14
A12
A14
A12
A14
A12
A14
A12
A14
A12
A14
A12
A14
A12
A14
A12
A17
A16
A17
A16
A17
A16
A17
A16
A17
A16
A17
A16
A17
A16
A17
A16
A18
A15
X
A15
A18
A15
A18
A15
X
A15
A18
A15
A18
A15
A18
A15
Notes:
PDF: 09005aef80a41b46/Source: 09005aef809f284b
288Mb_RLDRAM_II_CIO.Core.fm - Rev A 9/07 EN
1. X = “Don’t Care.”
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Operations
Configuration Tables in Multiplexed Address Mode
In multiplexed address mode, the read and write latencies are increased by one clock
cycle. However, the RLDRAM cycle time remains the same as when in non-multiplexed
address mode.
Table 22:
Cycle Time and READ/WRITE Latency Configuration Table in Multiplexed Mode
Configuration
Parameter
t
RC
t
RL
t
WL
Valid frequency range
Notes:
11
2
3
4
5
6
200–175
6
7
8
300–175
8
9
10
400–175
Units
t
CK
CK
t
CK
MHz
t
1. BL = 8 is not available.
REFRESH Command in Multiplexed Address Mode
Similar to other commands when in multiplexed address mode, AREF is executed on the
rising clock edge following the one on which the command is issued. However, since
only the bank address is required for AREF, the next command can be applied on the
following clock. The operation of the AREF command and any other command is represented in Figure 38 on page 61.
Figure 38:
BURST REFRESH Operation with Multiplexed Addressing
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
COMMAND
1
AC
NOP
AREF
AREF
AREF
AREF
AREF
AREF
AREF
AREF
ADDRESS
Ax
Ay
T10
T11
CK#
CK
BANK
Bank n
1
AC
Ax
Bank 0
Bank 1
Bank 2
Bank 3
Bank 4
Bank 5
Bank 6
Bank 7
Ay
Bank n
DON’T CARE
Notes:
PDF: 09005aef80a41b46/Source: 09005aef809f284b
288Mb_RLDRAM_II_CIO.Core.fm - Rev A 9/07 EN
1. Any command.
2. Bank n is chosen so that tRC is met.
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Operations
Figure 39:
Consecutive WRITE Bursts with Multiplexed Addressing
T0
T1
T2
T3
WRITE
NOP
WRITE
NOP
Ax
Ay
Ax
Ay
T4
T5
T6
WRITE
NOP
NOP
Ax
Ay
T6n
T7
T7n
T8
T8n
T9
CK#
CK
COMMAND
ADDRESS
BANK
Bank a
NOP
NOP
NOP
Bank a1
Bank b
DK#
DK
t
RC = 4
WL = 6
DI
a
DQ
DI
b
DM
TRANSITIONING DATA
Notes:
PDF: 09005aef80a41b46/Source: 09005aef809f284b
288Mb_RLDRAM_II_CIO.Core.fm - Rev A 9/07 EN
DON’T CARE
1. Data from the second WRITE command to bank a will appear on subsequent clock cycles
that are not shown.
2. DI a = data-in for bank a; DI b = data-in for bank b.
3. Three subsequent elements of the burst are applied following DI for each bank.
4. Each WRITE command may be to any bank; if the second WRITE is to the same bank, tRC
must be met.
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Operations
Figure 40:
WRITE-to-READ with Multiplexed Addressing
T0
T1
T2
T3
T4
T5
T6
WRITE
NOP
READ
NOP
NOP
NOP
NOP
Ax
Ay
Ax
Ay
T6n
T7
T7n
CK#
CK
COMMAND
ADDRESS
NOP
WL = 6
BANK
Bank a
Bank b
RL = 5
QK#
QK
DK#
DK
QVLD
DI
a
DQ
DO
b
DM
TRANSITIONING DATA
Notes:
PDF: 09005aef80a41b46/Source: 09005aef809f284b
288Mb_RLDRAM_II_CIO.Core.fm - Rev A 9/07 EN
1.
2.
3.
4.
5.
6.
DON’T CARE
DI a = data-in for bank a.
DO b = data-out from bank b.
One subsequent element of each burst follows DI a and DO b.
BL = 2.
Nominal conditions are assumed for specifications not defined.
Bank address can be to any bank, but the subsequent READ can only be to the same bank if
tRC has been met.
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288Mb: x9, x18, x36 2.5V VEXT, 1.8V VDD, HSTL, CIO, RLDRAM II
Operations
Figure 41:
Consecutive READ Bursts with Multiplexed Addressing
T0
T1
T2
T3
T4
T5
READ
NOP
READ
NOP
READ
NOP
Ax
Ay
Ax
Ay
Ax
T5n
T6
T6n
CK#
CK
COMMAND
ADDRESS
BANK
Bank a
Bank b
READ
Ay
Ax
Bank c
Bank d
RL = 5
QVLD
QK#
QK
DO
a
DQ
TRANSITIONING DATA
Notes:
PDF: 09005aef80a41b46/Source: 09005aef809f284b
288Mb_RLDRAM_II_CIO.Core.fm - Rev A 9/07 EN
DON’T CARE
1.
2.
3.
4.
5.
6.
DO a = data-out from bank a.
Nominal conditions are assumed for specifications not defined.
BL = 4.
Three subsequent elements of the burst appear following DO a.
Example applies only when READ commands are issued to same device.
Bank address can be to any bank, but the subsequent READ can only be to the same bank if
tRC has been met.
7. Data from the READ commands to banks b through bank d will appear on subsequent clock
cycles that are not shown.
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Operations
Figure 42:
CK#
READ-to-WRITE with Multiplexed Addressing
T0
T1
T2
T3
T4
T5
READ
NOP
WRITE
NOP
NOP
NOP
Ax
Ay
Ax
Ay
T5n
T6
T6n
T7
T8
NOP
NOP
NOP
T8n
CK
COMMAND
ADDRESS
BANK
Bank a
NOP
Bank b
DM
QK#
QK
DK#
DK
RL = 5
WL = RL + 1 = 6
QVLD
DO
an
DQ
DI
bn
TRANSITIONING DATA
Notes:
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1.
2.
3.
4.
5.
6.
7.
DON’T CARE
DO an = data-out from bank a.
DI bn = data-in for bank b.
Nominal conditions are assumed for specifications not defined.
BL = 4.
Three subsequent elements of the burst are applied following DO an.
Three subsequent elements of the burst which appear following DI bn are not all shown.
Bank address can be to any bank, but the WRITE command can only be to the same bank if
tRC has been met.
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IEEE 1149.1 Serial Boundary Scan (JTAG)
IEEE 1149.1 Serial Boundary Scan (JTAG)
RLDRAM incorporates a serial boundary-scan test access port (TAP) for the purpose of
testing the connectivity of the device once it has been mounted on a printed circuit
board (PCB). As the complexity of PCB high-density surface mounting techniques
increases, the boundary-scan architecture is a valuable resource for interconnectivity
debug. This port operates in accordance with IEEE Standard 1149.1-2001 (JTAG) with
the exception of the ZQ pin. To ensure proper boundary-scan testing of the ZQ pin, MRS
bit M8 needs to be set to 0 until the JTAG testing of the pin is complete. Note that upon
power up, the default state of MRS bit M8 is low.
The input signals of the test access port (TDI, TMS, and TCK) use VDD as a supply, while
the output signal of the TAP (TDO) uses VDDQ.
The JTAG test access port utilizes the TAP controller on the RLDRAM, from which the
instruction register, boundary scan register, bypass register, and ID register can be
selected. Each of these functions of the TAP controller is described in detail below.
Disabling the JTAG Feature
It is possible to operate RLDRAM without using the JTAG feature. To disable the TAP
controller, TCK must be tied LOW (VSS) to prevent clocking of the device. TDI and TMS
are internally pulled up and may be unconnected. They may alternately be connected to
VDD through a pull-up resistor. TDO should be left unconnected. Upon power-up, the
device will come up in a reset state, which will not interfere with the operation of the
device.
Test Access Port (TAP)
Test Clock (TCK)
The test clock is used only with the TAP controller. All inputs are captured on the rising
edge of TCK. All outputs are driven from the falling edge of TCK.
Test Mode Select (TMS)
The TMS input is used to give commands to the TAP controller and is sampled on the
rising edge of TCK.
All of the states in Figure 43: “TAP Controller State Diagram,” on page 68 are entered
through the serial input of the TMS pin. A “0” in the diagram represents a LOW on the
TMS pin during the rising edge of TCK while a “1” represents a HIGH on TMS.
Test Data-In (TDI)
The TDI ball is used to serially input test instructions and data into the registers and can
be connected to the input of any of the registers. The register between TDI and TDO is
chosen by the instruction that is loaded into the TAP instruction register. For information on loading the instruction register, see Figure 43 on page 68. TDI is connected to the
most significant bit (MSB) of any register (see Figure 44 on page 68).
Test Data-Out (TDO)
The TDO output ball is used to serially clock test instructions and data out from the
registers. The TDO output driver is only active during the Shift-IR and Shift-DR TAP
controller states. In all other states, the TDO pin is in a High-Z state. The output changes
on the falling edge of TCK. TDO is connected to the least significant bit (LSB) of any
register (see Figure 44 on page 68).
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IEEE 1149.1 Serial Boundary Scan (JTAG)
TAP Controller
The TAP controller is a finite state machine that uses the state of the TMS pin at the
rising edge of TCK to navigate through its various modes of operation. The TAP
controller state diagram can be seen in Figure 43 on page 68. Each state is described in
detail below.
Test-Logic-Reset
The test-logic-reset controller state is entered when TMS is held HIGH for at least five
consecutive rising edges of TCK. As long as TMS remains HIGH, the TAP controller will
remain in the test-logic-reset state. The test logic is inactive during this state.
Run-Test/Idle
The run-test/idle is a controller state in between scan operations. This state can be
maintained by holding TMS LOW. From here either the data register scan, or subsequently, the instruction register scan can be selected.
Select-DR-Scan
Select-DR-scan is a temporary controller state. All test data registers retain their previous
state while here.
Capture-DR
The capture-DR state is where the data is parallel-loaded into the test data registers. If
the boundary scan register is the currently selected register, then the data currently on
the pins is latched into the test data registers.
Shift-DR
Data is shifted serially through the data register while in this state. As new data is input
through the TDI pin, data is shifted out of the TDO pin.
Exit1-DR, Pause-DR, and Exit2-DR
The purpose of exit1-DR is used to provide a path to return back to the run-test/idle
state (through the update-DR state). The pause-DR state is entered when the shifting of
data through the test registers needs to be suspended. When shifting is to reconvene, the
controller enters the exit2-DR state and then can re-enter the shift-DR state.
Update-DR
When the EXTEST instruction is selected, there are latched parallel outputs of the
boundary-scan shift register that only change state during the update-DR controller
state.
Instruction Register States
The instruction register states of the TAP controller are similar to the data register states.
The desired instruction is serially shifted into the instruction register during the shift-IR
state and is loaded during the update-IR state.
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IEEE 1149.1 Serial Boundary Scan (JTAG)
Figure 43:
TAP Controller State Diagram
1
Test-logic
reset
0
Run-test/
Idle
0
1
Select
DR-scan
1
Select
IR-scan
0
1
0
1
Capture-DR
Capture-IR
0
0
Shift-DR
Shift-IR
0
1
1
Exit1-IR
0
Pause-IR
0
1
0
1
Exit2-DR
0
Exit2-IR
1
1
Update-DR
Figure 44:
1
0
Pause-DR
1
0
1
Exit1-DR
0
1
Update-IR
1
0
0
TAP Controller Block Diagram
0
Bypass register
7 6 5 4 3 2 1 0
TDI
Selection
circuitry
Instruction register
31 30 29 .
.
. 2 1 0
Selection
circuitry
TDO
Identification register
x1 . . . . . 2 1 0
Boundry scan register
TCK
TMS
Notes:
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TAP controller
1. x = 112 for all configurations.
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IEEE 1149.1 Serial Boundary Scan (JTAG)
Performing a TAP RESET
A reset is performed by forcing TMS HIGH (VDDQ) for five rising edges of TCK. This
RESET does not affect the operation of the RLDRAM and may be performed while the
RLDRAM is operating.
At power-up, the TAP is reset internally to ensure that TDO comes up in a High-Z state.
TAP Registers
Registers are connected between the TDI and TDO balls and allow data to be scanned
into and out of the RLDRAM test circuitry. Only one register can be selected at a time
through the instruction register. Data is serially loaded into the TDI ball on the rising
edge of TCK. Data is output on the TDO ball on the falling edge of TCK.
Instruction Register
Eight-bit instructions can be serially loaded into the instruction register. This register is
loaded during the update-IR state of the TAP controller. Upon power-up, the instruction
register is loaded with the IDCODE instruction. It is also loaded with the IDCODE
instruction if the controller is placed in a reset state as described in the previous section.
When the TAP controller is in the capture-IR state, the two LSBs are loaded with a binary
“01” pattern to allow for fault isolation of the board-level serial test data path.
Bypass Register
To save time when serially shifting data through registers, it is sometimes advantageous
to skip certain chips. The bypass register is a single-bit register that can be placed
between the TDI and TDO balls. This allows data to be shifted through the RLDRAM
with minimal delay. The bypass register is set LOW (VSS) when the BYPASS instruction is
executed.
Boundary Scan Register
The boundary scan register is connected to all the input and bidirectional balls on the
RLDRAM. Several balls are also included in the scan register to reserved balls. The
RLDRAM has a 113-bit register.
The boundary scan register is loaded with the contents of the RAM I/O ring when the
TAP controller is in the capture-DR state and is then placed between the TDI and TDO
balls when the controller is moved to the shift-DR state.
Table 29 on page 74 shows the order in which the bits are connected. Each bit corresponds to one of the balls on the RLDRAM package. The MSB of the register is connected
to TDI, and the LSB is connected to TDO.
Identification (ID) Register
The ID register is loaded with a vendor-specific, 32-bit code during the capture-DR state
when the IDCODE command is loaded in the instruction register. The IDCODE is hardwired into the RLDRAM and can be shifted out when the TAP controller is in the shift-DR
state. The ID register has a vendor code and other information described in Table 26 on
page 73.
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IEEE 1149.1 Serial Boundary Scan (JTAG)
TAP Instruction Set
Overview
Many different instructions (28) are possible with the 8-bit instruction register. All
combinations used are listed in Table 28 on page 74. These six instructions are described
in detail below. The remaining instructions are reserved and should not be used.
The TAP controller used in this RLDRAM is fully compliant to the 1149.1 convention.
Instructions are loaded into the TAP controller during the shift-IR state when the
instruction register is placed between TDI and TDO. During this state, instructions are
shifted through the instruction register through the TDI and TDO balls. To execute the
instruction once it is shifted in, the TAP controller needs to be moved into the update-IR
state.
EXTEST
The EXTEST instruction allows circuitry external to the component package to be tested.
Boundary-scan register cells at output balls are used to apply a test vector, while those at
input balls capture test results. Typically, the first test vector to be applied using the
EXTEST instruction will be shifted into the boundary scan register using the PRELOAD
instruction. Thus, during the update-IR state of EXTEST, the output driver is turned on,
and the PRELOAD data is driven onto the output balls.
IDCODE
The IDCODE instruction causes a vendor-specific, 32-bit code to be loaded into the
instruction register. It also places the instruction register between the TDI and TDO balls
and allows the IDCODE to be shifted out of the device when the TAP controller enters
the shift-DR state. The IDCODE instruction is loaded into the instruction register upon
power-up or whenever the TAP controller is given a test logic reset state.
High-Z
The High-Z instruction causes the boundary scan register to be connected between the
TDI and TDO. This places all RLDRAM outputs into a High-Z state.
CLAMP
When the CLAMP instruction is loaded into the instruction register, the data driven by
the output balls are determined from the values held in the boundary scan register.
SAMPLE/PRELOAD
When the SAMPLE/PRELOAD instruction is loaded into the instruction register and the
TAP controller is in the capture-DR state, a snapshot of data on the inputs and bidirectional balls is captured in the boundary scan register.
The user must be aware that the TAP controller clock can only operate at a frequency up
to 50 MHz, while the RLDRAM clock operates significantly faster. Because there is a large
difference between the clock frequencies, it is possible that during the capture-DR state,
an input or output will undergo a transition. The TAP may then try to capture a signal
while in transition (metastable state). This will not harm the device, but there is no guarantee as to the value that will be captured. Repeatable results may not be possible.
To ensure that the boundary scan register will capture the correct value of a signal, the
RLDRAM signal must be stabilized long enough to meet the TAP controller’s capture
setup plus hold time (tCS plus tCH). The RLDRAM clock input might not be captured
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IEEE 1149.1 Serial Boundary Scan (JTAG)
correctly if there is no way in a design to stop (or slow) the clock during a SAMPLE/
PRELOAD instruction. If this is an issue, it is still possible to capture all other signals and
simply ignore the value of the CK and CK# captured in the boundary scan register.
Once the data is captured, it is possible to shift out the data by putting the TAP into the
shift-DR state. This places the boundary scan register between the TDI and TDO balls.
BYPASS
When the BYPASS instruction is loaded in the instruction register and the TAP is placed
in a shift-DR state, the bypass register is placed between TDI and TDO. The advantage of
the BYPASS instruction is that it shortens the boundary scan path when multiple devices
are connected together on a board.
Reserved for Future Use
The remaining instructions are not implemented but are reserved for future use. Do not
use these instructions.
Figure 45:
JTAG Operation – Loading Instruction Code and Shifting Out Data
T0
T1
T2
T3
T4
T5
T6
T7
TCK
TMS
((
))
((
))
TDI
((
))
((
))
TAP
CONTROLLER
STATE
T8
T9
((
))
((
))
Test-LogicReset
Run-Test
Idle
Select-DRSCAN
Select-IRSCAN
Capture-IR
Shift-IR
Shift-IR
((
))
((
))
Exit 1-IR
Pause-IR
Pause-IR
((
))
((
))
TDO
8-bit instruction code
T10
T11
T12
T13
T14
T15
TCK
T17
T18
T19
Update-DR
Run-Test
Idle
Run-Test
Idle
((
))
((
))
TMS
((
))
((
))
TDI
TAP
CONTROLLER
STATE
T16
((
))
((
))
Exit 2-IR
Update-IR
Select-DRScan
Capture-DR
Shift-DR
Shift-DR
((
))
((
))
Exit1-DR
((
))
((
))
TDO
n-bit register between TDI and TDO
TRANSITIONING DATA
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DON’T CARE
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©2003 Micron Technology, Inc. All rights reserved.
288Mb: x9, x18, x36 2.5V VEXT, 1.8V VDD, HSTL, CIO, RLDRAM II
IEEE 1149.1 Serial Boundary Scan (JTAG)
Figure 46:
TAP Timing
T2
T1
T3
Test clock
(TCK)
tTHTL
tMVTH
tTHMX
tDVTH
tTHDX
T4
t
TLTH
T6
T5
tTHTH
Test mode select
(TMS)
Test data-in
(TDI)
tTLOV
tTLOX
Test data-out
(TDO)
UNDEFINED
Table 23:
DON’T CARE
TAP Input AC Logic Levels
+0°C ≤ TC ≤ +95°C; +1.7V ≤ VDD ≤ +1.9V, unless otherwise noted
Description
Symbol
Min
Max
Units
VIH
VIL
VREF + 0.3
–
–
VREF - 0.3
V
V
Max
Units
Input high (logic 1) voltage
Input low (logic 0) voltage
Notes:
Table 24:
1. All voltages referenced to VSS (GND).
TAP AC Electrical Characteristics
+0°C ≤ TC ≤ +95°C; +1.7V ≤ VDD ≤ +1.9V
Description
Symbol
Min
tTHTH
20
Clock
Clock cycle time
Clock frequency
Clock HIGH time
Clock LOW time
f
TF
tTHTL
tTLTH
50
10
10
ns
MHz
ns
ns
TDI/TDO times
t
TCK LOW to TDO unknown
TCK LOW to TDO valid
TDI valid to TCK HIGH
TCK HIGH to TDI invalid
TLOX
0
5
5
ns
ns
ns
ns
MVTH
tCS
5
5
ns
ns
tTHMX
5
5
ns
ns
tTLOV
tDVTH
tTHDX
10
Setup times
t
TMS setup
Capture setup
Hold times
TMS hold
Capture hold
t
CH
Notes:
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1.
tCS
tCH
and
refer to the setup and hold time requirements of latching data from the boundary scan register.
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IEEE 1149.1 Serial Boundary Scan (JTAG)
Table 25:
TAP DC Electrical Characteristics and Operating Conditions
+0°C ≤ TC ≤ +95°C; +1.7V ≤ VDD ≤ +1.9V, unless otherwise noted
Description
Condition
Input high (logic 1) voltage
Input low (logic 0) voltage
Input leakage current
Output leakage current
0V ≤ VIN ≤ VDD
Output disabled,
0V ≤ VIN ≤ VDDQ
IOLC = 100µA
IOLT = 2mA
|IOHC| = 100µA
|IOHT| = 2mA
Output low voltage
Output low voltage
Output high voltage
Output high voltage
Notes:
Table 26:
Min
Max
Units
Notes
VIH
VIL
ILI
ILO
VREF + 0.15
VSSQ - 0.3
–5.0
–5.0
VDD + 0.3
VREF - 0.15
5.0
5.0
V
V
µA
µA
1, 2
1, 2
0.2
0.4
V
V
V
V
1
1
1
1
VOL1
VOL2
VOH1
VOH2
VDDQ - 0.2
VDDQ - 0.4
1. All voltages referenced to VSS (GND).
2. Overshoot = VIH(AC) ≤ VDD + 0.7V for t ≤ tCK/2; undershoot = VIL(AC) ≥ –0.5V for t ≤ tCK/2;
during normal operation, VDDQ must not exceed VDD.
Identification Register Definitions
Instruction Field
All Devices
abcd
Revision number (31:28)
00jkidef10100111
Device ID (27:12)
Micron JEDEC ID code (11:1)
ID register presence indicator (0)
Table 27:
Symbol
00000101100
1
Description
ab = die revision
cd = 00 for x9, 01 for x18, 10 for x36
def = 000 for 288Mb, 001 for 576Mb
i = 0 for common I/O, 1 for separate I/O
jk = 01 for RLDRAM II, 00 for RLDRAM
Allows unique identification of RLDRAM vendor
Indicates the presence of an ID register
Scan Register Sizes
Register Name
Bit Size
8
1
32
113
Instruction
Bypass
ID
Boundary scan
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IEEE 1149.1 Serial Boundary Scan (JTAG)
Table 28:
Instruction Codes
Instruction
Code
Description
Extest
0000 0000
ID code
0010 0001
Sample/preload
Clamp
0000 0101
0000 0111
High-Z
0000 0011
Bypass
1111 1111
Captures I/O ring contents; Places the boundary scan register between TDI and TDO;
This operation does not affect RLDRAM operations
Loads the ID register with the vendor ID code and places the register between TDI and
TDO; This operation does not affect RLDRAM operations
Captures I/O ring contents; Places the boundary scan register between TDI and TDO
Selects the bypass register to be connected between TDI and TDO; Data driven by
output balls are determined from values held in the boundary scan register
Selects the bypass register to be connected between TDI and TDO; All outputs are
forced into High-Z
Places the bypass register between TDI and TDO; This operation does not affect
RLDRAM operations
Table 29:
Boundary Scan (Exit) Order
Bit#
Ball
Bit#
Ball
Bit#
Ball
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
K1
K2
L2
L1
M1
M3
M2
N1
P1
N3
N3
N2
N2
P3
P3
P2
P2
R2
R3
T2
T2
T3
T3
U2
U2
U3
U3
V2
U10
U10
U11
U11
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
R11
R11
P11
P11
P10
P10
N11
N11
N10
N10
P12
N12
M11
M10
M12
L12
L11
K11
K12
J12
J11
H11
H12
G12
G10
G11
E12
F12
F10
F10
F11
F11
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
C11
C11
C10
C10
B11
B11
B10
B10
B3
B3
B2
B2
C3
C3
C2
C2
D3
D3
D2
D2
E2
E2
E3
E3
F2
F2
F3
F3
E1
F1
G2
G3
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IEEE 1149.1 Serial Boundary Scan (JTAG)
Table 29:
Boundary Scan (Exit) Order (continued)
Bit#
Ball
Bit#
Ball
Bit#
Ball
33
34
35
36
37
38
T10
T10
T11
T11
R10
R10
71
72
73
74
75
76
E10
E10
E11
E11
D11
D10
109
110
111
112
113
–
G1
H1
H2
J2
J1
–
®
8000 S. Federal Way, P.O. Box 6, Boise, ID 83707-0006, Tel: 208-368-3900
[email protected] www.micron.com Customer Comment Line: 800-932-4992
Micron, the M logo, and the Micron logo are trademarks of Micron Technology, Inc. RLDRAM is a trademark of Qimonda AG in various
countries, and is used by Micron Technology, Inc. under license from Qimonda. All other trademarks are the property of their respective
owners. This data sheet contains minimum and maximum limits specified over the power supply and temperature range set forth herein.
Although considered final, these specifications are subject to change, as further product development and data characterization sometimes occur.
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