Issue 5.2 April 2001 Description The PUMA68 range of devices provide a high density surface mount industry standard memory solution which may accommodate various memory technologies including SRAM, EEPROM and Flash. The devices are designed to offer a defined upgrade path and may be user configured as 8, 16 or 32 bits wide. The PUMA68SV16000XB is a 512Kx32 SRAM module housed in a 68 Jleaded package which complies with the JEDEC 68 PLCC standard. Access times of 12, 15 or 17ns are available. The 3.3V low voltage device is available to commercial and industrial temperature grade. Features • Access times of 12/15/17 ns. • 3.3V + 10%. • Commercial and Industrial temperature grades • JEDEC standard 68 J Lead footprint. • Industry standard pinout. • May be organised as 512K x 32, 1M x 16, 2M X 8 • Operating Power (32 Bit) 2.74W (max) • Low power standby. (TTL) 0.87W (max) (CMOS) 145mW (max) • Completely Static Operation. Package Details PUMA 68 - Plastic 68 ‘J’ Leaded Package Max. Dimensions (mm) - 25.27 x 25.27 x 5.08 Block Diagram A0~A18 /OE /WE 512K x 8 SRAM 512K x 8 SRAM 512K x 8 512K x 8 SRAM SRAM /CS1 /CS2 /CS3 /CS4 D0~7 D8~15 D16~23 D24~31 Pin Definition See page 2. Pin Functions Description Signal Address Input Data Input/Output Chip Select Write Enable Output Enable No Connect Power Ground A0~A18 D0~D31 /CS1~4 /WE /OE NC VCC VSS 512 K x 32 Static RAM PUMA 68SV16000XB - 012/015/017 Pin Definition - PUMA68SV16000X PAGE 2 Pin Signal Pin Signal 1 VCC 35 VCC 2 NC 36 A13 3 /CS1 37 A12 4 /CS2 38 A11 5 /CS3 39 A10 6 /CS4 40 A9 7 A17 41 A8 8 A18 42 A7 9 D16 43 D0 10 D17 44 D1 11 D18 45 D2 12 D19 46 D3 13 VSS 47 VSS 14 D20 48 D4 15 D21 49 D5 16 D22 50 D6 17 D23 51 D7 18 VCC 52 VCC 19 D24 53 D8 20 D25 54 D9 21 D26 55 D10 22 D27 56 D11 23 VSS 57 VSS 24 D28 58 D12 25 D29 59 D13 26 D30 60 D14 27 D31 61 D15 28 A6 62 A14 29 A5 63 A15 30 A4 64 A16 31 A3 65 /WE 32 A2 66 /OE 33 A1 67 NC 34 A0 68 NC Issue 5.2 April 2001 Absolute Maximum Ratings(1) Symbol Voltage on any pin relative to VSS VT Power Dissipation PT Storage Temperature TSTG Min -0.3 to Max Unit +4.6 V 4.0 -55 W to O +125 C Notes : (1) Stresses above those listed may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability Recommended Operating Conditions Parameter Symbol Min Typ Max Unit Supply Voltage VCC 3.0 3.3 3.6 V Input High Voltage VIH 2.0 - VCC+0.3 V Input Low Voltage VIL -0.3 - 0.8 V Operating Temperature TA 0 - 70 TAI -40 - 85 (1) O C O C (I Suffix) Notes : (1) Pulse Width : -2.0V for less than 10ns. DC Electrical Characteristics (VCC=3.3V+10%, TA=-40OC to +85OC) Parameter Symbol Test Condition Input Leakage Current Output Leakage Current Average Supply Current (2) Min Typ Max Unit ILI VIN=0V to VCC -8 - 8 µA ILO VI/O=0V to VCC -8 - 8 µA (1) 32 Bit ICC32 /CS =VIL, II/O=0mA,f=fmax - - 760 mA 16 Bit ICC16 As Above. - - 490 mA 8 Bit ICC8 As Above. - - 370 mA TTL ISB /CS =VIH ,Min Cycle - - 240 mA CMOS ISB1 /CS>VCC-0.2V, 0.2V >VIN>VCC-0.2V, f=0 - - 40 mA Output Voltage Low VOL IOL=8.0mA, VCC=Min - - 0.4 V Output Voltage High VOH IOH=-4.0mA, VCC=Min 2.4 - - V Standby Supply Current Notes PAGE 3 (1) (1) /CS1~4 inputs operate simultaneously for 32 bit mode, in pairs for 16 bit mode and singly for 8 bit mode. (2) At f=fMAX address and data inputs are cycling at max frequency. Issue 5.2 April 2001 DC Operating Conditions Parameter Capacitance (VCC = 3.3V, TA = 25OC, F=1MHz.) Parameter Symbol Test Condition Min Typ Max Unit Input Capacitance, Address, /OE, /WE CIN1 VIN=0V - - 30 pF Output Capacitance, 8 bit mode (worst case) CI/O VI/O=0V - - 34 pF Note : These Parameters are calculated not measured. Test Conditions • • • • • • Output Load I/O Pin Input pulse levels : 0V to 3.0V Input rise and fall times : 3ns Input and Output timing reference levels : 1.5V Output Load : See Load Diagram. VCC = 3.3V+10% PUMA module tested in 32 bit mode. 166Ω 1.76V 30pF Operation Truth Table /CS1 /CS2 /CS3 /CS4 /OE /WE Supply Current Mode L H H H X L ICC8 Write D0~D7 H L H H X L ICC8 Write D8~D15 H H L H X L ICC8 Write D16~D23 H H H L X L ICC8 Write D24~D31 L L H H X L ICC16 Write D0~D15 H H L L X L ICC16 Write D16~D31 L L L L X L ICC32 Write D0~D31 L H H H L H ICC8 Read D0~D7 H L H H L H ICC8 Read D8~D15 H H L H L H ICC8 Read D16~D23 H H H L L H ICC8 Read D24~D31 L L H H L H ICC16 Read D0~D15 H H L L L H ICC16 Read D16~D31 L L L L L H ICC32 Read D0~D31 X X X X H H H H H H X X ICC32 /ICC16/ICC8 D0~D31 High-Z ISB, ISB1 D0~D31 Standby Notes : H=VIH : L=VIL : X=VIH or VIL PAGE 4 Issue 5.2 April 2001 12 Parameter 15 17 Symbol Min Max Min Max Min Max Units Read Cycle Time tRC 12 - 15 - 17 - ns Address Access Time tAA - 12 - 15 - 17 ns Chip Select Access Time tACS - 12 - 15 - 17 ns Output Enable to Output Valid tOE - 6 - 7 - 8 ns Output Hold From Address Change tOH 3 - 3 - 3 - ns Chip Selection to Output in Low Z tCLZ 3 - 3 - 3 - ns Output Enable to Output in Low Z tOLZ 0 - 0 - 0 - ns Chip Deselection to Output in High Z tCHZ 0 6 0 7 0 8 ns Output Disable to Output in High Z tOHZ 0 6 0 7 0 8 ns Write Cycle 12 Parameter 15 17 Symbol Min Max Min Max Min Max Units Write Cycle Time tWC 12 - 15 - 17 - ns Chip Selection to End of Write tCW 8 - 10 - 12 - ns Address Valid to End of Write tAW 8 - 10 - 12 - ns Address Setup Time tAS 0 - 0 - 0 - ns Write Pulse Width (/OE High) tWP1 8 - 10 - 12 - ns Write Pulse Width (/OE Low) tWP2 12 - 12 - 13 - ns Write Recovery Time tWR 0 - 0 - 0 - ns Write to Output in High Z tWHZ 0 6 0 7 0 8 ns Data to Write Time Overlap tDW 6 - 7 - 8 - ns Data Hold time from Write Time tDH 0 - 0 - 0 - ns Output Active from End of Write tOW 3 - 3 - 3 - ns PAGE 5 Issue 5.2 April 2001 AC Operating Conditions Read Cycle Timing Waveforms Read Cycle 1 (Address Controlled, /CS=/OE=VIL, /WE=VIH) tRC Address tOH Data Out tAA Previous Data Valid Data Valid Read Cycle 2 (/WE = VIH) tRC Address tAA tACS tCHZ(3,4,5) /CS tOHZ tOE /OE tOLZ tOH tCLZ(4,5) Data Out Valid Data NOTES(READ CYCLE) 1. /WE is high for read cycle. 2. All read cycle timing is referenced from the last valid address to the first transition address. 3. tCHZ and tOHZ are defined as the time at which the outputs achieve the open circuit condition and are not referenced to V OH or VOL levels. 4. At any given temperature and voltage condition, t CHZ(Max.) is less than t CLZ(Min.) both for a given device and from device to device. 5. Transition is measured ±200mV from steady state voltage with Load(B). This parameter is sampled and not 100% tested. 6. Device is continuously selected with /CS=V IL. 7. Address valid prior to coincident with /CS transition low. 8. For common I/O applications, minimization or elimination of bus contention conditions is necessary during read and write cycle. 9. /CS=/CS1~4 PAGE 6 Issue 5.2 April 2001 Write Cycle 1 (/OE = Clock) tWC Address tAW tWR(5) /OE tCW(3) /CS tAS(4) tWP(2) /WE tDW tDH High Z Data In Valid Data tOHZ(6) High Z(8) Data Out NOTES(WRITE CYCLE) 1. All write cycle timing is referenced from the last valid address to the first transition address. 2. A write occurs during the overlap of a low /CS and /WE. A write begins at the latest transition /CS going low and /WE going low ; A write ends at the earliest transition /CS going high or /WE going high. tWP is measured from the beginning of write to the end of write. 3. tCW is measured from the later of /CS going low to end of write. 4. tAS is measured from the address valid to the beginning of write. 5. tWR is measured from the end of write to the address change. tWR applied in case a write ends as /CS or /WE going high. 6. If OE, /CS and /WE are in the Read Mode during this period, the I/O pins are in the output low-Z state. Inputs of opposite phase of the output must not be applied because bus contention can occur. 7. For common I/O applications, minimization or elimination of bus contention conditions is necessary during read and write cycle. 8. If /CS goes low simultaneously with /WE going or after /WE going low, the outputs remain high impedance state. 9. Dout is the read data of the new address. 10.When /CS is low : I/O pins are in the output state. The input signals in the opposite phase leading to the output should not be applied. 11 ./CS=/CS1~4 PAGE 7 Issue 5.2 April 2001 Write Cycle 2 (/OE = Low Fixed) tWC Address tAW tWR(5) tCW(3) /CS tAS(4) tWP(2) /WE tDW tDH High Z Valid Data Data In tOW tWHZ(6) High Z(8) (10) (9) Data Out NOTES(WRITE CYCLE) 1. All write cycle timing is referenced from the last valid address to the first transition address. 2. A write occurs during the overlap of a low /CS and /WE. A write begins at the latest transition /CS going low and /WE going low ; A write ends at the earliest transition /CS going high or /WE going high. tWP is measured from the beginning of write to the end of write. 3. tCW is measured from the later of /CS going low to end of write. 4. tAS is measured from the address valid to the beginning of write. 5. tWR is measured from the end of write to the address change. tWR applied in case a write ends as /CS or /WE going high. 6. If OE, /CS and /WE are in the Read Mode during this period, the I/O pins are in the output low-Z state. Inputs of opposite phase of the output must not be applied because bus contention can occur. 7. For common I/O applications, minimization or elimination of bus contention conditions is necessary during read and write cycle. 8. If /CS goes low simultaneously with /WE going or after /WE going low, the outputs remain high impedance state. 9. Dout is the read data of the new address. 10.When /CS is low : I/O pins are in the output state. The input signals in the opposite phase leading to the output should not be applied. 11 ./CS=/CS1~4 PAGE 8 Issue 5.2 April 2001 Write Cycle 3 (/CS = Controlled) tWC Address tAW tWR(5) tCW(3) /CS tAS(4) tWP(2) /WE tDW tDH High Z High Z Data In Valid Data tLZ High Z tWHZ(6) High Z(8) Data Out NOTES(WRITE CYCLE) 1. All write cycle timing is referenced from the last valid address to the first transition address. 2. A write occurs during the overlap of a low /CS and /WE. A write begins at the latest transition /CS going low and /WE going low ; A write ends at the earliest transition /CS going high or /WE going high. t WP is measured from the beginning of write to the end of write. 3. tCW is measured from the later of /CS going low to end of write. 4. tAS is measured from the address valid to the beginning of write. 5. tWR is measured from the end of write to the address change. t WR applied in case a write ends as /CS or /WE going high. 6. If /OE, /CS and /WE are in the Read Mode during this period, the I/O pins are in the output low-Z state. Inputs of opposite phase of the output must not be applied because bus contention can occur. 7. For common I/O applications, minimization or elimination of bus contention conditions is necessary during read and write cycle. 8. If /CS goes low simultaneously with /WE going or after /WE going low, the outputs remain high impedance state. 9. Dout is the read data of the new address. 10.When /CS is low : I/O pins are in the output state. The input signals in the opposite phase leading to the output should not be applied. 11 /CS=/CS1~4 PAGE 9 Issue 5.2 April 2001 Package Details PUMA 68 Pin JEDEC Surface Mount PLCC 25.27 (0.995) 25.02 (0.985) Pin 1 Pin 68 XXXXXX-X 5.08 (0. 200) max 0.46 (0. 018) 1.27 (0. 050) 0.90 (0. 035) typ 23.11 (0.910) 24.13 (0.950) Notes: 1. All dimensions in mm (inches). PAGE 10 Issue 5.2 April 2001 Ordering Information Speed 012 = 12ns 015 = 15ns 017 = 17ns Temp. Range/Screening Blank = Commercial I = Industrial Pinout Configuration XB = CSP Based Industry Standard Pinout Memory Organisation 16000 = 512K x 32 configurable as 1M x 16 and 2M x 8 Technology Package SV = SRAM 3.3V+10% VCC PUMA 68 = 68 pin ‘J’ Leaded PLCC Note : Although this data is believed to be accurate the information contained herein is not intended to and does not create any warranty of merchantibility or fitness for a particular purpose. Our products are subject to a constant process of development. Data may be changed without notice. Products are not authorised for use as critical components in life support devices without the express written approval of a company director. PAGE 11 Issue 5.2 April 2001 Ordering Information PUMA 68SV16000XBI-015 All devices inspected to ANSI/J-STD-001B Class 2 standard Moisture Sensitivity Devices are moisture sensitive. Shelf Life in Sealed Bag 12 months at <40OC and <90% relative humidity (RH). After this bag has been opened, devices that will be subjected to infrared reflow, vapour phase reflow, or equivalent processing (peak package body temp 220OC) must be : A : Mounted within 72 Hours at factory conditions of <30OC/60% RH OR B : Stored at <20% RH If these conditions are not met or indicator card is >20% when read at 23OC +/-5% devices require baking as specified below. If baking is required, devices may be baked for :A : 24 hours at 125OC +/-5% for high temperature device containers OR B : 192 hours at 40OC +5OC/-0OC and <5% RH for low temperature device containers. Packaging Standard Devices packaged in dry nitrogen, JED-STD-020. Packaged in trays as standard. Tape and reel available for shipment quantities exceeding 200pcs upon request. Soldering Recomendations IR/Convection - Ramp Rate Temp. exceeding 183OC Peak Temperature Time within 5OC of peak Ramp down 6OC/sec max. 150 secs. max. 225OC 20 secs max. 6OC/sec max. Vapour Phase - Ramp up rate Peak Temperature Time within 5OC of peak Ramp down 6OC/sec max. 215 - 219OC 60 secs max. 6OC/sec max. The above conditions must not be exceeded Note : The above recomendations are based on standard industry practice. Failiure to comply with the above recomendations invalidates product warranty. PAGE 12 Issue 5.2 April 2001 Customer Guidelines Visual Inspection Standard