2M x 8 SRAM MODULE SYS82000RKXC - 70/85/10/12 Issue 1.3 : April 2001 Description Features The SYS82000RKXC is a plastic 16Mbit Static RAM Module housed in a standard 38 pin Single InLine package organised as 2M x 8 with access times of 85,100, or 120 ns. • • The module is constructed using four 512Kx8 SRAMs in TSOPII packages mounted onto an FR4 epoxy substrate. This offers an extremely high PCB packing density. • • • • • • The device is offered in standard and low power versions, with the -L module having a low voltage data retention mode for battery backed applications. Block Diagram Access Times of 85/100/120 ns. Low Power Disapation: Operating 600 mW (Max.) Standby-L Version 1.1 mW (Max.) 5 Volt Supply ± 10%. Completely Static Operation. Low Voltage VCC Data Retention. On-board Decoding & Decoupling Capacitors. 38 Pin Single-In-Line package (SIP). Upgrade path to SYS84000RKXC (32Mbits). Pin Definition NC A20 Vcc WE D2 D3 D0 A1 A2 A3 A4 GND D5 A10 A11 A5 A13 A14 A19 CS A15 A16 A12 A18 A6 D1 GND A0 A7 A8 A9 D7 D4 D6 A17 Vcc OE NC D0 - D7 A0 - A18 OE WE 512K x 8 SRAM 512K x 8 SRAM 512K x 8 SRAM 512K x 8 SRAM CS CS CS CS A19 A20 CS DECODER Pin Functions Address Inputs Data Input/Output Chip Select Write Enable Output Enable No Connect Power (+5V) Ground 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 Pin 38 is A21 on the SYS84000RKXC upgrade module. A0 ~ A20 D0 ~ D7 CS WE Package Details OE NC VCC GND Plastic 38 pin Single-In-Line (SIP) ISSUE 1.3 : April 2001 SYS82000RKXC - 85/10/12 DC OPERATING CONDITIONS Absolute Maximum Ratings (1) Parameter Symbol min typ max unit VT PT TSTG -0.3 -55 - +7 4.0 +125 V W o C Voltage on any pin relative to VSS Power Dissipation Storage Temperature Notes : (1) Stresses above those listed may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Recommended Operating Conditions Parameter Symbol min typ max VCC VIH VIL TA TAI 4.5 2.2 -0.3 0 -40 5.0 - 5.5 Vcc+0.3 0.8 70 85 Supply Voltage Input High Voltage Input Low Voltage Operating Temperature I/P Leakage Current Output Leakage Current Operating Supply Current Standby Supply Current TTL levels -L Version Output Low Voltage Output High Voltage Symbol Test Condition ILI ILO ICC ISB1 ISB2 VOL VOH Input Capacitance (CS,A19,A20) Input Capacitance (A0-18,OE,WE) I/O Capacitance min VIN = GND to VCC -4 CS = VIH, VI/O = GND to VCC -4 CS = VIL, min cycle, Duty = 100% CS = VIH CS = VCC-0.2V, 0.2 > VIN > VCC-0.2V IOL = 2.1mA IOH = -1.0mA 2.4 Capacitance (VCC=5V±10%,TA=25oC) Parameter V V V o C o C (I) TA 0 to 70OC DC Electrical Characteristics (VCC=5V±10%) Parameter unit typ - max Unit 4 4 109 12 200 0.4 - Note: Capacitance calculated, not measured. Symbol CIN1 CIN2 CI/O Test Condition typ max Unit VIN = 0V VIN = 0V VI/O = 0V - 8 32 10 pF pF pF 2 µA µA mA mA µA V V SYS82000RKXC - 85/10/12 ISSUE 1.3 April 2001 Operation Truth Table CS OE WE DATA PINS SUPPLY CURRENT MODE H X X High Impedance ISB1 , ISB2 Standby L L H Data Out ICC Read L X L Data In ICC Write L H H High Impedance ICC Output Disabled Notes : H = VIH : L =VIL : X = VIH or VIL AC Test Conditions Output Load * Input pulse levels: 0 V to 3.0V I/O Pin 645 Ω * Input rise and fall times: 5ns 1.76V * Input and Output timing reference levels: 1.5V 100pF * Output load: see diagram * VCC = 5V± 10% Low Vcc Data Retention Characteristics - L Version Only (TOP = 0°C to 70°C) Parameter VCC for Data Retention Symbol Test Condition VDR min -L Part typ max Unit 2.0 - - V VCC=3.0V,CS=VCC-0.2V,0.2V>Vin>Vcc-0.2 - See Retention Waveform 0 5 - 500 - µA ns ms CS>VCC-0.2V 0.2V>Vin>Vcc-0.2 Data Retention Current ICCDR Chip Deselect to Data Ret. Time tCDR Operation Recovery Time tR See Retention Waveform 3 ISSUE 1.3 : April 2001 SYS82000RKXC - 85/10/12 AC OPERATING CONDITIONS Read Cycle -85 Parameter -10 -12 Symbol min max min max min max Unit Read Cycle Time tRC 85 - 100 - 120 - ns Address Access Time tAA - 85 - 100 - 120 ns Chip Select Access Time tACS - 85 - 100 - 120 ns Output Enable to Output Valid tOE - 45 - 50 - 55 ns Output Hold from Address Change tOH 10 - 10 - 10 - ns Chip Selection to Output in Low Z tCLZ 10 - 10 - 10 - ns Output Enable to Output in Low Z tOLZ 5 - 5 - 5 - ns Chip Deselection to O/P in High Z tCHZ 0 30 0 35 0 40 ns Output Disable to Output in High Z tOHZ 0 30 0 35 0 40 ns Write Cycle -85 Parameter -10 -12 Symbol min max min max min Write Cycle Time tWC 85 - 100 - 120 - ns Chip Selection to End of Write tCW 75 - 80 - 100 - ns Address Setup Time tAS 0 - 0 - 0 - ns Address Valid to End of Write tAW 75 - 80 - 100 - ns Write Pulse Width tWP 65 - 70 - 80 - ns Write Recovery Time tWR 5 - 5 - 5 - ns Write to Output in High Z tWHZ 0 30 0 35 0 40 ns Data to Write Time Overlap tDW 35 - 40 - 45 - ns Data Hold from Write Time tDH 0 - 0 - 0 - ns Output active from end of write tOW 5 - 5 - 5 - ns 4 max Unit SYS82000RKXC - 85/10/12 ISSUE 1.3 April 2001 Read Cycle Timing Waveform (1,2) t RC Address t AA OE t OE t OH t OLZ CS t ACS Don't care. t OHZ (3) t CLZ (4,5) Dout Data Valid t CHZ (3,4,5) AC Read Characteristics Notes (1) WE is High for Read Cycle. (2) All read cycle timing is referenced from the last valid address to the first transition address. (3) tCHZ and tOHZ are defined as the time at which the outputs achieve open circuit conditions and are not referenced to output voltage levels. (4) At any given temperature and voltage condition, tCHZ (max) is less than tCLZ (min) both for a given module and from module to module. (5) These parameters are sampled and not 100% tested. Write Cycle No.1 Timing Waveform(1,4) tWC Address t WR(7) OE t AS(6) t AW t CW CS Don't Care WE t OHZ(3,9) tOW t WP(2) High-Z Dout t DW Din High-Z t DH Data Valid 5 (8) ISSUE 1.3 : April 2001 SYS82000RKXC - 85/10/12 Write Cycle No.2 Timing Waveform (1,5) tWC Address t AS(6) t CW t WR(7) CS t AW t WP(2) WE tOH t WHZ(3,9) t OW High-Z Dout t DW (8) (4) Don't Care t DH High-Z Din Data Valid AC Write Characteristics Notes (1) All write cycle timing is referenced from the last valid address to the first transition address. (2) All writes occur during the overlap of CS and WE low. (3) If OE, CS, and WE are in the Read mode during this period, the I/O pins are low impedance state. Inputs of opposite phase to the output must not be applied because bus contention can occur. (4) Dout is the Read data of the new address. (5) OE is continuously low. (6) Address is valid prior to or coincident with CS and WE low, too avoid inadvertant writes. (7) CS or WE must be high during address transitions. (8) When CS is low : I/O pins are in the output state. Input signals of opposite phase leading to the output should not be applied. (9) Defined as the time at which the outputs achieve open circuit conditions and are not referenced to output voltage levels. These parameters are sampled and not 100% tested. Data Retention Waveform DATA RETENTION MODE Vcc 4.5V 4.5V t CDR tR 2.2V 2.2V V DR CS CS > Vcc -0.2V 0V 6 SYS82000RKXC - 85/10/12 Package Information ISSUE 1.3 April 2001 Dimensions in mm Plastic 38 Pin Single-In-Line (SIP) 114.12 Max. 3.00 108.00 3.10 MAX 22.00 Max. 18.49 10.00 21.00 Max. 57.00 3.50 +/- 0.50 Ordering Information SYS82000RKXCLI - 85 Speed 85 10 12 = 85 ns = 100 ns = 120 ns Temperature Range Blank = Commercial Temperature I = Industrial Temperature Power Consumption Blank = Standard Part L = Low Power Part Package RKXC = Plastic 38 pin SIP Organization 82000 = 2M x 8 Memory Type SYS = Static RAM Note : Although this data is believed to be accurate, the information contained herein, is not intended to and does not create any warranty of merchantibility or fitness for a particular purpose. Our products are subject to a constant process of development. Data may be changed at any time without notice. Products are not authorised for use as critical components in life support devices without the express written approval of a company director. 7