MP1530 Triple Output Step-Up Plus Linear Regulators for TFT Bias The Future of Analog IC Technology DESCRIPTION FEATURES The MP1530 combines a triple output step-up converter with linear regulators to provide a complete DC/DC solution. It is designed to power TFT LCD panels from a regulated 3.3V or 5V supply. • • • This device integrates a 1.4MHz fixed-frequency step-up converter with positive and negative linear regulators. The step-up converter switch node drives two charge pumps, which supply powers to their respective linear regulators. The positive and negative linear regulator inputs can withstand up to 38V and down to -20V, respectively. A single on/off control enables all 3 outputs. The outputs are internally sequenced at startup for ease of use. An internal soft-start prevents input overload at startup. Cycle-by-cycle current limiting reduces component stress. The MP1530 is available in a tiny 3mm x 3mm, 16-pin QFN package or a 16-pin TSSOP package. EVALUATION BOARD REFERENCE Board Number Dimensions EV0055 2.4”X x 2.3”Y x 0.4”Z • • • • • • • • • 2.7 to 5.5V Operating Input Range 2.8A Switch Current Limit 3 Outputs In a Single Package Step-Up Converter up to 22V Positive 20mA Linear Regulator Negative 20mA Linear Regulator 250mΩ Internal Power MOSFET Switch Up to 95% Efficiency 1.4MHz Fixed Frequency Internal Power-On Sequencing Adjustable Soft-Start/Fault Timer Cycle-by-Cycle Over Current Protection Under Voltage Lockout Ready Flag 16-Pin, QFN (3mm x 3mm) or TSSOP Packages APPLICATIONS • • • • TFT LCD Displays Portable DVD Players Tablet PCs Car Navigation Displays “MPS” and “The Future of Analog IC Technology” are Trademarks of Monolithic Power Systems, Inc. TYPICAL APPLICATION VIN 3.3V/5V Efficiency vs Load Current (Step-Up Converter Only) 100 VIN = 5.0V 90 TO SW IN RDY EN SW COMP FB1 VMAIN IN2 MP1530 VGL IN3 GL FB2 GH FB3 MP1530 Rev. 1.4 5/19/2006 80 PGND VIN = 3.3V 70 60 50 40 30 20 REF GND VGH EFFICIENCY (%) CT OFF ON VMAIN = 13V 1 10 100 LOAD CURRENT (mA) www.MonolithicPower.com MPS Proprietary Information. Unauthorized Photocopy and Duplication Prohibited. © 2006 MPS. All Rights Reserved. 1000 1 MP1530 – TRIPLE OUTPUT STEP-UP PLUS LINEAR REGULATORS FOR TFT BIAS PACKAGE REFERENCE TOP VIEW PGND IN3 GH IN2 16 15 14 13 SW 1 12 GL CT 2 11 EN RDY 3 10 FB3 FB1 9 4 5 6 7 8 COMP IN GND REF Part Number* MP1530DQ * TOP VIEW Package QFN16 (3mm x 3mm) FB2 RDY 1 16 CT FB1 2 15 SW COMP 3 14 PGND IN 4 13 IN3 GND 5 12 GH REF 6 11 IN2 FB2 7 10 GL FB3 8 9 EN Temperature Part Number** Package Temperature –40°C to +85°C MP1530DM TSSOP16 –40°C to +85°C For Tape & Reel, add suffix –Z (eg. MP1530DQ–Z) For RoHS compliant packaging, add suffix –LF (eg. MP1530DQ–LF–Z) ABSOLUTE MAXIMUM RATINGS (1) IN Supply Voltage ..........................–0.3V to +6V SW Voltage ..................................–0.3V to +25V IN2, GL Voltage ...........................+0.3V to –25V IN3, GH Voltage...........................–0.3V to +40V IN2 to IN3 Voltage .......................–0.3V to +60V All Other Pins .................................–0.3V to +6V Junction Temperature ...............................125°C Lead Temperature ....................................260°C Storage Temperature ............. –65°C to +150°C ** For Tape & Reel, add suffix –Z (eg. MP1530DM–Z) For RoHS compliant packaging, add suffix –LF (eg. MP1530DM–LF–Z) Recommended Operating Conditions (2) Input Voltage .................................. 2.7V to 5.5V Main Output Voltage...........................VIN to 22V IN2, GL Voltage ................................ 0V to –20V IN3, GH Voltage ................................. 0V to 38V Operating Temperature .............–40°C to +85°C Thermal Resistance (3) θJA θJC QFN16 (3mm x 3mm) ............. 60 ...... 12... °C/W TSSOP16 ............................... 90 ...... 30... °C/W Notes: 1) Exceeding these ratings may damage the device. 2) The device is not guaranteed to function outside of its operating conditions. 3) Measured on approximately 1” square of 1 oz copper. MP1530 Rev. 1.4 5/19/2006 www.MonolithicPower.com MPS Proprietary Information. Unauthorized Photocopy and Duplication Prohibited. © 2006 MPS. All Rights Reserved. 2 MP1530 – TRIPLE OUTPUT STEP-UP PLUS LINEAR REGULATORS FOR TFT BIAS ELECTRICAL CHARACTERISTICS (4) VIN = 5V, TA = +25°C, unless otherwise noted. Parameter Symbol Condition Input Voltage Range IN Undervoltage Lockout Threshold IN Undervoltage Lockout Hysteresis VIN VUVLO VEN HIGH 2.7 2.25 Max Units 5.5 2.65 V V mV VEN ≤ 0.3V VEN > 2V, VFB1 = 1.4V EN Rising 0.5 1 µA 1.3 1.6 mA V V mV µA 1.6 0.3 100 1 fSW DM 1 85 1.4 90 6 3 6 MHz % ms µs ms 400 1000 ±100 1.25 0 ±100 ±100 V/V µA/V µA V mV nA nA CCT = 10nF Regulator #2 Turn-On/Turn-Off Delay Error Amplifier Error Amplifier Voltage Gain Error Amplifier Transconductance COMP Maximum Output Current FB1, FB3 Regulation Voltage FB2 Regulation Voltage FB1, FB3 Input Bias Current FB2 Input Bias Current Reference (REF) REF Regulation Voltage REF Load Regulation Output Switch (SW) CCT = 10nF AvEA GmEA 1.22 –25 VFB1 = VFB3 = 1.25V VFB2 = 0V IREF = 50µA 0µA < IREF < 200µA 1.22 VIN = 5V VIN = 3V SW On Resistance SW Current Limit SW Leakage Current GL Dropout Voltage (5) GH Dropout Voltage (5) GL Leakage Current GH Leakage Current Typ 100 IN Shutdown Current IN Quiescent Current EN Input High Voltage EN Input Low Voltage EN Hysteresis EN Input Bias Current Oscillator Switching Frequency Maximum Duty Cycle Soft Start Period IN Rising Min ILIM 2.8 VSW = 22V VGL = –10V, IGL = –20mA VGH = 20V, IGH = 20mA VIN2 = –15V, VGL = GND VIN3 = 25V, VGH = GND Thermal Shutdown 1.25 1 250 400 3.6 0.5 1.28 +25 1.28 1.2 V % 1 0.3 1 1 1 mΩ mΩ A µA V V µA µA 160 °C Notes: 4) Typical values are guaranteed by design, not production tested. 5) Dropout Voltage is the input to output differential at which the circuit ceases to regulate against further reduction in input voltage. MP1530 Rev. 1.4 5/19/2006 www.MonolithicPower.com MPS Proprietary Information. Unauthorized Photocopy and Duplication Prohibited. © 2006 MPS. All Rights Reserved. 3 MP1530 – TRIPLE OUTPUT STEP-UP PLUS LINEAR REGULATORS FOR TFT BIAS TYPICAL PERFORMANCE CHARACTERISTICS Circuit of Figure 3, VIN = 5V, VMAIN = 13V, IMAIN = 200mA, VGL = -8.5V, IGL = 10mA, VGH = 27V, IGH = 10mA, TA = +25°C, unless otherwise noted. Efficiency vs Load Current Step-Up Converter Load Regulation (Step-Up Converter Only) 13.005 100 VIN=5V 13.000 80 12.995 VIN=3.3V VMAIN (V) EFFICIENCY (%) 90 70 60 50 12.985 12.980 12.975 40 30 12.990 12.970 VMAIN=7.5V 1 10 100 LOAD CURRENT (mA) 1000 12.965 27.05 -8.475 27.03 -8.485 27.01 -8.495 26.99 -8.505 26.97 VGH (V) VGL (V) -8.465 -8.525 26.93 26.91 -8.545 26.89 -8.555 26.87 0 10 20 30 IGL (mA) 40 50 26.85 Power-On Sequence VEN 5V/div. VMAIN 5V/div. VGL 10V/div. 0 10 20 30 IGH (mA) 40 50 Power-On Sequence VCT 1V/div. VMAIN 5V/div. VGL 10V/div. VGH 10V/div. VGH 10V/div. 10ms/div. MP1530 Rev. 1.4 5/19/2006 1000 26.95 -8.535 -8.565 10 100 IMAIN (mA) Positive Linear Regulator Load Regulation Negative Linear Regulator Load Regulation -8.515 1 10ms/div. www.MonolithicPower.com MPS Proprietary Information. Unauthorized Photocopy and Duplication Prohibited. © 2006 MPS. All Rights Reserved. 4 MP1530 – TRIPLE OUTPUT STEP-UP PLUS LINEAR REGULATORS FOR TFT BIAS TYPICAL PERFORMANCE CHARACTERISTICS (continued) Circuit of Figure 3, VIN = 5V, VMAIN = 13V, IMAIN = 200mA, VGL = -8.5V, IGL = 10mA, VGH = 27V, IGH = 10mA, TA = +25°C, unless otherwise noted. Load Transient on VMAIN Normal Operation IMAIN = 20mA - 200mA Step IMAIN 200mA/div. VSW 5V/div. VMAIN AC 50mV/div. VMAIN AC 100mV/div. IINDUCTOR 0.5A/div. 400ns/div. Reference Voltage vs Temperature Fault Timer VMAIN Shorted to VIN 1.256 1.254 1.252 VREF (V) VMAIN 5V/div. VCT 1V/div. VGL 10V/div. 1.250 1.248 1.246 1.244 1.242 1.240 VGH 20V/div. 1.238 -50 2ms/div. 0 50 100 TEMPERATURE (°C) 150 Oscillator Frequency vs Temperature 1.50 FREQUENCY (MHz) 1.47 1.44 1.41 1.38 1.35 1.32 1.29 1.26 -50 MP1530 Rev. 1.4 5/19/2006 0 50 100 TEMPERATURE (°C) 150 www.MonolithicPower.com MPS Proprietary Information. Unauthorized Photocopy and Duplication Prohibited. © 2006 MPS. All Rights Reserved. 5 MP1530 – TRIPLE OUTPUT STEP-UP PLUS LINEAR REGULATORS FOR TFT BIAS PIN FUNCTIONS QFN Pin # 1 TSSOP Name Pin # 15 SW 2 16 CT 3 1 RDY 4 2 5 3 6 4 7 8 5 6 9 7 10 8 11 9 12 10 13 11 14 12 15 13 16 14 MP1530 Rev. 1.4 5/19/2006 Description Step-Up Converter Power Switch Node. Connect an inductor between the input source and SW, and connect a rectifier from SW to the main output to complete the step-up converter. SW is the drain of the internal 250mΩ N-Channel MOSFET switch. Timing Capacitor for Power Supply Soft-Start and Power-On Sequencing. A capacitor from CT to GND controls the soft-start and sequencing turn-on delay periods. See Power-On Sequencing and Start Up Timing Diagram. Regulators Not Ready. During startup RDY will be left high. Once the turn-on sequence is complete, this pin will be pulled low if all FB voltages exceed 80% of their specified thresholds. After all regulators are turned-on, a fault in any regulator that causes the respective FB voltage to fall below 80% of its threshold will cause RDY to go high after approximately 15µs. If the fault persists for more than approximately 6ms (for CCT=10nF), the entire chip will shut down. See Fault Sensing and Timer. FB1 Step-Up Converter Feedback Input. FB1 is the inverting input of the internal error amplifier. Connect a resistive voltage divider from the output of the step-up converter to FB1 to set the step-up converter output voltage. COMP Step-Up Converter Compensation Node. COMP is the output of the error amplifier. Connect a series RC network to compensate the regulation control loop of the step-up converter. IN Internal Power Input. IN supplies the power to the MP1530. Bypass IN to PGND with a 10µF or greater capacitor. GND Signal Ground. REF Reference Output. REF is the 1.25V reference voltage output. Bypass REF to GND with a 0.1µF or greater capacitor. Connect REF to the low-side resistor of the negative linear regulator feedback string. FB2 Negative Linear Regulator Feedback Input. Connect the FB2 feedback resistor string between GL and REF to set the negative linear regulator output voltage. FB2 regulation threshold is GND. FB3 Positive Linear Regulator Feedback Input. Connect the FB3 feedback resistor string between GH and GND to set the positive linear regulator output voltage. FB3 regulation threshold is 1.25V. EN On/Off Control Input. Drive EN high to turn on the MP1530, drive EN low to turn it off. For automatic startup, connect EN to IN. Once the MP1530 is turned on, it sequences the outputs on (See Power-On Sequencing). When turned off, all outputs are immediately disabled. GL Negative Linear Regulator Output. GL is the output of the negative linear regulator. GL can supply up to 20mA to the load. Bypass GL to GND with a 1µF or greater, low-ESR, ceramic capacitor. IN2 Negative Linear Regulator Input. IN2 is the input of the negative linear regulator. Drive IN2 with an inverting charge pump powered from SW. IN2 can go as low as -20V. For QFN package IN2 connects to exposed pad. GH Positive Linear Regulator Output. GH is the output of the positive linear regulator. GH can supply as much as 20mA to the load. Bypass GH to GND with a 1µF or greater, lowESR, ceramic capacitor. IN3 Positive Linear Regulator Input. IN3 is the input to the positive linear regulator. Drive IN3 with a doubling, tripling, or quadrupling charge pump from SW. IN3 voltage can go as high as 38V. PGND Power Ground. PGND is the source of the internal 250mΩ N-Channel MOSFET switch. Connect PGND to GND as close to the MP1530 as possible. www.MonolithicPower.com MPS Proprietary Information. Unauthorized Photocopy and Duplication Prohibited. © 2006 MPS. All Rights Reserved. 6 MP1530 – TRIPLE OUTPUT STEP-UP PLUS LINEAR REGULATORS FOR TFT BIAS BLOCK DIAGRAM IN REF REFERENCE VREF + GM SW -- FB1 PULSE-WIDTH MODULATOR COMP OSCILLATOR 0.8VREF + -- SOFT-START FAULT TIMER & SEQUENCING 0.2VREF + PGND 0.8VREF + -- -- VREF EN -- CT FB2 + + FB3 IN3 -- IN2 GH RDY GL GND Figure 1—Functional Block Diagram MP1530 Rev. 1.4 5/19/2006 www.MonolithicPower.com MPS Proprietary Information. Unauthorized Photocopy and Duplication Prohibited. © 2006 MPS. All Rights Reserved. 7 MP1530 – TRIPLE OUTPUT STEP-UP PLUS LINEAR REGULATORS FOR TFT BIAS OPERATION The MP1530 is a step-up converter with two integrated linear regulators to power TFT LCD panels. Typically the linear regulators are powered from charge-pumps driven from the switch node (SW). The user can set the positive charge-pump to be a doubler, tripler, or quadrupler to achieve the required linear regulator input voltage for the selected output voltage. Typically the negative charge-pump is configured as a 1x inverter. Step-Up Converter The step-up, fixed-frequency, 1.4MHz converter employs a current-mode control architecture that maximizes loop bandwidth to provide fasttransient responses needed for TFT LCD drivers. High switching frequency allows for smaller inductors and capacitors minimizing board space and thickness. Linear Regulators The positive linear regulator (GH) uses a P-Channel pass element to drop the input voltage down to the regulated output voltage. The feedback of the positive linear regulator is a conventional error amplifier with the regulation threshold at 1.25V. The negative linear regulator (GL) uses a N-Channel pass element to raise the negative input voltage up to the regulated output voltage. The feedback threshold for the negative linear regulator is ground. The resistor string goes from REF (1.25V) to FB2 and from FB2 to GL to set the negative output voltage. The difference between the voltage at IN3 and the voltage at IN2 is limited to 60V abs. max. Fault Sensing and Timer Each of the 3 outputs has an internal comparator that monitors its respective output voltage by measuring the voltage at its respective FB input. When any FB input indicates that the output voltage is below approximately 80% of the correct regulation voltage, the fault timer enables and the RDY pin goes high. MP1530 Rev. 1.4 5/19/2006 The fault timer uses the same CT capacitor as the soft-start sequencer. If any fault persists to the end of the fault timer (One CT cycle is 6ms for a 10nF capacitor), all outputs are disabled. Once the outputs are shut down due to the fault timer, the MP1530 must be re-enabled by either cycling EN or by cycling the input power. If the fault persists for less than the fault timer period, RDY will be pulled low and the part will function as though no fault has occurred. Power-On Sequencing and Soft-Start The MP1530 automatically sequences its outputs at startup. When EN goes from low to high, or if EN is held high and the input voltage IN rises above the under-voltage lockout threshold, the outputs turn on in the following sequence: 1. Step-up Converter 2. Negative Linear Regulator (GL) 3. Positive Linear Regulator (GH) Each output turns on with a soft-start voltage ramp. The soft-start ramp period is set by the timing capacitor connected between CT and GND. A 10nF capacitor at CT sets the soft-start ramp period to 6ms. The timing diagram is shown in Figure 2. After the MP1530 is enabled, the power-on reset spans three periods of the CT ramp. First the step-up converter is powered up with reference to the CT ramp and allowed one period of the CT ramp to settle. Next the negative linear regulator (GL) is soft-started by ramping REF, which coincides with the CT ramp, and also allowed one CT ramp period to settle. www.MonolithicPower.com MPS Proprietary Information. Unauthorized Photocopy and Duplication Prohibited. © 2006 MPS. All Rights Reserved. 8 MP1530 – TRIPLE OUTPUT STEP-UP PLUS LINEAR REGULATORS FOR TFT BIAS The positive linear regulator (GH) is then softstarted and allowed to settle in one period of CT ramp. Nine periods of the CT ramp have occurred since the chip enabled. If all outputs are in regulation (>80%), the CT will stop ramping and be held at ground. The RDY pin will be pulled down to an active low. If any output remains below regulation (<80%) before and through the nine CT periods, RDY will remain high and CT will begin its fault timer pulse. VGH OUTPUT VOLTAGES VMAIN VIN 0V VGL VIN IN 0V VEN HIGH EN 0V POWER ON RESET START 1 START 2 START 3 1.25V CT 0V VIN RDY 0V TIME Figure 2—Startup Timing Diagram MP1530 Rev. 1.4 5/19/2006 www.MonolithicPower.com MPS Proprietary Information. Unauthorized Photocopy and Duplication Prohibited. © 2006 MPS. All Rights Reserved. 9 MP1530 – TRIPLE OUTPUT STEP-UP PLUS LINEAR REGULATORS FOR TFT BIAS APPLICATION INFORMATION COMPONENT SELECTION Setting the Output Voltages Set the output voltage on each output by selecting the resistive voltage divider ratio. The voltage divider drops the output voltage to the feedback threshold voltage. Use 10kΩ to 50kΩ for the low-side resistor RL of the voltage divider. For the step-up converter, determine the highside resistor RH by the equation: RH = VMAIN − VFB1 ⎛ VFB1 ⎞ ⎜⎜ ⎟⎟ ⎝ RL ⎠ Where VMAIN is the output voltage of the step-up converter. For the positive charge-pump, determine the high-side resistor RH by the equation: RH = VGH − VFB3 ⎛ VFB3 ⎜⎜ ⎝ RL ⎞ ⎟⎟ ⎠ For the negative charge-pump, determine the high-side resistor RH by the equation: RH = − VGL ⎛ VREF ⎜⎜ ⎝ RL ⎞ ⎟⎟ ⎠ Selecting the Inductor The inductor is required to force the higher output voltage while being driven by the input voltage. A larger value inductor results in less ripple current that results in lower peak inductor current, reducing stress on the internal N-Channel.switch. However, the larger value inductor has a larger physical size, higher series resistance, and/or lower saturation current. A 4.7µH inductor is recommended for most applications. A good rule of thumb is to allow the peak-to-peak ripple current to be approximately 30-50% of the maximum input current. Make sure that the peak inductor current is below 75% of the current limit to prevent loss of regulation due to the current limit. Also make sure that the inductor does not MP1530 Rev. 1.4 5/19/2006 saturate under the worst-case load transient and startup conditions. Calculate the required inductance value by the equation: L= VIN × (VOUT - VIN ) VOUT × f SW × ∆I IIN(MAX ) = VOUT × ILOAD (MAX ) VIN × η ∆I = (30% − 50%)IIN(MAX ) Where ILOAD(MAX) is the maximum load current, ∆I is the peak-to-peak inductor ripple current, and η is efficiency. Selecting the Input Capacitor An input capacitor is required to supply the AC ripple current to the inductor, while limiting noise at the input source. A low ESR capacitor is required to keep the noise at the IC to a minimum. Since it absorbs the input switching current it requires an adequate ripple current rating. Use a capacitor with RMS current rating greater than the inductor ripple current (see Selecting The Inductor to determine the inductor ripple current). One 10µF ceramic capacitor is used in the application circuit of Figure 3 because of the high source impedance seen in typical lab setups. Actual applications usually have much lower source impedance since the step-up converter typically runs directly from the output of another regulated supply. Typically, the input capacitance can be reduced below the value used in the typical application circuit. To insure stable operation place the input capacitor as close to the IC as possible. Alternately a smaller high quality 0.1µF ceramic capacitor may be placed closer to the IC if the larger capacitor is placed further away. www.MonolithicPower.com MPS Proprietary Information. Unauthorized Photocopy and Duplication Prohibited. © 2006 MPS. All Rights Reserved. 10 MP1530 – TRIPLE OUTPUT STEP-UP PLUS LINEAR REGULATORS FOR TFT BIAS Selecting the Rectifier Diodes The MP1530’s high switching frequency demands high-speed rectifiers. Schottky diodes are recommended for most applications because of their fast recovery time and low forward voltage. Typically, a 1A Schottky diode is recommended for the step-up converter. 100mA Schottky diodes such as Central Semiconductor CMPSH-3 are recommended for low current charge-pump circuits. Selecting the Output Capacitor of the Step-Up Converter The output capacitor is required to maintain the DC output voltage. Low ESR capacitors are preferred to keep the output voltage ripple to a minimum. The characteristics of the output capacitor also affect the stability of the regulation control system. A 10µF ceramic capacitor works well in most applications. In the case of ceramic capacitors, the impedance of the capacitor at the switching frequency is dominated by the capacitance, and so the output voltage ripple is mostly independent of the ESR. The output voltage ripple is estimated to be: ⎛ VIN VRIPPLE ≅ ⎜⎜1 − VMAIN ⎝ ⎞ I ⎟⎟ × LOAD ⎠ C2 × f SW Where VRIPPLE is the output ripple voltage, ILOAD is the load current, and C2 is the capacitance of the output capacitor of the step-up converter. Selecting the Number of Charge-Pump Stages For highest efficiency, always choose the lowest number of charge-pump stages that meets the output requirement. The number of positive charge-pump stages NPOS is given by: NPOS = VGH − VDROPOUT − VMAIN VMAIN − 2VD Where VD is the forward voltage drop of the charge-pump diode, and VDROPOUT is the dropout margin for the linear regulator. MP1530 Rev. 1.4 5/19/2006 The number of negative charge-pump stages NNEG is given by: NNEG = − VGL + VDROPOUT VMAIN − 2VD Use VDROPOUT = 1V for positive charge-pump and VDROPOUT = 0.3V for negative charge-pump. Selecting the Flying Capacitor in ChargePump Stages Increasing the flying capacitor CX values increases the output current capability. A 0.1µF ceramic capacitor works well in most low current applications. The flying capacitor’s voltage rating must exceed the following: VCX > N × VMAIN Where N is the stage number in which the flying capacitor appears. Step-Up Converter Compensation The MP1530 uses current mode control which unlike voltage mode has only a single pole roll off due to the output filter. The DC gain (AVDC) is equated from the product of current control to output gain (AVCSCONTROL), error amplifier gain (AVEA), and the feedback divider. Av DC = A CSCONTROL × Av EA × A FB1 VIN ILOAD A CSCONTROL = 4 × A FB1 = Av DC = VFB1 VMAIN 1600 × VIN × VFB1 ILOAD × VMAIN The output filter pole is given in hertz by: fFILTERPOLE = ILOAD π × VMAIN × C2 The output filter zero is given in hertz by: fFILTERZERO = 1 2π × R ESR × C2 Where RESR is the output capacitor’s equivalent series resistance. www.MonolithicPower.com MPS Proprietary Information. Unauthorized Photocopy and Duplication Prohibited. © 2006 MPS. All Rights Reserved. 11 MP1530 – TRIPLE OUTPUT STEP-UP PLUS LINEAR REGULATORS FOR TFT BIAS With all boost regulators the right half plane zero (RHPZ) is given in hertz by: 2 fRHPZ ⎛ VIN ⎞ ⎟⎟ × VMAIN ⎜⎜ ⎝ VMAIN ⎠ = 2π × ILOAD × L1 Error Amplifier Compensation To stabilize the feedback loop dynamics the error amplifier compensation is as follows: 1 fPOLE1 ≈ 2π × 10 6 × C3 f ZERO1 ≈ 1 2π × R3 × C3 Where R3 and C3 are part of the compensation network in Figure 3. A 6.8kΩ and 10nF combination gives about 70° of phase margin and bandwidth of about 35KHz for most load conditions. Linear Regulator Compensation The positive and negative regulators are controlled by a transconductance amplifier and a pass transistor. The DC gain of either LDO is approximately 100dB with a slight dependency on load current. The output capacitor (CLDO) and resistance load (RLOAD) make-up the dominant pole. fLDOPOLE1 = 1 2π × R LOAD × C LDO The pass transistor’s internal pole is about 100Hz to 300Hz. To compensate for the two pole system and add more phase and gain margin, a capacitor network can be added in parallel with the high-side resistor. For the negative linear regulator: fNEGPOLE1 = 1 2π × R7 R5 × C9 fNEGZERO1 = 1 2π × R7 × C9 fPOSPOLE1 and fNEGPOLE1 are necessary to cancel out the zero created by the equivalent series resistance (RLDOESR) of the output capacitor. fLDOZERO = 1 2π × R LDOESR × C LDO For the component values shown in Figure 3, a 330pF capacitor provides about 30° of phase margin and a bandwidth of approximately 90KHz on both regulators. Layout Considerations Careful PC board layout is important to minimize ground bounce and noise. First, place the main boost converter inductor, output diode and output capacitor as close to the SW and PGND pins as possible with wide traces. Then place ceramic bypass capacitors near IN, IN2 and IN3 pins to the PGND pin. Keep the charge-pump circuitry close to the IC with wide traces. Place all FB resistive dividers close to their respective FB pins. Separate GND and PGND areas and connect them at one point as close to the IC as possible. Avoid having sensitive traces near the SW node and high current lines. Refer to the MP1530 demo board for an example of proper board layout. For the positive linear regulator: fPOSPOLE1 = 1 2π × R9 R8 × C7 fPOSZERO1 = MP1530 Rev. 1.4 5/19/2006 1 2π × R9 × C7 www.MonolithicPower.com MPS Proprietary Information. Unauthorized Photocopy and Duplication Prohibited. © 2006 MPS. All Rights Reserved. 12 MP1530 – TRIPLE OUTPUT STEP-UP PLUS LINEAR REGULATORS FOR TFT BIAS TYPICAL APPLICATION CIRCUITS VIN 3.3V/5V C4 10nF CT EN OFF ON RDY COMP TO SW IN SW D1 1N5819 VMAIN 13V FB1 C3 10nF D2 D4 IN2 MP1530 VGL -8.5V GL D3 IN3 VGH 27V FB2 GH C9 330pF REF GND FB3 PGND C7 330pF Figure 3—Triple Output Boost Application Circuit MP1530 Rev. 1.4 5/19/2006 www.MonolithicPower.com MPS Proprietary Information. Unauthorized Photocopy and Duplication Prohibited. © 2006 MPS. All Rights Reserved. 13 MP1530 – TRIPLE OUTPUT STEP-UP PLUS LINEAR REGULATORS FOR TFT BIAS PACKAGE INFORMATION QFN16 (3mm x 3mm) MP1530 Rev. 1.4 5/19/2006 www.MonolithicPower.com MPS Proprietary Information. Unauthorized Photocopy and Duplication Prohibited. © 2006 MPS. All Rights Reserved. 14 MP1530 – TRIPLE OUTPUT STEP-UP PLUS LINEAR REGULATORS FOR TFT BIAS TSSOP16 NOTICE: The information in this document is subject to change without notice. Please contact MPS for current specifications. Users should warrant and guarantee that third party Intellectual Property rights are not infringed upon when integrating MPS products into any application. MPS will not assume any legal responsibility for any said applications. MP1530 Rev. 1.4 5/19/2006 www.MonolithicPower.com MPS Proprietary Information. Unauthorized Photocopy and Duplication Prohibited. © 2006 MPS. All Rights Reserved. 15