SILICON MMIC QUADRATURE MODULATOR UPC8105GR FUNCTIONAL BLOCK DIAGRAM FEATURES • WIDE SUPPLY VOLTAGE RANGE: 2.7 ~ 5.5 V LO • BROADBAND OPERATION: MODOUT = 100 - 400 MHz, I/Q = DC to 10 MHz • INTERNAL 90° PHASE SHIFTER I I • POWER SAVE FUNCTION 0˚ φ • LOW POWER CONSUMPTION: 16 mA Typ. @ 3 V • SMALL SSOP 16 PACKAGE 90˚ Q Q • TAPE AND REEL PACKAGING AVAILABLE DESCRIPTION The UPC8105GR Silicon MMIC I/Q Modulator is manufactured using the NESAT III MMIC process. The NESAT III process produces transistors with fT approaching 20 GHz. The device was designed for use in Digital Mobile Communications circuits such as 900 MHz Digital Cordless and Cellular Phones, WLAN and PCN/PCS Handset Transmitters. NEC's stringent quality assurance and test procedures ensure the highest reliability and performance. ELECTRICAL CHARACTERISTICS (TA = 25°C, VCC = 3.0 V, VPS ≥ 1.8 V) PART NUMBER PACKAGE OUTLINE SYMBOLS ICC PMOD LOLEAK ImR IM3I/Q RLIN ZI/Q TPS(RISE) TPS (FALL) PARAMETERS AND CONDITIONS Total Circuit Current (no signal) VPS ≥ 1.8 V VPS ≤ 1.0 V Output Power - Modulator Local Oscillator Leakage VI/Q = 1.5 V (DC) Image Rejection + 500 mVp-p (AC) I/Q 3rd Order Intermodulation Distortion I/Q LO Input Return Loss Input Impedance I and Q Port Power Save Rise Time VPS ≤ 1.0 V to VPS ≥ 1.8V Power Save Fall Time VPS ≥1.8 V to VPS ≤1.0 V UPC8105GR S16 (SSOP 16) UNITS MIN TYP MAX mA µA dBm dBc dBc dBc dB kΩ µS µS 10 16 0.1 -16.5 -40 -40 -50 20 20 2 2 21 5 -12 -30 -30 -21 5 5 California Eastern Laboratories UPC8105GR ABSOLUTE MAXIMUM RATINGS1 (TA = 25°C) SYMBOLS UNITS RATINGS VCC Supply Voltage PARAMETERS V 6.0 VPS Enable Voltage for Power Save V 6.0 PD Power Dissipation2 mW 530 TOP Operating Temperature °C -40 to +85 °C -65 to +150 TSTG Storage Temperature RECOMMENDED OPERATING CONDITIONS SYMBOLS Notes: 1. Operation in excess of any one of these parameters may result in permanent damage. 2. Mounted on a 50x50x1.6 mm double copper clad epoxy glass PWB (TA = 85°C). PARAMETERS UNITS MIN TYP MAX VCC Supply Voltage V 2.7 3.0 TOP Operating Temperature °C -40 +25 +85 5.5 fMODOUT Modulator Output Frequency MHz 100 400 fLOIN LO1 Input Frequency1 MHz 100 400 fI/QIN I/Q Input Frequency2 MHz DC 10 Notes: 1. PLOIN = -10 dBm. 2. PI/QIN = 600 mVp-p max. TYPICAL PERFORMANCE CURVES (TA = 25°C, VCC = VPS = 3 V, I/Q DC Offset = I/Q DC Offset = 1.5 V, I/Q Input Signal = 500 mVp-p (Single-ended), PLOIN = -10 dBm unless otherwise specified) MODULATOR OUTPUT POWER, LO LEAKAGE , IMAGE REJECTION AND I/Q 3rd ORDER INTERMODULATION DISTORTION vs.LO INPUT POWER MODULATOR OUTPUT POWER, LO LEAKAGE , IMAGE REJECTION AND I/Q 3rd ORDER INTERMODULATION DISTORTION vs. LO INPUT FREQUENCY -20 LOL -30 -30 -40 IMR -40 -50 -60 IM3 I/O -70 -30 -20 -10 0 -50 +10 MODULATOR OUTPUT POWER, LO LEAKAGE , IMAGE REJECTION AND I/Q 3rd ORDER INTERMODULATION DISTORTION vs. I/Q INPUT SIGNAL LO Leakage, LOL ; Image Rejection, ImR; IM3 I/Q (dBc) POUT -20 -10 -20 -30 -30 LOL IMR -40 -50 IM3 I/Q -50 -70 0 0.5 I/Q Input Signal, P I/QIN (Vp-p) 1 Modulator Output Power, PMODOUT (dBm) -10 -60 -20 -20 IMR -30 -30 -40 -40 LOL -50 -50 IM3 I/O -60 -60 -70 -70 50 100 200 500 LO Input Frequency, fLO (MHz) LO Input Power, PLOIN (dBm) -40 LO Leakage, LOL; Image Rejection, ImR; IM3 I/Q (dBc) -20 -10 POUT Modulator Output Power, PMODOUT (dBm) POUT -10 -10 Modulator Output Power, PMODOUT (dBm) LO Leakage, LOL ; Image Rejection, ImR; IM3 I/Q (dBc) -10 UPC8105GR PIN FUNCTIONS Pin No. Symbol Supply Voltage Pin Voltage 1 LOIN — 0 2 LOIN (Bypass) 3 8 GND 4 I Description LO input for the phase shifter. This input impedance is internally matched to 50 Ω. 50 Ω 2 Connect to ground with minimum inductance. Track length should be kept as short as possible. VCC/2*2 — I VCC/2*2 — 6 Q VCC/2*2 — 7 Q VCC/2*2 — Input for I signal. This input impedance is larger than 20 kΩ. The relationship between the amplitude and the DC bias of the input signal are as follows: *1 VCC/2 (V) Amp. (mVp-p) ≥1.35 400 ≥1.5 600 ≥1.75 1000 — 4 5 7 6 Input for I signal. This input impedance is larger than 20 kΩ. VCC/2 biased DC signal should be input. Input for Q signal. This input impedance is larger than 20 kΩ. VCC/2 biased DC signal should be input. Input for Q signal. This input impedance is larger than 20 kΩ. The relationship between the amplitude and the DC bias of the input signal are as follows: VCC/2 (V) ≥1.35 ≥1.5 ≥1.75 MODOUT 1 Bypass of the LO input.This pin is grounded through an internal capacitor. For a single-ended design this pin should be left open. — 5 12 Equivalent Circuit Amp. (mVp-p) 400 600 1000 Output from the modulator. This is emitter follower output. Connect approx. 15 Ω in series to match to 50 Ω. 12 *1: In case I/Q input signals are single ended. I/Q signal inputs can be used either single-ended or differentially with proper terminations. *2: VCC/2 DC bias must be supplied to I, I, Q, Q. UPC8105GR PIN FUNCTIONS Pin No. Symbol Supply Voltage Pin Voltage 13 14 GND 0 — 15 VPS (Power Save) VPS Description Connect to the ground with minimum inductance. Track length should be kept as short as possible. Power save control pin can control the On/Sleep state with bias as follows: VPS (V) 1.8~5.5 0~1.0 16 VCC 2.7~5.5 Equivalent Circuit — 15 STATE ON SLEEP Supply voltage pin for the modulator. An internal regulator helps keep the device stable against temperature or VCC variation. MODULATOR INTERNAL FUNCTIONS Block Function/Operation Block Diagram from LOin 90° Phase Shifter Buffer Amplifier Mixer Adder Input signal from LO is sent to a T-type flip-flop through a frequency doubler. The output signal from the T-type F/F is changed to the same frequency as LO input with a quadrature phase shift of 0°, 90°, 180°, or 270°. These circuits provide self phase correction for proper quadrature signals. x2 .. 2 F/F Buffer amplifiers for each phase signal are sent to each mixer. Each signal from the buffer amps is quadrature modulated with two doublebalanced mixers. High accurate phase and amplitude inputs are realized to provide excellent image rejection. I I Q Q Output signal from each mixer is added and sent through a final amplifier stage to pin 16 for further off-chip filtering if necessary. To MODout UPC8105GR OUTLINE DIMENSIONS (Units in mm) INTERNAL BLOCK DIAGRAM PACKAGE OUTLINE SSOP 16 LO1 IN LO1 IN 1 2 90˚ Phase Shifter 16 VCC 15 V PS NEC C8105G (POWER SAVE) GND 3 14 GND I 4 13 GND I 5 12 MOD OUT Q 6 11 N.C. Q 7 GND 8 9 16 REG XXXXX 1 8 6.2±0.3 5.50 Max 4.4±0.2 1.44 0.1±0.1 N.C. PART NUMBER QUANTITY UPC8105GR-E1 2500/Reel 0.65 0.20±0.10 LEAD CONNECTIONS 1. LOIN 2. LOIN 3. GND 4. I Input 5. I Input 6. Q Input 7. Q Input 8. GND ORDERING INFORMATION Note: Embossed Tape, 12 mm wide. 0.9±0.2 +0.10 0.15 -0.05 1.8 Max 10 N.C. 9 XXX = Lot/Date Code 0.5±0.2 0.475 Max 9. N.C. 10. N.C. 11. N.C. 12. MODOUT 13. GND 14. GND 15. VPS (Power Save) 16. VCC All dimensions are typical unless specified otherwise. APPLICATION CIRCUIT Low-noise Transistor DEMO RX +N VCO I Q PLL SW PLL UPC8105GR I 0˚ Phase Shifter 90˚ TX PA UPC8106T EXCLUSIVE NORTH AMERICAN AGENT FOR Q RF, MICROWAVE & OPTOELECTRONIC SEMICONDUCTORS CALIFORNIA EASTERN LABORATORIES • Headquarters • 4590 Patrick Henry Drive • Santa Clara, CA 95054-1817 • (408) 988-3500 • Telex 34-6393 • FAX (408) 988-0279 24-Hour Fax-On-Demand: 800-390-3232 (U.S. and Canada only) • Internet: http://WWW.CEL.COM PRINTED IN USA ON RECYCLED PAPER -3/97 DATA SUBJECT TO CHANGE WITHOUT NOTICE