NEC UPD12115

DATA SHEET
MOS INTEGRATED CIRCUIT
μ PD12115
1.5 V/1.0 A GENERAL-PURPOSE
CMOS REGULATOR
DESCRIPTION
μ PD12115 is a general-purpose CMOS regulator which has 1.5 V output voltage and 1.0 A output current capacity.
This product is suitable for low power-supply-voltage LSI etc. By ON/OFF function, the power consumption can be
kept low level at the time of off-state.
FEATURES
PIN CONFIGURATION (Marking Side)
• Output Current: 1.0 A
5-PIN TO-252 (5-PIN MP-3ZK)
• Output Voltage: 1.5 V (Fixed type)
• Output Voltage Tolerance: VO ± 2.0% (TJ = 25°C)
6
1. INPUT
• Dropout Voltage: VDIF = 1.0 V MAX. (IO = 1.0 A)
2. ON/OFF
• Quiescent Current: 150 μ A TYP. (IO = 0 A)
3. GND
• Standby Current: 1 μ A
• Available for laminated ceramic capacitor: (Electric capacity 10 μ F or higher)
1 2 3 4 5
• On-chip over-current protection circuit
Note
4. NC
5. OUTPUT
6. GND (Fin)
• On-chip thermal shut down circuit
Note No.3 pin is cut and can not be connected
to substrate. No.6 is Fin and common to
GND pin.
APPLICATIONS
This regulator is suitable for low power-supply-voltage LSI which is used in digital appliances etc.
BLOCK DIAGRAM
ON/OFF
−
Buffer
+
Constant
Current
VIN
ON/OFF
Over-current
protection
−
Error
amp.
+
Reference
voltage
VOUT
Thermal
shut down
Triming
GND
The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
Not all products and/or types are available in every country. Please check with an NEC Electronics
sales representative for availability and additional information.
Document No. G18851EJ1V0DS00 (1st edition)
Date Published July 2007 NS
Printed in Japan
2007
μ PD12115
ORDERING INFORMATION
Part Number
Package
Output Voltage
Type
Marking
μ PD12115T1F
5-PIN TO-252 (5-PIN MP-3ZK)
1.5 V
Fixed
12115
Remark Since it is the tape-packaged product, “-E1” or “-E2” is added to the end of its product name.
Part Number
Package
μ PD12115T1F-E1-AT
Note
Package Type
• 16 mm wide embossed taping
5-PIN TO-252 (5-PIN MP-3ZK)
• Pin 1 on draw-out side
• 2,500 pcs/reel
μ PD12115T1F-E2-AT Note
• 16 mm wide embossed taping
5-PIN TO-252 (5-PIN MP-3ZK)
• Pin 1 at take-up side
• 2,500 pcs/reel
Note Pb-free (This product does not contain Pb in the external electrode and other parts.)
ABSOLUTE MAXIMUM RATINGS (TA = 25°C, unless otherwise specified)
Parameter
Symbol
Input Voltage
VIN
Rating
Unit
−0.3 to +6.0
V
−0.3 to VIN
V
PT
10
W
Operating Ambient Temperature
TA
−40 to +85
°C
Operating Junction Temperature
TJ
−40 to +150
°C
Storage Temperature
Tstg
−55 to +150
°C
Thermal Resistance (junction to ambient)
Rth(J-A)
125
°C/W
Thermal Resistance (junction to case)
Rth(J-C)
12.5
°C/W
ON/OFF Pin Voltage
VON/OFF
Internal Power Dissipation (TC = 25°C)
Note
Note Internally limited. When the operating junction temperature rises above 150°C, the internal circuit shuts down
the output voltage.
Caution Product quality may suffer if the absolute maximum rating is exceeded even momentarily for any
parameter. That is, the absolute maximum ratings are rated values at which the product is on the
verge of suffering physical damage, and therefore the product must be used under conditions that
ensure that the absolute maximum ratings are not exceeded.
TYPICAL CONNECTION
ON/OFF
D1
INPUT
INPUT
CIN
OUTPUT
GND
GND
2
OUTPUT
μ PD12115
Data Sheet G18851EJ1V0DS
COUT
D2
μ PD12115
CIN : 0.1 μ F or higher. Be sure to connect CIN to prevent parasitic oscillation. Set this value according to the length
of the line between the regulator and the INPUT pin. Use of a film capacitor or other capacitor with first-rate
voltage and temperature characteristics is recommended. If using a laminated ceramic capacitor, it is necessary
to ensure that CIN is 0.1 μ F or higher for the voltage and temperature range to be used.
COUT: 10 μ F or higher. Be sure to connect COUT to prevent oscillation and improve excessive load regulation. Place
CIN and COUT as close as possible to the IC pins (within 1 to 2 cm). Also, in case of using a laminated ceramic
capacitor, please note following items.
• It is necessary to ensure that COUT is 10 μ F or higher for the voltage and temperature range to be used.
• In case of using laminated ceramic capacitor, it is easy to become state of parasitic oscillation. Because ESR
of laminated ceramic capacitor is very low. Therefore, the capacitor and load condition (output current) which
fulfill the condition of the stable operation area of ESR shown below are recommended.
• Stable Operation Area as below is regulated under condition of which this product is not on a substrate.
Therefore impedance on substrate is not considered.
D1
: If the OUTPUT pin has a higher voltage than the INPUT pin, connect a diode.
D2
: If the OUTPUT pin has a lower voltage than the GND pin, connect a Schottky barrier diode.
Caution Make sure that no external voltage is applied to the OUTPUT pin.
μ PD12115 COUT ESR Stable Operation Area
Unstable Operation Area
10
Stable Operation Area
ESR (Ω)
1
0.1
Unstable Operation Area
0.01
0
200
400
600
800
1000
IO (mA)
RECOMMENDED OPERATING CONDITIONS
Parameter
Symbol
MIN.
TYP.
MAX.
Unit
Input Voltage
VIN
2.5
5.5
V
ON/OFF Pin Voltage
VON/OFF
0
VIN
V
Output Current
IO
0
1.0
A
Operating Ambient Temperature
TA
− 40
+ 85
°C
Operating Junction Temperature
TJ
− 40
+ 125
°C
Caution1. Turn on VIN and VON/OFF at the same time, or turn on VIN first and then VON/OFF.
Turn off VIN and VON/OFF at the same time, or turn off VON/OFF first and then VIN.
2. If absolute maximum rating is not exceeded, you can used this product above the recommended
operating range. However, since a margin with absolute maximum rating decreases, please use
this product after sufficient evaluation.
Data Sheet G18851EJ1V0DS
3
μ PD12115
ELECTRICAL CHARACTERISTICS
(TJ = 25°C, VIN = VON/OFF = 2.5 V, IO = 0.5 A, CIN = 0.1 μ F, COUT = 10 μ F, unless otherwise specified)
Parameter
Output Voltage
Symbol
Conditions
−
VO1
MIN.
TYP.
MAX.
Unit
1.47
1.5
1.53
V
(1.455)
−
(1.545)
V
2.5 V ≤ VIN ≤ 5.5 V
−
1
15
mV
REGL
0 A ≤ IO ≤ 1.0 A
−
1
15
mV
IBIAS1
IO = 0 A
−
150
300
μA
IBIAS2
IO = 1.0 A
−
(1600)
(3000)
μA
ΔIBIAS1
2.5 V ≤ VIN ≤ 5.5 V
−
(10)
(300)
μA
ΔIBIAS2
0 A ≤ IO ≤ 1.0 A
−
(1450)
(3000)
μA
Output Noise Voltage
Vn
10 Hz ≤ f ≤ 100 kHz
−
165
−
μ Vr.m.s.
Ripple Rejection
R•R
f = 1 kHz, 2.5 V ≤ VIN ≤ 3.5 V
−
65
−
dB
Dropout Voltage
VDIF
IO = 1.0 A
−
0.6
1.0
V
Short Circuit Current
IOshort
−
−
0.7
−
A
−
1.0
−
−
A
−
0.02
−
mV/°C
VO2
2.5 V ≤ VIN ≤ 5.5 V, 0 A ≤ IO ≤ 1.0 A
Line Regulation
REGIN
Load Regulation
Quiescent Current
Quiescent Current Change
Peak Output Current
IOpeak
Temperature Coefficient of
ΔVO/ΔT
IO = 5 mA, 0°C ≤ TJ ≤ 125°C
ON-state Voltage
VON
IO = 0 A
1.5
−
VIN
V
OFF-state Voltage
VOFF
IO = 0 A
−
−
0.5
V
Output Voltage
ON-state ON/OFF Pin Current
ION
IO = 0 A
−
−
2
μA
Standby Current
IBIAS(OFF)
VON/OFF = 0 V
−
−
1
μA
Remark Values in parentheses are product design values, and are thus provided as reference values.
4
Data Sheet G18851EJ1V0DS
μ PD12115
TYPICAL CHARACTERISTICS
Δ VO vs.TJ
PD vs. TA
10.0
Δ VO - Output Voltage Temperature
15
Wi
th i
10
nfin
ite
Change - mV
PD - Power Dissipation - W
20
hea
tsin
k
5
Without heatsink
1.0
0
50
0
85 100
VIN = VON/OFF = 2.5 V
IO = 5 mA
5.0
0
-5.0
-10.0
-40
150
-15
10
35
60
VO vs. VIN, IBIAS vs. VIN
IOpeak vs. VDIF
2.0
2.5
4000
3000
1.0
2000
VO
IO = 0.9 A
0.5 A
0.5 A
0A
0A
1000
IBIAS
0
0
1.0
2.0
3.0
4.0
5.0
IOpeak - Peak Output Current - A
1.5
IBIAS - Quiescent Current - μ A
VO - Output Voltage - V
TJ = 25°C
0.5
0
6.0
TJ = 25°C
2.0
1.5
1.0
0.5
0
0
1.0
1.2
70
1.0
60
0.8
0.6
0.4
0.2
0.6
4.0
5.0
5 mA
50
40
IO = 0.5 A
30
TJ = 25°C
VIN = 2.5 to 3.5 V
VON/OFF = 1.5 V
CIN = 0.1 μ F
COUT = 10 μ F
20
10
0
0
0.4
3.0
R • R vs. f
R • R - Ripple Rejection - dB
VDIF - Dropout Voltage - V
VDIF vs. IO
0.2
2.0
VDIF - Dropout Voltage - V
VIN - Input Voltage - V
0
110 125
TJ - Operating Junction Temperature - °C
TA - Operating Ambient Temperature - °C
0.9 A
85
0.8
1.0
10
100
1k
10 k
100 k
f - Frequency - Hz
IO - Output Current - A
Data Sheet G18851EJ1V0DS
5
μ PD12115
VO vs. IO
2.0
VO - Output Voltage - V
TJ = 25°C
VIN = VON/OFF = 2.5 V
1.5
1.0
0.5
0
0
0.4
0.8
1.2
1.6
2.0
IO - Output Current - A
6
Data Sheet G18851EJ1V0DS
μ PD12115
PACKAGE DRAWING (Unit: mm)
5-PIN TO-252 (MP-3ZK)
E
A
b1
E1
c1
L1
6
D1
D
H
1
2
3
4
5
A1
L2
c
x4
e
b
L
GAUGE PLANE
SEATING PLANE
c2
(UNIT:mm)
ITEM
D
D1
E
E1
H
NOTE
1.
No Plating area
DIMENSIONS
6.10 ±0.20
4.4TYP(4.0MIN)
6.50±0.20
4.4TYP(4.3MIN)
9.8TYP(10.3MAX)
A
2.30±0.10
A1
0 to 0.25
b
0.60±0.10
b1
5.0
c
0.50±0.10
c1
0.50±0.10
c2
0.508
e
1.14
L
1.52±0.12
L1
1.0
L2
0.80
P5T1F-114-1
2006
Data Sheet G18851EJ1V0DS
7
μ PD12115
RECOMMENDED MOUNTING CONDITIONS
The μ PD12115 should be soldered and mounted under the following recommended conditions.
For soldering methods and conditions other than those recommended below, contact an NEC Electronics sales
representative.
For technical information, see the following website.
Semiconductor Device Mount Manual (http://www.necel.com/pkg/en/mount/index.html)
μ PD12115T1F-AT
Note
: 5-PIN TO-252 (5-PIN MP-3ZK)
Process
Infrared reflow
Conditions
Symbol
Package peak temperature: 260°C, Time: 60 seconds MAX. (at 220°C or higher),
IR60-00-3
Count: Three times,
Flux: Rosin flux with low chlorine (0.2 Wt% or below) recommended.
Partial Heating Method
Pin temperature: 350°C or below,
P350
Heat time: 3 seconds or less (per each side of the device).
Note Pb-free (This product does not contain Pb in the external electrode and other parts.)
Caution Apply only one kind of soldering condition to a device, except for "partial heating method", or the
device will be damaged by heat stress.
REFERENCE DOCUMENTS
USER’S MANUAL USAGE OF THREE TERMINAL REGULATORS
INFORMATION VOLTAGE REGULATOR OF SMD
SEMICONDUCTOR DEVICE MOUNT MANUAL
8
Document No.G12702E
Document No.G11872E
http://www.necel.com/pkg/en/mount/index.html
Data Sheet G18851EJ1V0DS
μ PD12115
NOTES FOR CMOS DEVICES
1
VOLTAGE APPLICATION WAVEFORM AT INPUT PIN
Waveform distortion due to input noise or a reflected wave may cause malfunction. If the input of the
CMOS device stays in the area between VIL (MAX) and VIH (MIN) due to noise, etc., the device may
malfunction. Take care to prevent chattering noise from entering the device when the input level is fixed,
and also in the transition period when the input level passes through the area between VIL (MAX) and
VIH (MIN).
2
HANDLING OF UNUSED INPUT PINS
Unconnected CMOS device inputs can be cause of malfunction. If an input pin is unconnected, it is
possible that an internal input level may be generated due to noise, etc., causing malfunction. CMOS
devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed
high or low by using pull-up or pull-down circuitry. Each unused pin should be connected to VDD or GND
via a resistor if there is a possibility that it will be an output pin. All handling related to unused pins must
be judged separately for each device and according to related specifications governing the device.
3
PRECAUTION AGAINST ESD
A strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and
ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as
much as possible, and quickly dissipate it when it has occurred.
Environmental control must be
adequate. When it is dry, a humidifier should be used. It is recommended to avoid using insulators that
easily build up static electricity. Semiconductor devices must be stored and transported in an anti-static
container, static shielding bag or conductive material. All test and measurement tools including work
benches and floors should be grounded.
The operator should be grounded using a wrist strap.
Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for
PW boards with mounted semiconductor devices.
4
STATUS BEFORE INITIALIZATION
Power-on does not necessarily define the initial status of a MOS device. Immediately after the power
source is turned ON, devices with reset functions have not yet been initialized. Hence, power-on does
not guarantee output pin levels, I/O settings or contents of registers. A device is not initialized until the
reset signal is received. A reset operation must be executed immediately after power-on for devices
with reset functions.
5
POWER ON/OFF SEQUENCE
In the case of a device that uses different power supplies for the internal operation and external
interface, as a rule, switch on the external power supply after switching on the internal power supply.
When switching the power supply off, as a rule, switch off the external power supply and then the
internal power supply. Use of the reverse power on/off sequences may result in the application of an
overvoltage to the internal elements of the device, causing malfunction and degradation of internal
elements due to the passage of an abnormal current.
The correct power on/off sequence must be judged separately for each device and according to related
specifications governing the device.
6
INPUT OF SIGNAL DURING POWER OFF STATE
Do not input signals or an I/O pull-up power supply while the device is not powered. The current
injection that results from input of such a signal or I/O pull-up power supply may cause malfunction and
the abnormal current that passes in the device at this time may cause degradation of internal elements.
Input of signals during the power off state must be judged separately for each device and according to
related specifications governing the device.
Data Sheet G18851EJ1V0DS
9
μ PD12115
• The information in this document is current as of July, 2007. The information is subject to change
without notice. For actual design-in, refer to the latest publications of NEC Electronics data sheets or
data books, etc., for the most up-to-date specifications of NEC Electronics products. Not all
products and/or types are available in every country. Please check with an NEC Electronics sales
representative for availability and additional information.
• No part of this document may be copied or reproduced in any form or by any means without the prior
written consent of NEC Electronics. NEC Electronics assumes no responsibility for any errors that may
appear in this document.
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purposes in semiconductor product operation and application examples. The incorporation of these
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responsibility of the customer. NEC Electronics assumes no responsibility for any losses incurred by
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M8E 02. 11-1