DATA SHEET MOS INTEGRATED CIRCUIT μ PD121A10 2-POWER SUPPLY INPUT METHOD 1.0 V/2.0 A REGULATOR DESCRIPTION μ PD121A10 is the CMOS regulator which can output 2.0 A current. This regulator is suitable for power supply for 1.0 V ASIC core, for example our companies’ CB-90 (90 nm process LSI) etc. The dropout voltage is made small (0.7 V MAX. (IO = 1.0 A) by dividing bias voltage (VDD) from input voltage (VIN). Therefore this product can output under the conditions, VIN ≥ 1.62 V (VDD ≥ 4.0 V). Output voltage can be adjustable between 0.95 and 1.15 V. FEATURES PIN CONFIGURATION (Marking Side) • Output Current: 2.0 A • Output Voltage: 0.95 to 1.15 V 5-PIN TO-252 (5-PIN MP-3ZK) • Bias Voltage: 4.0 to 5.5 V 6 • Reference Voltage Tolerance: VREF ± 10 mV (TJ = 25°C) 1. INPUT • Low Dropout Voltage: VDIF = 0.7 V MAX. (IO = 1.0 A) 2. VDD (ON/OFF) • On-chip over-current protection circuit 3. GND • On-chip thermal shut down circuit 1 2 3 4 5 Note 4. SENSE 5. OUTPUT 6. GND (Fin) APPLICATIONS This regulator is suitable for low power supply voltage IC, Note No.3 pin is cut and can not be connected to for example core of CB-90 (90 nm process LSI) etc. substrate. No.6 is Fin and common to GND pin. BLOCK DIAGRAM VDD INPUT Constant current − Buffer Reference + voltage Over-current protection + Error amp. − OUTPUT SENSE Thermal shut down Triming GND The information in this document is subject to change without notice. Before using this document, please confirm that this is the latest version. Not all products and/or types are available in every country. Please check with an NEC Electronics sales representative for availability and additional information. Document No. G18843EJ1V0DS00 (1st edition) Date Published July 2007 NS Printed in Japan 2007 μ PD121A10 ORDERING INFORMATION Part Number Package Reference Voltage Output Voltage Marking μ PD121A10T1F 5-PIN TO-252 (5-PIN MP-3ZK) 0.6 V 0.95 to 1.15 V 121A10 Remark Since it is the tape-packaged product, “-E1” or “-E2” is added to the end of its product name. Part Number Note Package μ PD121A10T1F-E1-AT Package Type • 16 mm wide embossed taping 5-PIN TO-252 (5-PIN MP-3ZK) • Pin 1 on draw-out side • 2,500 pcs/reel μ PD121A10T1F-E2-AT • 16 mm wide embossed taping 5-PIN TO-252 (5-PIN MP-3ZK) • Pin 1 at take-up side • 2,500 pcs/reel Note Pb-free (This product does not contain Pb in the external electrode and other parts.) ABSOLUTE MAXIMUM RATINGS (TA = 25°C, unless otherwise specified) Parameter Symbol Rating Unit VIN −0.3 to +6.0 V VDD −0.3 to +6.0 V PT 10 W Operating Ambient Temperature TA −20 to +85 °C Operating Junction Temperature TJ −20 to +150 °C Storage Temperature Tstg −55 to +150 °C Thermal Resistance (junction to ambient) Rth(J-A) 125 °C/W Thermal Resistance (junction to case) Rth(J-C) 12.5 °C/W Input Voltage Bias Voltage Internal Power Dissipation (TC = 25°C) Note Note Internally limited. When the operating junction temperature rises above 150°C, the internal circuit shuts down the output voltage. Caution Product quality may suffer if the absolute maximum rating is exceeded even momentarily for any parameter. That is, the absolute maximum ratings are rated values at which the product is on the verge of suffering physical damage, and therefore the product must be used under conditions that ensure that the absolute maximum ratings are not exceeded. TYPICAL CONNECTION VDD D1 INPUT INPUT μ PD121A10 OUTPUT OUTPUT R1 GND D2 COUT CIN GND 2 Data Sheet G18843EJ1V0DS + SENSE R2 μ PD121A10 CIN : 0.1 μ F or higher. Be sure to connect CIN to prevent parasitic oscillation. Set this value according to the length of the line between the regulator and the INPUT pin. Use of a film capacitor or other capacitor with first-rate voltage and temperature characteristics is recommended. If using a laminated ceramic capacitor, it is necessary to ensure that CIN is 0.1 μ F or higher for the voltage and temperature range to be used. COUT : 10 μ F or higher. Be sure to connect COUT to prevent oscillation and improve excessive load regulation. Place CIN and COUT as close as possible to the IC pins (within 1 to 2 cm). Use the capacitor whose capacitance value is 10 μ F or more under use conditions. D1 : If the OUTPUT pin has a higher voltage than the INPUT pin, connect a diode. D2 : If the OUTPUT pin has a lower voltage than the GND pin, connect a Schottky barrier diode. R1, R2: The total amount of R1 and R2 is sure to below 200 kΩ (100 kΩ TYP.). VOUT = (1 + R1/R2) VREF Note Note When VOUT = 1 V: R1 = 40 kΩ, R2 = 60 kΩ Caution1. Make sure that no external voltage is applied to the OUTPUT pin. 2. VDD pins (Bias voltage) must be supplied in a separate power supply from that of INPUT pins (Input voltage). RECOMMENDED OPERATING CONDITIONS Parameter Symbol MIN. 1.62 Note TYP. MAX. Unit Input Voltage (VO = 1.0 V) VIN 2.0 2.65 V Output Voltage VO 0.95 1.0 1.15 V Bias Voltage VDD 4.0 5.0 5.5 V Output Current IO 0 2.0 A Operating Ambient Temperature TA − 20 + 85 °C Operating Junction Temperature TJ − 20 + 125 °C Note It needs 1.7 V ≤ VIN ≤ 2.65 V to output IO = 2.0 A. Caution1. Power on VIN first, and then VDD on start-up. When the power is turned off, turn off VDD first. Note that the voltage of VDD must not be kept 3.0 V or less. 2. If absolute maximum rating is not exceeded, you can used this product above the recommended operating range. However, since a margin with absolute maximum rating decreases, please use this product after sufficient evaluation. Data Sheet G18843EJ1V0DS 3 μ PD121A10 ELECTRICAL CHARACTERISTICS (TJ = 25°C, VIN = 2.0 V, VDD = 5.0 V, IO = 1.0 A, VO = 1.0 V, CIN = 0.1 μ F, COUT = 10 μ F, unless otherwise specified) Parameter Reference Voltage (SENSE pin) Symbol Conditions − TYP. MAX. Unit 0.59 0.6 0.61 V VREF2 −20°C ≤ TJ ≤ +125°C (0.58) − (0.62) V Line Regulation REGIN 1.7 V ≤ VIN ≤ 2.65 V − 1 15 mV Load Regulation REGL 0 A ≤ IO ≤ 2.0 A − 1 15 mV IBIAS1 IO = 0 A − 125 500 μA IBIAS2 IO = 2.0 A − 300 1000 μA ΔIBIAS1 4.0 V ≤ VDD ≤ 5.5 V, IO = 0 A − 12 300 μA ΔIBIAS2 0 A ≤ IO ≤ 2.0 A − 100 500 μA Output Noise Voltage Vn 10 Hz ≤ f ≤ 100 kHz − 230 − μ Vr.m.s. Ripple Rejection R•R f = 1 kHz, 1.8 V ≤ VIN ≤ 2.2 V − 56 − dB Dropout Voltage VDIF IO = 1.0 A − 0.17 0.7 V Short Circuit Current IOshort VO = 0 V − 3.0 − A 2.0 − − A − 0.14 − mV/°C Quiescent Current Quiescent Current Change VREF1 MIN. Peak Output Current IOpeak 4.0 V ≤ VDD ≤ 5.5 V Temperature Coefficient of ΔVO/ΔT IO = 0 A, 0°C ≤ TJ ≤ 125°C Output Voltage ON-state Voltage (VDD) VDD(ON) − 4.0 − − V OFF-state Voltage (VDD) VDD(OFF) − − − 0.5 V ON-state Bias Pin (VDD Pin) Current OFF-state Bias Pin (VDD Pin) Note Current IBIAS(ON1) IO = 0 A − IBIAS1 − μA IBIAS(ON2) IO = 2.0 A − IBIAS2 − μA IBIAS(OFF) IO = 0 A, VDD = 0 V − − 1 μA Note Standby Current Remark Values in parentheses are product design values, and are thus provided as reference values. 4 Data Sheet G18843EJ1V0DS μ PD121A10 TYPICAL CHARACTERISTICS Δ VREF vs.TJ 15 Wi th i 10 nfin ite Change - mV PD - Power Dissipation - W 20 hea tsin k 5 Without heatsink 1.0 0 50 0 Δ VREF - Reference Voltage Temperature PD vs. TA 85 100 150 10.0 VIN = 2.0 V VDD = 5.0 V IO = 1.0 A 5.0 0 -5.0 -10.0 -20 TA - Operating Ambient Temperature - °C 0 25 100 125 IBIAS vs. VDD 1.2 200 0.8 IBIAS - Quiescent Current - μ A 1.0 VO - Output Voltage - V 75 TJ - Operating Junction Temperature - °C VO vs. VDD IO = 0 A 0.1 A 1.0 A 0.6 0.4 0.2 TJ = 25°C V IN = 2.0 V 150 IO = 0 A 0.1 A 1.0 A 100 50 TJ = 25°C VIN = 2.0 V 0 0 0 1.0 2.0 3.0 4.0 5.0 6.0 0 VDD - Bias Voltage - V 1.0 2.0 3.0 4.0 5.0 6.0 VDD - Bias Voltage - V VDIF vs. TJ R • R vs. f 80 0.3 70 0.25 R • R - Ripple Rejection - dB VDIF - Dropout Voltage - V 50 0.2 0.15 0.1 0.05 0 -20 VDD = 5.0 V IO = 1.0 A 0 25 50 75 100 IO = 0 A 60 50 1.0 A 2.0 A 40 TJ = 25°C VIN = 1.8 to 2.2 V VDD = 5.0 V CIN = 0.1 μ F COUT = 10 μ F 30 20 10 0 125 TJ - Operating Junction Temperature - °C Data Sheet G18843EJ1V0DS 10 100 1k 10 k 100 k f - Frequency - Hz 5 μ PD121A10 VDD(ON) vs. TJ VDD(OFF) vs. TJ 1.5 VDD(OFF) - OFF-state Voltage - V VDD(ON) - ON-state Voltage - V 4.0 3.0 2.0 1.0 VIN = 2.0 V 0 -20 0 25 50 75 100 1.0 0.5 125 TJ - Operating Junction Temperature - °C VO - Output Voltage - V TJ = 25°C VIN = 2.0 V VDD = 5.0 V 1.0 0.75 0.50 0.25 0 0 1.0 2.0 3.0 4.0 5.0 IO - Output Current - A 6 0 25 50 75 100 125 TJ - Operating Junction Temperature - °C VO vs. IO 1.25 VIN = 2.0 V 0 -20 Data Sheet G18843EJ1V0DS μ PD121A10 PACKAGE DRAWING (Unit: mm) 5-PIN TO-252 (MP-3ZK) E A b1 E1 c1 L1 6 D1 D H 1 2 3 4 5 A1 L2 c x4 e b L GAUGE PLANE SEATING PLANE c2 (UNIT:mm) ITEM D D1 E E1 H NOTE 1. No Plating area DIMENSIONS 6.10 ±0.20 4.4TYP(4.0MIN) 6.50±0.20 4.4TYP(4.3MIN) 9.8TYP(10.3MAX) A 2.30±0.10 A1 0 to 0.25 b 0.60±0.10 b1 5.0 c 0.50±0.10 c1 0.50±0.10 c2 0.508 e 1.14 L 1.52±0.12 L1 1.0 L2 0.80 P5T1F-114-1 2006 Data Sheet G18843EJ1V0DS 7 μ PD121A10 RECOMMENDED MOUNTING CONDITIONS The μ PD121A10 should be soldered and mounted under the following recommended conditions. For soldering methods and conditions other than those recommended below, contact an NEC Electronics sales representative. For technical information, see the following website. Semiconductor Device Mount Manual (http://www.necel.com/pkg/en/mount/index.html) μ PD121A10T1F-AT Note : 5-PIN TO-252 (5-PIN MP-3ZK) Process Infrared reflow Conditions Symbol Package peak temperature: 260°C, Time: 60 seconds MAX. (at 220°C or higher), IR60-00-3 Count: Three times, Flux: Rosin flux with low chlorine (0.2 Wt% or below) recommended. Partial Heating Method Pin temperature: 350°C or below, P350 Heat time: 3 seconds or less (per each side of the device). Note Pb-free (This product does not contain Pb in the external electrode and other parts.) Caution Apply only one kind of soldering condition to a device, except for "partial heating method", or the device will be damaged by heat stress. REFERENCE DOCUMENTS USER’S MANUAL USAGE OF THREE TERMINAL REGULATORS Document No.G12702E INFORMATION VOLTAGE REGULATOR OF SMD Document No.G11872E SEMICONDUCTOR DEVICE MOUNT MANUAL http://www.necel.com/pkg/en/mount/index.html 8 Data Sheet G18843EJ1V0DS μ PD121A10 NOTES FOR CMOS DEVICES 1 VOLTAGE APPLICATION WAVEFORM AT INPUT PIN Waveform distortion due to input noise or a reflected wave may cause malfunction. If the input of the CMOS device stays in the area between VIL (MAX) and VIH (MIN) due to noise, etc., the device may malfunction. Take care to prevent chattering noise from entering the device when the input level is fixed, and also in the transition period when the input level passes through the area between VIL (MAX) and VIH (MIN). 2 HANDLING OF UNUSED INPUT PINS Unconnected CMOS device inputs can be cause of malfunction. If an input pin is unconnected, it is possible that an internal input level may be generated due to noise, etc., causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using pull-up or pull-down circuitry. Each unused pin should be connected to VDD or GND via a resistor if there is a possibility that it will be an output pin. All handling related to unused pins must be judged separately for each device and according to related specifications governing the device. 3 PRECAUTION AGAINST ESD A strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it when it has occurred. Environmental control must be adequate. When it is dry, a humidifier should be used. It is recommended to avoid using insulators that easily build up static electricity. Semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work benches and floors should be grounded. The operator should be grounded using a wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for PW boards with mounted semiconductor devices. 4 STATUS BEFORE INITIALIZATION Power-on does not necessarily define the initial status of a MOS device. Immediately after the power source is turned ON, devices with reset functions have not yet been initialized. Hence, power-on does not guarantee output pin levels, I/O settings or contents of registers. A device is not initialized until the reset signal is received. A reset operation must be executed immediately after power-on for devices with reset functions. 5 POWER ON/OFF SEQUENCE In the case of a device that uses different power supplies for the internal operation and external interface, as a rule, switch on the external power supply after switching on the internal power supply. When switching the power supply off, as a rule, switch off the external power supply and then the internal power supply. Use of the reverse power on/off sequences may result in the application of an overvoltage to the internal elements of the device, causing malfunction and degradation of internal elements due to the passage of an abnormal current. The correct power on/off sequence must be judged separately for each device and according to related specifications governing the device. 6 INPUT OF SIGNAL DURING POWER OFF STATE Do not input signals or an I/O pull-up power supply while the device is not powered. The current injection that results from input of such a signal or I/O pull-up power supply may cause malfunction and the abnormal current that passes in the device at this time may cause degradation of internal elements. Input of signals during the power off state must be judged separately for each device and according to related specifications governing the device. Data Sheet G18843EJ1V0DS 9 μ PD121A10 • The information in this document is current as of July, 2007. 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(2) "NEC Electronics products" means any product developed or manufactured by or for NEC Electronics (as defined above). M8E 02. 11-1