NEC UPD16781N-XXX

DATA SHEET
MOS INTEGRATED CIRCUIT
µ PD16781
480 OUTPUT TFT-LCD SOURCE DRIVER
DESCRIPTION
The µ PD16781 is a source driver for 480-output TFT-LCDs, providing support for only striped pixel array LCD.
The driver consists of a shift register for generating the sampling timing and sample & hold circuits for sampling the
analog voltage. The high picture quality obtained by the alternate sample & hold execution of the two types of on-chip
sample & hold circuits enables employment in applications such as car navigation panels.
FEATURES
• 5.0 V Drive (Dynamic range 4.6 VP-P, VDD2 = 5.0 V)
• 480 Output channel
• fCLK = 20 MHz MAX. (VDD1 = 3.0 V)
• 1-phase/3-phase sampling clocks supported
• Corresponds only to LCD of Stripe array color filter
• Two on-chip sample-and-hold circuits
• Small output deviation between pins (deviation between chip pins: ±20 mV MAX.)
• Switch between right and left shift using the R,/L pin
• Logic power supply voltage (VDD1): 3.0 to 5.5 V
• Driver power supply voltage(VDD2): 5.0 ± 0.5 V
Remark /xxx indicates active low signal.
ORDERING INFORMATION
Part Number
Package
µ PD16781N-xxx
TCP (TAB package)
Remark The TCP’s external shape is customized. To order the required shape, so please contact one of our sales
representatives.
The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
Not all devices/types available in every country. Please check with local NEC representative for
availability and additional information.
Document No.
S14634EJ1V0DS00 (1st edition)
Date Published February 2002 NS CP(K)
Printed in Japan
The mark ! shows major revised points.
©
1999
µ PD16781
★ 1. BLOCK DIAGRAM
STHR
R,/L
CLK1 to CLK3
MODE
STHL
VDD1 (3.3/5.0 V)
VSS1
160-bit Shift Register
C1 C2
C159 C160
Level Shifter
C1
C2
C3
CX
VDD2 (5.0 V)
VSS2
Sample And Hold
VSS3
Input
S1 S2
S479 S480
TEST
2. SAMPLE-AND HOLD CIRCUIT AND OUTPUT CIRCUIT
SHPn
CX
S&H1
SW
–
+
Video Line (Cn)
SW
CH1
Sn
VSS3
SW
–
+
CH1
VSS3
S&H2
2
DataSheet S14634EJ1V0DS
SW
µ PD16781
3. PIN CONFIGURATION (µ PD16781N-xxx) (Copper Foil Surface, Face-up)
S480
S479
S478
STHL
VDD2
VSS2
C1
C2
C3
VDD1
Copper foil
surface
CLK1
CLK2
CLK3
MODE
R,/L
CX
TEST
VSS1
VSS3
VSS2
VDD2
S3
STHR
S2
S1
Remark This figure does not specify the TCP package.
DataSheet S14634EJ1V0DS
3
µ PD16781
4. PIN FUNCTIONS
Pin Symbol
Pin Name
I/O
Description
C1 to C3
Video signal input
I
These pins are input video signals R, G, and B.
S1 to S480
Video signal output
O
These pins are output video signals, which have been sampled and hold.
The relationship between the video signal input (C1 to C3) and video signal output is
shown below.
C1: S3n−2 (n = 1, 2, ··········160)
C2: S3n−1
C3: S3n
STHR,
Cascade I/O
I/O
STHL
These pins are inputs/outputs for the start pulse for sample and hold timing.
High level of STHR/STHL is read at rising edge of CLK and start sampling video
signal. STHR serves as the input pin and STHL serves as output pin for the right
shift. For left shift, STHL serves as the input pins and STHR serves as the output
pin.
R,/L
Shift direction control
I
The shift direction control pin of shift register. The shift directions of the shift
registers are as follows.
R,/L = H (right shift): STHR input, S1 → S480, STHL output.
R,/L = L (left shift): STHL input, S480 → S1, STHR output.
CLK1 to CLK3
Shift clock input
I
The start pulse is read at rising edge of CLK. The sampling pulse SHPn is
generated at rising edge of CLK. For details, refer to 6. TIMING CHART.
The relationship between the clocks and the output pins is shown below.
(1) When MODE = L or open (sequential sampling)
CLK1 R,/L = H: S3n−2
R,/L = L: S3n
CLK2: S3n−1
CLK3 R,/L = H: S3n
R,/L = L: S3n−2
(1) When MODE = H (simultaneous sampling)
CLK1: S3n−2, S3n−1, S3n (n = 1, 2,·····160)
CLK2: Connect VDD1 or VSS1
CLK3: Connect VDD1 or VSS1
MODE
Mode select signal input
I
This pin is used to select whether the three analog input signals, C1, C2, and C3 are
sampled simultaneously or sequentially (This pin is pulled down in the IC).
MODE = H: Simultaneous sampling
MODE = L or open: Sequential sampling
CX
Hold capacitance control
I
input
Two Sample & hold circuits are switched.
CX = H S&H1: Sampling, S&H2: Output
CX = L S&H1: Output, S&H2: Sampling
TEST
Test
I
Fix this pin to the L level.
VDD1
Logic power supply
−
3.0 to 5.5 V
VDD2
Driver power supply
−
5.0 ± 0.5 V
VSS1
Logic ground
−
Grounding
VSS2
Driver ground
−
Grounding
VSS3
Sample & hold ground
−
It is ground of Sample & hold capacitance. Supply this terminal with the stable
GND.
4
DataSheet S14634EJ1V0DS
µ PD16781
Cautions 1. To prevent latch-up-breakdown, the power should be turned on in order VDD1, Logic input VDD2,
video signal input. It should be turned off in the opposite order. This relationship should be
followed during transition periods as well.
2. The sampling of the video signal of this IC is only the simultaneous 3 output sampling of C1 to C3.
Incidentally, it is designing abound of the input of the video signal in 10 MHz MAX.
If a video signal with a higher frequency is input, the data may not be correctly displayed.
3. Recommend a bypass capacitor of about 0.1 µF with good high-frequency characteristics between
★
VDD1 and VSS1, and VDD2 and VSS2 in each driver IC. Unless the power supply is reinforced,
the supply voltage may fluctuate, making the sampling voltage abnormal.
4. If noise is superimposed on the start pulse pin, the data may not be displayed. For this reason,
be sure to input CX signal during the vertical blanking period.
5. If the start pulse width is extended by half the clock or longer, the sampling start timing SHP1 does
not change from normal timing; therefore, the sampling operation is performed normally.
5. FUNCTION DESCRIPTION
5.1 Switching of Sample & Hold Circuits
Two sample-and-hold circuits are switched.
CX
Output
Sample & hold operation
L
Sample & Hold Circuit 1 (S&H1)
Sample & Hold Circuit 2 (S&H2)
H
Sample & Hold Circuit 2 (S&H2)
Sample & Hold Circuit 1 (S&H1)
5.2 Sample & Hold and Output
Relation between video signals C1, C2 and C3 and output pins and two sample & hold circuits.
CX
L
H
Remark
S1 (S480)
S2 (S479)
S3 (S478)
S4 (S477)
···
S479 (S2)
S480 (S1)
Sampling
C1-2 (C3-2)
C2-2 (C2-2)
C3-2 (C1-2)
C1-2 (C3-2)
···
C2-2 (C2-2)
C3-2 (C1-2)
Output
C1-1 (C3-1)
C2-1 (C2-1)
C3-1 (C1-1)
C1-1 (C3-1)
···
C2-1 (C2-1)
C3-1 (C1-1)
Sampling
C1-1 (C3-1)
C2-1 (C2-1)
C3-1 (C1-1)
C1-1 (C3-1)
···
C2-1 (C2-1)
C3-1 (C1-1)
Output
C1-2 (C3-2)
C2-2 (C2-2)
C3-2 (C1-2)
C1-2 (C3-2)
···
C2-2 (C2-2)
C3-2 (C1-2)
Cm-n = m: Video input, n: Sample & Hold
DataSheet S14634EJ1V0DS
5
µ PD16781
6. TIMING CHART
6.1 1-Phase Simultaneous Sampling
1
2
3
159
160
(1)
(2)
CLK1
STHR
(STHL)
SHP1-SHP3
(SHP480-SHP478)
SHP4-SHP6
(SHP477-SHP475)
SHP7-SHP9
(SHP474-SHP472)
S1-S3
(S480-S478)
S4-S6
(S477-S475)
S7-S9
(S474-S472)
SHP475-SHP477
(SHP6-SHP4)
S475-S477
(S6-S4)
SHP478-SHP480
(SHP3-SHP1)
S478-S480
(S3-S1)
STHR
(STHL)
SHP1-SHP3
(SHP480-SHP478)
S1-S3
(S480-S478)
SHP4-SHP6
(SHP477-SHP475)
6
S4-S6
(S477-S475)
DataSheet S14634EJ1V0DS
(3)
µ PD16781
6.2 3-phase Sequential Sampling, Right Shift
1
2
3
4
160
CLK1
CLK2
CLK3
STHR
SHP1
SHP2
SHP3
SHP4
S1
S2
S3
S4
S478
SHP478
S479
SHP479
S480
SHP480
DataSheet S14634EJ1V0DS
7
µ PD16781
6.3 3-phase Sequential Sampling, Left Shift
1
2
3
4
160
CLK1
CLK2
CLK3
STHL
SHP480
SHP479
SHP478
SHP477
S480
S479
S478
S477
S3
SHP3
S2
SHP2
S1
SHP1
8
DataSheet S14634EJ1V0DS
µ PD16781
7. ELECTRICAL SPECIFICATIONS
Absolute Maximum Ratings (TA = +25°°C, VSS1 =VSS2 = 0 V)
Parameter
Symbol
Rating
Unit
Logic Part Supply Voltage
VDD1
−0.3 to +7.0
V
Driver Part Supply Voltage
VDD2
−0.3 to +7.0
V
Input Voltage
VI
−0.3 to VDD1/2 + 0.3
V
Output Voltage
VO
−0.3 to VDD1/2 + 0.3
V
Operating Ambient Temperature
TA
−30 to +85
°C
Storage Temperature
Tstg
−55 to +125
°C
Caution
Product quality may suffer if the absolute maximum rating is exceeded even momentarily for any
parameter. That is, the absolute maximum ratings are rated values at which the product is on the verge
of suffering physical damage, and therefore the product must be used under conditions that ensure
that the absolute maximum ratings are not exceeded.
Recommended Operating Range (TA = −30 to +85°°C, VDD2 ≥ VDD1, VSS1 = VSS2 = 0 V)
Parameter
Symbol
Conditions
MIN.
TYP.
MAX.
Unit
5.5
V
5.5
V
Logic Part Supply Voltage
VDD1
3.0
Driver Part Supply Voltage
VDD2
4.5
Video Input Voltage
VVI
VSS2 + 0.2
VDD2 − 0.2
V
Driver Part Output Voltage
VO2
VSS2 + 0.2
VDD2 − 0.2
V
Clock Frequency
fCLK
CLK1 to CLK3
20
MHz
Output Load Capacitance
CL
1 output
50
pF
DataSheet S14634EJ1V0DS
5.0
9
µ PD16781
Electrical Characteristics (TA = –30 to +85°C, VDD1 = 3.0 to 5.5 V, VDD2 = 5.0 V ± 0.5 V, VDD2 ≥ VDD1, VSS1 = VSS2 = 0 V)
Parameter
Symbol
Low-Level Driver Part Output Voltage
VVOL
High-Level Driver Part Output Voltage
VVOH
High-Level Input Voltage
VIH
Low-Level Input Voltage
VIL
Input Leak Current
IIL
Conditions
MIN.
TYP.
S1 to S480
MAX.
Unit
VSS2 + 0.2
V
VDD2 – 0.2
CLK, STHR (L), R,/L, Osel, CX
V
0.7 VDD1
VDD1
V
VSS1
0.3 VDD1
V
Except for MODE pin
–1.0
+1.0
µA
MODE pin
VI = 0 V
–10
+10
µA
VI = VDD1 = 5 V
30
300
µA
High-Level Output Voltage
VLOH
STHR (STHL), IOH = –1.0 mA
Low-Level Output Voltage
VLOH
STHR (STHL), IOL = +1.0 mA
Reference Voltage
VREF1
VDD2 = 5.0 V, VVI = 0.5 V,
0.85 VDD1
V
0.15 VDD1
V
0.5
V
2.5
V
4.5
V
TA = 25°C
VREF2
VDD2 = 5.0 V, VVI = 2.5 V,
TA = 25°C
VREF3
VDD2 = 5.0 V, VVI = 4.5 V,
TA = 25°C
★
Output Voltage Deviation
∆VVO1
±20
mV
±20
mV
±20
mV
1.6
5.6
mA
12.0
16.0
mA
VDD2 = 5.0 V, VVI = 0.5 V,
TA = 25°C
★
∆VVO2
VDD2 = 5.0 V, VVI = 2.5 V,
★
∆VVO3
VDD2 = 5.0 V, VVI = 4.5 V,
TA = 25°C
TA = 25°C
★
★
Logic Dynamic Current Consumption
Driver Dynamic Current Consumption
IDD1
IDD2
VDD1 = 5.0 V, no load
VDD2 = 5.0 V, no load
Note
Note
Note fCLK = 15 MHz, fCX = 17 kHz.
10
DataSheet S14634EJ1V0DS
µ PD16781
Switching Characteristics (TA = –30 to +85°°C, VDD1 = 3.0 to 5.5 V, VDD2 = 5.0 V ± 0.5 V, VDD2 ≥ VDD1, VSS1 = VSS2 = 0 V)
Parameter
Start Pulse Delay Time
Driver Output Delay Time
Symbol
Conditions
MIN.
TYP.
MAX.
Unit
tPHL1
CL = 20 pF
7
43
ns
tPLH1
CLK → STHL (STHR)
7
43
ns
tPLH2
VDD2 = 5.0 V
8
µs
tPLH3
RL = 2 kΩ
16
µs
tPHL2
CL = 25 pF x 2
8
µs
16
µs
tPHL3
★ Input Capacitance
CI1
STHR(STHL), TA=25°C
10
20
pF
★
CI2
C1 to C3, TA=25°C
40
60
pF
★
CI3
STHR (STHL), C1 to C3
7
15
pF
MAX.
Unit
excluded input, TA=25°C
Timing Requirement (TA = –30 to +85°°C, VDD1 = 3.0 to 5.5 V, VSS1 = 0 V)
Parameter
Symbol
Clock Pulse Width
PW CLK
Clock Pulse High Period
Clock Pulse Low Period
★ CLK-CLK time
Conditions
CLK1 to CLK3
MIN.
TYP.
50
ns
PW CLK(H)
15
ns
PW CLK(L)
15
ns
tCL1-2
16.6
tCL2-3
PWCLK
2
ns
Start Pulse Setup Time
tsetup
7
ns
Start Pulse Setup Time
thold
7
ns
Start Pulse-CX Time
tSTH-CX
50
ns
CX Setup Time
tCXsetup
1.0
µs
CX Hold Time
tCXhold
50
ns
CLK Stop Period
Refer to 8. SWITHING CHARACTERISTICS
tCLKstop
WAVEFORM.
Remark Unless otherwise specified, the input level is defined to be VIH = 0.7 VDD1, VIL = 0.3 VDD1.
DataSheet S14634EJ1V0DS
11
3
160
161
162
479
480
481





2
0
1
2
VDD1
CLK1
VSS1
tsetup
thold
VDD1
STHR
(1st Dr.)
C1 to C3
VSS1
INVALID
S1 to S3
S4 to S6
S7 to
S9
S475 to
S477
S478 to
S480
tPLH1
S481 to
S483
tPHL1
VDD1
S1435 to
S1437
S1438 to
S1440
INVALID
S1 to S3
VSS1
tSTH-CX
DataSheet S14634EJ1V0DS
VDD1
STHL
(1st Dr.)
VSS1
tPLH1
tPHL1
VDD1
STHL
(4th Dr.)
VSS1
tCXhold
tCXsetup
VDD1
CX
VSS1
tPLH3
8. SWITCHING CHARACTERISTICS WAVEFORM (R,/L=H)
1
Unless otherwise specified, the input level is defined to be VIH = 0.7 VDD1, VIL = 0.3 VDD1.
0
tCLKstop : It is possible for the clock among this to stop.
PWCLK(L)
8.1 1-Phase Simultaneous Sampling
12
PWCLK
PWCLK(H)
tPLH2
Target Voltage ± 0.1 VDD1
Target Voltage ± 20 mV
Sn
(VOUT)
tPHL3
µ PD16781
tPHL2
tCLKstop : It is possible for the clock among this to stop.
PWCLK(L)
1
2
3
160
161
162
479
480
481





0
0
1
2
VDD1
CLK1
VSS1
0
1
2
tCL1-2 3
160
161
162
479
480
481
0
1
2
VDD1
CLK2
VSS1
1
0
2
160
tCL2-3
161
162
479
480
481
0
1
VDD1
CLK3
VSS1
tsetup
thold
★ 8.2 3-phase Sequential Sampling
PWCLK
PWCLK(H)
VDD1
STHR
(1st Dr.)
VSS1
VDD1
C1
INVALID
S1
S4
S7
S478
S475
S481
S1435
S1438
S1
INVALID
VSS1
DataSheet S14634EJ1V0DS
VDD1
C2
INVALID
S2
S5
S476
S479
S482
S1436
S1439
INVALID
S2
VSS1
VDD1
C3
INVALID
S3
S6
S477
S480
tPLH1
tPHL1
S483
S1437
S1440
INVALID
S3
VSS1
tSTH-CX
VDD1
STHL
(1st Dr.)
VSS1
tPLH1
tPHL1
VDD1
STHL
(4th Dr.)
VSS1
tCXhold
tCXsetup
VDD1
CX
VSS1
tPLH3
tPLH2
Target Voltage ± 20 mV
tPHL2
tPHL3
13
µ PD16781
Target Voltage ± 0.1 VDD1
Sn
(VOUT)
µ PD16781
9. RECOMMENDED MOUNTING CONDITIONS
The following conditions must be met for mounting conditions of the µ PD16781.
For more details, refer to the Semiconductor Device Mounting Technology Manual (C10535E).
Please consult with our sales offices in case other mounting process is used, or in case the mounting is done under
different conditions.
µ PD16781N-xxx: TCP (TAB Package)
Mounting Condition
Thermocompression
Mounting Method
Soldering
Condition
Heating tool 300 to 350°C, heating for 2 to 3 sec, pressure 100g (per
solder).
ACF
Temporaly bonding 70 to 100°C, pressure 3 to 8 kg/cm2, time 3 to 5 sec.
(Adhesive Conductive
Real bonding 165 to 180°C, pressure 25 to 45 kg/cm2, time 30 to 40 sec
Film)
(When using the anisotropy conductive film SUMIZAC1003 of Sumitomo
Bakelite, Ltd).
Caution
To find out the detailed conditions for mounting the ACF part, please contact the ACF manufacturing
company. Be sure to avoid using two or more mounting methods at a time.
14
DataSheet S14634EJ1V0DS
µ PD16781
NOTES FOR CMOS DEVICES
1
PRECAUTION AGAINST ESD FOR SEMICONDUCTORS
Note:
Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and
ultimately degrade the device operation. Steps must be taken to stop generation of static electricity
as much as possible, and quickly dissipate it once, when it has occurred. Environmental control
must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using
insulators that easily build static electricity. Semiconductor devices must be stored and transported
in an anti-static container, static shielding bag or conductive material. All test and measurement
tools including work bench and floor should be grounded. The operator should be grounded using
wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need
to be taken for PW boards with semiconductor devices on it.
2
HANDLING OF UNUSED INPUT PINS FOR CMOS
Note:
No connection for CMOS device inputs can be cause of malfunction. If no connection is provided
to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence
causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels
of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused
pin should be connected to V DD or GND with a resistor, if it is considered to have a possibility of
being an output pin. All handling related to the unused pins must be judged device by device and
related specifications governing the devices.
3
STATUS BEFORE INITIALIZATION OF MOS DEVICES
Note:
Power-on does not necessarily define initial status of MOS device. Production process of MOS
does not define the initial operation status of the device. Immediately after the power source is
turned ON, the devices with reset function have not yet been initialized. Hence, power-on does
not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the
reset signal is received. Reset operation must be executed immediately after power-on for devices
having reset function.
DataSheet S14634EJ1V0DS
15
µ PD16781
Reference Documents
NEC Semiconductor Device Reliability/Quality Control System (C10983E)
Quality Grades On NEC Semiconductor Devices (C11531E)
• The information in this document is current as of February, 2002. The information is subject to
change without notice. For actual design-in, refer to the latest publications of NEC's data sheets or
data books, etc., for the most up-to-date specifications of NEC semiconductor products. Not all
products and/or types are available in every country. Please check with an NEC sales representative
for availability and additional information.
• No part of this document may be copied or reproduced in any form or by any means without prior
written consent of NEC. NEC assumes no responsibility for any errors that may appear in this document.
• NEC does not assume any liability for infringement of patents, copyrights or other intellectual property rights of
third parties by or arising from the use of NEC semiconductor products listed in this document or any other
liability arising from the use of such products. No license, express, implied or otherwise, is granted under any
patents, copyrights or other intellectual property rights of NEC or others.
• Descriptions of circuits, software and other related information in this document are provided for illustrative
purposes in semiconductor product operation and application examples. The incorporation of these
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responsibility of customer. NEC assumes no responsibility for any losses incurred by customers or third
parties arising from the use of these circuits, software and information.
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agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely. To minimize
risks of damage to property or injury (including death) to persons arising from defects in NEC
semiconductor products, customers must incorporate sufficient safety measures in their design, such as
redundancy, fire-containment, and anti-failure features.
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"Standard", "Special" and "Specific". The "Specific" quality grade applies only to semiconductor products
developed based on a customer-designated "quality assurance program" for a specific application. The
recommended applications of a semiconductor product depend on its quality grade, as indicated below.
Customers must check the quality grade of each semiconductor product before using it in a particular
application.
"Standard": Computers, office equipment, communications equipment, test and measurement equipment, audio
and visual equipment, home electronic appliances, machine tools, personal electronic equipment
and industrial robots
"Special": Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster
systems, anti-crime systems, safety equipment and medical equipment (not specifically designed
for life support)
"Specific": Aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life
support systems and medical equipment for life support, etc.
The quality grade of NEC semiconductor products is "Standard" unless otherwise expressly specified in NEC's
data sheets or data books, etc. If customers wish to use NEC semiconductor products in applications not
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(Note)
(1) "NEC" as used in this statement means NEC Corporation and also includes its majority-owned subsidiaries.
(2) "NEC semiconductor products" means any semiconductor product developed or manufactured by or for
NEC (as defined above).
M8E 00. 4