NEC UPD8821

DATA SHEET
MOS INTEGRATED CIRCUIT
μPD8821
7300 PIXELS × 3 COLOR CCD LINEAR IMAGE SENSOR
DESCRIPTION
The μ PD8821 is a high-speed and high sensitive color CCD (Charge Coupled Device) linear image sensor which
changes optical images to electrical signal and has the function of color separation.
The μ PD8821 has 3 rows of 7300 pixels, and it is a 2-output/color type CCD sensor with 2 rows/color of charge
transfer register, which transfers the photo signal electrons of 7300 pixels separately in odd and even pixels.
Therefore, it is suitable for 600dpi/A3 high-speed color digital copiers, color scanners and so on by the use of the
package with heat sink that has high heat radiation.
FEATURES
• Valid photocell
: 7300 pixels × 3
• Photocell pitch
: 10 μ m
• Line spacing
: 40 μ m (4 lines) Red line-Green line, Green line-Blue line
• Color filter
: Primary colors (red, green, and blue), pigment filter (with 10 lx•hour tolerant)
• Resolution
: 24 dot/mm A3 (297 × 420 mm) size (shorter side)
• Data rate
: 60 MHz MAX. (30 MHz/ch max.)
• Output type
: 2 outputs in phase/color
• Power supply
: +10 V
• Drive clock level
: CMOS output under 5 V operation
• On-chip circuits
: Reset feed-through level clamp circuit
7
Voltage amplifiers
ORDERING INFORMATION
Part Number
Package
μ PD8821CZ-A
CCD linear image sensor 40-pin plastic DIP with heat sink (15.24 mm (600))
Remark
The μ PD8821CZ-A is a lead-free product.
The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
Not all products and/or types are available in every country. Please check with an NEC Electronics
sales representative for availability and additional information.
Document No. S17961EJ2V0DS00 (2nd edition)
Date Published July 2007 NS
Printed in Japan
The mark <R> shows major revised points.
The revised points can be easily searched by copying an "<R>" in the PDF file and specifying it in the "Find what:" field.
2006
μ PD8821
BLOCK DIAGRAM
VOD
36
VOUT2
37
φ CP
φ 2L
GND
φ 1BO
φ 2AO
φ 1B
φ 2A
35
34
33
32
31
25
26
CCD analog shift register
(Blue, even)
D140
D129
…
24
D140
S7300
…
D129
S7299
Photocell
(Blue)
S7300
S2
...
S1
D128
D27
Transfer gate
23
φ TG1
Transfer gate
VOUT1
38
CCD analog shift register
(Blue, odd)
GND
39
VOUT3
40
CCD analog shift register
(Green, odd)
Photocell
(Green)
S7299
S2
...
S1
D128
D27
Transfer gate
φ TG2
Transfer gate
VOUT4
CCD analog shift register
1
(Green, even)
GND
GND
2
VOUT6
3
18
CCD analog shift register
(Red, even)
…
D140
D129
S7300
Photocell
(Red)
S7299
S2
...
S1
D128
D27
Transfer gate
17
φ TG3
Transfer gate
VOUT5
(Red, odd)
4
CCD analog shift register
5
VOD
2
6
7
8
9
10
15
16
φR
φ 2L
GND
φ 2BO
φ 1AO
φ1A
φ2B
11
30
HS-VOD
HS-VOD
Data Sheet S17961EJ2V0DS
μ PD8821
PIN CONFIGURATION (Top View)
CCD linear image sensor 40-pin plastic DIP with heat sink (15.24 mm (600))
μ PD8821CZ-A
VOUT3
40
Output signal 3 (Green-odd)
Ground
2
GND
GND
39
Ground
Output signal 6 (Red-even)
3
VOUT6
VOUT1
38
Output signal 1 (Blue-odd)
Output signal 5 (Red-odd)
4
VOUT5
VOUT2
37
Output signal 2 (Blue-even)
Output unit drain voltage 2
5
VOD
VOD
36
Output unit drain voltage
Reset gate clock
6
φR
φ CP
35
Reset feed-through level clamp clock
Last stage shift register clock
7
φ 2L
φ 2L
34
Last stage shift register clock
Ground
8
GND
GND
33
Ground
Shift register clock 2BO
9
φ 2BO
φ 1BO
32
Shift register clock 1BO
Shift register clock 1AO
10
φ 1AO
φ 2AO
31
Shift register clock 2AO
Package Heat-Sink VOD
11
HS-VOD
HS-VOD
30
Package Heat-Sink VOD
No connection
12
NC
NC
29
No connection
No connection
13
NC
NC
28
No connection
No connection
14
NC
NC
27
No connection
Shift register clock 1A
15
φ 1A
φ 2A
26
Shift register clock 2A
Shift register clock 2B
16
φ 2B
φ 1B
25
Shift register clock 1B
Transfer gate clock 3
17
φ TG3
φ TG1
24
Transfer gate clock 1
Ground
18
GND
φ TG2
23
Transfer gate clock 2
No connection
19
NC
NC
22
No connection
No connection
20
NC
NC
21
No connection
Blue
7300
Green
7300
7300
Red
Caution
1
VOUT4
1
1
1
Output signal 4 (Green-even)
Pins 11 and 30 (HS-VOD) are connected only to the heat sink. These pins are not connected to VOD
(pins 5 or 36) inside this device.
Set HS-VOD (pins 11 and 30) to VOD (pins 5 and 36) in common on a board. Each VOD is connected
inside this device.
PHOTOCELL STRUCTURE DIAGRAM
10 μ m
7 μm
3 μm
Channel stopper
Aluminum
shield
Data Sheet S17961EJ2V0DS
3
μ PD8821
ABSOLUTE MAXIMUM RATINGS (TA = +25°C)
Parameter
Symbol
Ratings
Unit
Output drain voltage
VOD
–0.3 to +12.0
V
Heat sink voltage
HS-VOD
–0.3 to +12.0
V
Shift register clock voltage
Vφ 1, Vφ 2
–0.3 to +8.0
V
Last stage shift register clock voltage
Vφ 2L
–0.3 to +8.0
V
Reset gate clock voltage
Vφ R
–0.3 to +8.0
V
Reset feed-through level clamp clock voltage
Vφ CP
–0.3 to +8.0
V
Transfer gate clock voltage
Vφ TG1 to Vφ TG3
–0.3 to +8.0
V
Operating ambient temperature Note
TA
0 to +60
˚C
Storage temperature
Tstg
–40 to +100
˚C
Note
The operating ambient temperature is defined as an atmosphere temperature in a point 10 mm away on the
substrate, and 10 mm away from the short side of package 1 pin.
Caution
Product quality may suffer if the absolute maximum rating is exceeded even momentarily for any
parameter. That is, the absolute maximum ratings are rated values at which the product is on the
verge of suffering physical damage, and therefore the product must be used under conditions that
ensure that the absolute maximum ratings are not exceeded.
RECOMMENDED OPERATING CONDITIONS (TA = +25°C)
Parameter
Symbol
MIN.
TYP.
MAX.
Unit
Output drain voltage
VOD
9.5
10.0
10.5
V
Heat sink voltage
HS-VOD
9.5
10.0
10.5
V
Shift register clock high level
Vφ 1H, Vφ 2H
4.75
5.0
6.0
V
Shift register clock low level
Vφ 1L, Vφ 2L
–0.3
0.0
+0.25
V
Last stage shift register clock high level
Vφ 2LH
4.75
5.0
6.0
V
Last stage shift register clock low level
Vφ 2LL
–0.3
0.0
+0.25
V
Reset gate clock high level
Vφ RH
4.75
5.0
5.5
V
Reset gate clock low level
Vφ RL
-0.3
0.0
+0.5
V
Reset feed-through level clamp clock high level
Vφ CPH
4.75
5.0
6.0
V
Reset feed-through level clamp clock low level
Vφ CPL
–0.3
0.0
+0.5
V
Transfer gate clock high level Note
Vφ TG1H to Vφ TG3H
4.75
Vφ 1H
Vφ 1H
V
Transfer gate clock low level
Vφ TG1L to Vφ TG3L
–0.3
0.0
+0.5
V
Shift register clock amplitude
Vφ 1p-p, Vφ 2p-p
4.75
5.0
6.3
V
Last stage shift register clock amplitude
Vφ 2Lp-p
4.75
5.0
6.3
V
Reset gate clock amplitude
Vφ Rp-p
4.75
5.0
6.3
V
Reset feed-through level clamp clock amplitude
Vφ CPp-p
4.75
5.0
6.3
V
Transfer gate clock amplitude
Vφ TGp-p
4.5
5.0
6.3
V
Data rate
2 × fφ R
0.2
2
60
MHz
Note
When Transfer gate clock high level (Vφ TGH) is higher than shift register clock high level (Vφ 1H), image lag can
increase.
4
Data Sheet S17961EJ2V0DS
μ PD8821
ELECTRICAL CHARACTERISTICS
TA = +25°C, VOD = +10 V, fφ R = 1 MHz, data rate = 2 MHz, storage time = 10 ms, input clock = 5 Vp-p
light source (except Response2): 3200 K halogen lamp + C-500S (infrared cut filter, t = 1 mm)+ HA-50 (heat absorbing filter, t = 3 mm)
Parameter
Symbol
Saturation voltage
<R>
Test Conditions
Vsat
Saturation exposure
Red
SER
3200K+C500S+HA50
MIN.
TYP.
MAX.
Unit
1.2
1.5
–
V
–
0.15
–
lx•s
Green
SEG
–
0.19
–
lx•s
Blue
SEB
–
0.35
–
lx•s
–
6.0
18.0
%
Photo response non-uniformity
PRNU
VOUT = 1 V
Average dark signal
ADS
Light shielding
–
1.0
5.0
mV
Dark signal non-uniformity
DSNU
Light shielding
–
2.0
10.0
mV
Power consumption
PW
–
640
740
mW
Output impedance
ZO
Response1
Response peak
–
0.2
0.4
kΩ
6.86
9.8
12.74
V/lx•s
RG
5.53
7.9
10.27
V/lx•s
RB
Red
RR
Green
Blue
3.01
4.3
5.59
V/lx•s
Red
–
610
–
nm
Green
–
535
–
nm
Blue
–
460
–
nm
Image lag
IL
Offset level
VOS
Output fall delay time
Note
3200K+C500S+HA50
VOUT = 1 V
–
1.0
5.0
%
3.5
4.5
5.5
V
6.0
7.0
8.0
ns
td
t6L = 3 ns
Register imbalance
RI
VOUT = 1 V
–
0
4
%
Total transfer efficiency
TTE
VOUT = 1 V, fφ R = 30 MHz
94
98
–
%
Dynamic range
DR1
Vsat/DSNU
–
750
–
times
DR2
Vsat/σ
Reset feed-through noise
RFTN1
Light shielding
RFTN2
Light shielding random noise
Note
σ dark
Bit clamp, t17 > 4 ns
–
3000
–
times
–1000
–200
+500
mV
–1000
–200
+500
mV
–
0.5
–
mV
td is defined as period from 10% of φ 2L of VOUT1 to VOUT6, and td is reference data after VOUT1 to VOUT6 pins
with FET proving.
Data Sheet S17961EJ2V0DS
5
μ PD8821
INPUT PIN CAPACITANCE (TA = +25°C, VOD = +10 V)
Parameter
Shift register clock pin capacitance
Symbol
Note
Cφ 1
Cφ 2
Pin
Pin No
MIN.
TYP.
MAX.
Unit
φ 1AO
10
235
260
285
pF
φ 1BO
32
235
260
285
pF
φ 1A
15
235
260
285
pF
φ 1B
25
235
260
285
pF
φ 2AO
31
235
260
285
pF
φ 2BO
9
235
260
285
pF
φ 2A
26
235
260
285
pF
φ 2B
16
235
260
285
pF
7
4
5
6
pF
Last stage shift register clock pin capacitance
Cφ 2L
φ 2L
34
4
5
6
pF
Reset gate clock pin capacitance
Cφ R
φR
6
11
12
13
pF
Reset feed-through level clamp clock pin
Cφ CP
φ CP
35
13
15
17
pF
Cφ TG
φ TG1
24
190
210
230
pF
capacitance
Transfer gate clock pin capacitance
Note
φ TG2
23
155
170
185
pF
φ TG3
17
155
170
185
pF
Cφ 1, Cφ 2 are equivalent capacitance with driving device, including the co-capacitance between φ 1 and φ 2.
Remark
Pins 10, 15, 25 and 32 (φ 1), pins 9, 16, 26 and 31 (φ 2), pins 7 and 34 (φ 2L), are each connected inside of
the device.
6
Data Sheet S17961EJ2V0DS
Data Sheet S17961EJ2V0DS
25
26
5
6
3
4
1
2
(3 pixels/channel)
(3650 pixels/channel)
(3 pixels/channel)
Invalid photocell
27
28
Valid photocell
29
30
Invalid photocell
31
32
Optical black
119
120
(48 pixels/channel)
121
122
Register pixels
123
124
(13 pixels/channel)
125
126
A Note
127
128
Note Set the φ R and φ CP to low level during this period (A).
VOUT2,
VOUT4,
VOUT6
VOUT1,
VOUT3,
VOUT5
129
130
φ CP
131
132
φR
7425
7426
φ 2L
7427
7428
φ 2∗
7429
7430
φ 1∗
7431
7432
φ TG
7433
7434
TIMING CHART 1 (Bit Clamp Mode)
μ PD8821
7
8
Data Sheet S17961EJ2V0DS
Caution
10%
t8
10%
t10
t17
10%
t16
90%
t12
90%
t13
10%
10%
10%
t14
t15
90%
90%
t9
t6L
t7L
td
10%
10%
90%
10%
90%
t6
"10%" and "90%" define as the clock voltage with 5 Vp-p condition. i.e. "10%" shows 0.5 V, "90%" shows 4.5 V
VOUT1 to VOUT6
φ CP
φR
φ 2L
φ 2∗
φ 1∗
TIMING CHART 2 (Bit Clamp Mode)
VOS
t7
μ PD8821
μ PD8821
TIMING CHART 3 (Bit Clamp Mode, Line Clamp Mode)
t2
t3
t4
90% 90%
φ TG
10%
10%
t1
φ 1∗
90%
90%
t5
t8
t9 t10
t12 t13 t14
t15
φR
10%
90%
t17
t16
φ CP
Caution
90%
10%
10%
"10%" and "90%" define as the clock voltage with 5 Vp-p condition.
i.e. "10%" shows 0.5 V, "90%" shows 4.5 V
Symbol
t1, t5
t2, t4
t3
t6, t7
MIN.
TYP.
MAX.
Unit
100
300
1000
ns
0
10
–
ns
500
5000
20000
ns
0
10
–
ns
t6L, t7L
0
3
–
ns
t8, t10
0
3
–
ns
t9
6
125
20000
ns
t12, t14
0
3
–
ns
t13
8
125
20000
ns
t15
−3
+250
+1000
ns
t16
0
125
–
ns
t17
4
125
–
ns
t20
5
125
–
ns
Data Sheet S17961EJ2V0DS
9
Data Sheet S17961EJ2V0DS
A
25
26
5
6
3
4
1
2
(3 pixels/channel)
(3650 pixels/channel)
(3 pixels/channel)
Invalid photocell
27
28
Valid photocell
29
30
Invalid photocell
31
32
Optical black
119
120
(48 pixels/channel)
121
122
Register pixels
123
124
(13 pixels/channel)
125
126
Note
127
128
Note Set the φ R and φ CP to low level during this period (A).
VOUT2,
VOUT4,
VOUT6
VOUT1,
VOUT3,
VOUT5
129
130
φ CP
131
132
φR
7425
7426
φ 2L
7427
7428
φ 2∗
7429
7430
φ 1∗
7431
7432
φ TG
7433
10
7434
TIMING CHART 4 (Line Clamp Mode)
μ PD8821
Data Sheet S17961EJ2V0DS
Caution
Low
10%
t9
t10
10%
90%
10%
10%
t20
90%
90%
t8
t6L
t7L
td
10%
10%
90%
10%
90%
t6
"10%" and "90%" define as the clock voltage with 5 Vp-p condition. i.e. "10%" shows 0.5 V, "90%" shows 4.5 V
VOUT1 to VOUT6
φ CP
φR
φ 2L
φ 2∗
φ 1∗
TIMING CHART 5 (Line Clamp Mode)
VOS
t7
μ PD8821
11
μ PD8821
(φ 1AO, φ 2AO), (φ 1BO, φ 2BO), (φ 1A, φ 2B), (φ 1B, φ 2B) cross point
φ 1∗
φ 2∗
1.5 V or more
1.5 V or more
φ 1AO, φ 2L & φ 1BO, φ 2L cross points
φ 1∗
φ 2L
Remark
1.5 V or more
0 V or more
Adjust cross points (φ 1AO, φ 2AO) (φ 1BO, φ 2BO) (φ 1A, φ 2A) (φ 1B, φ 2B) and (φ 1∗, φ 2L) with input
resistance of each pin.
φ 1, φ 2, φ 2L clock width
Min. 3 ns
Min. 3 ns
Min. 4.75 V
4.75 V
4.75 V
φ 1AO, φ 1BO, φ 1A, φ 1B
φ 2AO, φ 2BO, φ 2A, φ 2B
φ 2L
φ 2L
Min. 3 ns
Min. 3 ns
φ 1AO, φ 1BO, φ 1A, φ 1B
φ 2AO, φ 2BO, φ 2A, φ 2B
0.25 V
0.25 V
Min. 4.75 V
12
Data Sheet S17961EJ2V0DS
μ PD8821
DEFINITIONS OF CHARACTERISTIC
1. Saturation voltage : Vsat
Output signal voltage at which the response linearity is lost.
2. Saturation exposure : SE
Product of intensity of illumination (lx) and storage time (s) when saturation of output voltage occurs.
3. Photo response non-uniformity : PRNU
The output signal non-uniformity of all the valid pixels when the photosensitive surface is applied with the light of
uniform illumination. This is calculated by the following formula, and it is defined by each six of them.
PRNU (%) =
Δx
x
× 100
Δx : maximum of | xj − x |
3650
xj
j=1
Σ
x=
3650
VOUT
x
Register Dark
DC level
Δx
4. Average dark signal : ADS
Average output signal voltage of all the valid pixels at light shielding. This is calculated by the following formula,
and it is defined by each six of them.
3650
Σd j
ADS (mV) =
j=1
3650
dj : Dark signal of valid pixel number j
Data Sheet S17961EJ2V0DS
13
μ PD8821
5. Dark signal non-uniformity : DSNU
Absolute maximum of the difference between ADS and voltage of the highest or lowest output pixel of all the valid
pixels at light shielding. This is calculated by the following formula, and it is defined by each six of them.
DSNU (mV) : maximum of | dj − ADS | j = 1 to 3650
dj : Dark signal of valid pixel number j
VOUT
ADS
Register Dark
DC level
DSNU
6. Output impedance : ZO
Impedance of the output pins viewed from outside.
7. Response : R
Output voltage divided by exposure (lx•s).
Note that the response varies with a light source (spectral characteristic).
8. Image lag : IL
The rate between the last output voltage and the next one after read out the data of a line.
φ TG
ON
Light
OFF
VOUT
V1
VOUT
IL (%) = V1 / VOUT × 100
9. Register imbalance : RI
The rate of the difference between the averages of the output voltage of Odd and Even pixels, against the
average output voltage of all the valid pixels.
RI (%) =
14
2
n
n
2
Σ(V2j -1 − V2j)
j=1
1
n
n
Σ Vj
j=1
× 100
n : Number of valid pixels
Vj : Output voltage of each pixel
Data Sheet S17961EJ2V0DS
μ PD8821
10. Light shielding random noise : σ dark
Light shielding random noise σ dark is defined as the standard deviation of a valid pixel output signal with 100
times (= 100 lines) data sampling at dark (light shielding).
100
σ (mV) =
Σ ( Vi − V )2
i=1
100
,
V=
1 100
Σ Vi
100 i=1
Vi :A valid pixel output signal among all of the valid pixels for each color.
VOUT
V1
line1
V2
line2
V100
line100
This is measured by the DC level sampling of only the signal level, not by CDS (Correlated Double Sampling).
11. Total transfer efficiently : TTE
The total transfer rate of CCD analog shift register. This is calculated by the following formula, it is defined by
each odd output.
TTE(%) = (1-Vb/average output of all the valid pixels) × 100
Vb
Vb: The spilt pixel output (7435th pixel)
7435
7431
7433
Data Sheet S17961EJ2V0DS
15
μ PD8821
12. Reset feed-through noise: RFTN
RFTN is the switching noise by φ R and φ CP, it is defined by each output.
φR
φ CP
φ 2L
+
+
VOS
VOUT1 to VOUT6
16
−
−
RFTN1
RFTN2
Data Sheet S17961EJ2V0DS
μ PD8821
STANDARD CHARACTERISTIC CURVES (1) (Reference Value)
DARK OUTPUT TEMPERATURE
CHARACTERISTIC
STORAGE TIME OUTPUT VOLTAGE
CHARACTERISTIC (TA = +25°C)
2
Relative Output Voltage
10
1
1
0.2
0.1
0.1
0
10
20
30
40
50
60
1
5
10
Storage Time (ms)
Operating Ambient Temperature TA (°C)
TOTAL SPECTRAL RESPONSE CHARACTERISTICS
(without infrared cut filter and heat absorbing filter)(TA = 25°C)
100%
R
G
80%
Response Ration (%)
Relative Output Voltage
100
B
60%
40%
20%
0%
400
500
600
700
800
Wavelength (nm)
Data Sheet S17961EJ2V0DS
17
μ PD8821
STANDARD CHARACTERISTIC CURVES (2) (Reference Value)
Power vs. TA (°C)
Response vs. TA (°C)
1000
1.10
Response
??? ratio
????(mW)
Power
(mW)
800
600
400
1.05
1.00
0.95
200
0
0.90
0
10
20
30
40
50
60
0
??????TA(?)
10
20
30
40
50
60
??????TA(?)
Operating Ambient
Temperature TA (°C)
Operating Ambient Temperature TA (°C)
td vs. TA (°C)
Offset level vs. TA (°C)
8
4.60
4.55
td (ns)
????????td(ns)
?????·????(V)
Offset level (V)
7
4.50
4.45
6
5
4
3
2
1
0
4.40
0
10
20
30
40
50
0
60
??????TA(?)
Operating Ambient Temperature TA (°C)
10
RFTN1 (mV)
????·????????·????RFTN1(mV)
0
-100
-200
-300
-400
-500
10
20
30
40
50
60
??????TA(?)
Operating Ambient
Temperature TA (°C)
18
30
40
??????TA(?)
50
60
Operating Ambient Temperature TA (°C)
RFTN1 vs. TA (°C)
0
20
Data Sheet S17961EJ2V0DS
μ PD8821
APPLICATION CIRCUIT EXAMPLE
+10 V
+
0.1 μF
1
B4
2
3
B6
4
B5
5
47 Ω
φR
7
φ2L
φ2BO
φ1AO
6
47 Ω
3
3
2Ω
φ2B
φTG3
VOD
VOD
φR
φ CP
φ 2L
φ 2L
φ 2AO
17
2Ω
VOUT2
φ 1AO
16
2Ω
VOUT5
φ 1BO
15
3
VOUT1
φ 2BO
14
2Ω
VOUT6
9
12
3
GND
GND
13
φ1A
GND
GND
11
+10 V
VOUT3
8
10
2Ω
VOUT4
18
19
20
HS-VOD
HS-VOD
NC
NC
NC
NC
NC
NC
φ1A
φ2A
φ2B
φ1B
φTG3
φTG1
φTG2
GND
NC
NC
NC
NC
40
2Ω
47 μF/25 V
B3
39
38
37
B1
B2
36
35
47 Ω
φCP
34
33
32
31
30
φ2L
47 Ω
2Ω
2Ω
3
φ1BO
3
φ2AO
3
φ2A
3
φ1B
29
28
+10 V
27
26
25
2Ω
24
2Ω
23
2Ω
22
2Ω
φTG1
φTG2
21
+5 V
B1 to B6 EQUIVALENT CIRCUIT
+10 V
+
+
1.5 kΩ
CCD
VOUT
47 μ F/25 V
100 Ω
10 μF/16 V 0.1 μF
Connects the 3 inverters for
each φ 1 and φ 2 pin.
2SA1206
Data Sheet S17961EJ2V0DS
19
μ PD8821
PACKAGE DRAWING
μPD8821CZ-A
CCD LINEAR IMAGE SENSOR 40-PIN PLASTIC DIP
(WITH HEAT SINK) (15.24 mm (600))
(Unit : mm)
94.4±0.5
94.0±0.5
1st valid pixel
34.7±0.4
2
14.3±0.3
1
9.75±0.4
14.7±0.3
21
40
20
1
1.27±0.15
A
6.22±0.5
B
15.24±0.20
B
A
0.46±0.1
11.1±0.2
5
11.1±0.2
5
3.0±0.2
43.18±0.4
0.9±0.1
0.25±0.05
4.0±0.5
SECTION A-A
(1.71)
16.67±0.5
2.54±0.25
10.0±0.2
SECTION B-B
7.4±0.3
3
7
6
4.51±0.3
4
5°
5°
1°
5
14.1±0.2
1°
5
14.8±0.2
Name
Glass cap
Dimensions
91.0×11.6×0.7
Refractive index
1.5
1 1st valid pixel
The center of the pin1
2 1st valid pixel
The center of the package
3 The surface of the CCD chip
The top of the cap
4 The bottom of the package
The surface of the CCD chip
5 The draft angle of the shaded portions (4 places) are 1 dgree.
6 There is no heat sink exposure from the package.
7 The center of the CCD chip
Package side(shaded portion)
40C-1CCD-PKG1
20
Data Sheet S17961EJ2V0DS
μ PD8821
RECOMMENDED SOLDERING CONDITIONS
When soldering this product, it is highly recommended to observe the conditions as shown below.
If other soldering processes are used, or if the soldering is performed under different conditions, please make sure
to consult with our sales offices.
Type of Through-hole Device
μ PD8821CZ-A: CCD linear image sensor 40-pin plastic DIP with heat sink (15.24 mm (600))
Process
Conditions
Partial heating method
Pin temperature: 380°C or below, Heat time: 3 seconds or less (per pin).
Cautions 1. During assembly care should be taken to prevent solder or flux from contacting the glass cap.
The optical characteristics could be degraded by such contact.
2. Soldering by the solder flow method may have deleterious effects on prevention of glass cap
soiling and heat resistance. So the method cannot be guaranteed.
NOTES OF HANDLING THE PACKAGES
The application of an excessive load to the package may cause the package to warp or break, or cause chips to
come off internally. Particular care should be taken when mounting the package on the circuit board. You should not
reform the lead frame. We recommend to use a IC-inserter when you assemble to PCB.
For this product, the reference value for the three-point bending strength
Note
is 280 [N] (at distance between
supports: 70 mm). Avoid imposing a load, however, on the inside portion as viewed from the face on which the window
(glass) is bonded to the package body.
Note
Three-point
bending
strength
test
Distance
between
supports:70mm,
Support
R:R2mm, Loading
rate:0.5mm/min.
Load
Load
70 mm
70 mm
Data Sheet S17961EJ2V0DS
21
μ PD8821
NOTES ON HANDLING THE PACKAGES
1 MOUNTING OF THE PACKAGE
The application of an excessive load to the package may cause the package to warp or break, or cause chips
to come off internally. Particular care should be taken when mounting the package on the circuit board. Don't
have any object come in contact with glass cap. You should not reform the lead frame. We recommended to
use a IC-inserter when you assemble to PCB.
Also, be care that the any of the following can cause the package to crack or dust to be generated.
1. Applying heat to the external leads for an extended period of time with soldering iron.
2. Applying repetitive bending stress to the external leads.
3. Rapid cooling or heating
2 GLASS CAP
Don’t either touch glass cap surface by hand or have any object come in contact with glass cap surface.
Care should be taken to avoid mechanical or thermal shock because the glass cap is easily to damage. For
dirt stuck through electricity ionized air is recommended.
3 OPERATE AND STORAGE ENVIRONMENTS
Operate in clean environments. CCD image sensors are precise optical equipment that should not be subject
to mechanical shocks. Exposure to high temperatures or humidity will affect the characteristics. So avoid
storage or usage in such conditions.
Keep in a case to protect from dust and dirt. Dew condensation may occur on CCD image sensors when the
devices are transported from a low-temperature environment to a high-temperature environment. Avoid such
rapid temperature changes.
For more details, refer to our document "Review of Quality and Reliability Handbook" (C12769E)
4 ELECTROSTATIC BREAKDOWN
CCD image sensor is protected against static electricity, but destruction due to static electricity is sometimes
detected. Before handling be sure to take the following protective measures.
1.
2.
3.
4.
5.
6.
22
Ground the tools such as soldering iron, radio cutting pliers of or pincer.
Install a conductive mat or on the floor or working table to prevent the generation of static electricity.
Either handle bare handed or use non-chargeable gloves, clothes or material.
Ionized air is recommended for discharge when handling CCD image sensor.
For the shipment of mounted substrates, use box treated for prevention of static charges.
Anyone who is handling CCD image sensors, mounting them on PCBs or testing or inspecting PCBs on
which CCD image sensors have been mounted must wear anti-static bands such as wrist straps and ankle
straps which are grounded via a series resistance connection of about 1 MΩ.
Data Sheet S17961EJ2V0DS
μ PD8821
NOTES FOR CMOS DEVICES
1
VOLTAGE APPLICATION WAVEFORM AT INPUT PIN
Waveform distortion due to input noise or a reflected wave may cause malfunction. If the input of the
CMOS device stays in the area between VIL (MAX) and VIH (MIN) due to noise, etc., the device may
malfunction. Take care to prevent chattering noise from entering the device when the input level is fixed,
and also in the transition period when the input level passes through the area between VIL (MAX) and
VIH (MIN).
2
HANDLING OF UNUSED INPUT PINS
Unconnected CMOS device inputs can be cause of malfunction. If an input pin is unconnected, it is
possible that an internal input level may be generated due to noise, etc., causing malfunction. CMOS
devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed
high or low by using pull-up or pull-down circuitry. Each unused pin should be connected to VDD or GND
via a resistor if there is a possibility that it will be an output pin. All handling related to unused pins must
be judged separately for each device and according to related specifications governing the device.
3
PRECAUTION AGAINST ESD
A strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and
ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as
much as possible, and quickly dissipate it when it has occurred.
Environmental control must be
adequate. When it is dry, a humidifier should be used. It is recommended to avoid using insulators that
easily build up static electricity. Semiconductor devices must be stored and transported in an anti-static
container, static shielding bag or conductive material. All test and measurement tools including work
benches and floors should be grounded.
The operator should be grounded using a wrist strap.
Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for
PW boards with mounted semiconductor devices.
4
STATUS BEFORE INITIALIZATION
Power-on does not necessarily define the initial status of a MOS device. Immediately after the power
source is turned ON, devices with reset functions have not yet been initialized. Hence, power-on does
not guarantee output pin levels, I/O settings or contents of registers. A device is not initialized until the
reset signal is received. A reset operation must be executed immediately after power-on for devices
with reset functions.
5
POWER ON/OFF SEQUENCE
In the case of a device that uses different power supplies for the internal operation and external
interface, as a rule, switch on the external power supply after switching on the internal power supply.
When switching the power supply off, as a rule, switch off the external power supply and then the
internal power supply. Use of the reverse power on/off sequences may result in the application of an
overvoltage to the internal elements of the device, causing malfunction and degradation of internal
elements due to the passage of an abnormal current.
The correct power on/off sequence must be judged separately for each device and according to related
specifications governing the device.
6
INPUT OF SIGNAL DURING POWER OFF STATE
Do not input signals or an I/O pull-up power supply while the device is not powered. The current
injection that results from input of such a signal or I/O pull-up power supply may cause malfunction and
the abnormal current that passes in the device at this time may cause degradation of internal elements.
Input of signals during the power off state must be judged separately for each device and according to
related specifications governing the device.
Data Sheet S17961EJ2V0DS
23
μ PD8821
• The information in this document is current as of July, 2007. The information is subject to change
without notice. For actual design-in, refer to the latest publications of NEC Electronics data sheets or
data books, etc., for the most up-to-date specifications of NEC Electronics products. Not all
products and/or types are available in every country. Please check with an NEC Electronics sales
representative for availability and additional information.
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The quality grade of NEC Electronics products is "Standard" unless otherwise expressly specified in NEC
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defined above).
M8E 02. 11-1