NJU7384 Pulse Input Bipolar Stepper Motor Driver ■ GENERAL DESCRIPTION ■ PACKAGE OUTLINE NJU7384 is a bipolar drive stepping motor driver. The control method used is a simple pulse train input control (STEP & DIR) method of programming. Also, low power consumption was realized as a result of the adoption of a highly efficient CMOS. As the control functions, the external input RESET and ENABLE functions are used, and as the protective function, a thermal shutdown (TSD) is incorporated. The package uses the low thermal resistance SSOP32 which NJU7384V can withstand a high output current. ■ FEATURES • Operating Voltage 3.0 to 5.5V（Logic : VDD） 4.0 to 8.0V（H bridge : VMM） • Maximum Output Current 700mA/ch • Pulse Input (STEP＆DIR) Control • Half / Full Step Change Function • Thermal Shutdown Circuit • Thermal Shutdown Alarm Output • RESET Function • ENABLE Function • CMOS Technology • Package Outline SSOP32 ■ BLOCK DIAGLAM VDD GATE DRIVE VMM1 RESET Ver.2007-08-20 OUTA1 OUTA2 PGNG1 VMM2 GATE DRIVE HSM CONTROL LOGIC DIR TRANSLATOR STEP OUTB1 OUTB2 ENABLE PGND2 GND TSD ALARM TSD -1- NJU7384 ■ PIN FUNCTION 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 1. NC 32. VMM1 2. NC 31. VMM1 3. NC 30. OUTA1 4. VDD 29. OUTA1 5. NC 28. OUTA2 6. STEP 27. OUTA2 7. DIR 26. PGND1 8. HSM 25. PGND1 9. RESET 24. PGND2 10. ENABLE 23. PGND2 11. TSD ALARM 22. OUTB2 12. NC 21. OUTB2 13. GND 20. OUTB1 14. NC 19. OUTB1 15. NC 18. VMM2 16. NC 17. VMM2 ■ PIN DESCRIPTION PIN No. 1,2,3 4 5 6 SYMBOL NC VDD NC STEP 7 8 9 DIR HSM RESET 10 ENABLE 11 TSD ALARM NC GND NC VMM2 OUTB1 OUTB2 PGND2 PGND1 OUTA2 OUTA1 VMM1 12 13 14,15,16 17,18 19,20 21,22 23,24 25,26 27,28 29,30 31,32 FUNCTION Non connection pins Logic Power-Supply input pin Non connection pin Pulse signal input pin for motor rotation control pin Forward / Reverse rotation control Full / Half step mode control pin Phase initialize signal input pin NOTE 1 pulse input ⇒ 1 clock motion Non connection pins Logic ground (GND) pin Non connection pins H bridge power-supply pins Output pin B1 Output pin B2 H bridge ground (GND) pin H bridge ground (GND) pin Output pin A2 Output pin A1 H bridge power-supply pins Connect to motor power-supply Connect to motor power-supply “H”= Forward (CW), ”L”= Reverse (CCW) “H”= Full step, ”L”= Half step “H”= Normal operation, ”L”= Phase initialize Output signal all off control signal “H”= Normal operation, input pin ”L”= Output all off TSD alarm output pin TSD operating =”L” signal output * Short all logic ground terminals and the H bridge ground terminal externally. * Short all H bridge power supply voltage terminals externally. * Fix the potential of unused logic input terminals externally. -2- Ver.2007-08-20 NJU7384 (Ta=25°C) ■ ABSOLUTE MAXIMUM RATINGS PARAMETER Logic Power Supply Voltage H Bridge Power Supply Voltage Logic Input Voltage Motor Output Current (Max) Logic Input Current Operating Temperature Range Operating Junction Temperature Range Storage Temperature Rnage Power Dissipation RATINGS SYMBOL(unit) NOTE +7.0 +9.0 -0.3 ~ VDD 700 10 -40 ~ +85 -40 ~ +150 -50 ~ +150 1175 VDD (V) VMM (V) VID (V) IOPEAK(mA/ch) IIPEAK (mA) Topr (°C) Tj(°C) Tstg(°C) PD (mW) *1) *2) *1) : VDD ≤ VMM *2) : EIAJ/JEDEC STD 2 Layer substrate ■ RECOMMENDED OPERATING CONDITIONS PARAMETER SYMBOL MIN. Logic Power Supply Voltage 3.0 VDD Range H Bridge Power Supply 4.0 VMM Voltage Range TYP. MAX. UNIT 5.0 5.5 V VDD ≤ VMM 6.0 8.0 V - Logic H Input Voltage VIH 3.5 - VDD V Logic L Input Voltage VIL 0 - 1.2 V STEP-ON Time tONMIN 10 - - µs STEP-OFF Time tOFFMIN 10 - - µs Data Setup Time tDS 1 - - µs Hold Time tDH 1 - - µs Input Clock Frequency fCLK - - 50 kHz Ver.2007-08-20 (Ta=25°C) NOTE VDD=5.0V, No load -3- NJU7384 (Ta=25°C, VDD=5V, VMM=6V) ■ ELECTRICAL CHARACTERISTICS PARAMETER SYMBOL CONDITION MIN. TYP. MAX. UNIT - 0.3 0.6 mA - 0.3 0.6 mA ■General I DD Operating Current I MM Thermal Shutdown Operating Temperature Thermal Shutdown Hysteresis STEP, DIR, HSM, RESET, ENABLE=”5V”, No Load, VDD Meas. STEP, DIR, HSM, RESET, ENABLE=”5V”, No load, VMM Meas. TTSD - - 180 - °C THYS - - 30 - °C - - 1 µA -1 - - µA ■Input (STEP, DIR, HSM, ENABLE, RESET Terminals) Logic Input Current IIH IIL STEP, DIR, HSM, ENABLE, RESET =”5V” STEP, DIR, HSM, ENABLE, RESET =”0V” ■H Bridge (Output) H Output Voltage VOH Io=+400mA 5.5 5.7 - V L Output Voltage VOL Io= -400mA - 0.2 0.4 V ROH Io=400mA - 0.75 1.25 Ω ROL Io=400mA - 0.50 1.00 Ω IO LEAK - - 1.0 - µA TSD Alarm L Output Voltage VTSD No external pull-up resistance - - 0.3 V TSD Pull-up Resistance RTSD - - 10 - kΩ Upper Side Output ON Resistance Under Side Output ON Resistance Output Leak Current ■Signal Output -4- Ver.2007-08-20 NJU7384 ■ TIMING CONDITION t ONMIN t OFFMIN 50% STEP t DS t DH DIR,HSM, RESET, ENABLE ■ TRUTH TABLE LOGIC IN VDD DIR HSM RESET ENABLE MODE OPERATE Hi Z CW CCW FULL STEP HALF STEP OPERATE RESET OPERATE Hi Z H L H L H L H L H L *VMM : Motor voltage supply *OPERATE : Follow the input logic *Hi Z : Output all off (A1, A2, B1,B2) ■ EXCITATION SEQUENCE Condition: FULL STEP, HSM=ENABLE=RESET 0 1 2 3 Pulse OUTA1 L H H L OUTA2 H L L H OUTB1 L L H H OUTB2 H H L L IA + + IB + + DIR=HIGH CW DIR=LOW CCW Condition: HALF STEP, HSM=LOW, ENABLE=RESET=HIGH Pulse OUTA1 OUTA2 OUTB1 OUTB2 IA IB DIR=HIGH DIR=LOW 0 L H L H CW CCW 1 Hi Z Hi Z L H 0 - 2 H L L H + - 3 H L Hi Z Hi Z + 0 4 H L H L + + 5 Hi Z Hi Z H L 0 + 6 L H H L + 7 L H Hi Z Hi Z 0 * Regarding the current flow direction, the direction A1→A2 and B1→B2 is indicated as +, and the direction A2→A1 and B2→B1 is indicated as –. Ver.2007-08-20 -5- NJU7384 ■ POWER SUPPLY ON/OFF TIMING Regarding the switch-on sequence of the logic power supply VDD and the motor power supply VMM, input VDD after VMM has risen. The recommended sequence is shown below. ON VDD ≤ VMM VDD ≤ VMM OFF VMM VDD The RESET signal is "L" level in the range of turning ON . And Phase logic is initialized. RESET The STEP terminal is a negative edge active. If STEP input terminal is no Signal. It signal level is fixed at “H “ level . STEP HSM/DIR ENABLE IA IB Excitation phase backup section Phase logic initialization section ■ RECOMMENDED STEP MODE CHANGEOVER (HSM) The current flowing through the stepping motor must be controlled continuously so that a mis-step does not occur. Also, the following precautions must be observed concerning changing of the setting of the HSM input. (1) A mis-step does not occur during changeover from a full step to a half step (2) Regarding changeover from a half step to a full step, (a) A mis-step does not occur during changeover from a half step (excitation sequence 0, 2, 4, 6) to a full step. (b) A mis-step occurs during changeover from a half step (excitation sequence 1, 3, 5, 7) to a full step. For the above reason, it is recommended that mode changeover from a half step to a full step be carried out during the period when the RESET input is “L” logic. -6- Ver.2007-08-20 NJU7384 ■ TIMING CHART • Fixed mode (Full step / Forward direction) Condition : DIR=”H”, HSM=”H” VMM, VDD DIR HSM excitation sequence No. 0 1 2 3 4 STEP RESET ENABLE IA IB Ver.2007-08-20 -7- NJU7384 • Direction change (Full step / Forward direction ⇒ Reverse direction) Condition : DIR=”H” ⇒ ”L”, HSM=”H” VMM, VDD DIR HSM excitation sequence No. 0 1 2 1 0 3 2 1 STEP RESET ENABLE IA IB -8- Ver.2007-08-20 NJU7384 • Step mode change (Full step ⇒ Half step) Condition : DIR=”H”, HSM=”H” ⇒ ”L” VMM, VDD DIR HALF STEP sequence HSM excitation sequence No. 0 1 2 5 6 7 0 1 0 1 2 3 4 5 6 7 0 STEP RESET ENABLE IA IB Ver.2007-08-20 -9- NJU7384 ■ APPLICATION CIRCUIT V MM(+6V) + + V DD(+5V) GND(V MM) V DD µ-COM CMOS,TTL-LS Input/Output Device RESET NORMAL/INHIBIT HSM RESET ENABLE OUTA1 STEPPER M OUTA2 PGND1 V MM2 GATE DRIVE FULL/HALF DIR CONTROL LOGIC CW/CCW STEP TRANSLATOR STEP GATE DRIVE V MM1 OUTB1 OUTB2 PGND2 TSD ALARM THERMAL SENSOR GND TSD GND(V DD) GND(V MM) [CAUTION] The specifications on this databook are only given for information , without any guarantee as regards either mistakes or omissions. The application circuits in this databook are described only to show representative usages of the product and not intended for the guarantee or permission of any right including the industrial rights. - 10 - Ver.2007-08-20