NJW1111 9-IN 3-OUT STEREO AUDIO SELECTOR ! GENERAL DESCRIPTION The NJW1111 is a 9-input 3-output stereo audio selector. It includes three independent 9input-1output stereo audio selectors and adjustable gain buffers. The NJW1111 performs superior audio characteristics such as low distortion, low output noise and low crosstalk. All of internal status and variables are controlled by three-wired serial bus. Selectable two Chip address is available for using two chips on same serial bus line. It is suitable for AV amplifier and receiver system and others. ! FEATURES • Operating Voltage • 9-Input, 3-Output Stereo Audio Selector • Operating Current • Low Distortion • Low Output Noise • Low Crosstalk • Channel Separation • Variable Gain Buffer • 3-Wired Serial Control • Bi-CMOS Technology • Package Outline ! PACKAGE OUTLINE NJW1111V ±4.5 to ±7.5V 8mA typ. 0.0007% typ. -116dBV typ. 110dB typ. 110dB typ. 0, 3 to 8dB/0.5dB step SSOP32 ! BLOCK DIAGRAM InB1 InB2 InB3 InB4 InB5 InB6 InB7 InB8 InB9 OutB1 OutB2 OutB3 ADR V+ V+ 10µF 10µF 10µF 10µF 10µF 10µF 10µF 10µF 10µF 10µF 10µF 10µF + + + + + + + + + + + + 32 31 30 29 28 27 26 25 24 23 22 21 + 100µF 20 19 18 100µF 17 GND Gain Gain 8dB to 3dB / 0.5dBstep 50KΩX１８ Gain 8dB to 3dB / 0.5dBstep Gain 8dB to 3dB / 0.5dBstep Gain 8dB to 3dB / 0.5dBstep Gain 8dB to 3dB / 0.5dBstep 8dB to 3dB / 0.5dBstep Control Logic GND 1 10µF + InA1 Ver.4.0 2 10µF + InA2 3 10µF + InA3 4 10µF + InA4 5 10µF + InA5 6 10µF + InA6 7 10µF + InA7 8 10µF + InA8 9 10µF + InA9 10 11 10µF + OutA1 12 10µF + OutA2 13 10µF 14 15 16 DATA CLOCK + OutA3 LATCH –1– NJW1111 !PIN CONFIGURATION 1 InA1 InB1 32 2 InA2 InB2 31 3 InA3 InB3 30 4 InA4 InB4 29 5 InA5 InB5 28 6 InA6 InB6 27 7 InA7 InB7 26 8 InA8 InB8 25 9 InA9 InB9 24 10 GND GND 23 11 OutA1 OutB1 22 12 OutA2 OutB2 21 13 OutA3 OutB3 20 14 LATCH 15 16 ADR 19 DATA V+ 16 18 CLOCK V- 17 No. Symbol Function No. Symbol Function 1 InA1 Ach Input 1 17 V- V- Power Supply Terminal 2 InA2 Ach Input 2 18 V+ V+ Power Supply Terminal 3 InA3 Ach Input 3 19 ADR Chip address setting terminal 4 InA4 Ach Input 4 20 OutB3 Bch Output 3 5 InA5 Ach Input 5 21 OutB2 Bch Output 2 6 InA6 Ach Input 6 22 OutB1 Bch Output 1 7 InA7 Ach Input 7 23 GND Ground Terminal 8 InA8 Ach Input 8 24 InB9 Bch Input 9 9 InA9 Ach Input 9 25 InB8 Bch Input 8 10 GND Ground Terminal 26 InB7 Bch Input 7 11 OutA1 Ach Output 1 27 InB6 Bch Input 6 12 OutA2 Ach Output 2 28 InB5 Bch Input 5 13 OutA3 Ach Output 3 29 InB4 Bch Input 4 14 LATCH LATCH 30 InB3 Bch Input 3 15 DATA DATA 31 InB2 Bch Input 2 16 CLOCK CLOCK 32 InB1 Bch Input 1 –2– Ver.4.0 NJW1111 ! ABSOLUTE MAXIMUM RATING (Ta=25°C) PARAMETER SYMBOL Power Supply Voltage V + RATING UNIT +8/-8 V + - Maximum Input Voltage VIM V /V 800 V Power Dissipation PD NOTE: EIA/JEDEC STANDARD Test board (76.2x114.3x1.6mm, 2layer, FR-4) mounting Operating Temperature Range Topr -40 to +85 °C Storage Temperature Range Tstg -40 to +125 °C mW ! RECOMMENDED OPERATING CONDITIONS (Ta=25°C) PARAMETER Operating Voltage SYMBOL + TEST CONDITION MIN. TYP. MAX. UNIT - ±4.5 ±7.0 ±7.5 V TEST CONDITION MIN. TYP. MAX. UNIT + 4.0 8.0 12.0 MA - 4.0 8.0 12.0 MA MIN. TYP. MAX. UNIT 10.6 12.9 (3.4) (4.4) -0.5 0 0.5 5.0 6.0 7.0 - V /V ! ELECTRICAL CHARACTERISTICS + ♦Power Supply (Ta=25°C, V /V =±7V) PARAMETER SYMBOL Supply Current 1 ICC V , No Signal Supply Current 2 IEE V No Signal ♦ AC CHARACTERISTICS (Ta=25°C, V /V =±7V, VIN=1Vrms,f=1kHz,RL=47kΩ) + PARAMETER SYMBOL Maximum Output Voltage VOM Voltage Gain 1 GV1 Voltage Gain 2 GV2 - TEST CONDITION THD=1% - - dBV (Vrms) dB VIN=200mVrms, Gain=6dB Total Harmonic Distortion 1 THD1 BW=400Hz-30kHz - 0.0007 0.02 Total Harmonic Distortion 2 THD2 Vin=2Vrms, BW=400Hz-30kHz - 0.001 - Total Harmonic Distortion 3 THD3 f=10kHz, BW=400Hz-30kHz - 0.001 - Mute Level ATT Selector=Mute, A-weighted - -110 - Output Noise VNO Rg=0Ω, A-Weighted - -116 -106 dBV (1.6) (5.0) (µVrms) Cross Talk 1 CT1 Rg=0Ω, A-Weighted - -110 - Cross Talk 2 CT2 Rg=0Ω, f=20kHz - -96 - Channel Separation 1 CS1 Rg=0Ω, A-Weighted - -110 -90 Channel Separation 2 CS2 Rg=0Ω, f=20kHz - -96 - % dB dB dB BW: Band Width ♦Logic Control Characteristics (Ta=25°C, V /V =±7V) + PARAMETER SYMBOL - TEST CONDITION MIN. TYP. MAX. UNIT + High Level Input Voltage VADRH ADR Terminal 2.5 - V Low Level Input Voltage VADRL ADR Terminal 0 - 1.5 V Ver.4.0 –3– NJW1111 ! TERMINAL DESCRIPTION PIN NO. SYMBOL FUNCTION TERMINAL DC VOLTAGE EQUIVALENT CIRCUIT V+ 1 to 9 32 to 24 InA1 to 9 InB1 to 9 Ach Input 1 to 9 Bch Input 1 to 9 0V 200Ω 50kΩ GND V-(sub) V+ V+ 50Ω 11 to 13 22 to 20 OutA1 to 3 OutB1 to 3 Ach Output 1 to 3 Bch Output 1 to 3 0V 50Ω 200Ω 18 + V V+ Power Supply Terminal V-(sub) V+ V-(sub) V+ 10 23 GND Ground Terminal 0V V-(sub) V+ 14 15 16 19 LATCH DATA CLOCK ADR LATCH DATA CLOCK Chip address setting terminal 4kΩ 0V 8kΩ V-(sub) –4– Ver.4.0 NJW1111 ! CONTROL DATA FORMAT t7 t4 t1 LATCH t8 t2 t3 CLOCK MSB D15 DATA (✴) LSB MSB First SYMBOL t1 t2 t3 t4 t5 t6 t7 t8 Ver.4.0 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 t5 t6 PARAMETER CLOCK Clock Width CLOCK Pulse Width (High) CLOCK Pulse Width (Low) LATCH Rise Hold Time DATA Setup Time DATA Hold Time CLOCK Setup Time LATCH High Pulse Width MIN TYP MAX UNIT 4 2 2 4 1.6 1.6 1.6 1.6 - - µsec µsec µsec µsec µsec µsec µsec µsec –5– NJW1111 ! CONTROL DATA NJW1111 control data is constructed with 16bits. MSB D15 D14 D13 D12 D11 D10 D9 D8 D7 Setting DATA D6 D5 D4 D3 Select Address D2 D1 D0 Chip Address MSB D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Gain1 Selector1 0 0 0 0 * * * * Gain2 Selector2 0 0 0 1 * * * * Gain3 Selector3 0 0 1 0 * * * * * Chip address is set by chip address select terminal (ADR) status. Chip address select Chip Address terminal D3 D2 D1 D0 Low 1 0 1 0 High 1 0 1 1 !INITIAL CONDITION MSB D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 0 0 0 0 0 0 0 0 0 0 0 0 * * * * 0 0 0 0 0 0 0 0 0 0 0 1 * * * * 0 0 0 0 0 0 0 0 0 0 1 0 * * * * * Chip address is set by chip address select terminal (ADR) status. –6– Ver.4.0 NJW1111 ! CONTROL DATA D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Gain1 Selector1 0 0 0 0 * * * * Gain2 Selector2 0 0 0 1 * * * * Gain3 Selector3 0 0 1 0 * * * * a)Gain DATA Setting D15 D14 D13 D2 0 0 0 0 0dB 0 0 0 1 +3.0 dB 0 0 1 0 +3.5 dB 0 0 1 1 +4.0 dB 0 1 0 0 +4.5 dB 0 1 0 1 +5.0 dB 0 1 1 0 +5.5 dB 0 1 1 1 +6.0 dB 1 0 0 0 +6.5 dB 1 0 0 1 +7.0 dB 1 0 1 0 +7.5 dB 1 0 1 1 +8.0 dB b)Input Selector DATA Setting D11 D10 D9 D8 0 0 0 0 Mute(✴) 0 0 0 1 InA1/B1 0 0 1 0 InA2/B2 0 0 1 1 InA3/B3 0 1 0 0 InA4/B4 0 1 0 1 InA5/B5 0 1 1 0 InA6/B6 0 1 1 1 InA7/B7 1 0 0 0 InA8/B8 1 0 0 1 InA9/B9 Ver.4.0 –7– NJW1111 ! APPLICATION CIRCUIT InB1 InB2 InB3 InB4 InB5 InB6 InB7 InB8 InB9 OutB1 OutB2 OutB3 ADR V+ V+ 10µF 10µF 10µF 10µF 10µF 10µF 10µF 10µF 10µF 10 µF 10µF 10µF + + + + + + + + + + + + 32 31 30 29 28 27 26 25 24 23 22 21 + 100µF 20 19 18 100µF 17 GND Gain Gain 8dB to 3dB / 0.5dBstep 50KΩX１８ Gain 8dB to 3dB / 0.5dBstep Gain 8dB to 3dB / 0.5dBstep Gain 8dB to 3dB / 0.5dBstep Gain 8dB to 3dB / 0.5dBstep 8dB to 3dB / 0.5dBstep Control Logic GND 1 10µF + InA1 2 10µF + InA2 3 10µF + InA3 4 10µF + InA4 5 10µF + InA5 6 10µF + InA6 7 10µF + InA7 8 10µF + InA8 9 10µF + InA9 10 11 10 µF + OutA1 12 10µF + OutA2 13 10µF 14 15 16 DATA CLOCK + OutA3 LATCH [CAUTION] The specifications on this databook are only given for information , without any guarantee as regards either mistakes or omissions. The application circuits in this databook are described only to show representative usages of the product and not intended for the guarantee or permission of any right including the industrial rights. –8– Ver.4.0