SM5168 series PLL Synthesizer IC OVERVIEW The SM5168 series are PLL synthesizer ICs fabricated using NPC’s Molybdenum-gate CMOS process. They provide several combinations of reference and comparator frequency divider ratios, set in master-slice, making them ideal for frequency synthesizers in IF stages of mobile communications devices. They also feature a lock detect signal output (LD). ■ ■ ■ ■ ■ 0.5 ± 0.2 6.4 ± 0.3 (Unit: mm) 4.4 ± 0.2 ■ 2.7 to 3.6V operating supply voltage range Maximum operating frequency • SM5168A× series: 200MHz, VDD = 2.7V • SM5168C× series: 340MHz, VDD = 2.7V Operating current consumption • SM5168A× series: 3.3mA (typ, 200MHz at 0.3Vp-p, VDD = 3.0 V) • SM5168C× series: 4mA (typ, 340MHz at 0.3Vp-p, VDD = 3.0 V) SM5168A× (built-in standby function) and SM168C× (dual frequency divider ratios) series available, as set by master-slice Charge pump output with output polarity for connection to passive filter Lock detect function output −30 to 85°C operating temperature range 8-pin plastic VSOP 0.575 typ +0.1 0.15 −0.05 3.1 ± 0.3 1.15 ± 0.05 ■ ■ PACKAGE DIMENSIONS 0.65 0.10 0.22 ± 0.1 0.1 ± 0.05 FEATURES 0.12 M APPLICATIONS ■ ■ ■ Mobile communications Portable telephones Related applications SERIES CONFIGURATION Frequency divider ratio range1 Maximum operating frequency Reference/comparator frequency dividers N counter R counter SM5168A× series 200MHz 1 272 to 65535 5 to 65535 Yes SM5168C× series 340MHz 2 272 to 65535 5 to 65535 No Version Standby function 1. SM5168C× series: Dual frequency divider ratios are set within the ratio ranges. ORDERING INFORMATION Device Package SM5168××V 8-pin VSOP SEIKO NPC CORPORATION —1 SM5168 series PINOUT (Top view) SM5168A× series SM5168C× series VDD 1 8 XIN DO 2 7 LD TEST VSS 3 6 TEST OPR FIN 4 5 TR VDD 1 8 XIN DO 2 7 LD VSS 3 6 FIN 4 5 PIN DESCRIPTION Number Name I/O 1 VDD – 2.7 to 3.6V supply 2 DO O Phase comparator error signal three-state output pin. Built-in charge pump means that this output can be connected to a low-pass filter. The output polarity is preset for connection to a passive filter. 3 VSS – Ground pin 4 FIN I Phase comparator frequency divider (N-counter) signal input pin. Feedback resistor built-in, so input can be AC-coupled. 5 OPR (SM5168A× series) Description Power-save control pin. Start when HIGH, standby mode when LOW. I TR (SM5168C× series) Frequency divider switching control. Switches between 2 sets of reference and comparator frequency dividers. 6 TEST I Test pin. Leave open or connect to VSS for normal operation. 7 LD O Unlock signal output pin. (Unlocked when LOW) 8 XIN I Reference frequency divider (R-counter) external clock input pin. Feedback resistor built-in, so input can be AC-coupled. SEIKO NPC CORPORATION —2 SM5168 series BLOCK DIAGRAMS SM5168A× series XIN OPR R-counter (64) FR Control Circuit Phase Detector Charge Pump DO Lock Detector LD Charge Pump DO Lock Detector LD TEST FIN N-counter (890) FV XIN R-counter FR TR Decoder SM5168C× series Phase Detector TEST FIN N-counter FV SEIKO NPC CORPORATION —3 SM5168 series SPECIFICATIONS Absolute Maximum Ratings VSS = 0V Parameter Symbol Rating Unit Supply voltage VDD −0.3 to 6.0 V Input voltage range VIN VSS − 0.3 to VDD + 0.3 V TSTG −55 to 125 °C PD 100 mW Symbol Rating Unit Supply voltage VDD 2.7 to 3.6 V Operating temperature range TOPR −30 to 85 °C Storage temperature range Power dissipation Recommended Operating Conditions VSS = 0V Parameter SEIKO NPC CORPORATION —4 SM5168 series Electrical Characteristics VSS = 0V, VDD = 2.7 to 3.6V, Ta = −30 to 85°C unless otherwise noted. Rating Parameter Symbol Condition Unit min typ max 2.7 – 3.6 VDD = 3.0V – 3.3 – VDD = 3.3V – – 5.2 VDD = 3.0V – 4 – VDD = 3.6V – – 8 Supply voltage VDD V VDD operating current consumption 1 (SM5168A× series) IDD1 Note 1. VDD operating current consumption 2 (SM5168C× series) IDD2 Note 2. FIN maximum operating frequency 1 (SM5168A× series) fmax1 300mVp-p sine wave. Note 3. VDD = 2.7V 200 – – MHz XIN maximum operating frequency 1 (SM5168A× series) fmax2 300mVp-p sine wave Note 3. VDD = 2.7V 20 – – MHz FIN maximum operating frequency 2 (SM5168C× series) fmax1 300mVp-p sine wave Note 3. VDD = 2.7V 340 – – MHz XIN maximum operating frequency 2 (SM5168C× series) fmax2 300mVp-p sine wave Note 3. VDD = 2.7V 20 – – MHz FIN minimum operating input frequency fmin 300mVp-p sine wave Note 3. VDD = 3.6V – – 10 MHz FIN AC-coupled input voltage range VAC1 340MHz VDD = 2.7V 0.3 – – Vp-p XIN AC-coupled input voltage range VAC2 20MHz VDD = 2.7V 0.3 – – Vp-p mA mA OPR, TR LOW-level input voltage VIL VDD = 2.7V – – 0.3 V OPR, TR HIGH-level input voltage VIH VDD = 2.7V VDD − 0.3 – – V XIN LOW-level input current IIL1 VIN = 0V VDD = 3.6V – – 50 µA FIN LOW-level input current IIL2 VIN = 0V VDD = 3.6V – – 50 µA XIN HIGH-level input current IIH1 VIN = VDD VDD = 3.6V – – 50 µA FIN HIGH-level input current IIH2 VIN = VDD VDD = 3.6V – – 50 µA OPR, TR LOW-level input leakage current ILL VIN = 0V VDD = 3.6V – – 100 nA OPR, TR HIGH-level input leakage current ILH VIN = VDD VDD = 3.6V – – 100 nA DO, LD LOW-level output voltage VOL IOL = 0.25mA VDD = 2.7V – – 0.4 V DO, LD HIGH-level output voltage VOH IOH = 0.25mA VDD = 2.7V VDD − 0.4 – – V DO, LD LOW-level output current IOL VOL = 0.4V VDD = 2.7V 0.25 – – mA DO, LD HIGH-level output current IOH VOH = VDD − 0.4V VDD = 2.7V 0.25 – – mA DO three-state output high-impedance leakage current IOZL VOL = 0V VDD = 3.6V – – 100 nA IOZH VOH = VDD VDD = 3.6V – – 100 nA Note 1. Note 2. Note 3. fFIN = 200MHz (300mVp-p sine wave), fXIN = 20MHz (300mVp-p sine wave), TR = HIGH fFIN = 340MHz (300mVp-p sine wave), fXIN = 20MHz (300mVp-p sine wave), TR = HIGH Signal generator AC-coupled input with 50Ω termination. SEIKO NPC CORPORATION —5 SM5168 series FUNCTIONAL DESCRIPTION SM5168A× series Frequency dividers The comparator frequency divider (N-counter) and reference frequency divider (R-counter), one of each, are set in master-slice to the following values. ■ ■ Comparator frequency divider (N-counter) = 272 to 65535 Reference frequency divider (R-counter) = 5 to 65535 Standby mode When OPR goes from HIGH to LOW, the PLL is in standby mode with the following input/output conditions. Block State Input FIN LOW level Comparator frequency divider (N-counter) Stopped Input XIN LOW level Reference frequency divider (R-counter) Stopped Phase comparator Reset Output DO Floating Output LD LOW-level When OPR goes from LOW to HIGH, standby mode is released and the PLL is in operating mode, and the following start-up sequence is executed. Internal feedback resistance is connected to XIN to activate the reference frequency divider (R-counter). Internal feedback resistance is connected to FIN. The comparator frequency divider (N-counter) and the phase comparator are reset. DO is floating and LD is LOW. ↓ Reference frequency divider (R-counter) starts to perform frequency division. An internal signal (FR signal) is output on the 2nd clock cycle. ↓ Phase comparator starts and comparator frequency divider (N-counter) starts to perform frequency division. DO floating condition is released and LD goes HIGH. SEIKO NPC CORPORATION —6 SM5168 series SM5168C× series Frequency Dividers The comparator frequency divider (N-counter) and reference frequency divider (R-counter), with 2 sets of comparator frequency divider and reference frequency divider ratios, are set in master-slice. The frequency divider set selected is determined by the state of TR (pin 5). The ratio ranges are the same when TR is HIGH or LOW, and are: ■ ■ Comparator frequency divider (N-counter) = 272 to 65535 Reference frequency divider (R-counter) = 5 to 65535 Frequency Divider Switching When switching the frequency dividers using TR, the dividers switch in sync with the R-counter divider signal (FR) and the N-counter divider signal (FV) to minimize any disturbance in the PLL loop. TR = HIGH divider operation starts t1 t2 t2 t3 FV or FR TR Decoder output TR = LOW frequency divider TR = HIGH frequency divider Counter set signal TR = LOW frequency divider counter set TR = HIGH frequency divider counter set If tF represents the FIN cycle time: t1 = 48tF t2 = (divider ratio when TR = LOW) × tF t3 = (divider ratio when TR = HIGH) × tF If tX represents the XIN cycle time: t1 = 3tX t2 = (divider ratio when TR = LOW) × tX t3 = (divider ratio when TR = HIGH) × tX Both the R-counter and N-counter are configured with presettable counters. The divider outputs (FR and FV) are then input to the phase comparator which performs phase comparison on the falling edge of each signal. The FR/FV signals also function as the R/N-counter preset strobe signals, respectively. Consequently, when the TR signal level switches, the decoder output changes on the first FR/FV (R/N-counter preset strobe) signal and the counters are set in the new frequency dividers on the second FR/FV (R/N-counter preset strobe) signal. Frequency division with the new frequency dividers starts on the falling edge of the second FR/FV (R/N-counter preset strobe) signal. The timing in the diagram shows an example when TR goes from LOW to HIGH only, but the timing operation is identical under the reverse transition. The R/N-counters operate with the same timing, although the Ncounter has a dual modulus prescaler in the initial-stage which means the HIGH-level pulsewidth of the FV and FR signals is different. SEIKO NPC CORPORATION —7 SM5168 series DO Output Timing The phase comparator error signal charge pump signal is output on DO with polarity for connection to an external passive filter. The signals compared are FV and FR, which are the internal comparator frequency divider output signal and reference frequency divider output signal, respectively. The timing is shown in the following figure. FR FV DO LD INPUT/OUTPUT EQUIVALENT CIRCUITS DO FIN TYP100kΩ Lagging correction signal DO To internal counter FIN Leading correction signal From internal circuit TR TEST TR To internal circuit LD To internal circuit TEST XIN TYP100kΩ From internal circuit LD XIN To internal counter From internal circuit SEIKO NPC CORPORATION —8 SM5168 series Please pay your attention to the following points at time of using the products shown in this document. The products shown in this document (hereinafter “Products”) are not intended to be used for the apparatus that exerts harmful influence on human lives due to the defects, failure or malfunction of the Products. Customers are requested to obtain prior written agreement for such use from SEIKO NPC CORPORATION (hereinafter “NPC”). Customers shall be solely responsible for, and indemnify and hold NPC free and harmless from, any and all claims, damages, losses, expenses or lawsuits, due to such use without such agreement. NPC reserves the right to change the specifications of the Products in order to improve the characteristic or reliability thereof. NPC makes no claim or warranty that the contents described in this document dose not infringe any intellectual property right or other similar right owned by third parties. Therefore, NPC shall not be responsible for such problems, even if the use is in accordance with the descriptions provided in this document. Any descriptions including applications, circuits, and the parameters of the Products in this document are for reference to use the Products, and shall not be guaranteed free from defect, inapplicability to the design for the mass-production products without further testing or modification. Customers are requested not to export or re-export, directly or indirectly, the Products to any country or any entity not in compliance with or in violation of the national export administration laws, treaties, orders and regulations. Customers are requested appropriately take steps to obtain required permissions or approvals from appropriate government agencies. SEIKO NPC CORPORATION 15-6, Nihombashi-kabutocho, Chuo-ku, Tokyo 103-0026, Japan Telephone: +81-3-6667-6601 Facsimile: +81-3-6667-6611 http://www.npc.co.jp/ Email: [email protected] NC0008BE 2006.04 SEIKO NPC CORPORATION —9