NPC SM5865BM

ΣDECO SM5865BM
D/A Converter for Digital Audio
NIPPON PRECISION CIRCUITS INC.
OVERVIEW
PINOUT
The SM5865BM is a 24-bit input D/A converter for
digital audio equipment. It comprises newly developed DEM (dynamic element matching) circuits,
3rd-order Σ∆ noise shaper and 23-level quantizer to
control wide-band residual quantization noise in the
signal band, making it ideal for application with
high-frequency sampling formats. Also, the order of
the required final-stage analog lowpass filter can be
reduced, compared to filters for available devices,
enhancing output tone quality. The output stage
employs complementary outputs for high-accuracy
analog signals, with appropriate lowpass filtering of
the output signal.
(Top view)
DVSS
BCKI
TSTN
TO
DVDD
CKI
■
■
■
■
AVDDA
AVDDB
RBP
IOUTB
IOUTBN
RBN
CKDVN
12
13
AVSSB
PACKAGE DIMENSIONS
(Unit: mm)
24-pin SSOP
5.40 0.20
7.80 0.30
■
RAN
S M 5 8 6 5 BM
■
Single-channel D/A converter built-in
High performance
• 0.0004% total harmonic distortion and noise
• 114 dB dynamic range
• 117 dB signal-to-noise ratio
Σ∆ D/A converter
• 3rd-order noise shaper
• 23-level quantizer
Input data format
• 20 or 24-bit word length
• MSB first, right-justified format
• 8 or 4 times oversampling at fs = 16/32/44.1/48/
88.2/96/176.4/192 kHz
System clock frequency
• 192/256/384/512/768/1024 fs
Single 5 V operating supply voltage
24-pin SSOP package
Molybdenum-gate CMOS process
IOUTAN
RSTN
FEATURES
■
IOUTA
IWSL
CVSS
AVSSA
RAP
WCKI
A single SM5865BM IC can be used in combination
with an 8-times oversampling digital filter for conversion for a single audio channel.
■
24
1
DI
+ 0.1
0.15 − 0.05
10.05 0.20
10.20 0.30
P ackag e
SM5865BM
24-pin SSOP
0.8
0.36 0.10
0.10
0.12 M
+0.20
1.90−0.10
D e vice
0.10 0.10
1.80
ORDERING INFORMATION
0.50 0.20
0 10
NIPPON PRECISION CIRCUITS—1
SM5865BM
BLOCK DIAGRAM
TO
8
TSTN
RSTN
7
IWSL
6
WCKI
5
BCKI
4
DI
3
2
Input interface
9
DVDD
CKI
CKDVN
CVSS
10
Timing
control
Divider
Interpolation
11
1
12
Noise shaper
AVSSB
Noise shaper
13
24
23 Level
DEM DAC
23 Level
DEM DAC
14
16
15
DVSS
17
18
19
23 Level
DEM DAC
23 Level
DEM DAC
20
22
21
AVSSA
23
RAP
IOUTA
IOUTAN
RAN
AVDDA
AVDDB
RBP
IOUTB
IOUTBN
RBN
NIPPON PRECISION CIRCUITS—2
SM5865BM
PIN DESCRIPTION
Number
Name
I/O
Description
1
DV S S
–
Digital ground
2
DI
I
Data input
3
BCKI
I
Bit clock input
4
WCKI
I
W ord clock input
5
IWSL
Ip
Input data word length select. 24-bit when HIGH, and 20-bit when LOW .
6
RSTN
Ip
System reset. Reset when LOW .
7
TSTN
Ip
Test pin. Tie HIGH or leave open for normal operation.
8
TO
O
Test output
9
DV D D
–
Digital supply
10
CKI
I
System clock input
11
C K DV N
Ip
System clock frequency divider ratio select. 1 when HIGH (no division), and 2 when LOW .
12
CVSS
–
System clock ground
13
AV S S B
–
Analog ground B
14
RBN
I
Built-in resistor connection B
15
IOUTBN
O
Inverse-phase analog output B
16
IOUTB
O
In-phase analog output B
17
RBP
I
Built-in resistor connection B
18
AV D D B
–
Analog supply B
19
AV D D A
–
Analog supply A
20
RAN
I
Built-in resistor connection A
21
I O U TA N
O
Inverse-phase analog output A
22
I O U TA
O
In-phase analog output A
23
RAP
I
Built-in resistor connection A
24
AV S S A
–
Analog ground A
IP : Pull-up input
NIPPON PRECISION CIRCUITS—3
SM5865BM
SPECIFICATIONS
Absolute Maximum Ratings
DVSS = AVSSA = AVSSB = CVSS = 0 V, DVDD = AVDDA = AVDDB
P arameter
Symbol
Rating
Unit
Supply voltage range
DV D D , AV D D A , AV D D B
−0.3 to 7.0
V
Input voltage range 1
V IN
DV S S − 0.3 to DV D D + 0.3
V
Storage temperature range
T stg
−55 to 125
°C
Pow er dissipation
PD
250
mW
Symbol
Rating
Unit
DV D D , AV D D A , AV D D B
4.5 to 5.5
V
DV D D − AV D D A ,
DV D D − AV D D B ,
AV D D A − AV D D B ,
DV S S − AV S S A ,
DV S S − AV S S B ,
AV S S A − AV S S B ,
DV S S − CV S S ,
AV S S A − CV S S ,
AV S S B − CV S S
±0.1
V
T opr
−40 to 85
°C
1. Pins DI, BCKI, W C K I , C K DVN, IWSL, RSTN, T S T N .
Also applicable during supply switching.
Recommended Operating Conditions
DVSS = AVSSA = AVSSB = CVSS = 0 V, DVDD = AVDDA = AVDDB
P arameter
Supply voltage range
Supply voltage variation
Operating temperature range
NIPPON PRECISION CIRCUITS—4
SM5865BM
DC Electrical Characteristics
Recommended operating conditions, unless otherwise specified.
Rating
P arameter
Symbol
DV D D, AV D D A, AV D D B
supply current 1
ID D
Condition
Unit
min
typ
max
fC K I = 11.2896 MHz
–
6
10
mA
fC K I = 16.9344 MHz
–
9
13
mA
fC K I = 24.576 MHz
–
12
16
mA
fC K I = 36.864 MHz
–
18
23
mA
CKI HIGH-level input voltage
V IHC
0.7V D D
–
–
V
CKI LOW -level input voltage
V ILC
–
–
0.3V D D
V
CKI input voltage
V I N AC
1.0
–
–
Vp-p
A C coupling
HIGH-level input
voltage 2
V IH
2.4
–
–
V
L O W -level input
voltage 2
V IL
–
–
0.5
V
DV D D − 0.4
–
–
V
HIGH-level output
voltage 3
VOH
I O H = −1 m A
L O W -level output
voltage 3
VOL
IO L = 1 mA
–
–
0.4
V
CKI HIGH-level input current
II H C
V IN = DV D D
30
60
120
µA
CKI LOW -level input current
IILC
V IN = 0 V
30
60
120
µA
L O W -level input
current 4
IIL2
V IN = 0 V
–
9
18
µA
HIGH-level input leakage
current 5
IIH1
V IN = DV D D
–
–
1.0
µA
L O W -level input leakage
current 5
IIL1
V IN = 0 V
–
–
1.0
µA
HIGH-level input leakage
current 6
IIH2
V IN = DV D D
–
–
1.0
µA
1.
2.
3.
4.
5.
6.
No output load, NPC-standard input data pattern.
Pins DI, BCKI, W C K I , C K DVN, IWSL, RSTN, T S T N .
Pin TO .
Pins CKDVN, IWSL, RSTN, T S T N .
Pins DI, BCKI, W C K I .
Pins CKDVN, IWSL, RSTN, T S T N .
NIPPON PRECISION CIRCUITS—5
SM5865BM
AC Electrical Characteristics
System clock Input (CKI)
Rating
P arameter
Symbol
Unit
min
typ
max
CKI clock frequency
fC K I
5
–
60
MHz
HIGH-level clock pulsewidth
tC W H
5
–
–
ns
L O W -level clock pulsewidth
tC W L
5
–
–
ns
1/f CKI
VIHC
0.5VDD
VILC
CKI
t CWL
t CWH
Internal System Clock
Rating
P arameter
Internal system clock frequency
Symbol
Condition
fS Y S
Unit
min
typ
max
5
–
46
MHz
Internal system clock frequency is the same as the CKI clock frequency when CKDVN = HIGH.
Internal system clock frequency is half the CKI clock frequency when CKDVN = LOW .
Reset Input (RSTN)
Rating
P arameter
Symbol
Condition
At pow er ON
R S T N L OW -level pulsewidth
tR S T N
After pow er ON
Unit
min
typ
max
1
–
–
µs
100
–
–
ns
NIPPON PRECISION CIRCUITS—6
SM5865BM
Serial input (BCKI, DI, WCKI)
Rating
P arameter
Symbol
Unit
min
typ
max
BCKI HIGH-level pulsewidth
tB C W H
10
–
–
ns
B C K I L OW -level pulsewidth
tB C W L
10
–
–
ns
BCKI pulse cycle
tB C Y
22
–
–
ns
DI setup time
tD S
5
–
–
ns
DI hold time
tD H
5
–
–
ns
WCKI edge to first BCKI rising edge
tW B
10
–
–
ns
Last BCKI rising edge to W C K I e d g e
tB W
10
–
–
ns
BCKI
1.5V
t BCWH
t BCY
t BCWL
DI
1.5V
t DS
t DH
WCKI
1.5V
t WB
t BW
NIPPON PRECISION CIRCUITS—7
SM5865BM
AC Analog Characteristics
Measurement Conditions
External 8fs digital filter
: NPC SM5847AF
External operational amplifier
: JRC NJM5534D
Supply voltage
SM5865BM : DVDD = AVDDA = AVDDB = 5V, DVSS = AVSSA = AVSSB = CVSS = 0V
SM5847AF
: + 3V
NJM5534D
: ± 15V
Ambient temperature
: 25 °C
Input data of SM5847AF
: 48kHz sampling (fs), 24-bit data
System clock
: 24.576MHz (512fs)
Noise shaper operating rate
64fs
Audio analyzer
: Audio Precision System Two (RMS mode)
Measurement filter condition
: THD + N
22HzHPF, 20kHzLPF (FLP-A20K)
: D.R
22HzHPF, 22kHzLPF, A-weight (FIL-AWT)
: S/N
22HzHPF, 22kHzLPF, A-weight (FIL-AWT)
Measurement circuits diagram : See next page.
Analog Characteristics
Rating
P arameter
Output level 1
Total harmonic distortion
Symbol
Condition
Unit
min
typ
max
V out
1 kHz, 0 dB
1.22
1.27
1.32
Vr m s
THD + N
1 kHz, 0 dB
–
0.0004
(− 108dB)
0.0009
(− 101dB)
%
Dynamic range
D.R
1 kHz, −60 dB
108
114
–
dB
Signal-to-noise ratio
S/N
1 kHz, 0/−∞ dB
114
117
–
dB
Gain drift
G.D
–
10
–
ppm/°C
1. V O U T is the output level of the first I–V conversion stage.
Group Delay
Rating
P arameter
Group delay 1
Symbol
T gd
Condition
Unit
min
typ
max
–
–
2/fsi
s
1. fsi is the input sampling rate of S M 5 8 6 5 B M .
For example, fsi is 384kHz when this LSI is used in combination with an 8-times oversampling digital filter of whinch input sampling rate is 48kHz.
NIPPON PRECISION CIRCUITS—8
12
11
10
9
8
7
6
5
4
3
2
1
AVSSB
RBN
IOUTBN
IOUTB
RBP
AVDDB
AVDDA
RAN
IOUTAN
IOUTA
RAP
AVSSA
SM5865
CVSS
CKDVN
CKI
DVDD
TO
TSTN
RSTN
IWSL
WCKI
BCKI
DI
DVSS
IC1
13
14
15
16
17
18
19
20
21
22
23
24
GND
VDD
GND
GND
C4
220p
C3
220p
GND
C2
220p
C1
220p
3
2
3
2
Vee
4
7 U2
5534
6
Vcc
Vee
4
7 U1
5534
6
Vcc
R2
910
R1
910
3
2
Vee
4
GND
7 U3
5534
6
Vcc
C6
220p
R4
680
R3
680
C5
220p
C7
4.7µ
R5
470
GND
BNC
J1
SM5865BM
Measurement circuit
NIPPON PRECISION CIRCUITS—9
SM5865BM
FUNCTIONAL DESCRIPTION
Quantization Noise Reduction
The SM5865BM employs a 3rd-order 23-level quantizer noise shaper to effectively reduce quantization noise
in the audio band. The quantization noise component at 16fs to 96fs operation is shown in figure 1.
0
10
0 dB sine wave equivalent white noise level
20
16fs
30
24fs
40
16-bit, fs quantization noise level
50
32fs
48fs
64fs
60
70
80
Quantization noise
90
(dB)
100
96fs
110
120
130
20-bit, fs quantization noise level
140
150
24-bit, fs quantization noise level
160
170
180
0
0.5
1
1.5
2
2.5
3
3.5
4
Frequency (fs)
Figure 1. Quantization noise level
Internal Oversampling Operation
The SM5865BM accepts data output from an 8-times or 4-times oversampling digital filter, and oversampled
internally again up to the noise shaper operating rate. The internal oversampling factor is determined automatically from the system clock input frequency and the input sampling frequency. This internal oversampling factor (n) must be an integer satisfying the conditions shown in table 1.
Table 1. Operating conditions
P arameter
fW C K I and f C K I compulsor y conditions 1
Noise shaper operating frequency
C K DVN = HIGH
C K D V N = L OW
f CKI = f WCKI × 8 × n
f CKI = f WCKI × 16 × n
where n = 1, 2, 3, ...
where n = 1, 2, 3, ...
f CKI
f ns = f WCKI × n = ---------8
f CKI
f ns = f WCKI × n = ---------16
1. fW C K I = word clock frequency, fC K I = input system clock frequency, n = internal oversampling factor
NIPPON PRECISION CIRCUITS—10
SM5865BM
Word clock input
SM5865
WCKI
System clock input
CKI
System clock divider select
CKDVN
Figure 2. Clock-related inputs
Table 2 shows some possible combinations for the circuit configuration shown in figure 3.
fs
fWCKI
Interpolating filter
SM5865
(8-times/4-times)
fCKI
CKDVN
Figure 3. Circuit configuration
Table 2. System clock frequencies (CKDVN = HIGH)
fs
System clock frequency 1
fC K I
Noise shaper operating
rate
Internal factor
(8fs input)
Internal factor
(4fs input)
16 kHz
6.144 MHz (384fs)
48fs
6
12
16 kHz
8.192 MHz (512fs)
64fs
8
16
16 kHz
12.288 MHz (768fs)
96fs
12
24
32 kHz
6.144 MHz (192fs)
24fs
3
6
32 kHz
8.192 MHz (256fs)
32fs
4
8
32 kHz
12.288 MHz (384fs)
48fs
6
12
32 kHz
16.384 MHz (512fs)
64fs
8
16
32 kHz
24.576 MHz (768fs)
96fs
12
24
44.1 kHz
8.4672 MHz (192fs)
24fs
3
6
44.1 kHz
11.2896 MHz (256fs)
32fs
4
8
44.1 kHz
16.9344 MHz (384fs)
48fs
6
12
44.1 kHz
22.5792 MHz (512fs)
64fs
8
16
44.1 kHz
33.8688 MHz (768fs)
96fs
12
24
48 kHz
9.216 MHz (192fs)
24fs
3
6
48 kHz
12.288 MHz (256fs)
32fs
4
8
48 kHz
18.432 MHz (384fs)
48fs
6
12
48 kHz
24.576 MHz (512fs)
64fs
8
16
48 kHz
36.864 MHz (768fs)
96fs
12
24
NIPPON PRECISION CIRCUITS—11
SM5865BM
Table 2. System clock frequencies (CKDVN = HIGH)
fs
System clock frequency 1
fC K I
Noise shaper operating
rate
Internal factor
(8fs input)
Internal factor
(4fs input)
88.2 kHz
16.9344 MHz (192fs)
24fs
3
6
88.2 kHz
22.5792 MHz (256fs)
32fs
4
8
88.2 kHz
33.8688 MHz (384fs)
48fs
6
12
88.2 kHz
45.1584 MHz (512fs)
64fs
8
16
96 kHz
18.432 MHz (192fs)
24fs
3
6
96 kHz
24.576 MHz (256fs)
32fs
4
8
96 kHz
36.864 MHz (384fs)
48fs
6
12
176.4 kHz
33.8688 MHz (192fs)
24fs
3
6
176.4 kHz
45.1584 MHz (256fs)
32fs
4
8
192 kHz
36.864 MHz (192fs)
24fs
3
6
1. W h e n C K DVN = LOW , the system clock frequency f C K I is halved, so the values shown are half the input frequency required for the same sampling rate
and internal factors.
System Clock Divider (CKDVN)
Audio Data Input (DI, BCKI, WCKI, IWSL)
The SM5865BM has a built-in divide-by-2 system
clock frequency divider. The divider enables the
internal system clock to operate at half the input frequency, for example when the external master clock
input frequency is high.
Input data format
The audio data is input in MSB-first, 2s-complement, 24-bit/20-bit serial format. The input word bit
length is selected by IWSL, 24-bit when HIGH or
open circuit, and 20-bit when LOW.
System Reset (RSTN)
Jitter-free function
The device should be reset in the following cases.
■
■
At power ON
When the system clock CKI stops, or other abnormalities occur.
The device is reset by applying a LOW-level pulse
on RSTN.
Serial input data bits on DI are read into an SIPO
register (serial-to-parallel converter register) on the
rising edge of the bit clock BCKI where the serial
data is converted into parallel data. The internal parallel data control timing is derived from the system
clock, and is not affected by any jitter on the input
data clocks (WCKI and BCKI). After a reset operation is released when RSTN goes HIGH, the internal
timing and the WCKI input timing are phase compared on the first and subsequent WCKI falling
edges and the comparison result is used to perform
timing adjustment to maintain the word boundary
relationship between the internal timing and the
WCKI clock.
NIPPON PRECISION CIRCUITS—12
SM5865BM
TIMING DIAGRAMS
192fs System Clock Input Timing
1 / 8fs
WCKI
CKI
BCKI
(1)20bit *
LSB
MSB
DI
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
BCKI
(2)20bit
LSB
MSB
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
DI
BCKI
(3)24bit
LSB
MSB
DI
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
* Data can be input at any period within the word clock cycle.
NIPPON PRECISION CIRCUITS—13
SM5865BM
256fs System Clock Input Timing
1 / 8fs
WCKI
CKI
BCKI
(1)20bit *
LSB
MSB
DI
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
BCKI
(2)20bit
LSB
MSB
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
DI
BCKI
(3)24bit *
LSB
MSB
DI
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
BCKI
(4)24bit
LSB
MSB
DI
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
* Data can be input at any period within the word clock cycle.
NIPPON PRECISION CIRCUITS—14
SM5865BM
TYPICAL APPLICATIONS
Input Interface Circuit
XTI
SM5847
DOL
DOR
WCKO
BCKO
CKI
DI
WCKI
BCKI
SM5865
CKI
DI
WCKI
BCKI
SM5865
NIPPON PRECISION CIRCUITS—15
SM5865BM
Analog Output Circuit 1
RAP
23 Level
DEM DAC
23 Level
DEM DAC
IOUTA
IOUTAN
RAN
SM5865
RBP
23 Level
DEM DAC
23 Level
DEM DAC
IOUTB
IOUTBN
RBN
Analog Output Circuit 2
RAP
23 Level
DEM DAC
23 Level
DEM DAC
IOUTA
IOUTAN
RAN
SM5865
RBP
23 Level
DEM DAC
23 Level
DEM DAC
IOUTB
IOUTBN
RBN
Note that the analog output characteristics are not guaranteed for non-standard output circuit configurations.
NIPPON PRECISION CIRCUITS—16
SM5865BM
NIPPON PRECISION CIRCUITS INC. reserves the right to make changes to the products described in this data sheet in order to
improve the design or performance and to supply the best possible products. Nippon Precision Circuits Inc. assumes no responsibility fo r
the use of any circuits shown in this data sheet, conveys no license under any patent or other rights, and makes no claim that the circuits
are free from patent infringement. Applications for any devices shown in this data sheet are for illustration only and Nippon Precision
Circuits Inc. makes no claim or warranty that such applications will be suitable for the use specified without further testing or modification.
The products described in this data sheet are not intended to use for the apparatus which influence human lives due to the failure or
malfunction of the products. Customers are requested to comply with applicable laws and regulations in effect now and hereinafter,
including compliance with expor t controls on the distribution or dissemination of the products. Customers shall not expor t, directly or
indirectly, any products without first obtaining required licenses and approvals from appropriate government agencies.
NIPPON PRECISION CIRCUITS INC.
NIPPON PRECISION CIRCUITS INC.
4-3, Fukuzumi 2-chome
Koto-ku, Tokyo 135-8430, Japan
Telephone: 03-3642-6661
Facsimile: 03-3642-6698
NC9920AE
2000.01
NIPPON PRECISION CIRCUITS—17