SM5951A
8-channel DSD Editing System Signal Processor LSI
OVERVIEW
The SM5951A is an 8-channel DSD (Direct Stream Digital) editing system signal processor LSI. It takes 4
DSD input signals per channel, mixes them, and then converts the result back into 1-bit DSD data for output.
FEATURES
■
■
■
■
■
■
■
■
■
■
DSD signal sampling rate: 5.6448MHz (128 × 44.1kHz) and 2.8224MHz (64 × 44.1kHz) supported
8-channel DSD signal mixing
• 8-channel, 4 DSD signal inputs per channel mixing using arbitrary coefficients for each input
Raw signal switching function (auto bypass)
• Automatically switches to raw signal output with no switching noise and no signal degradation when mixing is not required, bypassing the mixing processing
Input/output format
• Normal input/output format where the data changes are synchronized to the bit clock cycle, and Manchester-type encoding input/output format where the data inverts during the bit clock cycle
Monitor output: Simultaneous 64 × 44.1kHz monitor data output when in 128 × 44.1kHz sampling rate mode
Microcontroller interface: Parallel bi-directional 8-bit/16-bit/32-bit data bus supported
Master clock: 45.1584MHz (1024 × 44.1kHz) or 56.448MHz (1280 × 44.1kHz)
2 voltage supplies: 3.3V (3.0 to 3.6V) and 2.5V (2.3 to 2.7V)
Operating temperature range: − 20 to 70°C
Package: 160-pin QFP
PACKAGE DIMENSIONS
(Unit: mm)
31.2 ± 0.4
28.0 ± 0.1
0.22 to 0.4
31.2 ± 0.4
28.0 ± 0.1
0.11 to 0.23
0.65
0.35
4.0MAX
3.35 ± 0.1
0 to 10.0
15
1.6
0.15
15
0.8
0.8 ± 0.2
ORDERING INFORMATION
Device
Package
SM5951AF
160-pin QFP
SEIKO NPC CORPORATION —1
SM5951A
BLOCK DIAGRAM
DSDI1_[3:0]
EDIT
DSD_OUT
DSDI2_[3:0]
DSDI8_[3:0]
(DSD_I/F)
DSDI7_[3:0]
DSDO [8:1]
(DSD64_I/F)
DSD
I/F
DSD_SW
DSDI6_[3:0]
REQ_GEN
DSDI5_[3:0]
MIXER_BLK
DSDI4_[3:0]
COEF_GEN
DSDI3_[3:0]
DSD64O [8:1]
BCKO
EXMUTE
BCKI
CS_X
RD_X
WR_X
ADDR [7:0]
MCU
I/F
CONV128TO64
SELDSDI
BCK64O
DATA [31:0]
SELBUS [1:0]
SEL1280
RST_X
FS
SELDSDO
CLOCK
GENERATOR
&
TIMING
CONTROL
(Internal Clocks & Control)
MOSYNC
CLK
TEST [8:1]
TEST Control
SEIKO NPC CORPORATION —2
SM5951A
PINOUT
91
90
89
88
87
86
85
84
83
82
81
108
107
106
105
104
103
102
101
100
99
98
97
96
95
94
93
92
111
110
109
114
113
112
121
122
123
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
37
38
39
40
31
32
33
34
35
36
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
1
2
3
4
5
6
7
8
9
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
VSS
SELDSDI
SELDSDO
VDDH
VSS
DSD64O8
DSD64O7
DSD64O6
DSD64O5
VDDL
VSS
DSD64O4
DSD64O3
DSD64O2
DSD64O1
VDDL
VSS
BCK64O
VDDH
VSS
BCKO
VDDL
VSS
DSDO8
DSDO7
DSDO6
DSDO5
VDDL
VSS
DSDO4
DSDO3
DSDO2
DSDO1
VDDH
VSS
TEST8
TEST7
TEST6
TEST5
VDDL
VDDL
DATA7
DATA6
DATA5
DATA4
VSS
VDDH
DATA3
DATA2
DATA1
DATA0
VSS
VDDL
RST_X
SELBUS1
SELBUS0
SEL1280
VSS
CLK
VDDL
ADDR7
ADDR6
ADDR5
ADDR4
ADDR3
ADDR2
ADDR1
ADDR0
VSS
VDDH
CS_X
WR_X
RD_X
VSS
VDDL
TEST1
TEST2
TEST3
TEST4
VSS
VDDL
EXMUTE
BCKI
FS
MOSYNC
DATA31
DATA30
DATA29
DATA28
VSS
VDDH
DATA27
DATA26
DATA25
DATA24
VSS
VDDL
DATA23
DATA22
DATA21
DATA20
VSS
VDDH
DATA19
DATA18
DATA17
DATA16
VSS
VDDL
DATA15
DATA14
DATA13
DATA12
VSS
VDDH
DATA11
DATA10
DATA9
DATA8
VSS
117
116
115
120
119
118
VSS
DSDI8_3
DSDI8_2
DSDI8_1
DSDI8_0
DSDI7_3
DSDI7_2
DSDI7_1
DSDI7_0
VDDH
VSS
DSDI6_3
DSDI6_2
DSDI6_1
DSDI6_0
DSDI5_3
DSDI5_2
DSDI5_1
DSDI5_0
VDDL
VSS
DSDI4_3
DSDI4_2
DSDI4_1
DSDI4_0
DSDI3_3
DSDI3_2
DSDI3_1
DSDI3_0
VDDH
VSS
DSDI2_3
DSDI2_2
DSDI2_1
DSDI2_0
DSDI1_3
DSDI1_2
DSDI1_1
DSDI1_0
VDDL
(Top view)
SEIKO NPC CORPORATION —3
SM5951A
Pin Layout Table
No.
Name
I/O
No.
Name
I/O
No.
Name
I/O
No.
Name
I/O
1
VDDL
−
41
VDDL
−
81
VDDL
−
121
VDDL
−
2
DATA7
I/O
42
TEST5
I
82
DSDI1_0
I
122
EXMUTE
I
3
DATA6
I/O
43
TEST6
I
83
DSDI1_1
I
123
BCKI
I
4
DATA5
I/O
44
TEST7
I
84
DSDI1_2
I
124
FS
I
5
DATA4
I/O
45
TEST8
I
85
DSDI1_3
I
125
MOSYNC
O
6
VSS
−
46
VSS
−
86
DSDI2_0
I
126
DATA31
I/O
7
VDDH
−
47
VDDH
−
87
DSDI2_1
I
127
DATA30
I/O
8
DATA3
I/O
48
DSDO1
O
88
DSDI2_2
I
128
DATA29
I/O
9
DATA2
I/O
49
DSDO2
O
89
DSDI2_3
I
129
DATA28
I/O
10
DATA1
I/O
50
DSDO3
O
90
VSS
−
130
VSS
−
11
DATA0
I/O
51
DSDO4
O
91
VDDH
−
131
VDDH
−
12
VSS
−
52
VSS
−
92
DSDI3_0
I
132
DATA27
I/O
13
VDDL
−
53
VDDL
−
93
DSDI3_1
I
133
DATA26
I/O
14
RST_X
I
54
DSDO5
O
94
DSDI3_2
I
134
DATA25
I/O
15
SELBUS1
I
55
DSDO6
O
95
DSDI3_3
I
135
DATA24
I/O
16
SELBUS0
I
56
DSDO7
O
96
DSDI4_0
I
136
VSS
−
17
SEL1280
I
57
DSDO8
O
97
DSDI4_1
I
137
VDDL
−
18
VSS
−
58
VSS
−
98
DSDI4_2
I
138
DATA23
I/O
19
CLK
I
59
VDDL
−
99
DSDI4_3
I
139
DATA22
I/O
20
VDDL
−
60
BCKO
O
100
VSS
−
140
DATA21
I/O
21
ADDR7
I
61
VSS
−
101
VDDL
−
141
DATA20
I/O
22
ADDR6
I
62
VDDH
−
102
DSDI5_0
I
142
VSS
−
23
ADDR5
I
63
BCK64O
O
103
DSDI5_1
I
143
VDDH
−
24
ADDR4
I
64
VSS
−
104
DSDI5_2
I
144
DATA19
I/O
25
ADDR3
I
65
VDDL
−
105
DSDI5_3
I
145
DATA18
I/O
26
ADDR2
I
66
DSD64O1
O
106
DSDI6_0
I
146
DATA17
I/O
27
ADDR1
I
67
DSD64O2
O
107
DSDI6_1
I
147
DATA16
I/O
28
ADDR0
I
68
DSD64O3
O
108
DSDI6_2
I
148
VSS
−
29
VSS
−
69
DSD64O4
O
109
DSDI6_3
I
149
VDDL
−
30
VDDH
−
70
VSS
−
110
VSS
−
150
DATA15
I/O
31
CS_X
I
71
VDDL
−
111
VDDH
−
151
DATA14
I/O
32
WR_X
I
72
DSD64O5
O
112
DSDI7_0
I
152
DATA13
I/O
33
RD_X
I
73
DSD64O6
O
113
DSDI7_1
I
153
DATA12
I/O
34
VSS
−
74
DSD64O7
O
114
DSDI7_2
I
154
VSS
−
35
VDDL
−
75
DSD64O8
O
115
DSDI7_3
I
155
VDDH
−
36
TEST1
I
76
VSS
−
116
DSDI8_0
I
156
DATA11
I/O
37
TEST2
I
77
VDDH
−
117
DSDI8_1
I
157
DATA10
I/O
38
TEST3
I
78
SELDSDO
I
118
DSDI8_2
I
158
DATA9
I/O
39
TEST4
I
79
SELDSDI
I
119
DSDI8_3
I
159
DATA8
I/O
40
VSS
−
80
VSS
−
120
VSS
−
160
VSS
−
SEIKO NPC CORPORATION —4
SM5951A
PIN DESCRIPTION
Number of
Pins
Name
I/O
Polarity1
Voltage
1
RST_X
I
PU, S
3.3V
System Reset
1
FS
I
−
3.3V
1fs Clock (44.1kHz)
1
CLK
I
−
3.3V
Master Clock
1
SEL1280
I
PD, S
3.3V
Select Master Clock Rate
[HIGH]: 1280 × 44.1kHz, [LOW]: 1024 × 44.1kHz
1
SELDSDI
I
PD, S
3.3V
Select DSD Input Format
[HIGH]: Manchester Encoding, [LOW]: Normal
1
SELDSDO
I
PD, S
3.3V
Select DSD Output Format
[HIGH]: Manchester Encoding, [LOW]: Normal
Functional Description
2
SELBUS [1:0]
I
PU, S
3.3V
Select MCU Data Bus Width
[SELBUS1, SELBUS0]
[LOW, LOW]: 8-bit
[LOW, HIGH]: 16-bit
[HIGH, × (LOW or HIGH)]: 32-bit
1
CS_X
I
PU
3.3V
MCU I/F: Chip Select
1
WR_X
I
PU, S
3.3V
MCU I/F: Write Enable
1
RD_X
I
PU, S
3.3V
MCU I/F: Read Enable
8
ADDR [7:0]
I
PU
3.3V
MCU I/F: Address Bus
32
DATA [31:0]
I/O
3mA
3.3V
MCU I/F: Data Bus
1
BCKI
I
S
3.3V
DSD Input: Bit Clock IN
4
DSDI1_[3:0]
I
−
3.3V
DSD Input: DSD CH1 Data (LINE0 to LINE3)
4
DSDI2_[3:0]
I
−
3.3V
DSD Input: DSD CH2 Data (LINE0 to LINE3)
4
DSDI3_[3:0]
I
−
3.3V
DSD Input: DSD CH3 Data (LINE0 to LINE3)
4
DSDI4_[3:0]
I
−
3.3V
DSD Input: DSD CH4 Data (LINE0 to LINE3)
4
DSDI5_[3:0]
I
−
3.3V
DSD Input: DSD CH5 Data (LINE0 to LINE3)
4
DSDI6_[3:0]
I
−
3.3V
DSD Input: DSD CH6 Data (LINE0 to LINE3)
4
DSDI7_[3:0]
I
−
3.3V
DSD Input: DSD CH7 Data (LINE0 to LINE3)
4
DSDI8_[3:0]
I
−
3.3V
DSD Input: DSD CH8 Data (LINE0 to LINE3)
1
EXMUTE
I
−
3.3V
DSD Input: External Mute Pattern
1
BCKO
O
6mA
3.3V
DSD Output: Bit Clock Out
8
DSDO [8:1]
O
3mA
3.3V
DSD Output: DSD Output DATA (CH1 to CH8)
1
BCK64O
O
6mA
3.3V
DSD 64fs Output: Bit Clock Out
8
DSD64O [8:1]
O
3mA
3.3V
DSD 64fs Output: DSD Output DATA (CH1 to CH8)
1
MOSYNC
O
3mA
3.3V
SYNC Monitor
8
TEST [8:1]
I
PD
3.3V
IOTEST_EN, SCAN_EN, ATPG_EN, FUNC_MODE etc.
10
VDDH
−
−
3.3V
Power Supply (I/O)
14
VDDL
−
−
2.5V
Power Supply (Core)
24
VSS
−
−
0V
Ground Level
1. Attributes: S = Schmitt type, PU = with pull-up resistor, PD = with pull-down resistor, mA = output current
SEIKO NPC CORPORATION —5
SM5951A
SPECIFICATIONS
Absolute Maximum Ratings
VSS = 0V
Symbol
Rating
Unit
Supply voltage 1
Parameter
VDDH
− 0.3 to 4.0
V
Supply voltage 2
V
VDDL
− 0.3 to 3.0
Input voltage (3.3V)
VIN
– 0.3 to VDDH + 0.5
V
Power dissipation
PD
1.3
W
TSTG
– 55 to 125
°C
Storage temperature range
Recommended Operating Conditions
VSS = 0V
Symbol
Rating
Unit
Supply voltage 1
Parameter
VDDH
3.0 to 3.6
V
Supply voltage 2
VDDL
2.3 to 2.7
V
Operating temperature
TOPR
– 20 to 70
°C
Electrical Characteristics
DC Characteristics
VDDH = 3.0 to 3.6V, VDDL = 2.3 to 2.7V, VSS = 0V, TOPR = − 20 to 70°C, unless otherwise noted
Pins
Symbol
Current consumption 1
VDDH
IDDH
Current consumption 2
VDDL
IDDL
HIGH-level
(*1)
VIH
LOW-level
(*1)
VIL
−
−
0.8
V
Positive
(*2)
VT+
1.1
−
2.4
V
Input voltage
Schmitt trigger
voltage
Condition
Rating
Parameter
typ
All pins no load
−
−
8
mA
All pins no load
−
−
550
mA
VDDH = 3.6V
2.0
−
−
V
VDDH = 3.0V
max
Unit
min
(*2)
VT−
0.6
−
1.8
V
(*2)
VH
0.1
−
−
V
HIGH-level
(*3)
VOH
IOH = − 3mA (Type 1),
− 6mA (Type 2)
VDDH
− 0.4
−
−
V
LOW-level
(*3)
VOL
IOL = 3mA (Type 1),
6mA (Type 2)
−
−
0.4
V
Negative
Hysteresis voltage
Output voltage
Input leakage current
(*1) (*2)
ILI
−5
−
5
µA
Pull-down resistance
(*4)
RPD
VI = VDDH
60
120
288
kΩ
Pull-up resistance
(*5)
RPU
VI = VSS
60
120
288
kΩ
HIGH-level holding current
(*6)
IBHH
VIN = 2.0V, VDDH = 3.0V
−
−
− 20
µA
LOW-level holding current
(*6)
IBHL
VIN = 0.8V, VDDH = 3.0V
−
−
17
µA
HIGH-level reverse current
(*6)
IBHHO
− 350
−
−
µA
LOW-level reverse current
(*6)
IBHLO
210
−
−
µA
VIN = 0.8V, VDDH = 3.6V
VIN = 2.0V, VDDH = 3.6V
Pin summary
(*1)
(*2)
(*3)
(*4)
(*5)
(*6)
Input pins and bi-directional pins in input mode
Schmitt-characteristic inputs and bi-directional pins in input mode
Output pins and bi-directional pins in output mode
Type 2: BCKO, BCK64O
Type 1: All outputs excluding those above
Inputs with pull-down resistor
Inputs with pull-up resistor
Input/outputs with bus hold circuit (DATA [31:0])
SEIKO NPC CORPORATION —6
SM5951A
AC Characteristics
VDDH = 3.0 to 3.6V, VDDL = 2.3 to 2.7V, VSS = 0V, TOPR = − 20 to 70°C unless otherwise noted.
When fs = 44.1kHz, the FS and BCKI clock inputs have the following frequency division relationship to the
master clock input on CLK.
■
■
When CLK = 1024fs:
(FS) cycle
= 1024 × CLK cycles
(BCKI) cycle [128fs mode] = 8 × CLK cycles (128fs)
(BCKI) cycle [64fs mode] = 16 × CLK cycles (64fs)
When CLK = 1280fs:
(FS) cycle
= 1280 × CLK cycles
(BCKI) cycle [128fs mode] = 10 × CLK cycles (128fs)
(BCKI) cycle [64fs mode] = 20 × CLK cycles (64fs)
System clock input
■
CLK pin
Rating
Parameter
Symbol
Unit
min
typ
max
HIGH-level pulsewidth
tMCWH
7
11.07 (1024fs)
8.86 (1280fs)
−
ns
LOW-level pulsewidth
tMCWL
7
11.07 (1024fs)
8.86 (1280fs)
−
ns
Pulse cycle
tMCY
16
22.14 (1024fs)
17.72 (1280fs)
−
ns
Rise/Fall time
tr, tf
−
−
2
ns
tMCY
tMCWH
tMCWL
VDDH 90%
VDDH 50%
VDDH 10%
CLK
tr
tf
1FS clock input
■
FS pin (44.1kHz)
Rating
Parameter
Symbol
Unit
min
typ
max
HIGH-level pulsewidth
tFSCWH
−
11.34
−
µs
LOW-level pulsewidth
tFSCWL
−
11.34
−
µs
Pulse cycle
tFSCY
−
22.68
−
µs
Rise/Fall time
tfsr, tfsf
−
−
10
ns
tFSCY
tFSCWH
tFSCWL
VDDH 90%
VDDH 50%
VDDH 10%
FS
tfsr
tfsf
SEIKO NPC CORPORATION —7
SM5951A
DSD input/output
FS, BCKI, DSDI××, EXMUTE, BCKO, BCK64O, DSDO×, DSD64O× pins
Parameter
Rating
Symbol
min
typ
max
Unit
DSD bit clock pulsewidth
tDSCW
80
177.16 (1/64fs)
88.58 (1/128fs)
−
ns
DSD bit clock pulse cycle
tDSCY
−
354.31 (1/64fs)
177.16 (1/128fs)
−
ns
DSD 64fs bit clock output pulsewidth
tDS64CW
−
177.16
−
ns
DSD 64fs clock output pulse cycle
tDS64CY
−
354.31
−
ns
tDSS
35
−
−
ns
DSD data input hold time 1
tDSH
35
−
−
ns
DSD data input setup time 2
tDSMS
−
−
18
ns
DSD data input hold time 2
tDSMH
0
−
−
ns
DSD data output delay time
tDSOD
0
−
10
ns
tDSCDLY
0
−
88
ns
DSD data input setup time 1
DSD bit clock output delay time 3
tDSCY
tDSCW
tDSCW
BCKI
tDSS
tDSH
1
DSDI
EXMUTE
tDSMS
tDSMH
2
DSDI
FS
tDSCY
tDSCDLY
tDSCW
tDSCW
BCKO
tDSOD
DSDO
1
tDSOD
DSDO
tDSOD
2
tDS64CY
tDSCDLY
tDS64CW
tDS64CW
BCK64O
tDSOD
DSD64O
1
tDSOD
DSD64O
tDSOD
2
1. Normal mode rating (input data setup time is referenced to the BCKI rising edge)
2. Manchester-type mode rating (input data setup time is referenced to the BCKI falling edge)
3. The delay in the state of internal synchronization relative to the FS input edge
SEIKO NPC CORPORATION —8
SM5951A
MCU interface
■
ADDR [7:0], CS_X, RD_X, WR_X, DATA [31:0] pins
Parameter
Rating
Symbol
min
typ
max
Unit
Access cycle time
tACCY
150
−
−
ns
ADDR, CS_X setup time
tADS
10
−
−
ns
ADDR, CS_X hold time
tADH
10
−
−
ns
RD_X pulsewidth
tRLW
100
−
−
ns
WR_X pulsewidth
tWLW
100
−
−
ns
Read data output delay time
tRDZD
0
−
20
ns
Read data defined delay time
tRDTD
0
−
60
ns
Read data output floating delay time
tRDFD
0
−
10
ns
Write data input setup time
tWDS
20
−
−
ns
Write data input hold time
tWDH
10
−
−
ns
<Data Read>
<Data Write>
tACCY
ADDR [7:0]
CS_X
tADS
tRLW
tADH
RD_X
tADS
tADH
tRDTD
WR_X
tRDZD
DATA (OUT)
tWLW
tRDFD
Hi-Z
Hi-Z
tWDS
tWDH
Hi-Z
DATA (IN)
Initialization
■
RST_X pin
Parameter
Symbol
Initialization time
tINTM
Rating
min
typ
max
6 × tMCY
−
−
Unit
ns
3.0V
VDDH
tINTM
tINTM
RST_X
SEIKO NPC CORPORATION —9
SM5951A
FUNCTIONAL DESCRIPTION
Data Input/Output Format
DSD input format
The DSD input format can be set to one of 2 types by the state of SELDSDI.
(1) Normal mode (SELDSDI = LOW)
DSD input data is read in close to the rising edge of the bit clock BCKI. Note that even if the input is phase
modulated, the data is still read in close to the rising edge of BCKI if the data is defined.
(1/64fs or 1/128fs)
BCKI
DSDI***
D1
D2
D1
D1
D2
D2
(2) Manchester-type input (SELDSDI = HIGH)
DSD input data is read in during the LOW-level pulse of the bit clock BCKI.
(1/64fs or 1/128fs)
BCKI
DSDI***
D1
D1
D2
D2
Note. DSDI***: DSDI1_[3:0], DSDI2_[3:0], DSDI3_[3:0], DSDI4_[3:0], DSDI5_[3:0], DSDI6_[3:0], DSDI7_[3:0], DSDI8_[3:0] pins
Note. When an external mute pattern is input on EXMUTE pin, data is read in normal mode format only, regardless of the state of SELDSDI.
SEIKO NPC CORPORATION —10
SM5951A
DSD output format
The DSD output format can be set to one of 2 types by the state of SELDSDO.
(1) Normal mode (SELDSDO = LOW)
DSD output data transitions occur on the falling edge of the bit clock BCKO.
(1/64fs or 1/128fs)
BCKO
BCK64O
DSDO*
D1
DSD64O*
D2
(2) Manchester-type output (SELDSDO = HIGH)
DSD output data transitions occur on the falling edge of the bit clock BCKO and then inverts on the rising
edge of the bit clock BCKO.
(1/64fs or 1/128fs)
BCKO
BCK64O
DSDO*
D1
DSD64O*
D1
D2
D2
Note. DSDO*: DSDO [8:1] pins, DSD64O*: DSD64O [8:1] pins
MCU Interface
Bus access control
The internal mode and coefficients can be set using either 8/16/32-bit data bus, facilitating easy connection to
various kinds of MCU bus.
The data bus control pins are active LOW. When the chip select (CS_X) is active, read/write control inputs are
valid. When write control (WR_X) is active, data is written in on the rising edge. Data is read out when the read
control (RD_X) is active.
<Data Read>
<Data Write>
ADDR [7:0]
CS_X
RD_X
WR_X
Hi-Z
DATA [31:0] (Out)
DATA [31:0] (In)
Hi-Z
Data (Out)
Hi-Z
Data (In)
Note. DATA [31:0] pins have an additional bus hold circuit which holds the previous data even when the pin is in a high-impedance ("Hi-Z") state.
SEIKO NPC CORPORATION —11
SM5951A
Data bus width selection
The width of the data bus for data access can be set to one of 3 types by the state of the SELBUS [1:0] pins.
(1) 32-bit bus: SELBUS [1:0] = (1, ×)
Micro Controller
(32bit Data Bus)
(2) 16-bit bus: SELBUS [1:0] = (0, 1)
Micro Controller
(16bit Data Bus)
SM5951A
SM5951A
(Chip_Enable)
CS_X
SELBUS1
VDDH
(Chip_Enable)
CS_X
SELBUS1
VSS
(Write_Enable)
WR_X
SELBUS0
VDDH or VSS
(Write_Enable)
WR_X
SELBUS0
VDDH
(Read_Enable)
RD_X
RD_X
(Read_Enable)
ADDR7
ADDR7
ADDR6
ADDR6
ADDR5
ADDR5
(Address)
ADDR4
(Address)
ADDR4
ADDR3
ADDR3
ADDR2
ADDR2
(VDDH or VSS)
ADDR1
(VDDH or VSS)
ADDR0
ADDR1
ADDR0
(VDDH or VSS)
(Data_Bus [31, 24])
DATA [31, 24]
(No Connect)
DATA [31, 24]
(Data_Bus [23, 16])
DATA [23, 16]
(No Connect)
DATA [23, 16]
(Data_Bus [15, 8])
DATA [15, 8]
(Data_Bus [15, 8])
DATA [15, 8]
DATA [7, 0]
(Data_Bus [7, 0])
DATA [7, 0]
(Data_Bus [7, 0])
Note. ADDR0, DATA [31:16] pins are not used.
Note. ADDR [1:0] pins are not used.
(3) 8-bit bus: SELBUS [1:0] = (0, 0)
Micro Controller
(8bit Data Bus)
SM5951A
(Chip_Enable)
CS_X
SELBUS1
VSS
(Write_Enable)
WR_X
SELBUS0
VSS
(Read_Enable)
RD_X
ADDR7
ADDR6
ADDR5
ADDR4
(Address)
ADDR3
ADDR2
ADDR1
ADDR0
(No Connect)
DATA [31, 24]
(No Connect)
DATA [23, 16]
(No Connect)
DATA [15, 8]
(Data_Bus [7, 0])
DATA [7, 0]
Note. DATA [31:8] pins are not used.
Internally, parameter settings and data are handled in 32-bit units, while the memory area addresses are handled in 8-bit units. For 8-bit and 16-bit access bus widths, the 2 least significant address bits (ADDR [1:0]) are
used to determine which internal data bits are accessed as shown in the following table.
32-bit Access
16-bit Access
8-bit Access
Internal
Data bit
ADDR [1:0]
Data Pin
ADDR [1:0]
Data Pin
ADDR [1:0]
Data Pin
7-0 bit
(×, ×)
DATA [7:0]
(0, ×)
DATA [7:0]
(0, 0)
DATA [7:0]
15-8 bit
(×, ×)
DATA [15:8]
(0, ×)
DATA [15:8]
(0, 1)
DATA [7:0]
23-16 bit
(×, ×)
DATA [23:16]
(1, ×)
DATA [7:0]
(1, 0)
DATA [7:0]
31-24 bit
(×, ×)
DATA [31:24]
(1, ×)
DATA [15:8]
(1, 1)
DATA [7:0]
Note. "×" in the address column are don't care bits.
SEIKO NPC CORPORATION —12
SM5951A
Address mapping
Address
Read/
Write
Initial Value
03h-00h
R/W
××××××8Bh
07h-04h
R
−
0Bh-08h
R/W
××076543h
0Fh-0Ch
R
−
13h-10h
R/W
××152B6Bh
7Fh-14h
−
−
83h-80h
R/W
××000000h
87h-84h
8Bh-88h
8Fh-8Ch
R/W
R/W
R/W
××000000h
××000000h
××000000h
93h-90h
R/W
××000000h
97h-94h
9Bh-98h
9Fh-9Ch
R/W
R/W
R/W
××000000h
××000000h
××000000h
A3h-A0h
R/W
××000000h
A7h-A4h
ABh-A8h
AFh-ACh
R/W
R/W
R/W
××000000h
××000000h
××000000h
B3h-B0h
R/W
××000000h
B7h-B4h
BBh-B8h
BFh-BCh
R/W
R/W
R/W
××000000h
××000000h
××000000h
C3h-C0h
R/W
××000000h
C7h-C4h
CBh-C8h
CFh-CCh
R/W
R/W
R/W
××000000h
××000000h
××000000h
D3h-D0h
R/W
××000000h
D7h-D4h
DBh-D8h
DFh-DCh
R/W
R/W
R/W
××000000h
××000000h
××000000h
E3h-E0h
R/W
××000000h
E7h-E4h
EBh-E8h
EFh-ECh
R/W
R/W
R/W
××000000h
××000000h
××000000h
F3h-F0h
R/W
××000000h
F7h-F4h
FBh-F8h
FFh-FCh
R/W
R/W
R/W
××000000h
××000000h
××000000h
31
Switching Status
[31:28] = STAT_CH8
[27:24] = STAT_CH7
Matching Status
[31:28] = MATCH_CH8
[27:24] = MATCH_CH7
24 23
DATA Bit
16 15
[23:20] = STAT_CH6
[19:16] = STAT_CH5
Pattern Match NO.
[23:20] = (reserved)
[19:16] = MATCH8
[23:20] = MATCH_CH6
[19:16] = MATCH_CH5
Delay Offset
[23:21] = (reserved)
[20:16] = DLY_DOWN
87
Control
[7] = OFFPAT
[6] = DCONVEN
[5:4] = DITH [1:0]
[3] = DITHEN
[2] = MUTESEL
[1] = DSD128
[0] = SRESET
[15:12] = STAT_CH4
[11:8] = STAT_CH3
[7:4] = STAT_CH2
[3:0] = STAT_CH1
[15:12] = MATCH7
[11:8] = MATCH6
[7:4] = MATCH5
[3:0] = MATCH4
[15:12] = MATCH_CH4
[11:8] = MATCH_CH3
[7:4] = MATCH_CH2
[3:0] = MATCH_CH1
[15] = (reserved)
[14:8] = DLY_64
[7] = (reserved)
[6:0] = DLY_128
0
CH1 Coefficient
[23:0] = CH1COEF1
[23:0] = CH1COEF2
[23:0] = CH1COEF3
[23:0] = CH1COEF4
CH2 Coefficient
[23:0] = CH2COEF1
[23:0] = CH2COEF2
[23:0] = CH2COEF3
[23:0] = CH2COEF4
CH3 Coefficient
[23:0] = CH3COEF1
[23:0] = CH3COEF2
[23:0] = CH3COEF3
[23:0] = CH3COEF4
CH4 Coefficient
[23:0] = CH4COEF1
[23:0] = CH4COEF2
[23:0] = CH4COEF3
[23:0] = CH4COEF4
CH5 Coefficient
[23:0] = CH5COEF1
[23:0] = CH5COEF2
[23:0] = CH5COEF3
[23:0] = CH5COEF4
CH6 Coefficient
[23:0] = CH6COEF1
[23:0] = CH6COEF2
[23:0] = CH6COEF3
[23:0] = CH6COEF4
CH7 Coefficient
[23:0] = CH7COEF1
[23:0] = CH7COEF2
[23:0] = CH7COEF3
[23:0] = CH7COEF4
CH8 Coefficient
[23:0] = CH8COEF1
[23:0] = CH8COEF2
[23:0] = CH8COEF3
[23:0] = CH8COEF4
SEIKO NPC CORPORATION —13
SM5951A
Control register
The IC operating state is set by the control register.
■
■
■
■
■
■
■
Address
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
00h
OFFPAT
DCONVEN
DITH1
DITH0
DITHEN
MUTESEL
DSD128
SRESET
Bit 0: SRESET (default = 1)
<Software reset>
1: State retention
0: Reset and resync
When set to “0”, it resets the internal computational block data and resynchronizes timing.
When reset and resynchronization finishes, it is automatically set to 1 and the device is in computation
mode.
This bit is write-only, and reading this bit has no meaning.
Bit 1: DSD128 (default = 1)
<DSD data sampling frequency select >
1: 128fs
0: 64fs
Selects the DSD input/output sampling frequency (fs = 44.1kHz).
However, the DSD64O output always has 64fs DSD sampling rate, regardless of this bit setting.
Bit 2: MUTESEL (default = 0)
<MUTE pattern select>
1: External input
0: Internal
Selects the mute pattern used when mixing.
The internally generated pattern is [10010110], while the external input mute pattern is entered on the
EXMUTE pin.
Bit 3: DITHEN (default = 1)
<Dither switch>
1: Dither ON
0: Dither OFF
This applies to the dither when converting the 128fs DSD signal (DSDO*) to the 64fs DSD signal
(DSD64O*).
Selects dither ON/OFF.
Bit [5, 4]: DITH (default = [0, 0])
<Dither level select>
[1, 1]: ± 1/256 [1, 0]: ± 1/128 [0, 1]: ± 1/64 [0, 0]: ± 1/32
This applies to the dither when converting the 128fs DSD signal (DSDO*) to the 64fs DSD signal
(DSD64O*).
Sets the dither level applied.
Bit 6: DCONVEN (default = 0)
<Down conversion ON/OFF>
1: ON
0: OFF
When 128fs DSD signal sampling frequency is selected, this bit selects whether down conversion to 64fs
DSD signal (DSD64O*) is performed or not.
Active only when DSD128 (Bit 1) is set to “1”.
Bit 7: OFFPAT (default = 1)
<DSD64O output select>
1: “96h” mute pattern
0: “H” fixed
When 128fs DSD signal is not selected and down conversion is OFF, this bit selects the 64fs DSD signal
(DSD64O*) output pattern.
When 128fs DSD signal is selected (DSD128 is set to “1”) and down conversion is ON (DCONVEN is set to
“1”), this bit is inactive and the down converted 64fs DSD signal is output on DSD64O*.
Note. DSDO*: DSDO [8:1] pins, DSD64O*: DSD64O [8:1] pins
SEIKO NPC CORPORATION —14
SM5951A
Switching status
The following addresses are used to monitor the switching status. This area of memory is read-only.
Address
Bit 7
Bit 6
04h
Address
Bit 15
Bit 3
Bit 2
Bit 14
Bit 13
Bit 23
Bit 22
Bit 21
Bit 12
Bit 11
Bit 10
07h
Bit 30
Bit 29
Bit 0
Bit 9
Bit 8
STAT_CH3 [3:0]
Bit 20
Bit 19
Bit 18
STAT_CH6 [3:0]
Bit 31
Bit 1
STAT_CH1 [3:0]
STAT_CH4 [3:0]
06h
Address
Bit 4
STAT_CH2 [3:0]
05h
Address
Bit 5
Bit 17
Bit 16
STAT_CH5 [3:0]
Bit 28
Bit 27
Bit 26
STAT_CH8 [3:0]
Bit 25
Bit 24
STAT_CH7 [3:0]
The value of each address indicates the following operating status.
0
: Input DSD data is being passed directly to the output
1
: Switching from direct output (state 0) to internal computation output
4
: Internal DSM computation result signal is being output
7 to 9 : Switching from state 4 to state 0
Other : Not used
Setting the number of pattern matching bits
The following addresses are used to set the minimum number of matching bits in each stage of the DSD input
signal switching process during mixing.
Address
Bit 7
Bit 6
08h
Address
Bit 15
Bit 14
0Bh
MATCH8 [3:0]
MATCH7 [3:0]
MATCH6 [3:0]
MATCH5 [3:0]
MATCH4 [3:0]
Bit 3
Bit 2
Bit 13
Bit 23
Bit 22
Bit 21
Bit 12
Bit 11
Bit 10
Bit 30
Bit 0
Bit 9
Bit 8
MATCH6 [3:0]
Bit 20
Bit 19
Bit 18
(reserved)
Bit 31
Bit 1
MATCH4 [3:0]
MATCH7 [3:0]
0Ah
Address
Bit 4
MATCH5 [3:0]
09h
Address
Bit 5
Bit 17
Bit 16
MATCH8 [3:0]
Bit 29
Bit 28
Bit 27
Bit 26
(reserved)
Bit 25
Bit 24
(reserved)
(Number of matching bits in 1st stage) − 1, (default = 7)
(Number of matching bits in 2nd stage) − 1, (default = 6)
(Number of matching bits in 3rd stage) − 1, (default = 5)
(Number of matching bits in 4th stage) − 1, (default = 4)
(Number of matching bits in 5th stage) − 1, (default = 3)
SEIKO NPC CORPORATION —15
SM5951A
Reading the number of pattern matching bits
The following addresses are used to read out the number of matching bits in each stage of the DSD input signal
switching process during mixing.
Address
Bit 7
Bit 6
0Ch
Address
Bit 15
Bit 14
Bit 3
Bit 13
Bit 23
Bit 22
Bit 21
Bit 12
Bit 11
Bit 30
0Fh
Bit 29
Bit 20
Bit 19
Bit 0
Bit 10
Bit 9
Bit 8
Bit 18
Bit 17
Bit 16
MATCH_CH5 [3:0]
Bit 28
Bit 27
MATCH_CH8 [3:0]
MATCH_CH1 [3:0]
MATCH_CH2 [3:0]
MATCH_CH3 [3:0]
MATCH_CH4 [3:0]
MATCH_CH5 [3:0]
MATCH_CH6 [3:0]
MATCH_CH7 [3:0]
MATCH_CH8 [3:0]
Bit 1
MATCH_CH3 [3:0]
MATCH_CH6 [3:0]
Bit 31
Bit 2
MATCH_CH1 [3:0]
MATCH_CH4 [3:0]
0Eh
Address
Bit 4
MATCH_CH2 [3:0]
0Dh
Address
Bit 5
Bit 26
Bit 25
Bit 24
MATCH_CH7 [3:0]
(Number of channel 1 matching bits) − 1
(Number of channel 2 matching bits) − 1
(Number of channel 3 matching bits) − 1
(Number of channel 4 matching bits) − 1
(Number of channel 5 matching bits) − 1
(Number of channel 6 matching bits) − 1
(Number of channel 7 matching bits) − 1
(Number of channel 8 matching bits) − 1
Output delay correction
These addresses are used to set the mixing delay correction for the DSD input. The setting adjusts the time
from DSD input to DSD output by an internal delay in units of the DSD rate. The actual adjustment is the value
written to memory + 1.
Address
Bit 7
10h
(reserved)
Address
Bit 15
11h
(reserved)
Address
Bit 23
12h
Address
Bit 6
Bit 5
Bit 4
Bit 3
Bit 14
Bit 0
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 18
Bit 17
Bit 16
Bit 25
Bit 24
DLY_64 [6:0]
Bit 22
Bit 30
13h
DLY_128 [6:0]
DLY_64 [6:0]
DLY_DOWN [4:0]
Bit 1
DLY_128 [6:0]
Bit 21
Bit 20
Bit 19
(reserved)
Bit 31
Bit 2
DLY_DOWN [4:0]
Bit 29
Bit 28
Bit 27
Bit 26
(reserved)
(default = 107)
(default = 43)
(default = 21)
: Delay value when sample rate is 128fs
: Delay value when sample rate is 64fs
: Delay value when down sampling from DSDO (128fs) to DSD64O
(64fs)
SEIKO NPC CORPORATION —16
SM5951A
Coefficients
The address space 80h to FFh contains 32 coefficient registers, comprising independent mixing coefficients for
the 4 DSD inputs for each of the 8 channels.
CHnCOEFm [23:0]: n-channel m-input coefficient (default = 0)
Coefficients are represented in linear, 2s-complement, 24-bit format. Minus coefficients have inverted polarity.
Gain setting and positive/inverse (minus) polarity are represented as follows:
Positive: 0dB (input level × 1.0) = 080000h
Inverse : 0dB (input level × − 1.0) = F80000h
Positive maximum: 7FFFFFh (+ 24dB)
Inverse maximum : 800000h (+ 24dB)
Note 1: When the gain setting is ≥ + 12dB, ∆Σ modulator saturation during requantization may cause noise to
increase considerably.
Note 2: Coefficients are read in during an interval close to the rising edge of FS (44.1kHz). If coefficient data
write timing starts and/or ends in this interval, computation using written-in data can be uncertain for
an interval of 1fs until it’s certainly renewed at the next fetch timing. Hence, writing coefficient data
during this interval should be avoided.
T = 1/44.1kHz
Recommended coefficient
write timing
FS
Coefficient register
COFF (n + 1)
COFF (n)
Internal computation
coefficient
COFF (n)
COFF (n + 1)
0.1µs 1.18µs
Read interval (max)
SEIKO NPC CORPORATION —17
SM5951A
Mixing
(CHnCOEF1)
DSDIn_0
(CHnCOEF2)
DELAY
SWITCH
DSDIn_1
(CHnCOEF3)
(DSD_OUTn)
DSM
DSDIn_2
(SW Control)
(CHnCOEF4)
DSDIn_3
(MUTE_COEF)
(Mute Pattern)
Input signal mixing
This stage mixes the 4 DSD input signals on each channel. Each DSD signal is multiplied by its corresponding
coefficient and then added, and the result is converted back into a 1-bit DSD signal by a ∆Σ modulator.
The DSD input signal represents + 1.0 when HIGH and − 1.0 when LOW.
If the mute pattern is selected during mixing, the muting coefficients are also multiplied and added.
Coefficient interpolation and output switching
The mixing coefficients are read in every 1fs cycle, and linearly interpolated for each DSD sample. The mute
pattern coefficients are automatically calculated from the other input coefficients.
If one of the 4 DSD input coefficients is 1.0 or − 1.0 and the other 3 input coefficients are all 0, the corresponding DSD input is switched directly to the output through a delay circuit, avoiding any signal degradation
caused by the ∆Σ modulator. If all 4 coefficients are 0, the mute pattern path is switched and output through the
delay circuit.
The DSM (∆Σ modulator) bypass condition is automatically calculated from the individual coefficients. The
bypass switching occurs when the DSM output matches the delayed output pattern in order to minimize noise
generation.
SEIKO NPC CORPORATION —18
SM5951A
128fs → 64fs Down Conversion
(DSD_OUTn)
(DSDOn)
FIR
Filter
DSM
(DSD64On)
The 128fs DSD output is passed through a 51-tap FIR filter that cuts high-frequency noise, then it is downsampled to 64fs. The signal is reconverted by a ∆Σ modulator into a 64fs DSD signal for output on DSO64On.
Synchronization
Input clock synchronization
The internal computation and interface operation timing are based on the internal word clock’s word boundary
signal (ENFS), regardless of the BCKI input state, so that they are always synchronized. They are synchronized
on the first rising edge of the word clock input on FS after initialization by pin RST_X rising edge or writing to
the SRESET bit (AD = 00h) of the control register. Also, BCKI is synchronized on the first falling edge after
initialization.
The internal synchronization status can be monitored on pin MOSYNC. The BCKI and FS synchronization
status are checked at the beginning of the word clock cycle. If synchronization is maintained for 2 consecutive
word clock cycles, MOSYNC goes HIGH, with the same timing as FS, to indicate successful synchronization.
MOSYNC immediately goes LOW whenever BCKI or FS lose synchronization, indicating resynchronization
is required.
RST_X
BCKI
(BCKI Sync)
...
(ASYNC)
(SYNC)
FS
BCKO, BCK64O
(DATA Clear)
MOSYNC
(Clock Out)
(CLR)
(ASYNC)
(SYNC)
SEIKO NPC CORPORATION —19
SM5951A
Monitoring word clock synchronization
The FS input rising edge synchronization status is always monitored internally. It is monitored in a window − 2
to + 1 master clock cycles wide relative to the current synchronization timing. If the FS input rising edge
occurs outside the window, an FS synchronization error occurs and resynchronization is required.
(FS Sync Error)
(FS Sync OK)
(FS Sync Error)
FS
CLK
(Clocked FS)
(ENFS)
(Internal FS Start timing)
( Internal FS Timing Watch Window )
Word Boundary Timing
Monitoring input bit clock synchronization
The BCKI input falling edge synchronization status is always monitored internally. It is monitored in a window
− 2 to + 1 master clock cycles wide relative to the current synchronization timing. If the BCKI input falling
edge occurs outside the window, a BCKI synchronization error occurs and resynchronization is required.
(BCKI Sync Error)
(BCKI Sync OK)
(BCKI Sync Error)
BCKI
CLK
(Clocked BCKI)
(Internal Bit
Boundary)
(Internal Bit Count Start timing )
( Internal Bit Timing Watch Window )
Bit Boundary Timing
SEIKO NPC CORPORATION —20
SM5951A
DSD Signal Delay Information and Adjustment
The DSD signal internal process flow is shown in the following diagram. Each stage of the process increases
the data delay, and the delay is adjusted internally so that the delay is approximately 1FS cycle.
DSDIn_m
I/O
Buff
MIX
(1)
DSM
(16)
Delay 128
or
Delay 64
SW
(1)
DSDOn
Delay = 18 (DSD sample)
FIR
Filter
(26)
DSM
(32)
Delay
Down
DSD64On
Delay = 58 (128fs sample)
Input-stage delay (I/O buffer)
The input processing delay due to DSD input format status and the BCKI/FS phase relationship is approximately 0.5 to 1.5 samples in length.
(1) Normal mode timing example
Delay (MAX)
BCKI (MAX)
DSDI (MAX)
n+1
Delay (MIN)
BCKI (MIN)
DSDI (MIN)
n+1
BCKI (MAX)
(Clocked)
BCKI (MIN)
(Clocked)
DSD buff1 (MAX)
(Input block)
n
DSD buff1 (MIN)
(Input block)
DSD buff2 [Ch8:Ch1]
(Input block)
n−1
n−2
n+1
n
n−1
n+2
n+1
n
n+1
CLK (1024fs)
(ENFS)
BCKO
n−1
DSD input
(edit block)
CH1 CH2 CH3 CH4 CH5 CH6 CH7 CH8
COEF input
(edit block)
n
n+1
CH1 CH2 CH3 CH4 CH5 CH6 CH7 CH8 CH1 CH2 CH3 CH4 CH5 CH6
CH7
CH8
CH1 CH2 CH3 CH4 CH5 CH6 CH7 CH8
SEIKO NPC CORPORATION —21
SM5951A
(2) Manchester-type input mode timing example
Delay (MAX)
BCKI (MAX)
DSDI (MAX)
n+1
n+1
Delay
(MIN)
BCKI (MIN)
n+1
DSDI (MIN)
n+1
BCKI (MAX)
(Clocked)
BCKI (MIN)
(Clocked)
DSD buff1 (MAX)
(Input block)
n
DSD buff1 (MIN)
(Input block)
DSD buff2 [Ch8:Ch1]
(Input block)
n−1
n−2
n+1
n
n+2
n+1
n−1
n
n+1
CLK (1024fs)
(ENFS)
BCKO
n−1
DSD input
(edit block)
CH1 CH2 CH3 CH4 CH5 CH6 CH7 CH8
COEF input
(edit block)
n
n+1
CH1 CH2 CH3 CH4 CH5 CH6 CH7 CH8 CH1 CH2 CH3 CH4 CH5 CH6
CH7
CH8
CH1 CH2 CH3 CH4 CH5 CH6 CH7 CH8
Internal computation delay
The mixing process internal data delay is determined by the DSD sampling frequency and is 18 samples in
length. The down-sampled 64fs output has an additional delay of 58 samples in length at 128fs rate.
Delay adjustment
The internal delay immediately before output can be adjusted in units of the sample rate. The delay adjustment
can be set in the following internal registers.
(1) DLY_128 [6:0] (Address = 10h)
DSDOn delay in 128fs mode
(2) DLY_64 [6:0] (Address = 11h)
DSDOn delay in 64fs mode
(3) DLY_DOWN [4:0] (Address = 12h) DSDOn → DSD64On delay
SEIKO NPC CORPORATION —22
SM5951A
Initialization
After power is applied, RST_X must be held LOW for the rated time to initialize the device.
During initialization, the data bus is in input mode. The output pins have the following state.
DSD data outputs: LOW
BCKO, BCK64O: LOW
MOSYNC
: LOW
When RST_X goes HIGH, the synchronization adjustment takes place and internal operation commences.
When the initialization is performed by software reset in SRESET (Address = 0), the coefficient registers
(Addresses = 80h to FFh) are cleared, but the internal state registers (Addresses = 00h to 7Fh) maintain their
current setting.
SEIKO NPC CORPORATION —23
SM5951A
Please pay your attention to the following points at time of using the products shown in this document.
The products shown in this document (hereinafter “Products”) are not intended to be used for the apparatus that exerts harmful influence on
human lives due to the defects, failure or malfunction of the Products. Customers are requested to obtain prior written agreement for such
use from SEIKO NPC CORPORATION (hereinafter “NPC”). Customers shall be solely responsible for, and indemnify and hold NPC free and
harmless from, any and all claims, damages, losses, expenses or lawsuits, due to such use without such agreement. NPC reserves the right
to change the specifications of the Products in order to improve the characteristic or reliability thereof. NPC makes no claim or warranty that
the contents described in this document dose not infringe any intellectual property right or other similar right owned by third parties.
Therefore, NPC shall not be responsible for such problems, even if the use is in accordance with the descriptions provided in this document.
Any descriptions including applications, circuits, and the parameters of the Products in this document are for reference to use the Products,
and shall not be guaranteed free from defect, inapplicability to the design for the mass-production products without further testing or
modification. Customers are requested not to export or re-export, directly or indirectly, the Products to any country or any entity not in
compliance with or in violation of the national export administration laws, treaties, orders and regulations. Customers are requested
appropriately take steps to obtain required permissions or approvals from appropriate government agencies.
SEIKO NPC CORPORATION
15-6, Nihombashi-kabutocho, Chuo-ku,
Tokyo 103-0026, Japan
Telephone: +81-3-6667-6601
Facsimile: +81-3-6667-6611
http://www.npc.co.jp/
Email: [email protected]
NC0319CE
2006.04
SEIKO NPC CORPORATION —24