SM9501A/B Radio Controlled Clock Receiver IC OVERVIEW Radio controlled clock FEATURES ■ Operating supply voltage range • 2.4 to 3.6V (A version) • 4.5 to 5.5V (B version) Operating current consumption • 55µA (typ) @3V (A version) • 55µA (typ) @5V (B version) Standby current consumption • 0.1µA (max) @3V (A version) • 0.1µA (max) @5V (B version) High sensitivity: 0.5µVrms input Wide frequency range (35kHz to 80kHz) Include analog switch for antennatuning capacitors change AGC gain hold function External crystal filter connection BiCMOS process Package:16-pin VSOP, Chip form (Top view) pre lim ina ■ PINOUT ■ ■ ■ ■ ORDERING INFORMATION Device Package IN3 OUT IN2 VSS FCN HLDN XO CP VSSA CB 8 XI 9 LF PACKAGE DIMENSIONS (Unit: mm) SM9501AV 16-pin VSOP SM9501BV CF9501A Chip form 4.4 ± 0.2 ■ PON + 0. 0.15 − 1 0.05 6.4 ± 0.2 ■ VDD IN1 0.275TYP 5.1 ± 0.2 1.15 ± 0.1 ■ 16 0.65 0.10 + 0.1 0.22 − 0.05 0 to 10 ° 0.10 ± 0.05 ■ 1 VDDA 0.5 ± 0.2 *1: ry The SM9501A/B is a BiCMOS RCC*1 receiver IC. It accepts low frequency standard wave input received from an external antenna, amplifies it, detects the data signal, and outputs a digital time code signal. 0.12 M NIPPON PRECISION CIRCUITS INC.—1 SM9501A/B PAD LAYOUT (CF9501A) (Unit: µm) IN3 IN2 FCN XO VSSA VDD 1 16 (1430,2360) 2 15 PON 3 14 OUT ina ry IN1 VDDA TN 4 13 VSS 12 HLDN 11 CP 10 CB 9 LF 5 6 7 DA9501 NPC XI (0,0) 8 lim Chip size: 1.43 × 2.36mm Chip thickness: 300 ± 30µm PAD size: 100µm (TN: 80µm) Chip base: VSS level PAD NAME and DIMENSIONS (CF9501A) Number Pad dimensions [µm] Name X Y VDDA 386 2117 2 IN1 177 2035 3 IN3 177 1766 4 IN2 177 1486 5 FCN 177 1217 6 XO 177 937 7 VSSA 177 586 8 XI 177 288 9 LF 1237 286 10 CB 1237 555 11 CP 1237 809 12 HLDN 1237 1078 13 VSS 1237 1302 14 OUT 1237 1755 15 PON 1237 2035 16 VDD 1031 2117 − TN1 1257 1506 pre 1 1. For test mode NIPPON PRECISION CIRCUITS INC.—2 SM9501A/B BLOCK DIAGRAM OUT PON VSS HLDN CP CB VDDA Bias ina ry VDD Decoder Peak/Bottom Hold Det. AGC Control IN1 AGC Amp IN3 IN2 Rectifier XO VSSA XI lim FCN Post Amp LPF LF PIN DESCRIPTION Number Name I/O1 A/D2 1 VDDA − A AGC amplifier (+) supply input 2 IN1 I A Antenna input 1 (fixed input) IN3 I A Antenna input 3 (via analog switch) IN2 I A Antenna input 2 (analog switch bypass) 5 FCN Ipu D Analog switch control input (active LOW) 6 XO O A Output for crystal filter 7 VSSA − A AGC amplifier (–) supply input 8 XI I A Input from crystal filter 9 LF O A Rectifier LPF capacitor connection 10 CB O A Bottom hold detector capacitor connection 11 CP O A Peak hold detector capacitor connection 12 HLDN Ipu D AGC gain hold control (active LOW) 13 VSS − A Substrate (–) supply input 14 OUT O D Clock time code output (active LOW) 15 PON Ipu D Standby state control input (active LOW) 16 VDD − A (+) supply input − TN Ipu D AGC amplifier gain control switch (active LOW, for test mode) 3 pre 4 Description 1. I: input, O: output, Ipu: input with pull-up resistor, –: supply pin 2. A: analog signal, D: digital signal NIPPON PRECISION CIRCUITS INC.—3 SM9501A/B SPECIFICATIONS Absolute Maximum Ratings VSS = 0V Symbol Supply voltage range VDD Input voltage range VIN Power dissipation PD Storage temperature range Tstg Condition Rating Unit −0.3 to +7.0 V ina ry Parameter −0.3 to VDD +0.3 V 16-pin VSOP 150 mW 16-pin VSOP −55 to +125 °C Chip form −65 to +150 °C Rating Unit A version 2.4 to 3.6 V B version 4.5 to 5.5 V A version −20 to +70 °C B version −40 to +85 °C Recommended Operating Conditions VSS = 0V Parameter Supply voltage range Symbol VDD Topr pre lim Operating temperature range Condition NIPPON PRECISION CIRCUITS INC.—4 SM9501A/B Electrical Characteristics 9501A version VDD = 2.4 to 3.6V, VSS = 0V, Ta = −20 to +70°C unless otherwise noted. Rating Parameter Symbol Condition Unit Minimum operating voltage VMIN Maximum operating voltage VMAX Maximum operating current consumption1 IDDM Operating current consumption1 Standby mode current consumption typ max ina ry min – – 2.4 V 3.6 – – V VDD = 3.0V, no input signal, PON: VSS, OUT: OPEN – 65 100 µA IDDT VDD = 3.0V, 500ms pulsewidth, 0.1mVrms input (differential input), PON: VSS, OUT: OPEN – 55 – µA IST PON, FCN, HLDN: VDD or OPEN – – 0.1 µA Minimum input voltage range VFMIN IN1–IN2 differential input – 0.5 1.0 µVrms Maximum input voltage range VFMAX IN1–IN2 differential input 80 – – mVrms FIN IN1–IN2 differential input 35 – 80 kHz Input frequency Analog switch resistance RA V|IN2–IN3| = 50mV, VIN2 = 0V – – 15 Ω Startup time2 tON When supply is applied – – 8 sec Startup time2 (PON) tPON From standby mode – – 8 sec II1 VIN = 0V – – –1.5 µA II2 VIN = 0V PON input current – – –1.5 µA II3 VIN = 0V – – –1.5 µA LOW-level output current IOL VDD = 2.4V, OUT = 0.5V 10 – – µA HIGH-level output current IOH VDD = 2.4V, OUT = 1.9V –10 – – µA Gain hold time tHLD ± 3dB change – – 1 sec – – 160 ms – – 200 ms 100 200 300 ms HLDN input current lim FCN input current Fall time output propagation delay3 tDN Rise time output propagation delay3 tUP LOW-level output pulsewidth4 (200ms) T200 LOW-level output pulsewidth4 (500ms) T500 400 500 650 ms LOW-level output pulsewidth4 (800ms) T800 700 800 900 ms Noise rejection ratio5 S/N – – 9 dB pre FIN = 40/60kHz, standard crystal, NPC standard jig VIN = 1µVrms to 80mVrms 1. Measured using the standard circuit. 2. The time taken under stable wave input conditions from when power is applied or standby is released, using PON, until stable digital output occurs within ratings. 3. The time taken, with 10:1 input signal amplitude ratio and 500ms pulsewidth, from when a change in signal input occurs until the output OUT changes. Note that this characteristic is very dependent on the antenna and crystal filter characteristics. The standard crystal used here has the following equivalent circuit coefficients. L1 C1 R1 f [kHz] L1 [kH] C1 [fF] R1 [kΩ] C0 [pF] 40 6.70280 2.36228 11.4492 1.42773 60 5.17396 1.36007 13.4826 1.04927 C0 4. Values obtained when using the standard crystal employed here. Note that these values are dependent on the crystal characteristics, and should be considered as reference values. 5. Time averaged rms values, where the noise is white noise and the measurement bandwidth is determined by the crystal filter equivalent used in the standard circuit. NIPPON PRECISION CIRCUITS INC.—5 SM9501A/B 9501B version VDD = 4.5 to 5.5V, VSS = 0V, Ta = −40 to +85°C unless otherwise noted. Rating Parameter Symbol Condition Unit min typ max 4.5 5.0 5.5 Supply voltage VDD Maximum operating current consumption1 IDDM VDD = 5.0V, Ta = 25°C, no input signal, PON: VSS, OUT: OPEN – 65 100 µA Operating current consumption1 IDDT VDD = 5.0V, Ta = 25°C, 500ms pulsewidth, 0.1mVrms input (differential input), PON: VSS, OUT: OPEN – 55 – µA Standby mode current consumption IST PON: VDD or OPEN, FCN: VDD or OPEN, HLDN: VDD or OPEN – – 0.1 µA IN1–IN2 differential input, FIN = 40kHz, 60kHz Ta = 25°C – 0.5 1.0 µVrms VFMIN Maximum input voltage range VFMAX ina ry Minimum input voltage range V IN1–IN2 differential input, FIN = 40kHz, 60kHz 80 – – mVrms Input frequency FIN IN1–IN2 differential input 35 – 80 kHz Analog switch resistance RA VIN2 = 0V, VIN3 = 50mV – – 15 Ω Startup time2 tON When supply is applied – – 8 sec Startup time2 (PON) tPON From standby mode – – 8 sec Gain hold time tHLD ± 3dB change 1 – – sec VIL PON, FCN, HLDN pins – – 0.5 V VIH PON, FCN, HLDN pins 0.8VDD – – V Input voltage VIL = 0V, PON, FCN, HLDN pins – – –3.2 µA VIH = VDD, PON, FCN, HLDN pins – – 0.1 µA LOW-level output current IOL VDD = 4.5V, OUT = 0.5V 10 – – µA HIGH-level output current IOH VDD = 4.5V, OUT = 4.0V –10 – – µA Fall time output propagation delay3 tDN – – 160 ms Rise time output propagation delay3 tUP – – 200 ms LOW-level output pulsewidth4 (200ms) T200 100 200 300 ms LOW-level output pulsewidth4 (500ms) T500 400 500 650 ms LOW-level output pulsewidth4 (800ms) T800 700 800 900 ms Noise rejection ratio5 S/N – – 9 dB lim IIL IIH Input current FIN = 40/60kHz, standard crystal, NPC standard jig VIN = 1µVrms to 80mVrms pre 1. Measured using the standard circuit. 2. The time taken under stable wave input conditions from when power is applied or standby is released, using PON, until stable digital output occurs within ratings. 3. The time taken, with 10:1 input signal amplitude ratio and 500ms pulsewidth, from when a change in signal input occurs until the output OUT changes. Note that this characteristic is very dependent on the antenna and crystal filter characteristics. The standard crystal used here has the following equivalent circuit coefficients. L1 C1 R1 f [kHz] L1 [kH] C1 [fF] R1 [kΩ] C0 [pF] 40 6.70280 2.36228 11.4492 1.42773 60 5.17396 1.36007 13.4826 1.04927 C0 4. Values obtained when using the standard crystal employed here. Note that these values are dependent on the crystal characteristics, and should be considered as reference values. 5. Time averaged rms values, where the noise is white noise and the measurement bandwidth is determined by the crystal filter equivalent used in the standard circuit. NIPPON PRECISION CIRCUITS INC.—6 SM9501A/B STANDARD CIRCUIT 0.1µF + − 50Ω VDDA VDD IN1 PON IN3 OUT ina ry VDD IN2 FCN *1 100kΩ 5.1kΩ 12pF 12pF 40kHz 60kHz VSS HLDN XO CP VSSA CB XI LF 0.22µF 1µF 1µF *1. These values are obtained when using NPC's standard crystal and should be considered as reference values. In case of using differnt crystal, the values are different. lim APPLICATION CIRCUIT ANT. VDD 0.1µF VDDA VDD IN1 PON IN3 OUT IN2 VSS FCN pre *1 100kΩ 5.1kΩ 12pF 12pF 40kHz 60kHz CONTROLLER HLDN XO CP VSSA CB XI LF 0.22µF 1µF 1µF *1. These values are obtained when using NPC's standard crystal and should be considered as reference values. In case of using differnt crystal, the values are different. NIPPON PRECISION CIRCUITS INC.—7 SM9501A/B FUNCTIONAL DESCRIPTION ina ry Antenna Input and Tuning Capacitor Switching Function FCN C1 C2 IN1 IN3 L1 AGC IN2 There are three antenna inputs: IN1, IN2, and IN3. When FCN is open (or HIGH), the internal analog switch is OFF and IN1–IN2 are the antenna inputs (60kHz mode). When FCN is LOW, the analog switch is ON, connecting IN3 and IN2. C2 is then connected in parallel to C1 in the tuning circuit, reducing the resonant frequency (40kHz mode). FCN Analog switch Open or HIGH OFF LOW ON Antenna input Tuning capacitor Receiver frequency Between IN1 and IN2 C1 60kHz Between IN1 and IN2, IN3 C1 + C2 parallel 40kHz lim FCN should be left open if not using the tuning capacitor switching function, and IN2 should be connected to IN3 externally. AGC Amplifier and Gain Hold Function The input voltage from the antenna is amplified by the AGC amplifier. The gain can be monitored by the voltage on pin CP, and can be changed by varying the CP voltage. An external capacitor Cp can be connected to CP to stabilize the voltage, but the gain tracking time is dependent on the capacitance. When HLDN is open (or HIGH), the gain automatically adjusts to follow the post-amplifier detector signal. When HLDN is LOW, the immediately preceding gain is held for an interval determined by the Cp capacitance. Gain tracking pre HLDN Open or HIGH Auto tracking LOW Gain held fixed HLDN CP Peak Hold Detector AGC Amp CB Bottom Hold Detector Cb Cp NIPPON PRECISION CIRCUITS INC.—8 SM9501A/B Crystal Filter Circuit XI XO Rx40 Cx40 40kHz Rx60 60kHz ina ry Cx60 External crystals are used as filters. Multiple frequencies (40kHz and 60kHz) are supported by connecting crystals in parallel. The center frequency and bandwidth of the filters is determined by the crystal characteristics. If the center frequency is lower than the target frequency, C×40 and C×60 can be added to change the resonant frequency. And R×40 and R×60 can be added to adjust the filter Q factor. Internally, pin XO is linked to pin XI by a phase-inverted signal passed through a capacitor, which cancels the high-frequency components that pass through the crystal parallel capacitances. Detector Circuit The amplified signal is full-wave rectified and passed through a lowpass filter detector. The detector output is input to peak hold (pin CP) and bottom hold (pin CB) circuits to form the decoder reference potentials and peak hold potential for AGC control. Peak hold Peak/ Bottom Hold Rectifier LPF VSS potential lim Amplifier VSS potential Bottom hold VSS potential Decoder Circuit The detector output and peak/bottom hold mid-level potential reference are used to decode the time code signal, which is output on pin OUT. The output is active-LOW, so that the output is LOW when the input amplitude is HIGH. LPF waveform pre Rectifier LPF VDD potential Decoder VSS potential OUT output Peak hold Peak/ Bottom Hold VSS potential Mid-level potential Bottom hold VSS potential Standby Function When PON is open (or HIGH), the device is in standby mode and the current consumption is reduced. Receiver operation starts when PON goes LOW. PON Mode OUT Open (or HIGH) Standby HIGH LOW Operating Time code NIPPON PRECISION CIRCUITS INC.—9 pre lim ina ry SM9501A/B Please pay your attention to the following points at time of using the products shown in this document. The products shown in this document (hereinafter “Products”) are not intended to be used for the apparatus that exerts harmful influence on human lives due to the defects, failure or malfunction of the Products. Customers are requested to obtain prior written agreement for such use from NIPPON PRECISION CIRCUITS INC. (hereinafter “NPC”). Customers shall be solely responsible for, and indemnify and hold NPC free and harmless from, any and all claims, damages, losses, expenses or lawsuits, due to such use without such agreement. NPC reserves the right to change the specifications of the Products in order to improve the characteristic or reliability thereof. NPC makes no claim or warranty that the contents described in this document dose not infringe any intellectual property right or other similar right owned by third parties. Therefore, NPC shall not be responsible for such problems, even if the use is in accordance with the descriptions provided in this document. Any descriptions including applications, circuits, and the parameters of the Products in this document are for reference to use the Products, and shall not be guaranteed free from defect, inapplicability to the design for the mass-production products without further testing or modification. Customers are requested not to export or re-export, directly or indirectly, the Products to any country or any entity not in compliance with or in violation of the national export administration laws, treaties, orders and regulations. Customers are requested appropriately take steps to obtain required permissions or approvals from appropriate government agencies. NIPPON PRECISION CIRCUITS INC. 4-3, Fukuzumi 2-chome, Koto-ku, Tokyo 135-8430, Japan Telephone: +81-3-3642-6661 Facsimile: +81-3-3642-6698 http://www.npc.co.jp/ Email: [email protected] NP0304CE 2004.10 NIPPON PRECISION CIRCUITS INC.—10