NTE8542 Integrated Circuit Tri−State Quad I/O Register General Description: The NTE8542 is a 4−bit storage register with two terminals per bit which may be used as either inputs or outputs when tied to two bus lines. Storage capability is obtained with positive edge triggered flip− flops having common clock and asynchronous clear. Each I/O terminal can be forced to a high impedance state (Hi−z state) using the Output Disable controls. Features: D Series 54/74 compatible D Input clamp diodes D Propagation delays . . . . . . . 25ns D Power dissipation . . . . . . 400mW D Operation . . . . . . . . . . . . . 40MHz Absolute Maximum Ratings: (Note 1) Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.0V Input Voltage, Vi . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5V Output Voltage, VO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5V Storage Temperature Range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to +150°C Lead Temperature (Soldering, 10 seconds) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +300°C Recommended Operating Conditions: Parameter Supply Voltage Temperature Symbol Min Max Unit VCC 4.75 5.25 V TA 0 +70 °C Note 1. “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be guaranteed. Except for “Operating Temperature Range” they are not meant to imply that the devices should be operated at these limits. The table of “Electrical Characteristics” provides conditions for actual device operation. Electrical Characteristics: (Notes 2 and 3) Parameter Symbol Test Conditions Logical “1” Input Voltage VIH VCC = Min Logical “1” Input Current IIH Logical “0” Input Voltage Logical “0” Input Current Min Typ Max Unit 2.0 − − V VCC = Max, VIN = 2.4V VCC = Max, VIN = 5.5V − − − − 40 1.0 μA VIL VCC = Min − − 0.8 V IIL VCC = Max, VIN = 0.4V − Input Clamp Voltage VCD VCC = Min, IIN = −12mA − − −1.5 V Logical “1” Output Voltage VOH VCC = Min, IOUT = −800μ 2.4 − − V Output Short Circuit Current IOS VCC = Max, VOUT = 0V, Note 4 −25 − −70 mA Logical “0” Output Voltage VOL VCC = Min, IOUT = 16mA − − 0.4 V Supply Current ICC VCC = Max − − 120 mA VCC = Max, VIN = 2.4V VCC = Max, VIN = 0.4V − − − − 40 −40 μA TRI−STATE I/O Current with Inputs and Outputs Disabled −1.0 −1.6 mA Propagation Delay to a Logical “0” from Clock to Output tpd0 RL = 400Ω, CL = 50pF TA = 25°C − 23 35 ns Propagation Delay to a Logical “0” from Clear to Output tpd0 RL = 400Ω, CL = 50pF TA = 25°C − 24 36 ns Propagation Delay to a Logical “1” from Clock to Output tpd1 RL = 400Ω, CL = 50pF TA = 25°C − 25 38 ns Delay from Disable to High Impedance State (from Logical “1” Level) t1H RL = 400Ω, CL = 5.0pF TA = 25°C − 6.0 15 ns Delay from Disable to High Impedance State (from Logical “0” Level) t0H RL = 400Ω, CL = 5.0pF TA = 25°C − 15 25 ns Delay from Disable to Logical “1” Level (from High Impedance State) tH1 RL = 400Ω, CL = 50pF TA = 25°C − 20 30 ns Delay from Disable to Logical “0” Level (from High Impedance State) tH0 RL = 400Ω, CL = 50pF TA = 25°C − 17 25 ns Maximum Clock Frequency fMAX RL = 400Ω, CL = 50pF TA = 25°C 30 40 − MHz Enable to Clock Set−Up Time tSO RL = 400Ω, CL = 50pF TA = 25°C 20 13 − ns Enable to Clock Set−Up Time tSI RL = 400Ω, CL = 50pF TA = 25°C 20 12 − ns Electrical Characteristics (Cont’d): (Notes 2 and 3) Symbol Parameter Test Conditions Min Typ Max Unit Date to Clock Set−Up Time tSO RL = 400Ω, CL = 50pF TA = 25°C 10 4.5 − ns Date to Clock Set−Up Time tSI RL = 400Ω, CL = 50pF TA = 25°C 5.0 −4.0 − ns Data to Clock Hold Time tHO RL = 400Ω, CL = 50pF TA = 25° 10 4.5 − ns Data to Clock Hold Time tHI RL = 400Ω, CL = 50pF TA = 25°C 5.0 −3.5 − ns Minimum Clock Pulse Width PWMIN RL = 400Ω, CL = 50pF TA = 25°C 20 − − ns Minimum Clear Pulse Width PWMIN RL = 400Ω, CL = 50pF TA = 25°C 20 − − ns Note 2. Unless otherwise specified min/max limits apply across the 0°C to +70°C range for the NTE8542. All typicals are given for VCC = 5.0V and TA = 25°C. Note 3. All currents into device pins shown as positive, out of device pins as negative, all voltages referenced to GND unless otherwise noted. All values shown as max or min on absolute value basis. MODE OF OPERATION: CLEAR DIS1 DIS2 E1 E2 A1 − 4 B1 − 4 0 0 1 1 1 Q Hi−z Output Data to Bus A 0 1 0 1 1 Hi−z Q Output Data to Bus B 0 0 0 1 1 Q Q Output Data to Both Buses 0 1 1 1 1 Hi−z Hi−z Store Data With Outputs in Hi−z State 0 X X 0 1 Data QN Enter Data From Bus A 0 X X 1 0 QN Data Enter Data From Bus B 0 X X 0 0 Data Data Enter Data From Both Buses (Logic “1” on Either Will Dominate) 1 X X X X X X X = Don’t Care State QN = Data After Clock Transition Comments Clear Pin Connection Diagram DIS2 1 16 VCC A1 2 15 DIS1 B1 3 14 A4 B2 4 13 B4 A2 5 12 B3 E2 6 11 A3 E1 7 10 Clock GND 8 9 16 9 1 8 Clear .260 (6.6) Max .870 (22.0) Max .200 (5.08) Max .100 (2.54) .700 (17.78) .099 (2.5) Min