SCLS467B − FEBRUARY 2003 − REVISED MAY 2004
D Qualification in Accordance With
PW PACKAGE
(TOP VIEW)
AEC-Q100†
D Qualified for Automotive Applications
D Customer-Specific Configuration Control
D
D
D
D
D
D
D
D
D
D
1A
1B
1CLR
1Q
2Q
2Cext
2Rext/Cext
GND
Can Be Supported Along With
Major-Change Approval
Typical VOLP (Output Ground Bounce)
<0.8 V at VCC = 3.3 V, TA = 25°C
Typical VOHV (Output VOH Undershoot)
>2.3 V at VCC = 3.3 V, TA = 25°C
Supports Mixed-Mode Voltage Operation on
All Ports
Schmitt-Trigger Circuitry on A, B, and CLR
Inputs for Slow Input Transition Rates
Edge Triggered From Active-High or
Active-Low Gated Logic Inputs
Ioff Supports Partial-Power-Down Mode
Operation
Retriggerable for Very Long Output Pulses,
Up To 100% Duty Cycle
Overriding Clear Terminates Output Pulse
Glitch-Free Power-Up Reset on Outputs
ESD Protection Exceeds JESD 22
− 2000-V Human-Body Model (A114-A)
− 200-V Machine Model (A115-A)
− 1000-V Charged-Device Model (C101)
1
16
2
15
3
14
4
13
5
12
6
11
7
10
8
9
VCC
1Rext/Cext
1Cext
1Q
2Q
2CLR
2B
2A
† Contact factory for details. Q100 qualification data available on
request.
description/ordering information
The SN74LV123A is a dual retriggerable monostable multivibrator designed for 2-V to 5.5-V VCC operation.
This edge-triggered multivibrator features output pulse-duration control by three methods. In the first method,
the A input is low, and the B input goes high. In the second method, the B input is high, and the A input goes
low. In the third method, the A input is low, the B input is high, and the clear (CLR) input goes high.
The output pulse duration is programmable by selecting external resistance and capacitance values. The
external timing capacitor must be connected between Cext and Rext/Cext (positive) and an external resistor
connected between Rext/Cext and VCC. To obtain variable pulse durations, connect an external variable
resistance between Rext/Cext and VCC. The output pulse duration also can be reduced by taking CLR low.
ORDERING INFORMATION
TA
PACKAGE‡
ORDERABLE
PART NUMBER
TOP-SIDE
MARKING
−40°C to 105°C
TSSOP − PW
Tape and reel SN74LV123ATPWRQ1 L123ATQ
‡ Package drawings, standard packing quantities, thermal data, symbolization, and PCB design
guidelines are available at www.ti.com/sc/package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright 2004, Texas Instruments Incorporated
!"# $ %&'# "$ (&)*%"# +"#',
+&%#$ %! # $('%%"#$ (' #-' #'!$ '."$ $#&!'#$
$#"+"+ /""#0, +&%# (%'$$1 +'$ # '%'$$"*0 %*&+'
#'$#1 "** (""!'#'$,
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1
SCLS467B − FEBRUARY 2003 − REVISED MAY 2004
description/ordering information (continued)
Pulse triggering occurs at a particular voltage level and is not directly related to the transition time of the input
pulse. The A, B, and CLR inputs have Schmitt triggers with sufficient hysteresis to handle slow input transition
rates with jitter-free triggering at the outputs.
Once triggered, the basic pulse duration can be extended by retriggering the gated low-level-active (A) or
high-level-active (B) input. Pulse duration can be reduced by taking CLR low. The input/output timing diagram
illustrates pulse control by retriggering the inputs and early clearing.
During power up, Q outputs are in the low state, and Q outputs are in the high state. The outputs are glitch free,
without applying a reset pulse.
This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs,
preventing damaging current backflow through the device when it is powered down.
FUNCTION TABLE
(each multivibrator)
INPUTS
OUTPUTS
CLR
A
B
Q
Q
L
X
X
X
H
X
L
L†
H
H†
X
X
L
L†
H†
H
L
↑
H
↓
H
↑
L
H
† These outputs are based on the
assumption
that
the
indicated
steady-state conditions at the A and
B inputs have been set up long enough to
complete any pulse started before the
setup.
logic diagram, each multivibrator (positive logic)
Rext/Cext
A
Cext
B
Q
CLR
2
R
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Q
SCLS467B − FEBRUARY 2003 − REVISED MAY 2004
input/output timing diagram
trr
A
B
CLR
Rext/Cext
Q
Q
tw
tw
tw + trr
absolute maximum ratings over operating free-air temperature (unless otherwise noted)†
Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V
Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V
Voltage range applied to any output in the high-impedance
or power-off state, VO (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V
Output voltage range in high or low state, VO (see Notes 1 and 2) . . . . . . . . . . . . . . . . . −0.5 V to VCC + 0.5 V
Output voltage range in power-off state, VO (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V
Input clamp current, IIK (VI < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −20 mA
Output clamp current, IOK (VO < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −50 mA
Continuous output current, IO (VO = 0 to VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±25 mA
Continuous current through VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA
Package thermal impedance, θJA (see Note 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113°C/W
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output current ratings are observed.
2. This value is limited to 5.5 V maximum.
3. The package thermal impedance is calculated in accordance with JESD 51-7.
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3
SCLS467B − FEBRUARY 2003 − REVISED MAY 2004
recommended operating conditions (see Note 4)
VCC
VIH
VIL
VI
VO
IOH
IOL
Supply voltage
VCC = 2 V
VCC = 2.3 V to 2.7 V
High-level input voltage
VCC = 3 V to 3.6 V
VCC = 4.5 V to 5.5 V
MIN
MAX
2
5.5
VCC × 0.7
VCC × 0.7
0.5
VCC × 0.3
VCC × 0.3
Input voltage
0
Output voltage
0
VCC = 2 V
VCC = 2.3 V to 2.7 V
External timing resistance
Cext
External timing capacitance
∆t/∆VCC
TA
Power-up ramp rate
VCC × 0.3
5.5
VCC
−50
−6
50
V
µA
mA
µA
2
VCC = 3 V to 3.6 V
VCC = 4.5 V to 5.5 V
6
mA
12
5
kΩ
1
No restriction
1
Operating free-air temperature
V
−12
VCC = 2 V
VCC = 2.3 V to 2.7 V
VCC = 2 V
VCC ≥ 3 V
V
−2
VCC = 3 V to 3.6 V
VCC = 4.5 V to 5.5 V
Low-level output current
Rext
V
VCC × 0.7
VCC = 3 V to 3.6 V
VCC = 4.5 V to 5.5 V
High-level output current
V
1.5
VCC = 2 V
VCC = 2.3 V to 2.7 V
Low-level input voltage
UNIT
−40
pF
ms/V
105
°C
NOTE 4: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
4
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SCLS467B − FEBRUARY 2003 − REVISED MAY 2004
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
IOH = −50 µA
IOH = −2 mA
VOH
2 V to 5.5 V
IOH = −6 mA
IOH = −12 mA
IOL = 50 µA
IOL = 2 mA
VOL
MIN
VCC
2.3 V
VCC−0.1
2
3V
2.48
4.5 V
3.8
TYP
0.1
2.3 V
0.4
3V
0.44
4.5 V
0.55
±2.5
Rext/Cext†
VI = 5.5 V or GND
2 V to 5.5 V
A, B, and CLR
VI = 5.5 V or GND
0 to 5.5 V
±1
ICC
Quiescent
VI = VCC or GND,
5.5 V
20
ICC
Active state
(per circuit)
VI = VCC or GND,
Rext/Cext = 0.5 VCC
II
±1
0
Ioff
IO = 0
3V
280
4.5 V
650
5.5 V
975
VI or VO = 0 to 5.5 V
Ci
0
VI = VCC or GND
UNIT
V
2 V to 5.5 V
IOL = 6 mA
IOL = 12 mA
MAX
5
3.3 V
1.9
5V
1.9
V
µA
µA
µA
µA
pF
† This test is performed with the terminal in the off-state condition.
timing requirements over recommended operating free-air temperature range, VCC = 3.3 V ± 0.3 V
(unless otherwise noted) (see Figure 1)
TEST CONDITIONS
tw
Pulse
duration
trr
Pulse retrigger time
MIN
TA = 25°C
TYP
MAX
MIN
CLR
5
5
A or B trigger
Cext = 100 pF
5
‡
76
5
‡
Cext = 0.01 µF
‡
1.8
‡
Rext = 1 kΩ
MAX
UNIT
ns
ns
µs
‡ See retriggering data in the application information section.
timing requirements over recommended operating free-air temperature range, VCC = 5 V ± 0.5 V
(unless otherwise noted) (see Figure 1)
TEST CONDITIONS
tw
Pulse
duration
trr
Pulse retrigger time
TA = 25°C
MIN
TYP
MAX
MIN
CLR
5
5
A or B trigger
Cext = 100 pF
5
‡
59
5
‡
Cext = 0.01 µF
‡
1.5
‡
Rext = 1 kΩ
MAX
UNIT
ns
ns
µs
‡ See retriggering data in the application information section.
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5
SCLS467B − FEBRUARY 2003 − REVISED MAY 2004
switching characteristics over recommended operating
VCC = 3.3 V ± 0.3 V (unless otherwise noted) (see Figure 1)
PARAMETER
tpd
FROM
(INPUT)
TO
(OUTPUT)
A or B
Q or Q
CLR
Q or Q
CLR trigger
Q or Q
tw†
Q or Q
TEST
CONDITIONS
free-air
MIN
TA = 25°C
TYP
MAX
CL = 50 pF,
Cext = 0.1 µF,
Rext = 10 kΩ
1
27.5
10.5
19.3
1
22
12.3
25.9
1
29.5
182
240
90
100
110
0.9
1
1.1
tpd
TO
(OUTPUT)
A or B
Q or Q
CLR
Q or Q
CLR trigger
Q or Q
tw†
Q or Q
TEST
CONDITIONS
CL = 50 pF,
Cext = 28 pF,
Rext = 2 kΩ
CL = 50 pF,
Cext = 0.01 µF,
Rext = 10 kΩ
CL = 50 pF,
Cext = 0.1 µF,
Rext = 10 kΩ
90
110
µs
0.9
1.1
ms
MIN
MAX
8.3
14
1
16
7.4
11.4
1
13
8.7
14.9
1
17
167
200
90
100
110
0.9
1
1.1
∆tw‡
† tw = Duration of pulse at Q and Q outputs
‡ ∆tw = Output pulse-duration variation (Q and Q) between circuits in same package
ns
ns
temperature
TA = 25°C
TYP
MAX
CL = 50 pF
UNIT
%
free-air
MIN
range,
300
±1
switching characteristics over recommended operating
VCC = 5 V ± 0.5 V (unless otherwise noted) (see Figure 1)
FROM
(INPUT)
MAX
24.1
∆tw‡
CL = 50 pF
† tw = Duration of pulse at Q and Q outputs
‡ ∆tw = Output pulse-duration variation (Q and Q) between circuits in same package
PARAMETER
MIN
11.8
CL = 50 pF
CL = 50 pF,
Cext = 28 pF,
Rext = 2 kΩ
CL = 50 pF,
Cext = 0.01 µF,
Rext = 10 kΩ
temperature
range,
UNIT
ns
240
ns
90
110
µs
0.9
1.1
ms
±1
%
operating characteristics, TA = 25°C
PARAMETER
Cpd
6
Power dissipation capacitance
TEST CONDITIONS
CL = 50 pF,
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f = 10 MHz
VCC
3.3 V
TYP
5V
49
UNIT
44
pF
SCLS467B − FEBRUARY 2003 − REVISED MAY 2004
PARAMETER MEASUREMENT INFORMATION
From Output
Under Test
Test
Point
tw
CL
(see Note A)
VCC
Inputs or
Outputs
50% VCC
50% VCC
0V
LOAD CIRCUIT
VOLTAGE WAVEFORMS
PULSE DURATION
VCC
Input A
(see Note B)
50% VCC
0V
VCC
Input B
(see Note B)
50% VCC
50% VCC
0V
50% VCC
VOH
In-Phase
Output
50% VCC
In-Phase
Output
VOL
VOH
VOL
50% VCC
Out-of-Phase
Output
VOH
50% VCC
VOL
tPLH
tPHL
tPHL
50% VCC
tPHL
tPLH
0V
tPLH
Out-of-Phase
Output
VCC
Input CLR
(see Note B)
50% VCC
VOH
50% VCC
VOL
VOLTAGE WAVEFORMS
DELAY TIMES
VOLTAGE WAVEFORMS
DELAY TIMES
NOTES: A. CL includes probe and jig capacitance.
B. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tr + 3 ns, tf + 3 ns.
C. The outputs are measured one at a time, with one input transition per measurement.
Figure 1. Load Circuit and Voltage Waveforms
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7
SCLS467B − FEBRUARY 2003 − REVISED MAY 2004
APPLICATION INFORMATION†
OUTPUT PULSE DURATION
vs
EXTERNAL TIMING CAPACITANCE
1.00E+07
VCC = 3 V
TA = 25°C
1.00E+06
t w − Output Pulse Duration − ns
t w − Output Pulse Duration − ns
1.00E+07
OUTPUT PULSE DURATION
vs
EXTERNAL TIMING CAPACITANCE
RT = 1 MΩ
1.00E+05
RT = 100 kΩ
1.00E+04
RT = 10 kΩ
1.00E+03
1.00E+06
RT = 1 MΩ
1.00E+05
RT = 100 kΩ
1.00E+04
RT = 10 kΩ
1.00E+03
RT = 1 kΩ
1.00E+02
101
VCC = 4.5 V
TA = 25°C
RT = 1 kΩ
102
103
104
1.00E+02
101
105
Figure 2
1.20
Output Pulse Duration Constant − K
t rr − Minimum Retrigger Time − µs
RT = 1 kΩ
TA = 25°C
CT = 0.01 µF
1.00
CT = 1000 pF
0.10
CT = 100 pF
0.01
3
105
OUTPUT PULSE-DURATION CONSTANT
vs
SUPPLY VOLTAGE
10.00
2
104
Figure 3
MINIMUM TRIGGER TIME
vs
VCC CHARACTERISTICS
1
103
CT − External Timing Capacitance − pF
CT − External Timing Capacitance − pF
0
102
4
5
6
1.15
RT = 10 kΩ
TA = 25°C
tw = K × C T × R T
1.10
CT = 1000 pF
1.05
CT = 0.01 µF
1.00
CT = 1 µF, CT = 0.1 µF
0.95
0.90
1.5
2
VCC − Supply Voltage − V
2.5
3
3.5
4
4.5 5
VCC − Supply Voltage − V
5.5
6
Figure 5
Figure 4
† Operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied.
8
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MECHANICAL DATA
MTSS001C – JANUARY 1995 – REVISED FEBRUARY 1999
PW (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
14 PINS SHOWN
0,30
0,19
0,65
14
0,10 M
8
0,15 NOM
4,50
4,30
6,60
6,20
Gage Plane
0,25
1
7
0°– 8°
A
0,75
0,50
Seating Plane
0,15
0,05
1,20 MAX
PINS **
0,10
8
14
16
20
24
28
A MAX
3,10
5,10
5,10
6,60
7,90
9,80
A MIN
2,90
4,90
4,90
6,40
7,70
9,60
DIM
4040064/F 01/97
NOTES: A.
B.
C.
D.
All linear dimensions are in millimeters.
This drawing is subject to change without notice.
Body dimensions do not include mold flash or protrusion not to exceed 0,15.
Falls within JEDEC MO-153
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