VISHAY SUR50N024-06P

SPICE Device Model SUR50N024-06P
Vishay Siliconix
N-Channel 20-V (D-S) 175° MOSFET
CHARACTERISTICS
• N-Channel Vertical DMOS
• Macro Model (Subcircuit Model)
• Level 3 MOS
• Apply for both Linear and Switching Application
• Accurate over the −55 to 125°C Temperature Range
• Model the Gate Charge, Transient, and Diode Reverse Recovery
Characteristics
DESCRIPTION
The attached spice model describes the typical electrical
characteristics of the n-channel vertical DMOS. The subcircuit
model is extracted and optimized over the −55 to 125°C
temperature ranges under the pulsed 0-V to 10-V gate drive. The
saturated output impedance is best fit at the gate bias near the
threshold voltage.
A novel gate-to-drain feedback capacitance network is used to model
the gate charge characteristics while avoiding convergence difficulties
of the switched Cgd model. All model parameter values are optimized
to provide a best fit to the measured electrical data and are not
intended as an exact physical interpretation of the device.
SUBCIRCUIT MODEL SCHEMATIC
This document is intended as a SPICE modeling guideline and does not constitute a commercial product data sheet. Designers should refer to the appropriate
data sheet of the same number for guaranteed specification limits.
Document Number: 73019
S-60245Rev. B, 20-Feb-06
www.vishay.com
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SPICE Device Model SUR50N024-06P
Vishay Siliconix
SPECIFICATIONS (TJ = 25°C UNLESS OTHERWISE NOTED)
Parameter
Symbol
Test Condition
Simulated
Data
Measured
Data
VGS(th)
VDS = VGS, ID = 250 µA
1.4
ID(on)
VDS = 5 V, VGS = 10 V
964
VGS = 10 V, ID = 20 A
0.0041
VGS = 10 V, ID = 20 A, TJ = 125°C
0.0057
VGS = 4.5 V, ID = 20 A
0.0065
0.0073
IS = 50 A, VGS = 0 V
0.91
1.2
2418
2550
816
900
Unit
Static
Gate Threshold Voltage
On-State Drain Current
a
Drain-Source On-State Resistancea
Forward Voltagea
rDS(on)
VSD
V
A
0.0046
Ω
V
b
Dynamic
Input Capacitance
Ciss
VGS = 0 V, VDS = 10 V, f = 1 MHz
Output Capacitance
Coss
Reverse Transfer Capacitance
Crss
348
415
Total Gate Chargec
Qg
20
19
c
VDS = 10 V, VGS = 4.5 V, ID = 50 A
Gate-Source Charge
Qgs
7.5
7.5
Gate-Drain Chargec
Qgd
6
6
Turn-On Delay Timec
td(on)
11
11
10
10
9
24
9
9
31
35
c
tr
Turn-Off Delay Timec
td(off)
Rise Time
Fall Timec
tf
Source-Drain Reverse Recovery Time
trr
VDD = 10 V, RL = 0.20 Ω
ID ≅ 50 A, VGEN = 10 V, RG = 2.5 Ω
IF = 50 A, di/dt = 100 A/µs
pF
nC
ns
Notes
a. Pulse test; pulse width ≤ 300 µs, duty cycle ≤ 2%.
b. Guaranteed by design, not subject to production testing.
c. Independent of operating temperature.
www.vishay.com
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Document Number: 73019
S-60245Rev. B, 20-Feb-06
SPICE Device Model SUR50N024-06P
Vishay Siliconix
COMPARISON OF MODEL WITH MEASURED DATA (TJ=25°C UNLESS OTHERWISE NOTED)
Document Number: 73019
S-60245Rev. B, 20-Feb-06
www.vishay.com
3