LX1752 ® TM Dual Interleaving PWM Controller P RODUCTION D ATA S HEET The LX1752 is a dual output synchronous buck controller using voltage mode PWM architecture. The single input voltage supply feature simplifies the design and offers a wide range of operation from 4.5 to 22 volts. Each PWM has a Soft-Start pin for programming the output sequencing and serves as the shutdown control. Current limit threshold is set with a single external resistor and protects the high-side and low-side MOSFETs by sensing the voltage drop generated from RDSON. Each PWM channel has its own external feedback compensation for performance optimization. Internal gate drive circuitry provides 5V for the external upper and lower N channel MOSFETS. Output voltages as low as 700mV, load currents up to 15A per phase and efficiency of 93% can be achieved with the flexible controller. Operating alone or with other LX1752’s on a bus, three multi-phase interleaving options are available: two PWM channels with 180° separation; three PWM channels at 120° or four PWM channels at 90°. This phasing is set by the tri-state input pin PSET. This architecture minimizes the input capacitor requirements. The entire power supply design occupies a small footprint with the LX1752’s low profile 28 pin, MLP package of 4x5x1mm (JEDEC MO-220). Dual PWM Controller, Synchronous Operation Voltage Mode PWM with External Compensation Single Input Supply, wide range 4.5V to 22V Precision Reference Outputs as low as 700mV Selectable PWM Frequency up to 1.5Mhz Synchronization Pin for PWM Frequency Independent and Programmable Soft Start/Enable for Power Sequencing Integrated High Current MOSFET Drivers Programmable Current Limit Lossless Current Sensing for Current Limit and Short Circuit Protection Pb-free, RoHS Compliant WWW . Microsemi .C OM KEY FEATURES GENERAL DESCRIPTION APPLICATIONS IMPORTANT: For the most current data, consult MICROSEMI’s website: http://www.microsemi.com Multi-Output Power Supplies Video Card Power Supplies PC Peripherals Set Top Boxes Point of Load DC-DC Converters PACKAGE ORDER INFO PRODUCT HIGHLIGHT VIN 4.5V to 22V TA (°C) LQ Plastic MLPQ 28 pin RoHS Compliant / Pb-free VSX VIN HOX VCCL VCX PSET HRX SSENX 0 to 85 LX1752 Part Note: Available in Tape & Reel. Append the letters “TR” to the part number. (i.e. LX1752CLQ-TR) CSX LX1752 AGND VOUT LX1752CLQ LOX SYNC SYNC PGX SHDN SHDNX RFREQ EAXEAOX ONE OF 2 PWM SECTIONS Copyright © 2007 Rev. 1.0, 2008-07-31 Microsemi Analog Mixed Signal Group 11861 Western Avenue, Garden Grove, CA. 92841, 714-898-8121, Fax: 714-893-2570 Page 1 LX1752 ® TM Dual Interleaving PWM Controller P RODUCTION D ATA S HEET PACKAGE PIN OUT E01 EA1SSEN1 RFREQ PSET VREF GND SYNC SHDN2 SSEN2 EA2EO2 VIN CS2 1 28 27 26 25 24 23 22 2 21 3 20 4 19 5 18 6 17 7 16 8 15 9 10 11 12 13 14 SHDN1 CS1 VS1 VC1 H01 HR1 L01 PGND L02 VCCL HR2 H02 VC2 VS2 Supply Input Voltage(VIN) .............................................................. -0.3V to 22V Supply Voltage (VCCL) .................................................................. -0.3V to 6.0V Topside Driver Supply Input Voltage (VCX) .................................... -0.3V to 28V Topside Current Sense Input (VSx) .................................................. -0.3V to 28V Current Sense Input (CSX) .................................. -0.3V(-2.0V for ≤ 50ns), to 28V Topside Driver Return Input Voltage (VHRX).... -0.3V(-2.0V for ≤ 50ns), to 28V Error Amplifier Inputs (EAX-) ........................................................ -0.3V to 5.5V Logic Inputs (SYNC, PSET, SHDNX) .............................................-0.3 to VCCL Differential Voltage: VHOX-VHRX (High Side Return)......................... -0.3V to 6V Soft Start Input (SSENX)..................................................................-0.3V to VREF Maximum LDO Output Current (VCCL) ...................................................100mA Maximum Operating Junction Temperature ................................................ 150°C Operating Temperature ....................................................................-20°C to 85°C Storage Temperature Range...........................................................-65°C to 150°C Peak Package Solder Reflow Temp (40 seconds max exposure).... 260°C (+0, -5) WWW . Microsemi .C OM ABSOLUTE MAXIMUM RATINGS LQ PACKAGE (Top View) Note: Exceeding these ratings could cause damage to the device. All voltages are with respect to Ground. Currents are positive into, negative out of specified terminal. x denotes respective pin designator (1 or 2). MSC 1752 XXXX THERMAL DATA LQ Plastic MLPQ 28-Pin THERMAL RESISTANCE-JUNCTION TO AMBIENT, θJA 27°C/W Junction Temperature Calculation: TJ = TA + (PD x θJA). The θJA numbers are guidelines for the thermal performance of the device/pc-board system. All of the above assume no ambient airflow. LQ PACKAGE MARKINGS “xxxx” Denote Date Code and Lot Identification RoHS / Pb-free 100% matte Tin Pin Finish FUNCTIONAL PIN DESCRIPTION Pin Description GND 1 Analog Ground. Connect this pin to a local analog ground plane. All low level signals are referenced to this ground and should return to this pin. SYNC 2 SYNC Control Line used on the multi-channel bus. Wire OR’d negative going pulse with a common pull-up resistor. SHDNX 3, 22 The Shutdown pin is an I/O pin which connects to an internal open drain transistor and an external pull up resistor. During a fault, this pin will be low during the discharge portion of hiccup mode, and high during the recovery (soft start) portion of hiccup mode.. Used primarily for test purposes. May be used as a system level fault monitor. Each SHDN pin requires a pull-up resistor of 500Ω to 4.7K tied to VCCL. SSENX 4, 25 Soft Start Enable input. Connect a capacitor from SSENx to GND to set the soft-start time, the rise time of the output voltage during start up. If grounded the PWM is disabled. EAX - 5, 24 Error Amplifier Inverting Input for the corresponding PWM channel denoted by “X”. Connect to the output via external network to regulate the output voltage. EOX 6, 23 Error Amplifier Output – Connect to external loop compensation network for the corresponding PWM channel denoted by “X” to provide an error signal to the internal PWM comparator for duty cycle control. VIN 7 Copyright © 2007 Rev. 1.0, 2008-07-31 Controller Supply Voltage. This is the input to the internal 5V LDO. Microsemi Analog Mixed Signal Group 11861 Western Avenue, Garden Grove, CA. 92841, 714-898-8121, Fax: 714-893-2570 Page 2 LX1752 Name LX1752 ® TM Dual Interleaving PWM Controller P RODUCTION D ATA S HEET FUNCTIONAL PIN DESCRIPTION 8, 21 VSX 9, 20 Voltage reference for high side current sense. “X” denotes corresponding phase. Connect this pin directly to the high-side MOSFET’s drain. VCX 10, 19 PWM channel High-Side MOSFET Gate Driver Supply. Connect to the flying capacitor bootstrap supply to ensure proper high-side gate driver supply voltage. “X” denotes the corresponding PWM channel. HOX 11, 18 High Side MOSFET Gate Driver – “X” denotes corresponding PWM channel. HRX 12, 17 High Side driver return, connect this pin to the High Side MOSFET source. “X” denotes the corresponding PWM channel. VCCL 13 LOX 14, 16 WWW . Microsemi .C OM CSX Over-Current Limit Set – connecting a resistor between CSX pin and the junction of the drain of the low-side NMOSFET and the Source of the high-side MOSFET sets the current limit threshold for the corresponding PWM channel denoted by “X”. A minimum of 200 ohms must be in series with this input. Whenever the current limit threshold is reached for 4 consecutive clock cycles the shutdown latch is set and the Soft Start capacitor is discharged through an internal resistor initiating Shutdown and then a Soft Start to generate a hiccup mode current limit. Output of the +5V LDO regulator. Supplies the internal circuit and the external MOSFETs gate drivers. For 4.5V < VIN < 5.5V, this pin is connected externally to VIN. For VIN > 6V this pin supplies +5V to the internal circuit and the external MOSFETs gate drivers Connect a minimum of 4.7µF ceramic capacitor from this pin to GND. Low Side MOSFET Gate Driver – “X” denotes corresponding PWM channel. PGND 15 Power ground pin for the low-side MOSFET drivers. Connect low-side MOSFETs’ source directly to this pin, which connects to power ground plane RFREQ 26 The resistor value from this pin to GND sets the PWM frequency. PSET 27 A Tri-State logic level input that selects the phase position of the two PWM channels from the SYNC pulse. A logic low, GND, will set the PWM phases at 0 and 180 degrees. An open pin, Tri-State, will set the PWM phases at 90 and 270 degrees. A logic high, VCCL, will set the PWM phases at 120 and 240 degrees. VREF 28 An internally generated voltage reference of 0.8V that is buffered and brought out on this pin. If used, connect a 470pF ceramic capacitor to GND. Note: X Denotes the PWM Channel: 1 or 2 LX1752 Copyright © 2007 Rev. 1.0, 2008-07-31 Microsemi Analog Mixed Signal Group 11861 Western Avenue, Garden Grove, CA. 92841, 714-898-8121, Fax: 714-893-2570 Page 3 LX1752 ® TM Dual Interleaving PWM Controller P RODUCTION D ATA S HEET ELECTRICAL CHARACTERISTICS Parameter ` Symbol Test Conditions VIN Connect VCCL to VIN externally Operation Current Feedback Voltage IVIN EAx- High Side Minimum Pulse Width (NOTE 3, NOTE 5) PWMIN Maximum Duty Cycle PWMDC ` Buffered Reference Voltage ERROR AMPLIFIER ` DC Open Loop Gain, Unity gain bandwidth (NOTE 2) High Output Voltage Low Output Voltage Input Common Mode Range Input Bias Current CURRENT SENSE ` LX1752 Typ Max Units IC ELECTRICAL CHARACTERISTICS Input Voltage ` Min VREF AVUGBW VOH VOL No Switching Initial Accuracy; TA = 25°C 4.5V ≤ VIN ≤ 22V Switching Frequency = 800kHz to1.5Mhz Measured between 1.5V rise to 1.5V fall of HOX – HRX. Measured between HOX-HRX 1.5V rise to HOXHRX 1.5V fall. 0mA ≤ IVREF ≤ 1.0mA 6.0 4.5 0.691 0.689 22 5.5 6 0.700 80 88 92 0.784 0.800 I Source = 2mA I Sink = 100µA ISET CS Trip Threshold Offset CS Delay (Blanking) VTRIP TCSD OUTPUT DRIVERS – N Channel MOSFETS Drive Rise and Fall Time TR/F Dead Time – High Side to Low Side TDEAD or Low Side to High Side VCSx to VHRX = 0.2V; VPGND = 0V, Vcx to Vhrx = 5.0V Referenced to VCSX, VPGND = 0V (NOTE 5) ns 0.816 V 100 1.0 30 dB MHz V mV V nA 3.5 IIN mA V % 70 10 0.2 CS Bias Current (Source) 0.709 0.711 V 44 50 57 µA -20 0 150 20 mV ns CL = 1000pF measured between 1.5V crossings of HOX-HRX and LOX. 40 40 ns ns HOX_RDSON IHOX = 100mA (NOTE 5) IHOX = -100mA 4.8 3.3 Ohm Low Side Driver RDSON Drive High Drive Low LOX_RDSON ILOX = 100mA ILOX = -100mA 4.4 3.3 Ohm 1.6 220 MHz kHz VPP % Copyright © 2007 Rev. 1.0, 2008-07-31 FMAX FMIN VRAMP RFREQ = 19.1kΩ RFREQ = 178kΩ 1.4 180 4.5V ≤ VIN ≤22V Microsemi Analog Mixed Signal Group 11861 Western Avenue, Garden Grove, CA. 92841, 714-898-8121, Fax: 714-893-2570 1.5 200 1.2 ±5 LX1752 High Side Driver RDSON Drive High Drive Low SYNC-FREQUENCY GENERATOR Maximum Clock Frequency Minimum Clock Frequency Ramp Amplitude Frequency Stability WWW . Microsemi .C OM Unless otherwise specified, the following specifications apply over the operating ambient temperature 0°C ≤ TA ≤ 85°C except where otherwise noted and the following test conditions: VIN = 12V, VCX = 17V, HOX = 1000pF load to HRX, LOX =1000pF load to GND, VHRX = 12V, (f = 800kHz). Page 4 LX1752 ® TM Dual Interleaving PWM Controller P RODUCTION D ATA S HEET ELECTRICAL CHARACTERISTICS (CONTINUED) Parameter ` Symbol UVLO AND SOFT-START (SS) Start-Up Threshold (VCCL) Hysteresis (NOTE 2) SS Input Resistance SS Shutdown Threshold VCCL Rising ` ` ` ` VCCL LX1752 Typ 3.75 Internal + External Load: 0mA < IVCCL < 100mA; 6V < VIN<22V. PSET TRI-STATE INPUT Logic Level Low Threshold PSET Percentage of VCCL (NOTE 4) Logic Level Open Threshold Percentage of VCCL (NOTE 4) Logic Level High Threshold Percentage of VCCL (NOTE 4) LOGIC INPUT / OUTPUT – OPEN DRAIN EXTERNAL PULL UP RESISTOR Threshold Logic Low External Pull-up Resistance = 500 ohms to SYNC VCCL Sync Bus Input Pulse Width measured at 50% of VCCL; Fall time < 5ns, Rise time < 20ns Shutdown SHDN Threshold Logic Low; Falling Edge SWITCHING REGULATORS Phase to Phase Position PSET = VCCL; Measured HO1 to HO2 PSET = Open; Measured HO1 to HO2 PSET = GND; Measured HO1 to HO2 Thermal Shutdown Rising temperature; Hiccup Mode Operation at Die Temperature TSD Limit Rising temperature; Hiccup Mode Operation at Die Temperature Hysteresis TSD Limit Max Units 4.35 V 130 V kΩ mV 0.30 20 85 CSS = 0.1uF; VOUT rise time from 0V to 90% of output voltage set by feedback (NOTE 2) CSS = 0.1µF; 100% * On time/Off time + On time Hiccup Mode Duty Cycle INTERNAL LDO REGULATOR Regulated Output Min 0.2 RSS VSHDN Soft Start Time ` Test Conditions 4.30 ms 4 % 4.5 5.5 V 22 60 % % % 40 84 50 1.0 1.5 V 30 100 ns 0.8 1.5 V 80 140 160 102 165 180 120 190 210 WWW . Microsemi .C OM Unless otherwise specified, the following specifications apply over the operating ambient temperature 0°C ≤ TA ≤ 85°C except where otherwise noted and the following test conditions: VIN = 12V, VCX = 17V, HOX = 1000pF load to HRX, LOX =1000pF load to GND, VHRX = 12V, (f = 800kHz). Degrees Degrees Degrees 165 °C 10 °C LX1752 Copyright © 2007 Rev. 1.0, 2008-07-31 Microsemi Analog Mixed Signal Group 11861 Western Avenue, Garden Grove, CA. 92841, 714-898-8121, Fax: 714-893-2570 Page 5 LX1752 ® TM Dual Interleaving PWM Controller P RODUCTION D ATA S HEET Unless otherwise specified, the following specifications apply over the operating ambient temperature 0°C ≤ TA ≤ 85°C except where otherwise noted and the following test conditions: VIN = 12V; f = 800kHz; tested using the application circuit referenced in Figure 2. Parameter ` Symbol Test Conditions SWITCHING REGULATORS SYSTEM CHARACTERISTICS Line Regulation VIN = 6V to 22V Load Regulation 0 to 5 Amps Output Load Min LX1752 Typ 0.5 -0.2 Max 0.5 0.2 Units % % Note 1: X denotes the PWM Channel: 1 or 2. Note 2: Assured by design and characterization. Not ATE tested. Note 3: For switching frequencies less than 800kHz, minimum pulse width is defined by the formula PWMIN = 0.064 X 1/Fsw Note 4: PSET Logic Threshold specifications are dependent on VCCL voltage level. The following formulas apply: PSET Logic High min. threshold = 0.81 X VCCL + 0.140 (rising) PSET Logic Low max. threshold = 0.19 X VCCL + 0.028 (rising) Note 5: Guaranteed by design. Not ATE tested. WWW . Microsemi .C OM SYSTEM CHARACTERISTICS LX1752 Copyright © 2007 Rev. 1.0, 2008-07-31 Microsemi Analog Mixed Signal Group 11861 Western Avenue, Garden Grove, CA. 92841, 714-898-8121, Fax: 714-893-2570 Page 6 LX1752 ® TM Dual Interleaving PWM Controller P RODUCTION D ATA S HEET TYPICAL CHARACTERISTICS @ 25°C (REFER TO FIGURE 2) 0.5% 0.5% 0.4% 0.4% 0.3% 0.3% 0.2% 0.2% 0.1% Vout1 0.0% Vout2 -0.1% -0.2% % Voltage Change % Voltage Change LX1752 Load Regulation @ VIN = 12V 0.1% % Change V1 0.0% % Change V2 -0.1% -0.2% -0.3% -0.3% -0.4% -0.4% -0.5% -0.5% 5 10 15 20 25 0 1 2 Input Voltage (V) 3 4 5 6 Output Current Line Regulation Load Regulation Line Regulation - VCCL IVCCL = 20mA LX1752 Efficiency Vs. Output Current 800kHz; Vin = 12V; Vout1 = 5.0V; Vout2 = 3.3V 100.0% 1.0% 90.0% 0.8% 80.0% 0.6% 70.0% 0.4% 0.2% 0.0% % Change -0.2% Efficiency % Voltage Change WWW . Microsemi .C OM LX1752 Line Regulation - 1 Amp Load 60.0% 30.0% -0.6% 20.0% -0.8% 10.0% 5 10 15 20 25 Vout2 40.0% -0.4% -1.0% Vout1 50.0% 0.0% 0 Input Voltage (V) 1 2 3 4 5 6 Output Current VCCL Line Regulation Efficiency Vs. Output Current LX1752 Copyright © 2007 Rev. 1.0, 2008-07-31 Microsemi Analog Mixed Signal Group 11861 Western Avenue, Garden Grove, CA. 92841, 714-898-8121, Fax: 714-893-2570 Page 7 LX1752 ® TM Dual Interleaving PWM Controller P RODUCTION D ATA S HEET TYPICAL CHARACTERISTICS @ 25°C (REFER TO FIGURE 2) WWW . Microsemi .C OM VOUT1 VOUT1 Load Current Load Current Output Load Step Response Output Load Release Response VOUT2 PWM VOUT2 PWM Inductor Current Inductor Current Copyright © 2007 Rev. 1.0, 2008-07-31 Overcurrent Protection Limit - I limit set for 6.5A Microsemi Analog Mixed Signal Group 11861 Western Avenue, Garden Grove, CA. 92841, 714-898-8121, Fax: 714-893-2570 LX1752 Short Circuit Current Limit During Hiccup Mode Page 8 LX1752 ® TM Dual Interleaving PWM Controller P RODUCTION D ATA S HEET TYPICAL CHARACTERISTICS @ 25°C (REFER TO FIGURE 2) WWW . Microsemi .C OM VOUT1 PWM UNIT#1 VOUT1 PWM VOUT2 PWM UNIT#2 VOUT1 PWM SS1 UNIT#1 VOUT2 PWM SS2 UNIT#2 VOUT2 PWM Fault Hiccup Mode – VOUT2 Shorted Dual 1752s Synchronized and Interleaved at 90° Intervals VOUT2 VOUT2 PWM VOUT2 PWM Inductor Current EO2 EO2 Inductor Current VOUT2 Soft Start at Power-up Microsemi Analog Mixed Signal Group 11861 Western Avenue, Garden Grove, CA. 92841, 714-898-8121, Fax: 714-893-2570 LX1752 Copyright © 2007 Rev. 1.0, 2008-07-31 Zoom In Soft Start at Power-up Page 9 LX1752 ® TM Dual Interleaving PWM Controller P RODUCTION D ATA S HEET SIMPLIFIED BLOCK DIAGRAM WWW . Microsemi .C OM RSET VSx CSx +5V VIN + VCx - ISET CIN CS Comp 50uA CS Comp PWM - R + HOx Q LX HRx S CLKx EAOx ESR LOx 4 CYCLE COUNTER Error Comp COUT PGx VIN + EA-x Hiccup - - OUT X RAMPx + VIN Vref +5V + Amplifier/ Compensation SSx 100mv - SS COMP +5V Regulator BG + VCCL + 4.7K 20K VREF CSS SHDNx F 500k AGND FAULT S UVLO R SSMSK TSD VCCL CLK1 PSET RAMP1 TRI - STATE INPUT PSET MUX RAMP2 CLK2 RFREQ PHASE SHIFT FROM SYNC PSET PWM1 PWM2 HIGH 120 240 TRI 90 270 LOW 0 180 +5V IRAMP 500 SYNC FREQ RAMP SYNC BUSS LX1752 HIGH & LOW LIMIT DETECTOR CFREQ Figure 1 – Simplified Block Diagram Copyright © 2007 Rev. 1.0, 2008-07-31 Microsemi Analog Mixed Signal Group 11861 Western Avenue, Garden Grove, CA. 92841, 714-898-8121, Fax: 714-893-2570 Page 10 Analog Mixed Signal Group 11861 Western Avenue, Garden Grove, CA. 92841, 714-898-8121, Fax: 714-893-2570 Microsemi TO ADDITIONAL LX1752'S 21.0K 1% 1uF 8 7 6 5 4 3 2 1 2.32K 0.22uF 1.2nF 1K +12V 4.7K 4.7K CS2 VIN EO2 EA2- SSEN2 SHDN2 SYNC GND 40.2K 1% 25 LX1752 U1 1.0uF 1.2nF PGND LO1 HR1 HO1 VC1 VS1 CS1 SHDN1 0.1uF 23 EO1 LO2 28 VREF VS2 9 27 PSET VC2 10 26 RFREQ HO2 11 SSEN1 HR2 12 24 EA1VCCL 13 160K 5.62K 1% LX1752 Copyright © 2007 Rev. 1.0, 2008-07-31 6.3V 4.7uF 15 16 17 18 19 20 21 22 160K 0.1uF 2.32K 0.1uF CMDSH-3 +5V LDO CMDSH-3 3.40K 1% 1/2 IRF8910 1 2 8 1/2 IRF8910 3 4 6 21.0K 1% 6 7 5 3 1 3.3uH 10uF +12V 1/2 IRF8910 4 1/2 IRF8910 2 8 5 7 6.3V 820uF + 6.3V 820uF 3.3uH 10uF +12V 10uF + RTN VOUT2 RTN 5.0V @ 5 AMPS 3.3V @ 5 AMPS 10uF VOUT1 ® 14 TM WWW . Microsemi .C OM +5V LDO LX1752 Dual Interleaving PWM Controller P RODUCTION D ATA S HEET APPLICATION CIRCUIT Figure 2 – LX1752 Application Schematic Page 11 LX1752 ® TM Dual Interleaving PWM Controller P RODUCTION D ATA S HEET THEORY OF OPERATION The LX1752 is an independent dual-output, voltage-mode, Synchronous Buck controller integrated circuit. Output current sensing is through RDSON measurement of the external power MOSFETs, and is set by a single userprogrammable resistor for each output. The internal PWM clock frequency is user programmable from 200kHz to 1.5MHz, via a single programming resistor. Synchronizing of the internal PWM clock is possible for multiple LX1752 ICs using either an internally generated sync pulse, or a sync signal from an external source. Synchronized LX1752 IC’s PWM outputs can be phase positioned relative to each other via a single pin configuration, allowing 90°, 120°, or 180° phase separation between outputs. Each of the two LX1752 outputs has external feedback compensation, for flexibility of output filter component selection. An externally generated clock pulse may be used to synchronize multiple LX1752 ICs. The LX1752 synchronizes to an external signal by resetting the PWM ramp on the falling edge of the signal input at the SYNC pin. When using an external clock for synchronizing, the external clock should be provided through an open drain or open collector connection, with an external pull-up resistor between the SYNC and VCCL pins. . For proper operation, the external clock frequency must be at least 15% higher than the LX1752 internal PWM frequency set by RFREQ, and external clock widths should be less than ½ the nominal period set by RFREQ. Figure 3 and 4 are an example of an external sync circuit and the resultant waveforms at the moment of sync clock capture. OSCILLATOR FREQUENCY WWW . Microsemi .C OM DETAIL DESCRIPTION VCCL (LX1752 PIN 13) The LX1752 IC’s internal PWM oscillator is userprogrammable from 200kHz to 1.5MHz. Programming is provided by a single resistor, RFREQ, connected between the RFREQ and GND pins. The value of this resistor is based on the following formula: 1K TO LX1752 SYNC PIN (PIN 2) EXTERNAL SYNC CLOCK RFREQ (KΩ) = 1 27.56E −9 × FOSC − 5.156 2N7002 10K EXTERNAL CLOCK SYNCHRONIZATION Copyright © 2007 Rev. 1.0, 2008-07-31 Figure 3. External Sync Circuit LX1752 HR1 PIN EXTERNAL SYNC CLOCK LX1752 SYNC PIN Figure 4. LX1752 External Sync Waveforms Microsemi Analog Mixed Signal Group 11861 Western Avenue, Garden Grove, CA. 92841, 714-898-8121, Fax: 714-893-2570 Page 12 LX1752 The LX1752 provides external clock synchronization of the PWM clock, for multiple LX1752 ICs. This feature is implemented via a common buss connected to the LX1752 IC’s SYNC pin. The SYNC pin is an I/O pin, with an open drain switch to ground providing the internally-generated output sync pulse. This allows each LX1752 SYNC pin to connect to a common buss in a wired-OR configuration. For proper operation, a pull-up resistor between the LX1752 IC’s VCCL and SYNC pins must be provided. The total parallel pull-up resistance must be greater than 500 Ohms for all ICs connected to the common buss. The total pull-up resistance on the SYNC pins is sized such that the sync pulse rise time is (at maximum) less than ½ the PWM clock period. Under synchronized operation, each LX1752 is synchronized to the falling edge of the sync pulse. Multiple LX1752 ICs will synchronize to the controller with the highest PWM clock frequency. For proper operation, it is advised to set one controller’s PWM frequency 15% higher than the others to insure it will always provide the master clock frequency. LX1752 ® TM Dual Interleaving PWM Controller P RODUCTION D ATA S HEET THEORY OF OPERATION OPEN GND 90° 0° 270° 180° OVER-CURRENT PROTECTION AND HICCUP MODE INTERNAL LDO REGULATOR The LX1752 contains a +5V LDO regulator for providing power to internal circuits, external flying bootstrap capacitors, MOSFET gate drives, and pull-up resistors for the SYNC and SHDN pins. The +5V LDO output is available at the VCCL pin. For proper operation, a minimum 4.7uF capacitor is required between the VCCL and GND pins. Total continuous LDO current should be limited to 100mA. X Microsemi Analog Mixed Signal Group 11861 Western Avenue, Garden Grove, CA. 92841, 714-898-8121, Fax: 714-893-2570 Page 13 LX1752 The LX1752 senses the RDS(ON) of both the upper (Control) and the lower (Synchronous) MOSFET for current limit detection. RDSON Sensing is done via three pins: CSX, VSX, and PGND. The upper (Control) FET RDSON is sensed via the CSX and VSX pins. The lower (Synchronous) FET RDSON is sensed via the CSX and PGND pins. Current limit is set by the resistor on the CSX pin, and is based on the UNDER VOLTAGE LOCKOUT (UVLO) following calculation: At power up, the LX1752 monitors the internal LDO voltage at the VCCL pin. The VIN supply voltage has to be sufficient to produce a voltage greater than the UVLO I × RDS ON (max) R CS = LIM threshold at the VCCL pin before the controller will come out Ics (min) of the under-voltage lock-out state. At VCCL voltages below Where ICS (min) = minimum CS pin programming current the UVLO threshold, Both soft-start (SS) pins are held low, the internal PWM oscillator is disabled, and all MOSFETs The upper and lower MOSFET current sense contain an are held off. internal blanking circuit which delays current sensing for SOFT-START 150ns after their respective MOSFET is switched on. This reduces possible false current limit detection due to ringing. Once the VCCL output is above the UVLO threshold, a RCS values should be chosen such that delays created by the capacitor connected between the SSX and GND pins begins CSX resistor and any PCB capacitance on the CSX pin are charging by a 20kΩ internal resistor connected to an 800mV less than 100ns; this is to insure the CSX pin voltage rises reference. The capacitor voltage at the SS pin rises as a simple RC circuit. The voltage at the SS pin controls its faster than the current sense blanking time. For best operation of the LX1752 current sense circuit, the respective output voltage through the error amplifier’s nonVSX pin and CSX resistor must be Kelvin-connected to their inverting input. The output voltage will follow the SS pin respective output MOSFET Drain and Source pins. When an voltage if sufficient charging current is provided to the output over current limit is detected, a signal to reset the PWM latch capacitor. Due to the exponential rise of the SSX pin voltage, is generated, and the output PWM is truncated on a cycle by the fastest output voltage rate of rise occurs during the first cycle basis. After 4 continuous PWM cycles of current limit time constant of the SSX capacitor, and the internal 20KΩ detection, hiccup mode is started. At the initial start of resistor. During this period, the feedback reference voltage hiccup mode, the HO output MOSFET for that phase is held will reach 63% of its nominal setting. This rate of rise can be Copyright © 2007 Rev. 1.0, 2008-07-31 WWW . Microsemi .C OM off, and the soft-start capacitor (CSS) is discharged at a rate 1/25 of the soft-start rate. When the SS pin voltage decreases The LX1752 offers phase positioning of the output PWMs. to the 0.1V PWM enable threshold, the hiccup mode cycle Using two synchronized LX1752 controllers, up to four “off time” finishes, the output PWM is switched on, and the PWM outputs may be interleaved at 90° intervals or 3 PWM circuit soft-starts again. During the soft start period, Hiccup outputs at 120° intervals. Output phase positioning relative mode is disabled, however, cycle by cycle current limit is to the SYNC pin signal can be configured via the LX1752’s functional, insuring output current is kept at the current limit PSET pin. The PSET pin is a tri-mode input pin, whose state setting. Once SSENX reaches 720 mV (90% of the 800mV SSENX pin reference voltage), if an over current condition determines the PWM output’s phase relationship. still exists, hiccup mode will again be initiated, the SS capacitor will discharge, and the PWM output will be PSET PIN SETTINGS switched off until the SS voltage decreases to 0.1V. The low PSET PWM 1 Position PWM 2 Position duty cycle of hiccup mode, in combination with cycle by Connection (Relative to SYNC (Relative to SYNC cycle current limiting, reduces the power dissipation of the pin signal) pin signal) output MOSFETs during a fault condition, thus providing a VCCL 120° 240° very reliable and robust overload and short circuit protection OUTPUT PHASE POSITIONING LX1752 ® TM Dual Interleaving PWM Controller P RODUCTION D ATA S HEET THEORY OF OPERATION ISTARTUP = C OUT BUFFERED VREF OUTPUT .63 × VOUT + ILOAD 20E 3 × C SS The LX1752 provides a buffered output of the internal 800mV reference. This output may be used as a reference for an external LDO or any application where an 800mV For lowest in-rush currents, soft start capacitors should be reference is required. Current is limited to a maximum of sized such that the output voltage rise is slower than the input 1mA from this output. voltage (VIN) rise during power-up. EXTERNAL FEEDBACK AND COMPENSATION COMPONENTS EXTERNAL PWM ENABLE The LX1752’s PWM outputs can be disabled externally by holding the SSX pin below 0.1V with an open drain transistor connected to ground. At SSX pin ≤ 0.1V, both output MOSFETS are held off. Using this method, PWM enable WWW . Microsemi .C OM used to calculate the average startup current seen by the and soft start can be controlled through an external signal. inductor: This method is useful for controlled power-up sequencing. The LX1752 has pin access to each output’s respective error amplifier inverting and output signals. This topology offers full freedom for output filter component selection and control loop optimization for stable high bandwidth operation. See compensation section below. LX1752 Copyright © 2007 Rev. 1.0, 2008-07-31 Microsemi Analog Mixed Signal Group 11861 Western Avenue, Garden Grove, CA. 92841, 714-898-8121, Fax: 714-893-2570 Page 14 LX1752 ® TM Dual Interleaving PWM Controller P RODUCTION D ATA S HEET APPLICATION INFORMATION Where: VRIPPLE(ESR ) = IRIPPLE × ESR VRIPPLE( C ) = IRIPPLE 8 × C × FSW VRIPPLE(ESL ) = Copyright © 2007 Rev. 1.0, 2008-07-31 The following formula is used for calculating the input RMS current for each output: VIN × ESL L + ESL IINRMS = IOUT(MAX ) × VOUT ( VIN − VOUT ) Microsemi Analog Mixed Signal Group 11861 Western Avenue, Garden Grove, CA. 92841, 714-898-8121, Fax: 714-893-2570 VIN Page 15 LX1752 RMS ripple current is the primary factor when selecting the input capacitor. Input RMS ripple current is based on operating duty cycle (D), and is at a maximum at D = 50%. WWW . Microsemi .C OM High output current may require paralleling multiple capacitors to meet output ripple requirement, as it reduces The Output Inductor value is selected based on the desired ESR and ESL, which are the major contributors to output ripple current. Inductor Ripple current should be in the range ripple voltage. of 20% to 40% of the maximum output current. Higher inductance values result in lower peak to peak ripple current, For step load conditions, capacitor ESR will be the dominant at the expense of slower transient response. Lower inductor factor determining the size of the initial output voltage values provide a higher current slew rate in response to a step excursion. Capacitor ESR should be selected such that: change in load current, however peak to peak ripple current increases, requiring an output filter capacitor with a smaller ESR × (IRIPPLE + ΔI) < VTRANSIENT ESR specification to meet output ripple voltage requirements. The Inductor value can be calculated by: Where IRIPPLE = peak to peak inductor ripple current V − VOUT D L = IN × ΔI is the maximum load current step change IRIPPLE FSW VTRANSIENT is the maximum allowed output voltage excursion during a load step change Where D = Operating Duty Cycle FSW = PWM Switching Frequency A second consideration when determining the output IRIPPLE = Desired Peak to Peak Ripple Current capacitor is the minimum capacitance value required to limit voltage overshoot during a large load release, such as a transient from full load to no load. In this case, the output OUTPUT CAPACITOR SELECTION capacitor must be large enough to absorb the excess energy present in the inductor. Minimum output capacitance is The key selection parameters for the output capacitor are the based on the desired maximum overshoot and output actual capacitance value, the equivalent series resistance inductor value, and is calculated by the following formula: (ESR), the equivalent series inductance (ESL), and the voltage rating requirements, which affect overall stability, output ripple voltage, and step load transient response. (ITRAN ) 2 × L CMIN = (VOUT + VOVERSHOOT )2 − VOUT 2 The output ripple has three components: variation in the charge stored in the output capacitor, the voltage drop across the ESR, and the voltage drop across the ESL, caused by the Where ITRAN = specified maximum load transient (full load to current into and out of the capacitor. The following no load) equations estimate the worst-case output ripple voltage: L = output inductor value VOVERSHOOT = maximum allowable voltage overshoot VRIPPLE = VRIPPLE(ESR ) + VRIPPLE( C ) + VRIPPLE(ESL ) INPUT CAPACITOR SELECTION OUTPUT INDUCTOR SELECTION LX1752 ® TM Dual Interleaving PWM Controller P RODUCTION D ATA S HEET APPLICATION INFORMATION Input capacitance is largely dependent on the source impedance of the power source; however, for most cases the general rule of thumb is to use a total minimum capacitance of 10uF for every ampere of input ripple current. This is best achieved through a combination of ceramic capacitors placed as close to the output FETS as possible, and an electrolytic capacitor placed in close proximity to the LX1752 and it’s associated circuit components. Control to Output Section Output LC Filter PWM Modulator Loop Gain (Must = 1 at Crossover Frequency) Error Amplifier Figure 6. Separating the Loop Components FEEDBACK AND COMPENSATION COMPONENT SELECTION To achieve a proper closed loop system, first the crossover frequency is determined, after which the Control To Output The LX1752 is a voltage mode controller that uses external Section is analyzed for it’s gain and rolloff response at that feedback components to establish output DC voltage and frequency. Once the response at the crossover frequency is closed-loop bandwidth. This control scheme consists of an known, the error amplifier compensation components are error amplifier, whose output controls a PWM modulator, chosen such that the overall gain of the two sections is equal which in turn drives an LC filter to produce the DC output to 1 (or 0dB) at the crossover frequency: (See Figure 5). A simple way to analyze the closed loop GFC = GCTO × GEAXO = 1 system is to break the loop and separate the elements into two sections: first, the combined PWM modulator and output LC Where GFC = loop gain at crossover frequency filter, called the Control To Output section, and second, the GCTO = Control To Output Section Gain at crossover Error Amplifier section (See Figure 6). Once separated, the frequency total gain through the two sections is analyzed. GEAXO = Error Amplifier Section Gain at crossover frequency Supply Rail Input (VIN) Output LC Filter PWM Modulator Output Voltage (VOUT) WWW . Microsemi .C OM Supply Rail Input (VIN) The LC filter creates a complex pole (-2 Slope) in the Control To Output Section’s response, along with a zero created by the output capacitor ESR. So, in addition to the Gain of 1 at the crossover frequency, the phase response of the Error Amplifier Section must be designed such that the response of the Control To Output Section is compensated to achieve a first order response (-1 slope) at the crossover frequency (See Figure 7). This will insure that the phase margin at the crossover frequency is greater than 45°. This is accomplished by designing the Error Amplifier’s response to counteract the pole and zero created by the output LC filter. 10 L-C Corner Frequency 5 Error Amplifier 0 -2 Slope -10 LX1752 Figure 5. Voltage Mode Control Scheme Gain (dB) -5 -15 ESR-C Corner Frequency -20 -25 -1 Slope -30 -35 -40 10 100 1000 10000 100000 Frequency (Hz) Figure 7. Output Filter Gain Vs. Frequency Copyright © 2007 Rev. 1.0, 2008-07-31 Microsemi Analog Mixed Signal Group 11861 Western Avenue, Garden Grove, CA. 92841, 714-898-8121, Fax: 714-893-2570 Page 16 LX1752 ® TM Dual Interleaving PWM Controller P RODUCTION D ATA S HEET APPLICATION INFORMATION RINPUT ERRAMP _ Closed-loop output voltage will drive this node to 0.7V WWW . Microsemi .C OM regulator output When selecting feedback and compensation components, the following steps are required: 1) Determine the input resistor value. 2) Determine the output voltage setting resistor. 3) Determine the Control-To-Output gain at the desired crossover frequency. 4) Determine the Error Amplifier gain at the desired crossover frequency. 5) Decide if Type Two or Type Three compensation is used 6) Calculate the feedback components for the desired compensation type. Error + 1. DETERMINE THE INPUT RESISTOR VALUE: + Vref RSET 0.7 The input resistor is sized based on the error amplifier input bias current specification. High bias currents can create output voltage errors in large-value input resistors due to the IR drop created by this current. The LX1752 has a specified Figure 8. Output DC Setting Resistors input bias current of 30nA (max.). This will generate a 30uV (max.) output voltage error for every 1k Ω of input resistance. 3. DETERMINE THE CONTROL TO OUTPUT GAIN AT THE This error is small enough to neglect in most cases. For this DESIRED CROSSOVER FREQUENCY: example, use 21kΩ (See Figure 8). The first step in determining the control to output gain is to decide on the closed-loop bandwidth, or crossover frequency 2. DETERMINE THE OUTPUT VOLTAGE SETTING RESISTOR: of the system. Bandwidths that are too wide (high crossover The voltage setting resistor is the resistor connected between frequency) can amplify switching noise. Bandwidths that are the error amplifier’s inverting input and ground. This too low will have poor transient response times. resistor, in conjunction with the input resistor, forms a DC voltage divider that determines the output voltage level (see Figure 8). Because the voltage divider is connected to the The general rule-of-thumb is thatth the crossover frequency input of the error amplifier, the control loop will force the DC (FC) should be no greater than 1/5 the switching frequency, output voltage such that the voltage developed across the or : setting resistor will equal the feedback voltage reference, VFB. VFB for the LX1752 is specified at a nominal 0.7V at F room temperature. The following equation determines the (Equation 2) FC ≤ SW 5 voltage setting resistor: (Equation 1) R SET = R INPUT × 0.7 VOUT − 0.7 Copyright © 2007 Rev. 1.0, 2008-07-31 Microsemi Analog Mixed Signal Group 11861 Western Avenue, Garden Grove, CA. 92841, 714-898-8121, Fax: 714-893-2570 Page 17 LX1752 For our example, If RINPUT = 21kΩ, and desired VOUT = 5V, then RSET = 3.42kΩ. The error amplifier gain will limit the maximum crossover frequency. The total bandwidth capable will be based on the output filter components, the DC input voltage, and the error amplifier gain. A good rule of thumb would be to limit the bandwidth to 100kHz or less. Once the crossover frequency has been determined, the next step is to determine the total input to output gain of the Control to Output Section at the crossover frequency. The input to output gain expression for the Control to Output Section is: LX1752 ® TM Dual Interleaving PWM Controller P RODUCTION D ATA S HEET APPLICATION INFORMATION Where VIN = DC input voltage to the output Mosfets GPWM = PWM Modulator Gain GLC = Output LC filter Gain The PWM Modulator Gain is based on the peak to peak PWM ramp voltage, and is simply: 1 VRAMP Where VRAMP = the peak to peak ramp amplitude GPWM = (Equation 4) The LX1752 has a nominal ramp amplitude = 1.2V The output LC filter creates two frequency corners in the output response: First, a complex pole with -2 slope (40dB/Decade) rolloff and 180° phase shift is created at the LC resonance frequency. Second, a zero, is created at the output capacitor and its respective Equivalent Series Resistance (ESR) corner frequency. These two frequency corners are found by the following equations: (Equation 5) FP = Example Calculations: Using the application circuit: VIN = 12V L = 3.3uH C= 820uF ESR = 21mΩ Ramp Amplitude = 1.2V Crossover Frequency = 80kHz Using equations 5 and 6, find the pole and zero frequency corners: FP = FZ = FZ = 2π LC 1 2π(RC) 1 = 833E −3 1.2 Using Equation 3, the total Control to Output Section gain at the crossover can be determined: G CTO = 12 × 833E −3 × 12.65E −3 = 126.45E −3 4. DETERMINE THE ERROR AMPLIFIER GAIN AT THE DESIRED CROSSOVER FREQUENCY: Our example Control to Output Section gain is 0.12645 at the crossover frequency. The error amplifier gain required for unity gain at the crossover frequency will be: Microsemi Analog Mixed Signal Group 11861 Western Avenue, Garden Grove, CA. 92841, 714-898-8121, Fax: 714-893-2570 Page 18 LX1752 Or Copyright © 2007 Rev. 1.0, 2008-07-31 3.06kHz 2 = 12.65E −3 9.25kHz × 80kHz GPWM = At the crossover frequency, the LC filter’s response can be found using the calculated pole and zero. This method of calculating the response will depend on the relationship of the output capacitor-ESR zero corner frequency to the chosen crossover frequency: 2 = 3.06kHz The PWM Modulator gain is found using equation 4: R = Output Filter Capacitor ESR FP ;FZ ≤ FC (FZ × FC ) × 820E −6 1 = 9.25kHz 2π × 21E −3 × 820E −6 GLC = C = Output Filter Capacitor GLC = 2π 3.3E 1 Where L = Output Filter Inductor (Equation 7) 1 −6 The ESR-capacitor zero frequency of our example is less than the crossover frequency. Use equation 7 to determine the LC filter gain at the crossover frequency: And (Equation 6) GLC 2 ⎞ ⎟⎟ ;FZ > FC ⎠ WWW . Microsemi .C OM (Equation 8) G CTO = VIN × GPWM × GLC (Equation 3) ⎛F = ⎜⎜ P ⎝ FC LX1752 ® TM Dual Interleaving PWM Controller P RODUCTION D ATA S HEET APPLICATION INFORMATION 1 = 1 = 7.908 126.45E −3 available phase margin present in the Control to Output Section at the crossover frequency. Because Type Two compensation does not provide an extra phase boost after the Once the required Error Amplifier gain is determined, the complex LC pole, the phase boost provided by the output Error Amplifier open loop gain should be examined to assure capacitor – ESR combination is critical when using Type the Error Amplifier has enough open-loop gain at the Two compensation. Therefore, the relationship of the complex LC pole, FP, to the ESR-capacitor zero, FZ,. becomes crossover frequency to satisfy the above gain requirement: important: if Fz/Fp is 5 or less, then Type Two GEAOL Compensation may be used. Type Three compensation (Equation 10) GEAXO ≤ ⎛ GEAOL × 2π ⋅ FC ⎞ should be used otherwise. ⎜ ⎟ +1 ⎜ 2π ⋅ F ⎟ EAOL ⎝ ⎠ G CTO Where GEAOL = Error Amplifier Open Loop Gain WWW . Microsemi .C OM GEAXO = (Equation 9) regulator output FEAOL = Error Amplifier Open Loop Bandwidth C3 Using the LX1752 Error Amplifier as an example: R3 GEAOL = 70dB, gain magnitude = 3162 C1 R2 R1 FEAOL = 10MHz C2 _ ERRAMP 3162 = 120.24 ⎛ 3162 × 2π × 80kHz ⎞ ⎜ ⎟ +1 2π × 10MHz ⎠ ⎝ Error + + Vref R4 0.7 The above equation shows there is ample Error Amplifier open-loop gain available at the crossover frequency. Figure 9. Type 3 Compensation 5. DECIDE IF TYPE TWO OR TYPE THREE COMPENSATION IS USED. Copyright © 2007 Rev. 1.0, 2008-07-31 C1 R2 R1 ERRAMP _ Error + + Vref LX1752 At this point, the compensation type can be decided. The two standard methods for compensating a Voltage Mode Buck converter are Type Two and Type Three compensation (the name references the number of compensating slopes in the response; Type Two has two, Type Three has three). See Figures 9 & 10. Both Type Two and Type Three compensation are identical in that they are designed to offset the complex pole and ESR zero of the output LC filter. Where they differ is in the number of compensating poles and zeros provided. Type Two compensation is known as a “single pole-zero” compensation, in that it supplies a single compensating zero, and a single compensating pole in the Error Amplifier’s response. The Type Three compensation is known as “pole-zero pair” compensation, in that it supplies two compensating poles and two compensating zeros. The deciding factor for which of the two methods of compensating the loop can be used is based on the amount of regulator output C2 R3 0.7 Figure 10. Type 2 Compensation Microsemi Analog Mixed Signal Group 11861 Western Avenue, Garden Grove, CA. 92841, 714-898-8121, Fax: 714-893-2570 Page 19 LX1752 ® TM Dual Interleaving PWM Controller P RODUCTION D ATA S HEET APPLICATION INFORMATION Type Three compensation contains 2 poles and 2 zeros in the feedback loop to counteract the complex pole created by the L-C output filter, and the zero created by the ESR output capacitor. Type 3 compensation should be used when the desired crossover frequency is lower than the ESR zero frequency, or when it is higher than the ESR zero frequency and the ESR zero frequency is higher than 4 to 5 times the output LC filter corner frequency. Typical feedback response is shown in Figure 11. 100 90 80 4. Finally, the last compensation pole (fP2) is set equal to 1/2 the switching frequency: (Equation 14) fP 2 = FSW 2 In order for the feedback response to be correct, the feedback loop must be set to two gain levels, GFB1, and GFB2 GFB2 is the highest gain value of the two levels, and is the gain required to boost the control to output gain to 1 at the crossover frequency. GFB2 is established after the first compensation pole frequency (fP1), and is the complement of the total control to output gain (GCTO) at the selected crossover frequency: Gain (dB) 70 (Equation 15) 60 G FB 2 = 50 WWW . Microsemi .C OM TYPE THREE COMPENSATION COMPONENT SELECTION. 1 G CTO 40 30 GFB2 fp1 20 fp2 GFB1 10 fz1 fz2 0 1 10 100 1000 Frequency (Hz) 10000 100000 1000000 Crossover Frequency (FC) GFB1 is the gain level established after the first compensation zero frequency (fz1). GFB1 gain is derived from the crossover frequency gain (GFB2). The method for calculating GFB1 is dependent on whether the output capacitor – ESR zero corner frequency is greater or less than the crossover frequency. Condition 1; FZ ≤ FC Figure 11. Typical Type 3 Feedback Response (Equation 16) To calculate the values, first the two compensation zeros and two compensation poles must be set. The two compensation zeros are set to counteract the complex L-C pole at two locations, both multiples of the complex L-C pole: 1. Set the first compensation zero frequency (fz1) to the L-C pole/4: F (Equation 11) fZ 1 = P 4 Next, the first compensation pole (fP1) is set equal to the ESR - capacitor zero frequency: (Equation 13) fP 1 = FZ 3. Copyright © 2007 Rev. 1.0, 2008-07-31 Condition 2; FC ≤ FZ This condition occurs when the capacitor-ESR zero frequency corner is greater than the chosen cutoff frequency. This is a common condition with ceramic output capacitors. For this condition, GFB1 is found by: (Equation 17) ⎛f 2⎞ G FB 1 = G FB 2 × ⎜⎜ Z ⎟⎟ ⎝ FC ⎠ To calculate the compensation component values (Reference Figure 9): First, select resistor R1. This topic is covered under “Determine the Input Resistor Value” on page 17. Resistor R4 may be selected at this time; however it is for setting the output DC level only, and is not used in the compensation calculations. R4 is covered under “Determine the Output Voltage Setting Resistor” on page 17. Microsemi Analog Mixed Signal Group 11861 Western Avenue, Garden Grove, CA. 92841, 714-898-8121, Fax: 714-893-2570 Page 20 LX1752 Set the second compensation zero frequency (fZ2) equal to the L-C pole frequency: (Equation 12) fZ 2 = FP 2. ⎛f 2⎞ G FB 1 = G FB 2 × ⎜⎜ Z ⎟⎟ ⎝ fP 1 ⎠ LX1752 ® TM Dual Interleaving PWM Controller P RODUCTION D ATA S HEET APPLICATION INFORMATION (Equation 18) • R2 = R1 × G FB 1 Calculate the value for C1; C1 & R2 set the first zero frequency: Capacitor ESR = 5.5mΩ (2 capacitor ESR values of 11mΩ in parallel) Crossover Frequency = 80kHz Referencing Figure 7: Copyright © 2007 Rev. 1.0, 2008-07-31 C1 = 1 2π ( fZ 1)R2 Microsemi Analog Mixed Signal Group 11861 Western Avenue, Garden Grove, CA. 92841, 714-898-8121, Fax: 714-893-2570 Page 21 LX1752 Step 1 – Determine the input resistor (R1) value: Keep the input resistor value as low as practical to reduce input bias errors. For this example, choose 10.7kΩ 1% (1% part for DC output voltage The next value is for R3; R3||R1 & R2 set the gain for GFB2: accuracy). Step 2 – Determine the DC output “setting” resistor (R4): R1 × R2 (Equation 20) R3 = Using Equation 1, and the values chosen for RINPUT (R1× GFB 2) − R2 and VOUT: RSET (R4) = 13.6kΩ. Use 13.7kΩ 1% (1% part for Calculate C2; C2 & R1 + R3 set the second zero frequency: DC output voltage accuracy). 1 Step 3 – Determine the Control to Output Section Gain: (Equation 21) C2 = 2π ( fZ 2)(R1 + R3) Using Equation 5, and the values chosen for L and C: FP = 1.96kHz Using Equation 6, and the values chosen for ESR and Finally, the value for C3 + C1 & R2 sets the second pole C: frequency: FZ = 9.65kHz C1 (Equation 22) C3 = The ESR – Capacitor zero frequency is less than the (2π ( fP 2) ⋅ C1 ⋅ R2) − 1 chosen crossover frequency. Use Equation 7 to calculate the gain of the LC filter section: The first pole frequency, fP1, will be correct with the values GLC = 4.974E-3 chosen. To verify: Using Equation 4, PWM modulator gain is: GPWM = 0.833 1 Finally, using Equation 3 and the chosen VIN value (Equation 23) fP 1 = 2π (R3C2) of 3.4V: GCTO = 14.086E-3 Example Calculations: Step 4 - Determine required Error Amplifier Gain: Using Equation 9, the required Error Amplifier Gain: Assume the following design parameters and component GEAXO = 71 values: Use Equation 10 to determine the Error Amplifier open-loop gain at the crossover frequency: • VIN = 3.4V GEAXO ≤ 120.2 • VOUT = 1.24V Based on equation 10, there is enough gain available. • VRAMP = 1.2V Step 5 – Determine Type Two or Type Three compensation: • PWM frequency = 800kHz For this example, FZ/FP is greater than 4. We will use • Error Amplifier Gain = 3162 (70dB) Type Three Compensation. • Error Amplifier Bandwidth = 10MHz Step 6 – Select Type Three components (reference Figure 9): • Output Inductor (L) = 2.2uH Using Equations 11 through 14, determine the • Output Capacitor (C) = 3000uF (2 X 1500uF compensation frequency components: capacitors in parallel) fz1 = 490Hz (Equation 19) WWW . Microsemi .C OM • Next, calculate the value of R2; R1 & R2 will set the gain for GFB1: LX1752 ® TM Dual Interleaving PWM Controller P RODUCTION D ATA S HEET APPLICATION INFORMATION Overall Loop Gain & Phase Calculate the highest of the two feedback gains using Equation 15: GFB2 = 71 The ESR – Capacitor zero frequency is less than the chosen crossover frequency. Use Equation 16 to calculate the lower of the two feedback gains: GFB1 = 14.4 Using Equations 18 through 22, calculate the values for the compensation components: R2 = 154kΩ; use 150kΩ 5% R3 = 2.72kΩ; use 2.7kΩ 5% C1 = 2.11nF; use 2.2nF C2 = 6.05nF; use 5.6nF C3 = 2.6pF; too small; omit this capacitor. 150 100 50 WWW . Microsemi .C OM Figure 13 is the Bode Plot of the closed loop response of our example. fz2 = 1.96kHz fp1 = 9.65kHz fp2 = 400kHz 0 50 100 150 In this example, C3 value of 2.6pF is far too small to be of practical use. In this case it may be omitted without any consequence. If the additional roll off provided by C3 is still desired, the value of RINPUT (R1) may be set lower, and the feedback components recalculated. This will raise the value of C3. As an alternative, set FP2 to a lower frequency, however do not set lower than 1.5 X the crossover frequency (FC). Figure 12 is the schematic of the example feedback compensation. 10 100 3 1 .10 4 Frequency 1 .10 5 1 .10 6 1 .10 Gain Phase Figure 13. Bode Plot of Example Circuit regulator output C3 C1 2.2n Not Used R3 2.7k 5% R2 R1 10.7k 1% 150k 5% _ LX1752 ERRAMP C2 5.6n Error + + 0.7 Vref R4 13.7k 1% Figure 12. Example Circuit Feedback and Compensation Copyright © 2007 Rev. 1.0, 2008-07-31 Microsemi Analog Mixed Signal Group 11861 Western Avenue, Garden Grove, CA. 92841, 714-898-8121, Fax: 714-893-2570 Page 22 LX1752 ® TM Dual Interleaving PWM Controller P RODUCTION D ATA S HEET APPLICATION INFORMATION Gain (dB) 70 (Equation 26) 60 50 40 30 GFB 20 fp1 fz1 10 0 1 10 100 1000 Frequency (Hz) 10000 100000 Crossover Frequency (FC) 1000000 Figure 14. Typical Type 2 Feedback Response GFB = WWW . Microsemi .C OM As in Type 3 Compensation, establish the frequency corners: 1. Set the first compensation zero frequency (fz1) to Type Two compensation contains a single zero and pole in the L-C pole/4: the feedback loop to counteract the complex pole created by F the L-C output filter. This type of compensation does not (Equation 24) fZ 1 = P 4 provide an extra phase boost after the complex LC pole frequency, which is provided by Type 3 compensation. This type of compensation is used when the phase margin of the 2. Set the compensation pole (fP1) equal to 1/2 the Control to Output section is greater than the minimum closed switching frequency: loop phase margin desired at the crossover frequency. F Typical frequency response is shown in Figure 14. (Equation 25) fP 1 = SW 2 100 Type Two compensation has only one gain level to be 90 concerned with. This is the gain required to boost the control 80 to output gain to 1 at the crossover frequency: TYPE TWO COMPENSATION COMPONENT SELECTION. 1 G CTO To calculate the compensation component values (Reference Figure 8): First, select resistor R1. This topic is covered under “Determine the Input Resistor Value” on page 15. Resistor R3 may be selected at this time; however it is for setting the output DC level only, and is not used in the compensation calculations. R3 is covered under “Determine the Output Voltage Setting Resistor” on page 16. Next, calculate the value of R2; R1 & R2 will set the gain for The component values for Type 2 compensation are found GFB: using identical equations and methods as in Type 3. The main differences are that Type 2 has only one gain level, one R2 = R1× G FB (Equation 27) compensating zero, and one compensating pole to calculate. Calculate the value for C1; C1 & R2 set the compensating zero frequency: 1 (Equation 28) C1 = 2π ( fZ 1)R2 Copyright © 2007 Rev. 1.0, 2008-07-31 Microsemi Analog Mixed Signal Group 11861 Western Avenue, Garden Grove, CA. 92841, 714-898-8121, Fax: 714-893-2570 Page 23 LX1752 Finally, the value for C2 + C1 & R2 sets the compensating pole frequency: C1 (Equation 29) C2 = (2π ( fP 1) ⋅ C1 ⋅ R2) − 1 LX1752 ® TM Dual Interleaving PWM Controller P RODUCTION D ATA S HEET APPLICATION INFORMATION The maximum VDS rating of the MOSFET should exceed by at least 10% the maximum DC input voltage, plus any voltage transients that might be present on the DC line, over all operating temperatures. The maximum drain current rating of the MOSFET should be chosen to cover all operating current conditions, at all operating temperatures. Overcurrent limits, and current spikes should all be considered before selecting a MOSFET. RDSON and total gate charge should always be as small as possible. RDSON and total gate charge (Qg) will vary inversely with each other; ie. lower gate charges typically are at the expense of higher RDSON ratings. (Equation 31) ⎛ ⎞ V 2 PD RDS( SYNC ) ( W ) = (ILOAD ) × RDS 0N × ⎜⎜1 − OUT ⎟⎟ VIN ⎠ ⎝ Note: specify RDSON at maximum junction temperature. In addition to channel loss, body diode conduction loss must be considered. Body diode conduction loss (PDBD) is found using the following equation: (Equation 32) PD BD( SYNC ) ( W ) = 2 × ILOAD × VF × TDT × FSW Microsemi Analog Mixed Signal Group 11861 Western Avenue, Garden Grove, CA. 92841, 714-898-8121, Fax: 714-893-2570 Page 24 LX1752 Where VF = Body Diode Forward Voltage TDT = PWM output dead time MOSFETs must be chosen such that their maximum power FSW = PWM output switching frequency dissipation is not exceeded at any time in the application, and Switching losses for the Synchronous FET are limited to the that the junction temperature for the device does not exceed gate input losses due to the input capacitance (CISS). PDCISS the maximum rating for the part under all conditions. The is found by: power dissipation of the MOSFET will depend largely on two principle factors affecting loss: conduction losses, and (Equation 33) switching losses. 2 At lower frequency switching, conduction losses make up the PD CISS( SYNC) ( W ) = 0.5 × C ISS × (VGS ) × FSW bulk of the total power dissipation in the MOSFETs. Two Where VGS = peak gate drive voltage factors determine conduction losses: channel conduction Most datasheets specify CISS in a graph of capacitance vs. losses (for both Control and Synchronous FETs), and body VDS. Due to the zero voltage switching of the Synchronous diode conduction losses (Synchronous FET only). FET, CISS should be chosen at VDS = 0 for this calculation. Copyright © 2007 Rev. 1.0, 2008-07-31 WWW . Microsemi .C OM For conduction losses in the Control (Upper) FET, channel loss is the only concern (under normal operation the body When selecting output MOSFETs, There are five important diode does not conduct). Channel loss is due to the IR drop parameters to be concerned with: Maximum VDS rating, across the MOSFET’s RDSON. When calculating channel Maximum Drain Current rating, RDSON, Total Gate Charge, loss, RDSON should be specified at the maximum junction and Maximum Power Dissipation. temperature of the FET. Most datasheets specify RDSON at 25°C, and provide a graph for estimating the RDSON at a The upper and lower MOSFET positions, in many cases, can specific junction temperature. Channel loss for the upper be satisfied with the same part value FET, making the use of FET (PDRDS(CONTROL)) can be calculated with the following dual MOSFET packages attractive. However, in cases where formula: output current and switching frequency are high, the MOSFET chosen for the upper (Control) FET may differ (Equation 30) from the lower (Synchronous) FET. (I )2 × RDS 0N × VOUT PD RDS( CONTROL ) ( W ) = LOAD VIN For example, in a high frequency switcher application, the power dissipated in the Control FET may be more dependent Note: specify RDSON at maximum junction temperature. on switching losses, in which case a FET with a lower total For conduction losses in the Synchronous (Lower) FET, both gate charge (Qg) should be considered. The opposite is true channel and body diode losses must be considered. As in the for the Synchronous FET, where conduction losses may be Control FET calculations, channel loss is a function of the dominating factor in the total power dissipation. In this RDS , and should be evaluated using the specified RDS ON ON case a FET with a lower RDSON would be considered. at the part’s specified maximum junction temperature: OUTPUT MOSFET SELECTION LX1752 ® TM Dual Interleaving PWM Controller P RODUCTION D ATA S HEET APPLICATION INFORMATION (Equation 34) PD ( SYNC ) ( W ) = PD RDS( SYNC ) + PD BD( SYNC ) + PD CISS( SYNC ) Switching losses in the Control FET are due to overlap switching loss, gate input loss, losses due to MOSFET capacitances, and Synchronous FET body diode reverse recovery charge. To calculate overlap switching loss, first the average gate current must be calculated. This is found through by the average of the upper and lower drive RDSON, added to the MOSFET internal gate resistance, which is specified on most datasheets. If not specified, 2.0 Ohms may be substituted. In the LX1752, the average drive on-resistance is 3.0Ω. Average gate current can now be found by: (Equation 35) IG = 0.5 × TS = (Equation 39) PD SW ( CONTROL ) = (PD OLS + PD GATE ) × 1.2 Total power dissipation in the Control FET can now be calculated: VGS R DRIVE + R GATE Where RDRIVE = average controller gate drive On resistance RGATE = MOSFET gate resistance Once average gate current is known, the next step is to calculate the average gate switching time: (Equation 36) Losses due to Synchronous FET reverse body diode recovery are based on QRR, a parameter not clearly defined in most datasheets. A good rule of thumb would be to increase the total power dissipation due to switching loss by 20% to account for losses due to QRR and MOSFET capacitances. The total Control FET switching loss would be the sum of the losses, increased by 20%: QGS 2 + Q GD IG Where QGS2 is the portion of gate to source gate charge after the gate reaches Vth to the plateau of the gate charge curve, and QGD is MOSFET gate-drain charge. Refer to the MOSFET datasheet for more detail. (Equation 40) PD CONTROL ( W ) = PD SW ( CONTROL ) + PD RDS( CONTROL ) Once the power dissipations of both MOSFETS are known, the operating junction temperatures can be calculated using thermal resistance specifications contained in the MOSFET datasheet. PRINTED CIRCUIT BOARD LAYOUT RECOMMENDATIONS Microsemi Analog Mixed Signal Group 11861 Western Avenue, Garden Grove, CA. 92841, 714-898-8121, Fax: 714-893-2570 Page 25 LX1752 Careful attention to PCB layout is necessary to insure proper operation with minimal noise generation. When laying out the PCB, these guidelines should be followed: 1) Keep the input capacitor, output capacitor, output With switching time (TS), load current, PWM frequency, and inductor and output MOSFETs (upper and lower), close maximum VIN known, overlap switching loss can be together, and tie all high current output returns directly calculated by: to a suitable power ground plane. 2) Keep the high current ground return paths separate from (Equation 37) PD OLS = IOUT × TS × VIN × FSW the signal return paths. It is recommended that a separate signal ground plane be used, with a common tie point between the power ground plane and the signal Gate input loss (PDGATE) is found by: ground plane established at the IC signal ground pin. 3) Place the input decoupling capacitor has close to the (Equation 38) upper and lower MOSFETs as practical. Connections R GATE between this capacitor and the upper and lower PD GATE = Q G × VGS × FSW × MOSFET’s Drain and Source connections should be as R DRIVE + R GATE Copyright © 2007 Rev. 1.0, 2008-07-31 WWW . Microsemi .C OM Where: FSW = PWM switching frequency RGATE = gate input resistance Where QG = total gate charge (datasheet value) VGS = peak gate drive voltage RDRIVE = high side driver on resistance Total power loss in the Synchronous FET will be the sum of the conduction and the switching losses: LX1752 TM ® Dual Interleaving PWM Controller P RODUCTION D ATA S HEET APPLICATION INFORMATION 9) Stray capacitance to ground on CSx pins should be minimized. If possible, remove ground and power planes in the area directly below CSX pins, and place each respective CSX resistor as close to the LX1752 as practical; preferably on the same PCB side as the LX1752. 10) Place all compensation and feedback components as close to their respective error amplifier pins as practical. Keep the error amplifier input connections (EAX-) as short as possible. 11) Place the frequency programming resistor, RFREQ as close to the RFREQ and GND pins as practical. 12) Refer to the Evaluation Board for an example of the PCB layout. WWW . Microsemi .C OM short as practical. 4) The LDO filter capacitor should be placed as close to the VCCL pin as practical. 5) PGND connection to the Source pin of the Lower MOSFET should be as short as practical, and should be established with a direct connection (using no vias) if possible. 6) VSX Pin connections should be Kelvin connected directly at the Upper MOSFET’s drain pin(s). 7) HRX connection to the Upper MOSFET’s Source pin should be as short as practical, and should be established with a direct connection (using no vias) if possible. 8) LOX and HOX should be connected to their respective MOSFET gate pins with as short a trace as practical, and should be established with a direct connection (using no vias) if possible. LX1752 Copyright © 2007 Rev. 1.0, 2008-07-31 Microsemi Analog Mixed Signal Group 11861 Western Avenue, Garden Grove, CA. 92841, 714-898-8121, Fax: 714-893-2570 Page 26 LX1752 ® TM Dual Interleaving PWM Controller P RODUCTION D ATA S HEET LQ 28-Pin 4x5mm D L D2 E E2 b e K A3 A Dim A A1 A3 K e L b D2 E2 D E MILLIMETERS MIN MAX 0.80 1.00 0.00 0.02 0.20 REF 0.20 REF 0.50 BSC 0.30 0.50 0.18 0.30 2.50 2.75 3.50 3.75 4.00 BSC 5.00 BSC INCHES MIN MAX 0.031 0.039 0 0.008 0.008 REF 0.008 REF 0.02 BSC 0.012 0.02 0.007 0.012 0.098 0.108 0.138 0.148 0.158 BSC 0.197 BSC WWW . Microsemi .C OM PACKAGE DIMENSIONS A1 LX1752 Copyright © 2007 Rev. 1.0, 2008-07-31 Microsemi Analog Mixed Signal Group 11861 Western Avenue, Garden Grove, CA. 92841, 714-898-8121, Fax: 714-893-2570 Page 27 LX1752 TM ® Dual Interleaving PWM Controller P RODUCTION D ATA S HEET NOTES WWW . Microsemi .C OM LX1752 PRELIMINARY DATA – Information contained in this document is pre-production data and is proprietary to Microsemi. It may not be modified in any way without the express written consent of Microsemi. Product referred to herein is offered in pre-production form only and may not have completed Microsemi’s Quality Assurance process for Release to Production. Microsemi reserves the right to change or discontinue this proposed product at any time. Copyright © 2007 Rev. 1.0, 2008-07-31 Microsemi Analog Mixed Signal Group 11861 Western Avenue, Garden Grove, CA. 92841, 714-898-8121, Fax: 714-893-2570 Page 28