LP3981 Micropower, 300mA Ultra Low-Dropout CMOS Voltage Regulator General Description The LP3981’s performance is optimized for battery powered systems to deliver ultra low noise, extremely low dropout voltage and low quiescent current. Regulator ground current increases only slightly in dropout, further prolonging the battery life. Power supply rejection is better than 60 dB at low frequencies. This high power supply rejection is maintained down to lower input voltage levels common to battery operated circuits. The device is ideal for mobile phone and similar battery powered wireless applications. It provides up to 300 mA, from a 2.5V to 6V input, consuming less than 1µA in disable mode. The LP3981 is available in MSOP-8 package. For LP3981 in LLP-6 package, contact NSC sales offices. Performance is specified for −40˚C to +125˚C temperature range. The device available in the following output voltages; 2.5V, 2.7V, 2.8V, 2.83V, 3.0V, 3.03V and 3.3V as standard. Other output options can be made available, please contact your local NSC sales office. Key Specifications n 2.5 to 6.0V input range n 300mA guaranteed output n n n n n n n 60dB PSRR at 1kHz ≤1µA quiescent current when shut down Fast Turn-On time: 120 µs (typ.) with CBYPASS = 0.01uF 132mV typ dropout with 300mA load 35µVrms output noise over 10Hz to 100kHz −40 to +125˚C junction temperature range for operation 2.5V, 2.7V, 2.8V, 2.83V, 3.0V, 3.03V, and 3.3V outputs standard Features n Small, space saving MSOP-8 n Low Thermal Resistance in LLP-6 package gives excellent power capability n Logic controlled enable n Stable with ceramic and high quality tantalum capacitors n Fast turn-on n Thermal shutdown and short-circuit current limit Applications n n n n n CDMA cellular handsets Wideband CDMA cellular handsets GSM cellular handsets Portable information appliances Tiny 3.3V ± 5% to 2.5V, 300mA converter Typical Application Circuit 20020302 Note: Pin Numbers in parenthesis indicate LLP-6 package. © 2003 National Semiconductor Corporation DS200203 www.national.com LP3981 Micropower, 300mA Ultra Low-Dropout CMOS Voltage Regulator March 2003 LP3981 Block Diagram 20020301 Pin Descriptions Name MSOP-8 LLP-6 VEN 7 6 Enable Input Logic, Enable High GND 5 4 Common Ground VOUT 1 1 Output Voltage of the LDO VIN 2 2 Input Voltage of the LDO Bypass 6 5 Optional bypass capacitor for noise reduction VOUT-SENSE 4 3 Output. Voltage Sense Pin. Should be connected to VOUT for proper operation. N.C 3, 8 Connection Diagrams Function LLP-6 Package MSOP-8 Package 20020370 Top View See NS Package Number LDC06D 20020307 Top View See NS Package Number MUA008AE www.national.com 2 LP3981 Ordering Information For LLP-6 Package Output Voltage (V) Grade LP3981 Supplied as 1000 Units, Tape and Reel LP3981 Supplied as 4500 Units, Tape and Reel Package Marking 2.5 STD LP3981ILD-2.5 LP3981ILDX-2.5 LO1UB 2.7 STD LP3981ILD-2.7 LP3981ILDX-2.7 LO1VB 2.8 STD LP3981ILD-2.8 LP3981ILDX-2.8 LO1ZB 2.83 STD LP3981ILD-2.83 LP3981ILDX-2.83 L01SB 3.0 STD LP3981ILD-3.0 LP3981ILDX-3.0 L017B 3.03 STD LP3981ILD-3.03 LP3981ILDX-3.03 LO1YB 3.3 STD LP3981ILD -3.3 LP3981ILDX-3.3 LO1XB For MSOP-8 Package Output Voltage (V) Grade LP3981 Supplied as 1000 Units, Tape and Reel LP3981 Supplied as 3500 Units, Tape and Reel Package Marking 2.5 STD LP3981IMM-2.5 LP3981IMMX-2.5 LFKB 2.7 STD LP3981IMM-2.7 LP3981IMMX-2.7 LFLB 2.8 STD LP3981IMM-2.8 LP3981IMMX-2.8 LFTB 2.83 STD LP3981IMM-2.83 LP3981IMMX-2.83 LDUB 3.0 STD LP3981IMM-3.0 LP3981IMMX-3.0 LF3B 3.03 STD LP3981IMM-3.03 LP3981IMMX-3.03 LFPB 3.3 STD LP3981IMM-3.3 LP3981IMMX-3.3 LFNB *Please contact factory regarding the availability of voltage options not listed here. 3 www.national.com LP3981 Absolute Maximum Ratings Maximum Power Dissipation at 25˚C MSOP-8 LLP-6 (Notes 1, 2) If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. VIN, VEN ESD Rating(Note 4) Human Body Model Machine Model −0.3 to 6.5V VOUT, VOUT-SENSE −0.3 to VIN + 0.3, Max 6.5V Junction Temperature 150˚C Storage Temperature −65˚C to +150˚C 595mW 2.5W 2kV 200V Operating Ratings (Notes 1, 2) VIN 2.7 to 6V VEN 0 to VIN Lead Temp. Junction Temperature Pad Temp. Maximum Power Dissipation (Note 5) MSOP-8 LLP-6 Power Dissipation (Note 3) θJA (MSOP-8) θJA (LLP-6) 210˚C/W 50˚C/W −40˚C to +125˚C 476mW 2.0W Electrical Characteristics Unless otherwise specified: VEN = 1.2V, VIN = VOUT + 0.5V, CIN = 2.2 µF, CBP = 0.033 µF, IOUT = 1mA, COUT = 2.2 µF. Typical values and imits appearing in standard typeface are for TJ = 25˚C. Limits appearing in boldface type apply over the entire junction temperature range for operation, −40˚C to +125˚C. (Notes 6, 7) Symbol Parameter Conditions Typ Output Voltage Tolerance ∆VOUT Line Regulation Error VIN = VOUT + 0.5V to 6.0V, TA < +85˚C 0.005 VIN = VOUT + 0.5V to 6.0V, TJ ≤125˚C Load Regulation Error (Note 8) PSRR Power Supply Rejection Ratio (Note 10) IQ Quiescent Current Dropout Voltage (Note 9) 0.0003 VIN = VOUT(nom) + 1V, f = 1 kHz, IOUT = 50 mA (Figure 2) 50 VIN = VOUT(nom) + 1V, f = 10 kHz, IOUT = 50 mA (Figure 2) 55 −2 −3 2 3 −0.1 0.1 0.2 0.005 70 120 VEN = 1.2V, IOUT = 1 to 300 mA, VOUT = 2.5V(Note 12) 170 210 VEN = 0.4V 0.003 1.5 IOUT = 1 mA 0.5 5 IOUT = 200 mA 88 133 IOUT = 300 mA 132 200 600 Output Grounded (Steady State) en Output Noise Voltage BW = 10 Hz to 100 kHz, CBP = 0.033µF Units % of VOUT(nom) %/V %/V %/mA dB VEN = 1.2V, IOUT = 1 mA Short Circuit Current Limit µA mV mA 35 µVrms Thermal Shutdown Temperature 160 ˚C Thermal Shutdown Hysteresis 20 ˚C IOUT(PK) Peak Output Current VOUT ≥ VOUT (nom) - 5% IEN Maximum Input Current at VEN VEN = 0 and VIN VIL Logic Low Input threshold VIN = 2.7 to 6.0V VIH Logic High Input threshold VIN = 2.7 to 6.0V www.national.com Max −0.2 IOUT = 1 mA to 300 mA ISC TSD Limit Min 4 455 300 0.001 µA 0.4 1.4 V V (Continued) Unless otherwise specified: VEN = 1.2V, VIN = VOUT + 0.5V, CIN = 2.2 µF, CBP = 0.033 µF, IOUT = 1mA, COUT = 2.2 µF. Typical values and imits appearing in standard typeface are for TJ = 25˚C. Limits appearing in boldface type apply over the entire junction temperature range for operation, −40˚C to +125˚C. (Notes 6, 7) Symbol TON Parameter Turn-On Time (Note 10) (Note 11) Conditions CBYPASS = 0.033 µF Limit Typ Min Units Max 240 µs 350 Note 1: Absolute Maximum Ratings are limits beyond which damage to the device may occur. Operating Ratings are conditions under which operation of the device is guaranteed. Operating Ratings do not imply guaranteed performance limits. For guaranteed performance limits and associated test conditions, see the Electrical Characteristics tables. Note 2: All voltages are with respect to the potential at the GND pin. Note 3: The figures given for Absolute Maximum Power disipation for the device are calculated using the following equations: where TJ(MAX) is the maximum junction temperature, TA is the ambient temperature, and θ JA is the junction-to-ambient thermal resistance. E.g. for the LLP package θ JA =50˚C/W, TJ(MAX) =150˚C and using TA =25˚C the maximum power dissipation is found to be 2.5W. The derating factor (−1/θJA) = −20mW/˚C, thus below 25˚C the power dissipation figure can be increased by 20W per degree, and similarity decreased by this factor for temperatures above 25˚C Note 4: The human body model is 100pF discharged through 1.5kΩ resistor into each pin. The machine model is a 200 pF capacitor discharged directly into each pin. Note 5: As for the Maximum Power dissipation, the maximum power in operation is dependant on the ambient temperature. This can be calculated in teh same way using TJ =125˚C, giving 2W as the maximum power dissipation for the LLP package in operation. The same derating factor applies. Note 6: All limits are guaranteed. All electrical characteristics having room-temperature limits are tested during production with TJ = 25˚C or correlated using Statistical Quality Control (SQC) methods. All hot and cold limits are guaranteed by correlating the electrical characteristics to process and temperature variations and applying statistical process control. Note 7: The target output voltage, which is labeled VOUT(nom), is the desired voltage option. Note 8: An increase in the load current results in a slight decrease in the output voltage and vice versa. Note 9: Dropout voltage is the input-to-output voltage difference at which the output voltage is 100mV below its nominal value. This specification does not apply for input voltages below 2.5V. Note 10: Guaranteed by design. Note 11: Turn-on time is time measured between the enable input just exceeding VIH and the output voltage just reaching 95% of its nominal value. Note 12: For VOUT > 2.5C, Increase IQ(MAX) by 2.5µA for every 0.1V increase in VOUT(NOM). i.e. IQ(MAX) = 210 + ((VOUT(NOM) - 2.5) * 25)µA Output Capacitor, Recommended Specification Limit Symbol Parameter Conditions Typ COUT Output Capacitor Capacitance 2.2 22 µF ESR 5 500 mΩ Min Max Units 20020308 FIGURE 1. Line Transient Response Input Perturbation 5 www.national.com LP3981 Electrical Characteristics LP3981 20020309 FIGURE 2. PSRR Input Perturbation Typical Performance Characteristics Unless otherwise specified, CIN = COUT = 2.2 µF Ceramic, CBP = 0.033 µF, VIN = VOUT + 0.5V, TA = 25˚C, Enable pin is tied to VIN. Output Voltage vs. Temperature (VOUT = 2.83V) Dropout Voltage vs. Temperature (VOUT = 2.85V) 20020317 20020318 Ground Current vs. Load Current (VOUT = 2.85V) Output Short Circuit Current 20020320 20020319 www.national.com 6 Output Short Circuit Current Ripple Rejection (VIN = VOUT + 1V) 20020332 20020321 Ripple Rejection (VIN = VOUT + 1V) Ripple Rejection (VIN = VOUT + 1V) 20020322 20020323 Load Transient Response (VIN = 3.5V) Load Transient Response (VIN = 3.5V) 20020324 20020325 7 www.national.com LP3981 Typical Performance Characteristics Unless otherwise specified, CIN = COUT = 2.2 µF Ceramic, CBP = 0.033 µF, VIN = VOUT + 0.5V, TA = 25˚C, Enable pin is tied to VIN. (Continued) LP3981 Typical Performance Characteristics Unless otherwise specified, CIN = COUT = 2.2 µF Ceramic, CBP = 0.033 µF, VIN = VOUT + 0.5V, TA = 25˚C, Enable pin is tied to VIN. (Continued) Line Transient Response (VIN = VOUT + 1V to VOUT + 1.6V) Line Transient Response (VIN = VOUT + 1V to VOUT + 1.6V) 20020326 20020327 Line Transient Response (VIN = VOUT + 1V to VOUT + 1.6V) Line Transient Response (VIN = VOUT + 1V to VOUT + 1.6V) 20020328 20020329 Enable Response (TON) Enable Response (TON) 20020330 20020331 As stated in notes 3 and 5 in the electrical specifications sections, the allowable power dissipation for the device in a given package can be calculated using the equation: Application Hints POWER DISSIPATION AND DEVICE OPERATION The permissible power dissipation for any package is a measure of the capability of the device to pass heat from the power source, the junctions of the IC, to the ultimate heat sink, the ambient environment. Thus, the power dissipation is dependant on the ambient temperature and the thermal resistance across the various interfaces between the die and ambient air. www.national.com With a θJA = 50˚C/W, the device in theLLP package returns a value of 2.0W with a maximum junction temperature of 8 NOISE BYPASS CAPACITOR (Continued) Connecting a 0.033µF capacitor between the CBP pin and ground significantly reduces noise on the regulator output. This cap is connected directly to a high impedance node in the bad gap reference circuit. Any significant loading on this node will cause a change on the regulated output voltage. For this reason, DC leakage current through this pin must be kept as low as possible for best output voltage accuracy. 125˚C and an ambient temperature of 25˚C. The device in a MSOP package returns a figure of 0.476W, ( θJA = 210˚C/ W). The actual power dissipation across the device can be represented by the following equation: PD = (VIN − VOUT) x IOUT This establishes the relationship between the power dissipation allowed due to thermal considerations, the voltage drop across the device, and the continuous current capability of the device. The device can deliver 300mA but care must be taken when choosing the continuous current output for the device under the operating load conditions. The types of capacitors best suited for the noise bypass capacitor are ceramic and film. Hight-quality ceramic capacitors with either NPO or COG dielectric typically have very low leakage. Polypropolene and polycarbonate film capacitors are available in small surface-mount packages and typically have extremely low leakage current. Unlike many other LDO’s, addition of a noise reduction capacitor does not effect the transient response of the device. EXTERNAL CAPACITORS Like any low-dropout regulator, the LP3981 requires external capacitors for regulator stability. The LP3981 is specifically designed for portable applications requiring minimum board space and smallest components. These capacitors must be correctly selected for good performance. CAPACITOR CHARACTERISTICS The LP3981 is designed to work with ceramic capacitors on the output to take advantage of the benefits they offer: for capacitance values in the range of 1µF to 4.7µF range, ceramic capacitors are the smallest, least expensive and have the lowest ESR values (which makes them best for eliminating high frequency noise). The ESR of a typical 1µF ceramic capacitor is in the range of 20 mΩ to 40 mΩ, which easily meets the ESR requirement for stability by the LP3981. The ceramic capacitor’s capacitance can vary with temperature. Most large value ceramic capacitors () 2.2µF) are manufactured with Z5U or Y5V temperature characteristics, which results in the capacitance dropping by more than 50% as the temperature goes from 25˚C to 85˚C. INPUT CAPACITOR An input capacitance of ) 2.2µF is required between the LP3981 input pin and ground (the amount of the capacitance may be increased without limit). This capacitor must be located a distance of not more than 1cm from the input pin and returned to a clean analog ground. Any good quality ceramic, tantalum, or film capacitor may be used at the input. Important: Tantalum capacitors can suffer catastrophic failures due to surge current when connected to a lowimpedance source of power (like a battery or a very large capacitor). If a tantalum capacitor is used at the input, it must be guaranteed by the manufacturer to have a surge current rating sufficient for the application. There are no requirements for the ESR on the input capacitor, but tolerance and temperature coefficient must be considered when selecting the capacitor to ensure the capacitance will be ) 2.2µF over the entire operating temperature range. A better choice for temperature coefficient in a ceramic capacitor is X7R, which holds the capacitance within ± 15%. Tantalum capacitors are less desirable than ceramic for use as output capacitors because they are more expensive when comparing equivalent capacitance and voltage ratings in the 1µF to 4.7µF range. Another important consideration is that tantalum capacitors have higher ESR values than equivalent size ceramics. This means that while it may be possible to find a tantalum capacitor with an ESR value within the stable range, it would have to be larger in capacitance (which means bigger and more costly ) than a ceramic capacitor with the same ESR value. It should also be noted that the ESR of a typical tantalum will increase about 2:1 as the temperature goes from 25˚C down to −40˚C, so some guard band must be allowed. OUTPUT CAPACITOR The LP3981 is designed specifically to work with very small ceramic output capacitors. A ceramic capacitor (dielectric types Z5U, Y5V or X7R) in 2.2 to 22 µF range with 5mΩ to 500mΩ ESR range is suitable in the LP3981 application circuit. It may also be possible to use tantalum or film capacitors at the output, but these are not as attractive for reasons of size and cost (see next section Capacitor Characteristics). The output capacitor must meet the requirement for minimum amount of capacitance and also have an ESR (Equivalent Series Resistance) value which is within a stable range (5 mΩ to 500 mΩ). ON/OFF INPUT OPERATION The LP3981 is turned off by pulling the VEN pin low, and turned on by pulling it high. If this feature is not used, the VEN pin should be tied to VIN to keep the regulator output on at all time. To assure proper operation, the signal source used to drive the VEN input must be able to swing above and below the specified turn-on/off voltage thresholds listed in the Electrical Characteristics section under VIL and VIH. NO-LOAD STABILITY The LP3981 will remain stable and in regulation with no external load. This is specially important in CMOS RAM keep-alive applications. FAST ON-TIME The LP3981 utilizes a speed up circuitry to ramp up the internal VREF voltage to its final value to achieve a fast output turn on time. 9 www.national.com LP3981 Application Hints LP3981 Physical Dimensions inches (millimeters) unless otherwise noted NS Package Number MUA008AE www.national.com 10 LP3981 Micropower, 300mA Ultra Low-Dropout CMOS Voltage Regulator Physical Dimensions inches (millimeters) unless otherwise noted (Continued) NS Package Number LDC06D LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT AND GENERAL COUNSEL OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. National Semiconductor Americas Customer Support Center Email: [email protected] Tel: 1-800-272-9959 www.national.com National Semiconductor Europe Customer Support Center Fax: +49 (0) 180-530 85 86 Email: [email protected] Deutsch Tel: +49 (0) 69 9508 6208 English Tel: +44 (0) 870 24 0 2171 Français Tel: +33 (0) 1 41 91 8790 2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. 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