TP5510 Full Duplex Analog Front End (AFE) for Consumer Applications General Description Features The TP5510 consists of a m-law monolithic AFE device utilizing the A/D and D/A conversion architecture shown in Figure 1 , and a serial data interface. The device is fabricated using National’s advanced double-poly CMOS process (microCMOS). The A/D portion of the device consists of an input gain adjust amplifier, an active RC pre-filter which eliminates very high frequency noise, and a switched-capacitor band-pass filter that rejects signals below 200 Hz and above 3400 Hz. Also included are auto-zero circuitry and a compressing A/D which samples the filtered signal and converts it to the m-law digital format. The decode portion of the device consists of an expanding D/A, which reconstructs the analog signal from the compressed m-law code, a low-pass filter which corrects for the sin x/x response of the D/A output and rejects signals above 3400 Hz, followed by a singleended power amplifier capable of driving low impedance loads. The device requires a 1.536 MHz, 1.544 MHz or 2.048 MHz master clock, bit clocks which may vary from 64 kHz to 2.048 MHz; and 8 kHz frame sync pulses. Y Y Y Y Y Y Y Y Y Y Y Y Y Complete A/D and D/A with filter system including: Ð Serial Data Interface Ð Encode high-pass and low-pass filter Ð Decode low-pass filter with sin x/x correction Ð Active RC noise filters Ð m-law compatible A/D and D/A Ð Internal precision voltage reference Ð Internal auto-zero circuitry m-lawÐTP5510 g 5V operation Low operating powerÐtypically 60 mW Power-down standby modeÐtypically 3 mW Automatic power-down TTL or CMOS compatible digital interfaces Maximizes PC card circuit density Plastic DIP and SOIC packages 8-bit digital I/O 13-bit dynamic range Use with DSP processor Applications: Tapeless Answering Machines, Cordless Phones, Cellular Radio Connection Diagram Dual-In-Line Package TL/H/11186 – 1 Top View Order Number TP5510WM See NS Package Number M16B Order Number TP5510N See NS Package Number N16A TRI-STATEÉ is a registered trademark of National Semiconductor Corporation. C1996 National Semiconductor Corporation TL/H/11186 RRD-B30M27/Printed in U. S. A. http://www.national.com TP5510 Full Duplex Analog Front End (AFE) for Consumer Applications February 1997 Block Diagram TL/H/11186 – 2 FIGURE 1 Pin Description Symbol VBB GNDA VFDO Analog output of the receive power amplifier. VCC Positive power supply pin. VCC e a 5V g 5%. http://www.national.com Symbol Function Negative power supply pin. VBB e b5V g 5%. Analog ground. All signals are referenced to this pin. FSD DD Function Decode frame sync pulse which enables BCLKR to shift data into DD. FSD is an 8 kHz pulse train. See Figures 2 and 3 for timing details. Decode data input. Data is shifted into DD following the FSD leading edge. BCLKD/CLKSEL The bit clock which shifts data into DD after the FSD leading edge. May vary from 64 kHz to 2.048 MHz. Alternatively, may be a logic input which selects either 1.536 MHz/1.544 MHz or 2.048 MHz for master clock in synchronous mode and BCLKD is used for both encode and decode directions (see Table 1). 2 Pin Description (Continued) Symbol MCLKD/PDN and the BCLKD/CLKSEL can be used to select the proper internal divider for a master clock of 1.536 MHz, 1.544 MHz or 2.048 MHz. For 1.544 MHz operation, the device automatically compensates for the 193rd clock pulse each frame. With a fixed level on the BCLKD/CLKSEL pin, BCLKE will be selected as the bit clock for both the encode and decode directions. Table 1 indicates the frequencies of operation which can be selected, depending on the state of BCLKD/ CLKSEL. In this synchronous mode, the bit clock, BCLKE, may be from 64 kHz to 2.048 MHz, but must be synchronous with MCLKE. Each FSE pulse begins the encoding cycle and the data from the previous encode cycle is shifted out of the enabled DE output on the positive edge of BCLKE. After 8-bit clock periods, the TRI-STATE DE output is returned to a high impedance state. With an FSD pulse, data is latched via the DD input on the negative edge of BCLKE (or BCLKD if running). FSE and FSD must be synchronous with MCLKE/D. Function Encode master clock. Must be 1.536 MHz, 1.544 MHz or 2.048 MHz. May be asynchronous with MCLKE, but should be synchronous with MCLKE for best performance. When MCLKD is connected continuously low, MCLKE is selected for all internal timing. When MCLKD is connected continuously high, the device is powered down. MCLKE Encode master clock. Must be 1.536 MHz, 1.544 MHz or 2.048 MHz. May be asynchronous with MCLKD. Best performance is realized from synchronous operation. FSE Encode frame sync pulse input which enables BCLKE to shift out the data on DE. FSE is an 8 kHz pulse train, see Figures 2 and 3 for timing details. BCLKE The bit clock which shifts out the data on DE. May vary from 64 kHz to 2.048 MHz, but must be synchronous with MCLKE. DE The TRI-STATEÉ data output which is enabled by FSE. TSE Open drain output which pulses low during the A/D time slot. GSE Analog output of the encode input amplifier. Used to externally set gain. VFEIb Inverting input of the encode input amplifier. VFEI a Non-inverting input of the encode input amplifier. TABLE I. Selection of Master Clock Frequencies BCLKD/CLKSEL Master Clock Frequency Selected TP5510 Clocked 0 1 1.536 MHz or 1.544 MHz 2.048 MHz 1.536 MHz or 1.544 MHz ASYNCHRONOUS OPERATION For asynchronous operation, separate encode and decode clocks may be applied. MCLKE and MCLKD must be 1.536 MHz or 1.544 MHz for the TP5510, and need not be synchronous. For best transmission performance, however, MCLKD should be synchronous with MCLKE, which is easily achieved by applying only static logic levels to the MCLKD/ PDN pin. This will automatically connect MCLKE to all internal MCLKD functions (see Pin Description). For 1.544 MHz operation, the device automatically compensates for the 193rd clock pulse each frame. FSE starts each A/D conversion cycle and must be synchronous with MCLKE and BCLKE. FSD starts each D/A conversion cycle and must be synchronous with BCLKD. BCLKD must be a clock, the logic levels shown in Table 1 are not valid in asynchronous mode. BCLKE and BCLKD may operate from 64 kHz to 2.048 MHz. Functional Description POWER-UP When power is first applied, power-on reset circuitry initializes the AFE and places it into a power-down state. All nonessential circuits are deactivated and the DE and VFDO outputs are put in high impedance states. To power-up the device, a logical low level or clock must be applied to the MCLKD/PDN pin and FSE and/or FSD pulses must be present. Thus, 2 power-down control modes are available. The first is to pull the MCLKD/PDN pin high; the alternative is to hold both FSE and FSD inputs continuously lowÐthe device will power-down approximately 2 ms after the last FSE or FSD pulse. Power-up will occur on the first FSE or FSD pulse. The TRI-STATE data output, DE, will remain in the high impedance state until the second FSE pulse. SHORT FRAME SYNC OPERATION The AFE can utilize either a short frame sync pulse or a long frame sync pulse. Upon power initialization, the device assumes a short frame mode. In this mode, both frame sync pulses, FSE and FSD, must be one bit clock period long, with timing relationships specified in Figure 2 . With FSE high during a falling edge of BCLKE, the next rising edge of BCLKE enables the DE TRI-STATE output buffer, which will output the sign bit. The following seven rising edges clock out the remaining seven bits, and the next falling edge disables the DE output. With FSD high during a falling edge of BCLKD (BCLKE in synchronous mode), the next falling edge of BCLKE latches in the sign bit. The following seven falling SYNCHRONOUS OPERATION For synchronous operation, the same master clock and bit clock should be used for both the encode and decode directions. In this mode, a clock must be applied to MCLKE and the MCLKD/PDN pin can be used as a power-down control. A low level on MCLKD/PDN powers up the device and a high level powers down the device. In either case, MCLKE will be selected as the master clock for both the encode and decode circuits. A bit clock must also be applied to BCLKE 3 http://www.national.com Functional Description (Continued) pacitor bandpass filter clocked at 256 kHz. The output of this filter directly drives the A/D sample-and-hold circuit. The A/D is of compressing type according to m-law coding conventions. A precision voltage reference is trimmed in manufacturing to provide an input overload (tMAX) of nominally 2.5V peak (See Table of Transmission Characteristics). The FSE frame sync pulse controls the sampling of the filter output, and then the successive-approximation encoding cycle begins. The 8-bit code is then loaded into a buffer and shifted out through DE at the next FSE pulse. The total encoding delay will be approximately 165 ms (due to the encode filter) plus 125 ms (due to encoding delay), which totals 290 ms. Any offset voltage due to the filters or comparator is cancelled by sign bit integration. edges latch in the seven remaining bits. Both devices may utilize the short frame sync pulse in synchronous or asynchronous operating mode. LONG FRAME SYNC OPERATION To use the long frame mode, both the frame sync pulses, FSE and FSD, must be three or more bit clock periods long, with timing relationships specified in Figure 3 . Based on the transmit frame sync, FSE, the AFE will sense whether short or long frame sync pulses are being used. For 64 kHz operation, the frame sync pulse must be kept low for a minimum of 160 ns. The DE TRI-STATE output buffer is enabled with the rising edge of FSE or the rising edge of BCLKE, whichever comes later, and the first bit clocked out is the sign bit. The following seven BCLKE rising edges clock out the remaining seven bits. The DE output is disabled by the falling BCLKE edge following the eighth rising edge, or by FSE going low, whichever comes later. A rising edge on the decode frame sync pulse, FSD, will cause the data at DD to be latched in on the next eight falling edges of BCLKD (BCLKE in synchronous mode). Both devices may utilize the long frame sync pulse in synchronous or asynchronous mode. DECODE SECTION The decode section consists of an expanding DAC which drives a fifth order switched-capacitor low pass filter clocked at 256 kHz. The DAC is m-law and the 5th order low pass filter corrects for the sin x/x attenuation due to the 8 kHz sample/hold. The filter is then followed by a 2nd order RC active post-filter/power amplifier capable of driving a 600X load to a level of 7.2 dBm. The decode section is unity-gain. Upon the occurrence of FSD, the data at the DD input is clocked in on the falling edge of the next eight BCLKD (BCLKE) periods. At the end of the DAC time slot, the D/A conversion cycle begins, and 10 ms later the DAC output is updated. The total DAC delay is E 10 ms (DAC update) plus 110 ms (filter delay) plus 62.5 ms ((/2 frame), which gives approximately 180 ms. ENCODE SECTION The encode section input is an operational amplifier with provision for gain adjustment using two external resistors, see Figure 4 . The low noise and wide bandwidth allow gains in excess of 20 dB across the audio passband to be realized. The op amp drives a unity-gain filter consisting of RC active pre-filter, followed by an eighth order switched-ca- http://www.national.com 4 Absolute Maximum Ratings Voltage at any Digital Input or Output If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/Distributors for availability and specifications. VCC to GNDA VCC a 0.3V to GNDAb0.3V b 25§ C to a 125§ C Operating Temperature Range b 65§ C to a 150§ C Storage Temperature Range Lead Temperature (Soldering, 10 seconds) 300§ C ESD (Human Body Model) 2000V Latch-Up Immunity e 100 mA on any Pin 7V VBB to GNDA Voltage at any Analog Input or Output b 7V VCC a 0.3V to VBBb0.3V Electrical Characteristics Unless otherwise noted, limits printed in BOLD characters are guaranteed for VCC e 5.0V g 5%, VBB e b 5.0V g 5%; TA e 0§ C to 70§ C by correlation with 100% electrical testing at TA e 25§ C. All other limits are assured by correlation with other production tests and/or product design and characterization. All signals referenced to GNDA. Typicals specified at VCC e 5.0V, VBB e b5.0V, TA e 25§ C. Symbol Parameter Conditions Min Typ Max Units 0.6 V 0.4 0.4 0.4 V V V DIGITAL INTERFACE VIL Input Low Voltage VIH Input High Voltage VOL Output Low Voltage DE, IL e 3.2 mA SIGD, IL e 1.0 mA TSE, IL e 3.2 mA, Open Drain VOH Output High Voltage DE, IH eb3.2 mA SIGD, IH eb1.0 mA IIL Input Low Current GNDAsVINsVIL, All Digital Inputs b 10 10 mA IIH Input High Current VIHsVINsVCC b 10 10 mA IOZ Output Current in High Impedance State (TRI-STATE) DE, GNDAsVOsVCC b 10 10 200 2.2 V 2.4 2.4 V V mA ANALOG INTERFACE WITH ENCODE INPUT AMPLIFIER (ALL DEVICES) IIEA Input Leakage Current b 2.5V s V s a 2.5V, VFEI a or VFEI b b 200 RIEA Input Resistance b 2.5V s V s a 2.5V, VFEI a or VFEI b 10 ROEA Output Resistance Closed Loop, Unity Gain RLEA Load Resistance GSE nA MX 1 3 10 X kX CLEA Load Capacitance GSE VOEA Output Dynamic Range GSE, RLt10 kX b 2.8 50 AVEA Voltage Gain VFEI a to GSE 5000 FUEA Unity Gain Bandwidth VOSEA Offset Voltage VCMEA Common-Mode Voltage CMRREA l 60 dB CMRREA Common-Mode Rejection Ratio DC Test 60 dB PSRREA Power Supply Rejection Ratio DC Test 60 dB 1 2.8 pF V V/V 2 MHz b 20 20 b 2.5 2.5 mV V ANALOG INTERFACE WITH DECODE FILTER (ALL DEVICES) RODF Output Resistance Pin VFDO RLDF Load Resistance VFDO e g 2.5V CLDF Load Capacitance VOSDO Output DC Offset Voltage 1 3 600 X X b 200 500 pF 200 mV POWER DISSIPATION (ALL DEVICES) ICC0 Power-Down Current No Load (Note) 0.5 3 mA IBB0 Power-Down Current No Load (Note) 0.05 1 mA ICC1 Power-Up Active Current No Load 6.0 12 mA IBB1 Power-Up Active Current No Load 6.0 12 mA Note: ICC0 and IBB0 are measured after first achieving a power-up state. 5 http://www.national.com Timing Specifications Unless otherwise noted, limits printed in BOLD characters are guaranteed for VCC e 5.0V g 5%, VBB e b 5.0V g 5%; TA e 0§ C to 70§ C by correlation with 100% electrical testing at TA e 25§ C. All other limits are assured by correlation with other production tests and/or product design and characterization. All signals referenced to GNDA. Typicals specified at VCC e 5.0V, VBB e b5.0V, TA e 25§ C. All timing parameters are measured at VOH e 2.0V and VOL e 0.7V. See Definitions and Timing Conventions section for test methods information. Symbol Parameter Conditions Min Typ Max Frequency of Master Clocks Depends on the Device Used and the BCLKD/CLKSEL Pin. MCLKE and MCLKD tDM Rise Time of Master Clock MCLKE and MCLKD 50 ns tFM Fall Time of Master Clock MCLKE and MCLKD 50 ns tPB Period of Bit Clock tDB Rise Time of Bit Clock BCLKE and BCLKD tFB Fall Time of Bit Clock BCLKE and BCLKD tWMH Width of Master Clock High MCLKE and MCLKD 160 ns tWML Width of Master Clock Low MCLKE and MCLKD 160 ns tSBFM Set-Up Time from BCLKE High to MCLKE Falling Edge First Bit Clock after the Leading Edge of FSE 100 ns tSFFM Set-Up Time from FSE High to MCLKE Falling Edge Long Frame Only 100 ns tWBH Width of Bit Clock High VIH e 2.2V 160 ns tWBL Width of Bit Clock Low VIL e 0.6V 160 ns tHBFL Holding Time from Bit Clock Low to Frame Sync Long Frame Only 0 ns tHBFS Holding Time from Bit Clock High to Frame Sync Short Frame Only 0 ns tSFB Set-Up Time from Frame Sync to Bit Clock Low Long Frame Only 115 ns tDBD Delay Time from BCLKE High to Data Valid Load e 150 pF plus 2 LSTTL Loads tDBTS Delay Time to TSE Low Load e 150 pF plus 2 LSTTL Loads tDZC Delay Time from BCLKE Low to Data Output Disabled tDZF Delay Time to Valid Data from FSE or BCLKE, Whichever Comes Later tSDB Set-Up Time from DD Valid to BCLKD/E Low 50 ns tHBD Hold Time from BCLKD/E Low to DD Invalid 50 ns tSF Set-Up Time from FSE/D to BCLKE/D Low Short Frame Sync Pulse (1 Bit Clock Period Long) 50 ns tHF Hold Time from BCLKE/D Low to FSE/D Low Short Frame Sync Pulse (1 Bit Clock Period Long) 100 ns tHBFl Hold Time from 3rd Period of Bit Clock Low to Frame Sync (FSE or FSD) Long Frame Sync Pulse (from 3 to 8 Bit Clock Periods Long) 100 ns tWFL Minimum Width of the Frame Sync Pulse (Low Level) 64k Bit/s Operating Mode 160 ns http://www.national.com 1.536 1.544 2.048 Units 1/tPM 485 488 MHz MHz MHz 15725 ns 50 ns 50 ns 0 140 140 ns CL e 0 pF to 150 pF 50 165 ns CL e 0 pF to 150 pF 20 165 ns 6 ns Timing Diagrams TL/H/11186 – 3 FIGURE 2. Short Frame Sync Timing TL/H/11186 – 4 FIGURE 3. Long Frame Sync Timing 7 http://www.national.com Transmission Characteristics Unless otherwise noted, limits printed in BOLD characters are guaranteed for VCC e 5.0V g 5%, VBB e b5.0V g 5%; TA e 0§ C to 70§ C by correlation with 100% electrical testing at TA e 25§ C. All other limits are assured by correlation with other production tests and/or product design and characterization. GNDA e 0V, f e 1.02 kHz, VIN e 0 dBm0, encode input amplifier connected for unity gain non-inverting. Typicals specified at VCC e 5.0V, VBB e b 5.0V, TA e 25§ C. Symbol Parameter Conditions Min Typ Max Units AMPLITUDE RESPONSE Absolute Levels (Definition of Nominal Gain) Nominal 0 dBm0 Level is 4 dBm (600X) 0 dBm0 1.2276 Vrms Max Overload Level TP5510, (3.17 dBm0) 2.501 VPK GEA Encode Gain, Absolute TA e 25§ C, VCC e 5V, VBB eb5V Input at GSE e 0 dBm0 at 1020 Hz GER Encode Gain, Relative to GEA f e 16 Hz f e 50 Hz f e 60 Hz f e 200 Hz f e 300 Hzb3000 Hz f e 3400 Hz f e 4000 Hz f e 4600 Hz and Up, Measure Response from 0 Hz to 4000 Hz b 2.0 b 0.5 b 1.5 tMAX b 0.5 0.5 dB b 35 b 25 b 21 b 0.1 0.15 0.5 b 10 b 25 dB dB dB dB dB dB dB dB GEAT Absolute Encode Gain Variation with Temperature Relative to GEA b 0.3 0.3 dB GERL Encode Gain Variations with Level Sinusoidal Test Method Reference Level eb10 dBm0 VFEI a eb40 dBm0 to a 3 dBm0 VFEI a eb50 dBm0 to b40 dBm0 b 0.4 b 0.8 0.4 0.8 dB dB GDA Decode Gain, Absolute TA e 25§ C, VCC e 5V, VBB eb5V Input e Digital Code Sequence for 0 dBm0 Signal at 1020 Hz b 0.5 0.5 dB GDR Decode Gain, Relative to GDA f e 0 Hz to 3000 Hz f e 3400 Hz f e 4000 Hz b 0.5 b 1.5 0.5 0.5 b 14 dB dB dB GDAT Absolute Decode Gain Variation with Temperature Relative to GDA b 0.3 0.3 dB GDAV Absolute Decode Gain Variation with Supply Voltage Relative to GDA b 0.05 0.05 dB GDRL Decode Gain Variations with Level Sinusoidal Test Method; Reference Input PCM Code Corresponds to an Ideally Encoded PCM Level eb 40 dBm0 to a 3 dBm0 eb 50 dBm0 to b 40 dBm0 eb 55 dBm0 to b 50 dBm0 b 0.4 b 0.8 b 2.5 0.4 0.8 2.5 dB dB dB RL e 600X b 2.5 2.5 V VDO Decode Output Drive Level http://www.national.com 8 Transmission Characteristics Unless otherwise noted, limits printed in BOLD characters are guaranteed for VCC e 5.0V g 5%, VBB e b5.0V g 5%; TA e 0§ C to 70§ C by correlation with 100% electrical testing at TA e 25§ C. All other limits are assured by correlation with other production tests and/or product design and characterization. GNDA e 0V, f e 1.02 kHz, VIN e 0 dBm0, encode input amplifier connected for unity gain non-inverting. Typicals specified at VCC e 5.0V, VBB e b 5.0V, TA e 25§ C. (Continued) Symbol Parameter Conditions Min Typ Max Units 16 dBrnC0 11 dBrnC0 b 53 dBm0 NOISE NEC Encode Noise, C Message Weighted TP5510 (Note 1) 12 NDC Decode Noise, C Message Weighted Digital Code is Alternating Positive and Negative Zero ÐTP5510 8 NDS Noise, Single Frequency f e 0 kHz to 100 kHz, Loop Around Measurement, VFEI a e 0 Vrms PPSRE Positive Power Supply Rejection, Encode VFEI a e b50 dBm0 VCC e 5.0 VDC a 100 mVrms f e 0 kHz – 50 kHz (Note 2) b 30 dBC NPSRE Negative Power Supply Rejection, Encode VFEI a e b50 dBm0 VBB eb5.0 VDC a 100 mVrms f e 0 kHz – 50 kHz (Note 2) b 30 dBC PPSRD Positive Power Supply Rejection, Decode PCM Code Equals Positive Zero VCC e 5.0 VDC a 100 mVrms Measure VFD0 f e 0 Hz – 4000 Hz f e 4 kHz – 50 kHz 30 30 dBC dB PCM Code Equals Positive Zero VBB eb5.0 VDC a 100 mVrms Measure VFD0 f e 0 Hz – 4000 Hz f e 4 kHz – 50 kHz 30 30 dBC dB NPSRD Negative Power Supply Rejection, Decode 9 http://www.national.com Transmission Characteristics Unless otherwise noted, limits printed in BOLD characters are guaranteed for VCC e 5.0V g 5%, VBB e b5.0V g 5%; TA e 0§ C to 70§ C by correlation with 100% electrical testing at TA e 25§ C. All other limits are assured by correlation with other production tests and/or product design and characterization. GNDA e 0V, f e 1.02 kHz, VIN e 0 dBm0, encode input amplifier connected for unity gain non-inverting. Typicals specified at VCC e 5.0V, VBB e b 5.0V, TA e 25§ C. (Continued) Symbol SOS Parameter Conditions Spurious Out-of-Band Signals at the Channel Output Loop Around Measurement, 0 dBm0, 300 Hz to 3400 Hz Input Digital Code Applied at DD. 4600 Hz–7600 Hz 7600 Hz–8400 Hz 8400 Hz–100,000 Hz Min Typ Max Units b 30 dB b 30 b 30 b 30 dB dB dB DISTORTION STDE STDD Signal to Total Distortion Encode or Decode Half-Channel Sinusoidal Test Method (Note 3) Level e 3.0 dBm0 e 0 dBm0 to b 30 dBm0 e b 40 dBm0 SFDE Single Frequency Distortion, Encode b 41 dB SFDD Single Frequency Distortion, Decode b 41 dB IMD Intermodulation Distortion b 35 dB b 90 b 70 dB b 90 b 70 dB 28 30 25 dBC dBC dBC Loop Around Measurement, VFEncode a eb4 dBm0 to b21 dBm0, Two Frequencies in the Range 300 Hz–3400 Hz CROSSTALK CTE-D Encode to Decode Crosstalk, 0 dBm0 Encode Level f e 300 Hz–3400 Hz DD e Quiet Code CTD-E Decode to Encode Crosstalk, 0 dBm0 Decode Level f e 300 Hz–3400 Hz, VFEI e Multitone (Note 2) Format at DE Output TP5510 m-Law VIN (at GSE) e a Full-Scale VIN (at GSE) e 0V VIN (at GSE) ebFull-Scale http://www.national.com 10 1 0 0 0 0 0 0 0 Ð0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 Applications Information minimizes the interaction of ground return currents flowing through a common bus impedance. 0.1 mF supply decoupling capacitors should be connected from this common ground point to VCC and VBB, as close to the device as possible. For best performance, if more than 1 AFE is on a card, the ground point of each AFE on a card should be connected to a common card ground in star formation, rather than via a ground bus. This common ground point should be decoupled to VCC and VBB with 10 mF capacitors. POWER SUPPLIES While the pins of the AFE are well protected against electrical misuse, it is recommended but not mandatory that the standard CMOS practice be followed, ensuring that ground is connected to the device before any other connections are made. In applications where the printed circuit board may be plugged into a ‘‘hot’’ socket with power and clocks already present, an extra long ground pin in the connector should be used. All ground connections to each device should meet at a common point as close as possible to the GNDA pin. This Physical Dimensions inches (millimeters) unless otherwise noted Molded Small Outline Package (WM) Order Number TP5510WM NS Package Number M16B 11 http://www.national.com TP5510 Full Duplex Analog Front End (AFE) for Consumer Applications Physical Dimensions inches (millimeters) unless otherwise noted (Continued) Molded Dual-In-Line Package (N) Order Number TP5510N NS Package Number N16A LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. National Semiconductor Corporation Americas Tel: 1(800) 272-9959 Fax: 1(800) 737-7018 Email: support @ nsc.com http://www.national.com 2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. National Semiconductor Europe Fax: a49 (0) 180-530 85 86 Email: europe.support @ nsc.com Deutsch Tel: a49 (0) 180-530 85 85 English Tel: a49 (0) 180-532 78 32 Fran3ais Tel: a49 (0) 180-532 93 58 Italiano Tel: a49 (0) 180-534 16 80 National Semiconductor Southeast Asia Fax: (852) 2376 3901 Email: sea.support @ nsc.com National Semiconductor Japan Ltd. Tel: 81-3-5620-7561 Fax: 81-3-5620-6179 National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications.