NSC NSC800N

NSC800 TM High-Performance
Low-Power CMOS Microprocessor
General Description
Features
The NSC800 is an 8-bit CMOS microprocessor that functions as the central processing unit (CPU) in National Semiconductor’s NSC800 microcomputer family. National’s
microCMOS technology used to fabricate this device provides system designers with performance equivalent to
comparable NMOS products, but with the low power advantage of CMOS. Some of the many system functions incorporated on the device, are vectored priority interrupts, refresh
control, power-save feature and interrupt acknowledge. The
NSC800 is available in dual-in-line and surface mounted
chip carrier packages.
The system designer can choose not only from the dedicated CMOS peripherals that allow direct interfacing to the
NSC800 but from the full line of National’s CMOS products
to allow a low-power system solution. The dedicated peripherals include NSC810A RAM I/O Timer, NSC858 UART,
and NSC831 I/O.
All devices are available in commercial, industrial and military temperature ranges along with two added reliability
flows. The first is an extended burn in test and the second is
the military class C screening in accordance with Method
5004 of MIL-STD-883.
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Fully compatible with Z80É instruction set:
Powerful set of 158 instructions
10 addressing modes
22 internal registers
Low power: 50 mW at 5V VCC
Unique power-save feature
Multiplexed bus structure
Schmitt trigger input on reset
On-chip bus controller and clock generator
Variable power supply 2.4Vb6.0V
On-chip 8-bit dynamic RAM refresh circuitry
Speed: 1.0 ms instruction cycle at 4.0 MHz
NSC800-4
4.0 MHz
NSC800-35 3.5 MHz
NSC800-3
2.5 MHz
NSC800-1
1.0 MHz
Capable of addressing 64k bytes of memory and 256
I/O devices
Five interrupt request lines on-chip
Block Diagram
TL/C/5171 – 73
NSC800TM is a trademark of National Semiconductor Corp.
TRI-STATEÉ is a registered trademark of National Semiconductor Corp.
Z80É is a registered trademark of Zilog Corp.
C1995 National Semiconductor Corporation
TL/C/5171
RRD-B30M105/Printed in U. S. A.
NSC800 High-Performance Low-Power CMOS Microprocessor
June 1992
Table of Contents
1.0 ABSOLUTE MAXIMUM RATINGS
9.0 TIMING AND CONTROL
9.5 Bus Access Control
9.6 Interrupt Control
2.0 OPERATING CONDITIONS
3.0 DC ELECTRICAL CHARACTERISTICS
4.0 AC ELECTRICAL CHARACTERISTICS
NSC800 SOFTWARE
5.0 TIMING WAVEFORMS
NSC800 HARDWARE
10.0 INTRODUCTION
11.0 ADDRESSING MODES
6.0 PIN DESCRIPTIONS
11.1 Register
11.2 Implied
11.3 Immediate
11.4 Immediate Extended
11.5 Direct Addressing
11.6 Register Indirect
11.7 Indexed
11.8 Relative
11.9 Modified Page Zero
11.10 Bit
6.1 Input Signals
6.2 Output Signals
6.3 Input/Output Signals
7.0 CONNECTION DIAGRAMS
8.0 FUNCTIONAL DESCRIPTION
8.1 Register Array
8.2 Dedicated Registers
8.2.1 Program Counter
8.2.2 Stack Pointer
8.2.3 Index Register
8.2.4 Interrupt Register
8.2.5 Refresh Register
12.0 INSTRUCTION SET
12.1 Instruction Set Index/Alphabetical
12.2 Instruction Set Mnemonic Notation
12.3 Assembled Object Code Notation
12.4 8-Bit Loads
12.5 16-Bit Loads
12.6 8-Bit Arithmetic
12.7 16-Bit Arithmetic
12.8 Bit Set, Reset, and Test
12.9 Rotate and Shift
12.10 Exchanges
12.11 Memory Block Moves and Searches
12.12 Input/Output
12.13 CPU Control
12.14 Program Control
12.15 Instruction Set: Alphabetical Order
12.16 Instruction Set: Numerical Order
8.3 CPU Working and Alternate Register Sets
8.3.1 CPU Working Registers
8.3.2 Alternate Registers
8.4 Register Functions
8.4.1 Accumulator
8.4.2 F RegisterÐFlags
8.4.3 Carry (C)
8.4.4 Adds/Subtract (N)
8.4.5 Parity/Overflow (P/V)
8.4.6 Half Carry (H)
8.4.7 Zero Flag (Z)
8.4.8 Sign Flag (S)
8.4.9 Additional General Purpose Registers
8.4.10 Alternate Configurations
13.0 DATA ACQUISITION SYSTEM
8.5 Arithmetic Logic Unit (ALU)
8.6 Instruction Register and Decoder
14.0 NSC800M/883B MIL STD 883/CLASS C
SCREENING
9.0 TIMING AND CONTROL
15.0 BURN-IN CIRCUITS
9.1 Internal Clock Generator
9.2 CPU Timing
9.3 Initialization
9.4 Power Save Feature
16.0 ORDERING INFORMATION
17.0 RELIABILITY INFORMATION
2
1.0 Absolute Maximum Ratings (Note 1)
2.0 Operating Conditions
NSC800-1
x TA e 0§ C to a 70§ C
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Storage Temperature
Voltage on Any Pin
with Respect to Ground
TA e b40§ C to a 85§ C
NSC800-3
b 65§ C to a 150§ C
b 0.3V to VCC a 0.3V
Maximum VCC
Power Dissipation
Lead Temp. (Soldering, 10 seconds)
7V
1W
300§ C
x TA e 0§ C to a 70§ C
NSC800-35/883C
NSC800-4
x
x
NSC800-4MIL
x
TA
TA
TA
TA
TA
TA
e b 40§ C to a 85§ C
e b 55§ C to a 125§ C
e b 55§ C to a 125§ C
e 0§ C to a 70§ C
e b 40§ C to a 85§ C
e b 55§ C to a 90§ C
3.0 DC Electrical Characteristics VCC e 5V g 10%, GND e 0V, unless otherwise specified.
Max
Units
VIH
Symbol
Logical 1 Input Voltage
Parameter
Conditions
0.8 VCC
VCC
V
VIL
Logical 0 Input Voltage
0
0.2 VCC
V
VHY
Hysteresis at RESET IN input
VCC e 5V
0.25
VOH1
Logical 1 Output Voltage
IOUT e b1.0 mA
2.4
VOH2
Logical 1 Output Voltage
IOUT e b10 mA
VCC b0.5
VOL1
Logical 0 Output Voltage
IOUT e 2 mA
0
0.4
V
VOL2
Logical 0 Output Voltage
IOUT e 10 mA
0
0.1
V
IIL
Input Leakage Current
0 s VIN s VCC
b 10.0
10.0
mA
IOL
Output Leakage Current
0 s VIN s VCC
b 10.0
10.0
mA
ICC
Active Supply Current
IOUT e 0, f(XIN) e 2 MHz, TA e 25§ C
8
11
mA
ICC
Active Supply Current
IOUT e 0, f(XIN) e 5 MHz, TA e 25§ C
10
15
mA
ICC
Active Supply Current
IOUT e 0, f(XIN) e 7 MHz,
TA e 25§ C
15
21
mA
ICC
Active Supply Current
IOUT e 0, f(XIN) e 8 MHz, TA e 25§ C
15
21
mA
IQ
Quiescent Current
IOUT e 0, PS e 0, VIN e 0 or VIN e VCC
f(XIN) e 0 MHz, TA e 25§ C, XIN e 0, CLK e 1
2
5
mA
IPS
Power-Save Current
IOUT e 0, PS e 0, VIN e 0 or VIN e VCC
f(XIN) e 5.0 MHz , TA e 25§
5
7
mA
CIN
Input Capacitance
6
10
pF
COUT
Output Capacitance
8
12
pF
VCC
Power Supply Voltage
5
6
V
(Note 2)
Min
2.4
Typ
0.5
V
V
V
Note 1: Absolute Maximum Ratings indicate limits beyond which permanent damage may occur. Continuous operation at these limits is not intended and should be
limited to those conditions specified under DC Electrical Characteristics.
Note 2: CPU operation at lower voltages will reduce the maximum operating speed. Operation at voltages other than 5V g 10% is guaranteed by design, not
tested.
3
4.0 AC Electrical Characteristics VCC e 5V g 10%, GND e 0V, unless otherwise specified
Symbol
Parameter
NSC800-1
NSC800-3
NSC800-35
NSC800-4
Min
Max
Min
Max
Min
Max
Min
Units
Notes
Max
tX
Period at XIN and XOUT
Pins
500
3333 200 3333
142
3333
125 3333
ns
T
Period at Clock Output
( e 2 tX)
1000 6667 400 6667
284
6667
250 6667
ns
tR
Clock Rise Time
110
110
90
80
ns
Measured from
10% – 90% of signal
tF
Clock Fall Time
70
60
55
50
ns
Measured from
10% – 90% of signal
tL
Clock Low Time
435
150
90
80
ns
50% duty cycle, square
wave input on XIN
tH
Clock High Time
450
145
85
75
ns
50% duty cycle, square
wave input on XIN
tACC(OP)
ALE to Valid Data
1340
490
340
300
ns
Add t for each WAIT STATE
tACC(MR)
ALE to Valid Data
1875
620
405
360
ns
Add t for each WAIT STATE
tAFR
AD(0 – 7) Float after
RD Falling
0
0
0
0
ns
tBABE
BACK Rising to Bus
Enable
1000
400
300
250
ns
tBABF
BACK Falling to
Bus Float
50
50
50
50
ns
tBACL
BACK Fall to CLK
Falling
tBRH
BREQ Hold Time
tBRS
BREQ Set-Up Time
tCAF
Clock Falling ALE
Falling
0
70
0
65
0
60
0
55
ns
tCAR
Clock Rising to ALE
Rising
0
100
0
100
0
90
0
80
ns
tCRD
Clock Rising to
Read Rising
100
90
90
80
ns
tCRF
Clock Rising to
Refresh Falling
80
70
70
65
ns
tDAI
ALE Falling to INTA
Falling
445
tDAR
ALE Falling to
RD Falling
400
575
160
250
100
180
90
160
ns
tDAW
ALE Falling to
WR Falling
900
1010 350
420
225
300
200
265
ns
tD(BACK)1 ALE Falling to BACK
Falling
2460
975
tD(BACK)2 BREQ Rising to BACK
Rising
500
1610 200
700
1360
475
1685 200
760
550
250
tD(I)
ALE Falling to INTR,
NMI, RSTA-C, PS,
BREQ, Inputs Valid
tDPA
Rising PS to
Falling ALE
tD(WAIT)
ALE Falling to
WAIT Input Valid
425
125
60
55
ns
ns
0
0
0
0
100
50
50
45
500
160
95
85
635
140
540
580
170
OPÐ Opcode Fetch
MRÐ Memory Read
4
ns
560
125
284
140
ns
125
ns
Add t for each WAIT state
Add t for opcode fetch cycles
475
ns
250
ns
Add t for each WAIT state
Add t for opcode fetch cycles
510
ns
See Figure 14 also
125
ns
4.0 AC Electrical Characteristics VCC e 5V g 10%, GND e 0V, unless otherwise specified (Continued)
Symbol
Parameter
NSC800-1
NSC800-3
NSC800-35
NSC800-4
Min
Min
Min
Min
Max
Max
Max
Units
TH(ADH)1 A(8–15) Hold Time During
Opcode Fetch
0
0
0
0
ns
TH(ADH)2 A(8–15) Hold Time During
Memory or IO, RD and WR
400
100
85
60
ns
TH(ADL)
AD(0–7) Hold Time
100
60
35
30
ns
TH(WD)
Write Data Hold Time
400
100
85
75
ns
tINH
Interrupt Hold Time
0
0
0
0
ns
tINS
Interrupt Set-Up Time
100
50
50
45
ns
tNMI
Width of NMI Input
50
30
25
20
ns
tRDH
Data Hold after Read
0
0
0
0
ns
tRFLF
RFSH Rising to ALE
Falling
60
50
45
40
ns
tRL(MR)
RD Rising to ALE Rising
(Memory Read)
390
100
50
45
ns
tS(AD)
AD(0–7) Set-Up Time
300
45
45
40
ns
tS(ALE)
A(8–15), SO, SI, IO/M
Set-Up Time
350
70
55
50
ns
tS(WD)
Write Data Set-Up Time
385
75
35
30
ns
tW(ALE)
ALE Width
430
130
115
100
ns
tWH
WAIT Hold Time
0
0
0
0
ns
tW(I)
Width of INTR, RSTA-C,
PS, BREQ
500
200
140
125
ns
tW(INTA)
INTA Strobe Width
1000
400
225
200
ns
tWL
WR Rising to ALE Rising
450
130
70
70
ns
tW(RD)
Read Strobe Width During
Opcode Fetch
960
360
210
185
ns
tW(RFSH)
Refresh Strobe Width
1925
725
450
395
ns
tWS
WAIT Set-Up Time
100
70
60
55
ns
tW(WAIT)
WAIT Input Width
550
250
195
175
ns
tW(WR)
Write Strobe Width
985
370
250
220
tXCF
XIN to Clock Falling
25
100
15
95
5
90
5
80
ns
tXCR
XIN to Clock Rising
25
85
15
85
5
90
5
80
ns
ns
Note 1: Test conditions: t e 1000 ns for NSC800-1, 400 ns for NSC800, 285 ns for NSC800-35, 250 ns for NSC800-4.
Note 2: Output timings are measured with a purely capacitive load of 100 pF.
5
Notes
Max
Add two t states for first
INTA of each interrupt
response string Add t for
each WAIT state
Add t for each WAIT
State Add t/2 for Memory
Read Cycles
Add t for each WAIT state
5.0 Timing Waveforms
Opcode Fetch Cycle
TL/C/5171 – 3
Memory Read and Write Cycle
TL/C/5171 – 4
6
5.0 Timing Waveforms (Continued)
InterruptÐPower-Save Cycle
TL/C/5171 – 5
Note 1: This t state is the last t state of the last M cycle of any instruction.
Note 2: Response to INTR input.
Note 3: Response to PS input.
Bus Acknowledge Cycle
TL/C/5171 – 6
*Waveform not drawn to proportion. Use only for specifying test points.
AC Testing Input/Output Waveform
AC Testing Load Circuit
TL/C/5171 – 7
TL/C/5171 – 8
7
NSC800 HARDWARE
6.0 Pin Descriptions
6.1 INPUT SIGNALS
Reset Input (RESET IN): Active low. Sets A (8–15) and AD
(0 – 7) to TRI-STATEÉ (high impedance). Clears the contents of PC, I and R registers, disables interrupts, and activates reset out.
Bus Request (BREQ): Active low. Used when another device requests the system bus. The NSC800 recognizes
BREQ at the end of the current machine cycle, and sets
A(8 – 15), AD(0 – 7), IO/M, RD, and WR to the high impedance state. RFSH is high during a bus request cycle. The
CPU acknowledges the bus request via the BACK output
signal.
Non-Maskable Interrupt (NMI): Active low. The non-maskable interrupt, generated by the peripheral device(s), is the
highest priority interrupt. The edge sensitive interrupt requires only a pulse to set an internal flip-flop which generates the internal interrupt request. The NMI flip-flop is monitored on the same clock edge as the other interrupts. It
must also meet the minimum set-up time spec for the interrupt to be accepted in the current machine instruction.
When the processor accepts the interrupt the flip-flop resets
automatically. Interrupt execution is independent of the interrupt enable flip-flop. NMI execution results in saving the
PC on the stack and automatic branching to restart address
X’0066 in memory.
Restart Interrupts, A, B, C (RSTA, RSTB, RSTC): Active
low level sensitive. The CPU recognizes restarts generated
by the peripherals at the end of the current instruction, if
their respective interrupt enable and master enable bits are
set. Execution is identical to NMI except the interrupts vector to the following restart addresses:
Restart
Name
Address (X’)
0066
NMI
RSTA
003C
RSTB
0034
RSTC
002C
INTR (Mode 1)
0038
The order of priority is fixed. The list above starts with the
highest priority.
Interrupt Request (INTR): Active low, level sensitive. The
CPU recognizes an interrupt request at the end of the current instruction provided that the interrupt enable and master interrupt enable bits are set. INTR is the lowest priority
interrupt. Program control selects one of three response
modes which determines the method of servicing INTR in
conjunction with INTA. See Interrupt Control.
Wait (WAIT): Active low. When set low during RD, WR or
INTA machine cycles (during the WR machine cycle, wait
must be valid prior to write going active) the CPU extends its
machine cycle in increments of t (wait) states. The wait machine cycle continues until the WAIT input returns high.
The wait strobe input will be accepted only during machine
cycles that have RD, WR or INTA strobes and during the
machine cycle immediately after an interrupt has been accepted by the CPU. The later cycle has its RD strobe suppressed but it will still accept the wait.
Power-Save (PS): Active low. PS is sampled during the last
t state of the current instruction cycle. When PS is low, the
CPU stops executing at the end of current instruction and
keeps itself in the low-power mode. Normal operation resumes when PS returns high (see Power Save Feature description).
CRYSTAL (XIN, XOUT): XIN can be used as an external
clock input. A crystal can be connected across XIN and
XOUT to provide a source for the system clock.
6.2 OUTPUT SIGNALS
Bus Acknowledge (BACK): Active low. BACK indicates to
the bus requesting device that the CPU bus and its control
signals are in the TRI-STATE mode. The requesting device
then commands the bus and its control signals.
Address Bits 8 – 15 [A(8 – 15)]: Active high. These are the
most significant 8 bits of the memory address during a
memory instruction. During an I/O instruction, the port address on the lower 8 address bits gets duplicated onto A(8 –
15). During a BREQ/BACK cycle, the A(8 – 15) bus is in the
TRI-STATE mode.
Reset Out (RESET OUT): Active high. When RESET OUT
is high, it indicates the CPU is being reset. This signal is
normally used to reset the peripheral devices.
Input/Output/Memory (IO/M): An active high on the IO/M
output signifies that the current machine cycle is an input/
output cycle. An active low on the IO/M output signifies that
the current machine cycle is a memory cycle. It is TRISTATE during BREQ/BACK cycles.
Refresh (RFSH): Active low. The refresh output indicates
that the dynamic RAM refresh cycle is in progress. RFSH
goes low during T3 and T4 states of all M1 cycles. During
the refresh cycle, AD(0 – 7) has the refresh address and
A(8 – 15) indicates the interrupt vector register data. RFSH is
high during BREQ/BACK cycles.
Address Latch Enable (ALE): Active high. ALE is active
only during the T1 state of any M cycle and also T3 state of
the M1 cycle. The high to low transition of ALE indicates
that a valid memory, I/O or refresh address is available on
the AD(0 – 7) lines.
Read Strobe (RD): Active low. The CPU receives data via
the AD(0 – 7) lines on the trailing edge of the RD strobe. The
RD line is in the TRI-STATE mode during BREQ/BACK cycles.
Write Strobe (WR): Active low. The CPU sends data via the
AD(0 – 7) lines while the WR strobe is low. The WR line is in
the TRI-STATE mode during BREQ/BACK cycles.
Clock (CLK): CLK is the output provided for use as a system clock. The CLK output is a square wave at one half the
input frequency.
Interrupt Acknowledge (INTA): Active low. This signal
strobes the interrupt response vector from the interrupting
peripheral devices onto the AD(0 – 7) lines. INTA is active
during the M1 cycle immediately following the t state where
the CPU recognized the INTR interrupt request.
Two of the three interrupt request modes use INTA. In
mode 0 one to four INTA signals strobe a one to four byte
instruction onto the AD(0 – 7) lines. In mode 2 one INTA signal strobes the lower byte of an interrupt response vector
onto the bus. In mode 1, INTA is inactive and the CPU response to INTR is the same as for an NMI or restart interrupt.
8
6.0 Pin Descriptions (Continued)
Status (SO, S1): Bus status outputs provide encoded information regarding the current M cycle as follows:
Status
Machine Cycle
Opcode Fetch
Memory Read
Memory Write
I/O Read
I/O Write
Halt*
Internal Operation*
Acknowledge of Int**
6.3 INPUT/OUTPUT SIGNALS
Multiplexed Address/Data [AD(0 – 7)]: Active high
At RD Time:
Input data to CPU.
At WR Time:
Output data from CPU.
At Falling Edge Least significant byte of address
of ALE Time:
during memory reference cycle. 8-bit
port address during I/O reference
cycle.
During BREQ/ High impedance.
BACK Cycle:
Control
S0
S1
IO/M
RD
WR
1
0
1
0
1
0
0
1
1
1
0
1
0
0
1
1
0
0
0
1
1
0
0
0
0
0
1
0
1
0
1
1
1
1
0
1
0
1
1
1
*ALE is not suppressed in this cycle.
**This is the cycle that occurs immediately after the CPU accepts an interrupt (RSTA, RSTB, RSTC, INTR, NMI).
Note 1: During halt, CPU continues to do dummy opcode fetch from location
following the halt instruction with a halt status. This is so CPU can continue
to do its dynamic RAM refresh.
Note 2: No early status is provided for interrupt or hardware restarts.
7.0 Connection Diagrams
Chip Carrier Package
Dual-In-Line Package
Top View
TL/C/5171 – 11
Order Number NSC800E or V
See NS Package E44B or V44A
Top View
TL/C/5171–10
Order Number NSC800D or N
See NS Package D40C or N40A
9
8.0 Functional Description
As illustrated in Figure 1 , the NSC800 is an 8-bit parallel
device. The major functional blocks are: the ALU, register
array, interrupt control, timing and control logic. These areas
are connected via the 8-bit internal data bus. Detailed descriptions of these blocks ae provided in the following sections.
This section reviews the CPU architecture shown below, focusing on the functional aspects from a hardware perspective, including timing details.
TL/C/5171 – 9
Note: Applicable pinout for 40-pin
dual-in-line package within parentheses
FIGURE 1. NSC800 CPU Functional Block Diagram
10
8.0 Functional Description (Continued)
8.2.2 Stack Pointer (SP)
8.1 REGISTER ARRAY
The NSC800 register array is divided into two parts: the
dedicated registers and the working registers, as shown in
Figure 2 .
Main Reg. Set
Alternate Reg. Set
V
â
WV
â
The 16-bit stack pointer contains the address of the current
top of stack that is located in external system RAM. The
stack is organized in a last-in, first-out (LIFO) structure. The
pointer decrements before data is pushed onto the stack,
and increments after data is popped from the stack.
Various operations store or retrieve, data on the stack. This,
along with the usage of subroutine calls and interrupts, allows simple implementation of subroutine and interrupt
nesting as well as alleviating many problems of data manipulation.
8.2.3 Index Register (IX and IY)
The NSC800 contains two index registers to hold independent, 16-bit base addresses used in the indexed addressing
mode. In this mode, an index register, either IX or IY, contains a base address of an area in memory making it a pointer for data tables.
In all instructions employing indexed modes of operation,
another byte acts as a signed two’s complement displacement. This addressing mode enables easy data table manipulations.
8.2.4 Interrupt Register (I)
When the NSC800 provides a Mode 2 response to INTR,
the action taken is an indirect call to the memory location
containing the service routine address. The pointer to the
address of the service routine is formed by two bytes, the
high-byte is from the I Register and the low-byte is from the
interrupting peripheral. The peripheral always provides an
even address for the lower byte (LSB e 0). When the processor receives the lower byte from the peripheral it concatenates it in the following manner:
W
Accumulator Flags Accumulator Flags
A
F
AÊ
FÊ
B
C
BÊ
CÊ
D
E
DÊ
EÊ
H
L
HÊ
LÊ
Interrupt
Vector I
*
Working
Registers
Memory
Refresh R
Index Register IX
Dedicated
Registers
Index Register IY
Stack Pointer SP
Program Counter PC
–
FIGURE 2. NSC800 Register Array
8.2 DEDICATED REGISTERS
There are 6 dedicated registers in the NSC800: two 8-bit
and four 16-bit registers (see Figure 3 ).
Although their contents are under program control, the program has no control over their operational functions, unlike
the CPU working registers. The function of each dedicated
register is described as follows:
CPU Dedicated Registers
Program Counter PC
Stack Pointer SP
Index Register IX
Index Register IY
Interrupt Vector Register I
Memory Refresh Register R
I Register
8 bits
(16)
(16)
(16)
(16)
(8)
(8)
External byte
0
u
The LSB of the external byte must be zero.
FIGURE 4a. Interrupt Register
The even memory location contains the low-order byte, the
next consecutive location contains the high-order byte of
the pointer to the beginning address of the interrupt service
routine.
8.2.5 Refresh Register (R)
For systems that use dynamic memories rather than static
RAM’s, the NSC800 provides an integral 8-bit memory refresh counter. The contents of the register are incremented
after each opcode fetch and are sent out on the lower portion of the address bus, along with a refresh control signal.
This provides a totally transparent refresh cycle and does
not slow down CPU operation.
The program can read and write to the R register, although
this is usually done only for test purposes.
FIGURE 3. Dedicated Registers
8.2.1 Program Counter (PC)
The program counter contains the 16-bit address of the current instruction being fetched from memory. The PC increments after its contents have been transferred to the address lines. When a program jump occurs, the PC receives
the new address which overrides the incrementer.
There are many conditional and unconditional jumps, calls,
and return instructions in the NSC800’s instruction repertoire that allow easy manipulation of this register in controlling the program execution (i.e. JP NZ nn, JR Zd2, CALL
NC, nn).
11
8.0 Functional Description (Continued)
8.3 CPU WORKING AND ALTERNATE REGISTER SETS
8.3.1 CPU Working Registers
8.4 REGISTER FUNCTIONS
8.4.1 Accumulator (A Register)
The portion of the register array shown in Figure 4b represents the CPU working registers. These sixteen 8-bit registers are general-purpose registers because they perform a
multitude of functions, depending on the instruction being
executed. They are grouped together also due to the types
of instructions that use them, particularly alternate set operations.
The F (flag) register is a special-purpose register because
its contents are more a result of machine status rather than
program data. The F register is included because of its interaction with the A register, and its manipulations in the alternate register set operations.
8.3.2 Alternate Registers
The NSC800 registers designated as CPU working registers
have one common feature: the existence of a duplicate register in an alternate register set. This architectural concept
simplifies programming during operations such as interrupt
response, when the machine status represented by the contents of the registers must be saved.
The alternate register concept makes one set of registers
available to the programmer at any given time. Two instructions (EX AF, A‘F’ and EXX), exchange the current working
set of registers with their alternate set. One exchange between the A and F registers and their respective duplicates
(A’ and F’) saves the primary status information contained in
the accumulator and the flag register. The second exchange
instruction performs the exchange between the remaining
registers, B, C, D, E, H, and L, and their respective alternates B’, C’, D’, E’, H’, and L’. This essentially saves the
contents of the original complement of registers while providing the programmer with a usable alternate set.
The A register serves as a source or destination register for
data manipulation instructions. In addition, it serves as the
accumulator for the results of 8-bit arithmetic and logic operations.
The A register also has a special status in some types of
operations; that is, certain addressing modes are reserved
for the A register only, although the function is available for
all the other registers. For example, any register can be
loaded by immediate, register indirect, or indexed addressing modes. The A register, however, can also be loaded via
an additional register indirect addressing.
Another special feature of the A register is that it produces
more efficient memory coding than equivalent instruction
functions directed to other registers. Any register can be
rotated; however, while it requires a two-byte instruction to
normally rotate any register, a single-byte instruction is
available for rotating the contents of the accumulator (A register).
8.4.2 F Register - Flags
The NSC800 flag register consists of six status bits that
contain information regarding the results of previous CPU
operations. The register can be read by pushing the contents onto the stack and then reading it, however, it cannot
be written to. It is classified as a register because of its
affiliation with the accumulator and the existence of a duplicate register for use in exchange instructions with the accumulator.
Of the six flags shown in Figure 5 , only four can be directly
tested by the programmer via conditional jump, call, and
return instructions. They are the Sign (S), Zero (Z), Parity/
Overflow (P/V), and Carry (C) flags. The Half Carry (H) and
Add/Subtract (N) flags are used for internal operations related to BCD arithmetic.
CPU Main Working Register Set
Accumulator A
(8)
Register B
(8)
Register D
(8)
Register H
(8)
Flags F
Register C
Register E
Register L
(8)
(8)
(8)
(8)
CPU Alternate Working Register Set
Accumulator A’
(8)
Flags F’
Register B’
(8)
Register C’
Register D’
(8)
Register E’
Register H’
(8)
Register L’
(8)
(8)
(8)
(8)
TL/C/5171 – 23
FIGURE 5. Flag Register
FIGURE 4b. CPU Working and Alternate Registers
12
8.0 Functional Description (Continued)
The following operations affect the P/V flag according to
the parity of the result of the operation:
8.4.3 Carry (C)
A carry from the highest order bit of the accumulator during
an add instruction, or a borrow generated during a subtraction instruction sets the carry flag. Specific shift and rotate
instructions also affect this bit.
Two specific instructions in the NSC800 instruction repertoire set (SCF) or complement (CCF) the carry flag.
Other operations that affect the C flag are as follows:
#
#
#
#
#
Logic Operations
Rotate and Shift
Rotate Digits
Decimal Adjust
Input Register Indirect
The following operations affect the P/V flag according to
the overflow result of the operation.
#
#
#
#
#
#
#
Adds
Subtracts
Logic Operations (always resets C flag)
Rotate Accumulator
Rotate and Shifts
Decimal Adjust
Negation of Accumulator
Other operations do not affect the C flag.
8.4.4 Adds/Subtract (N)
This flag is used in conjunction with the H flag to ensure that
the proper BCD correction algorithm is used during the decimal adjust instruction (DAA). The correction algorithm depends on whether an add or subtract was previously done
with BCD operands.
The operations that set the N flag are:
#
#
#
#
#
#
#
#
#
#
Adds (16 bit with carry, 8-bit with/without carry)
Subtracts (16 bit with carry, 8-bit with/without carry)
Increments and Decrements
Negation of Accumulator
The P/V flag has no significance immediately after the following operations.
#
#
Block I/O
Bit Tests
In block transfers and compares, the P/V flag indicates the
status of the BC register, always ending in the reset state
after an auto repeat of a block move. Other operations do
not affect the P/V flag.
8.4.6 Half Carry (H)
This flag indicates a BCD carry, or borrow, result from the
low-order four bits of operation. It can be used to correct the
results of a previously packed decimal add, or subtract, operation by use of the Decimal Adjust Instruction (DAA).
The following operations affect the H flag:
Subtractions
Decrements (8-bit)
Complementing of the Accumulator
Block I/O
#
#
#
#
#
#
Adds (8-bit)
Subtracts (8-bit)
Increments and Decrements
Decimal Adjust
Negation of Accumulator
Always Set by: Logic AND
Complement Accumulator
Bit Testing
# Always Reset By: Logic OR’s and XOR’s
Rotates and Shifts
Set Carry
Input Register Indirect
Block Transfers
Loads of I and R Registers
The H flag has no significance immediately after the following operations.
# 16-bit Adds with/without carry
# 16-Bit Subtracts with carry
# Complement of the carry
# Block I/O
# Block Searches
Other operations do not affect the H flag.
Block Searches
Negation of the Accumulator
The operations that reset the N flag are:
# Adds
# Increments
# Logic Operations
# Rotates
# Set and Complement Carry
# Input Register Indirect
# Block Transfers
# Load of the I or R Registers
# Bit Tests
Other operations do not affect the N flag.
8.4.5 Parity/Overflow (P/V)
The Parity/Overflow flag is a dual-purpose flag that indicates results of logic and arithmetic operations. In logic operations, the P/V flag indicates the parity of the result; the
flag is set (high) if the result is even, reset (low) if the result
is odd. In arithmetic operations, it represents an overflow
condition when the result, interpreted as signed two’s complement arithmetic, is out of range for the eight-bit accumulator (i.e. b128 to a 127).
13
8.0 Functional Description (Continued)
8.4.7 Zero Flag (Z)
8.4.9 Additional General-Purpose Registers
Loading a zero in the accumulator or when a zero results
from an operation sets the zero flag.
The following operations affect the zero flag.
The other general-purpose registers are the B, C, D, E, H
and L registers and their alternate register set, B’, C’, D’, E’,
H’ and L’. The general-purpose registers can be used interchangeably.
In addition, the B and C registers perform special functions
in the NSC800 expanded I/O capabilities, particularly block
I/O operations. In these functions, the C register can address I/O ports; the B register provides a counter function
when used in the register indirect address mode.
When used with the special condition jump instruction
(DJNZ) the B register again provides the counter function.
8.4.10 Alternate Configurations
The six 8-bit general purpose registers (B,C,D,E,H,L) will
combine to form three 16-bit registers. This occurs by concatenating the B and C registers to form the BC register, the
D and E registers form the DE register, and the H and L
registers form the HL register.
Having these 16-bit registers allows 16-bit data handling,
thereby expanding the number of 16-bit registers available
for memory addressing modes. The HL register typically
provides the pointer address for use in register indirect addressing of the memory.
The DE register provides a second memory pointer register
for the NSC800’s powerful block transfer operations. The
BC register also provides an assist to the block transfer
operations by acting as a byte-counter for these operations.
#
#
#
#
#
#
#
#
#
#
#
#
#
Adds (16-bit with carry, 8-bit with/without carry)
Subtracts (16-bit with carry, 8-bit with/without carry)
Logic Operations
Increments and Decrements
Rotate and Shifts
Rotate Digits
Decimal Adjust
Input Register Indirect
Block I/O (always set after auto repeat block I/O)
Block Searches
Load of I and R Registers
Bit Tests
Negation of Accumulator
The Z flag has no signficance immediately after the following operations:
# Block Transfers
Other operations do not affect the zero flag.
8.4.8 Sign Flag (S)
The sign flag stores the state of bit 7 (the most-significant bit and sign bit) of the accumulator following an arithmetic operation. This flag is of use when dealing with signed
numbers.
The sign flag is affected by the following operation according to the result:
#
#
#
#
#
#
#
#
#
#
#
8.5 ARITHMETIC-LOGIC UNIT (ALU)
The arithmetic, logic and rotate instructions are performed
by the ALU. The ALU internally communicates with the registers and data buffer on the 8-bit internal data bus.
Adds (16-bit with carry, 8-bit with/without carry)
8.6 INSTRUCTION REGISTER AND DECODER
During an opcode fetch, the first byte of an instruction is
transferred from the data buffer (i.e. its on the internal data
bus) to the instruction register. The instruction register feeds
the instruction decoder, which gated by timing signals, generates the control signals that read or write data from or to
the registers, control the ALU and provide all required external control signals.
Subtracts (16-bit with carry, 8-bit with/without carry)
Logic Operations
Increments and Decrements
Rotate and Shifts
Rotate Digits
Decimal Adjust
Input Register Indirect
Block Search
Load of I and R Registers
Negation of Accumulator
The S flag has no significance immediately after the following operations:
#
#
#
Block I/O
Block Transfers
Bit Tests
Other operations do not affect the sign bit.
14
9.0 Timing and Control
9.1 INTERNAL CLOCK GENERATOR
An inverter oscillator contained on the NSC800 chip provides all necessary timing signals. The chip operation frequency is equal to one half of the frequency of this oscillator.
The oscillator frequency can be controlled by one of the
following methods:
1. Leaving the XOUT pin unterminated and driving the XIN
pin with an externally generated clock as shown in Figure
6 . When driving XIN with a square wave, the minimum
duty cycle is 30% high.
2 MHz k
f(XTAL)
2
R e 1 MX
C1 e 20 pF
C2 e 34 pF
(Recommended)
TL/C/5171 – 14
FIGURE 7. Use Of Crystal
The CPU has a minimum clock frequency input ( @ XIN) of
300 kHz, which results in 150 kHz system clock speed. All
registers internal to the chip are static, however there is
dynamic logic which limits the minimum clock speed. The
input clock can be stopped without fear of losing any data or
damaging the part. You stop it in the phase of the clock that
has XIN low and CLK OUT high. When restarting the CPU,
precautions must be taken so that the input clock meets
these minimum specification. Once started, the CPU will
continue operation from the same location at which it was
stopped. During DC operation of the CPU, typical current
drain will be 2 mA. This current drain can be reduced by
placing the CPU in a wait state during an opcode fetch cycle
then stopping the clock. For clock stop circuit, see Figure 8 .
TL/C/5171 – 13
FIGURE 6. Use of External Clock
2. Connecting a crystal with the proper biasing network between XIN and XOUT as shown in Figure 7 . Recommended crystal is a parallel resonance AT cut crystal.
Note 1: If the crystal frequency is between 1 MHz and 2 MHz a series
resistor, RS, (470X to 1500X) should be connected between
XOUT and R, XTAL and CZ. Additionally, the capacitance of C1
and C2 should be increased by 2 to 3 times the recommended
value. For crystal frequencies less than 1 MHz higher values of
C1 and C2 may be required. Crystal parameters will also affect
the capacitive loading requirements.
TL/C/5171 – 36
FIGURE 8. Clock Stop Circuit
15
9.0 Timing and Control (Continued)
During an input or output instruction, the CPU duplicates the
lower half of the address [AD(0 – 7)] onto the upper address
bus [A(8 – 15)]. The eight bits of address will stay on A(8 –
15) for the entire machine cycle and can be used for chip
selection directly.
9.2 CPU TIMING
The NSC800 uses a multiplexed bus for data and addresses. The 16-bit address bus is divided into a high-order 8-bit
address bus that handles bits 8–15 of the address, and a
low-order 8-bit multiplexed address/data bus that handles
bits 0 – 7 of the address and bits 0–7 of the data. Strobe
outputs from the NSC800 (ALE, RD and WR) indicate when
a valid address or data is present on the bus. IO/M indicates whether the ensuing cycle accesses memory or I/O.
Figure 9 illustrates the timing relationship for opcode fetch
cycles with and without a wait state.
TL/C/5171 – 15
FIGURE 9a. Opcode Fetch Cycles without WAIT States
TL/C/5171 – 16
FIGURE 9b. Opcode Fetch Cycles with WAIT States
16
9.0 Timing and Control (Continued)
that when it goes inactive, the CPU continues its opcode
fetch by latching in the data on the rising edge of RD from
the AD(0 – 7) lines. During t3, RFSH goes active and AD(0 –
7) has the dynamic RAM refresh address from register R
and A(8 – 15) the interrupt vector from register I.
During the opcode fetch, the CPU places the contents of
the PC on the address bus. The falling edge of ALE indicates a valid address on the AD(0–7) lines. The WAIT input
is sampled during t2 and if active causes the NSC800 to
insert a wait state (tw). WAIT is sampled again during tw so
TL/C/5171 – 17
FIGURE 10a. Memory Read/Write Cycles without WAIT States
TL/C/5171 – 18
FIGURE 10b. Memory Read and Write with WAIT States
17
9.0 Timing and Control (Continued)
Figure 10 shows the timing for memory read (other than
opcode fetchs) and write cycles with and without a wait
t
state. The RD stobe is widened by
(half the machine
2
state) for memory reads so that the actual latching of the
input data occurs later.
Figure 11 shows the timing for input and output cycles with
and without wait states. The CPU automatically inserts one
wait state into each I/O instruction to allow sufficient time
for an I/O port to decode the address.
TL/C/5171 – 19
FIGURE 11a. Input and Output Cycles without WAIT States
TL/C/5171 – 20
*WAIT state automatically inserted during IO operation.
FIGURE 11b. Input and Output Cycles with WAIT States
18
9.0 Timing and Control (Continued)
9.3 INITIALIZATION
RESET IN initializes the NSC800; RESET OUT initializes the
peripheral components. The Schmitt trigger at the RESET
IN input facilitates using an R-C network reset scheme during power up (see Figure 12 ).
To ensure proper power-up conditions for the NSC800, the
following power-up and initialization procedure is recommended:
1. Apply power (VCC and GND) and set RESET IN active
(low). Allow sufficient time (approximately 30 ms if a crystal is used) for the oscillator and internal clocks to stabilize. RESET IN must remain low for at least 3t state (CLK)
times. RESET OUT goes high as soon as the active
RESET IN signal is clocked into the first flip-flop after the
on-chip Schmitt trigger. RESET OUT signal is available to
reset the peripherals.
2. Set RESET IN high. RESET OUT then goes low as the
inactive RESET IN signal is clocked into the first flip-flop
after the on-chip Schmitt trigger. Following this the CPU
initiates the first opcode fetch cycle.
Note: The NSC800 initialization includes: Clear PC to
X’0000 (the first opcode fetch, therefore, is from memory
location X’0000). Clear registers I (Interrupt Vector Base)
and R (Refresh Counter) to X’00. Clear interrupt control register bits IEA, IEB and IEC. The interrupt control bit IEI is set
to 1 to maintain INS8080A/Z80A compatibility (see INTERRUPTS for more details). The CPU disables maskable interrupts and enters INTR Mode 0. While RESET IN is active
(low), the A(8–15) and AD(0–7) lines go to high impedance
(TRI-STATE) and all CPU strobes go to the inactive state
(see Figure 13 ).
TL/C/5171 – 21
FIGURE 12. Power-On Reset
9.4 POWER-SAVE FEATURE
The NSC800 provides a unique power-save mode by the
means of the PS pin. PS input is sampled at the last t state
of the last M cycle of an instruction. After recognizing an
active (low) level on PS, The NSC800 stops its internal
clocks, thereby reducing its power dissipation to one half of
operating power, yet maintaining all register values and internal control status. The NSC800 keeps its oscillator running, and makes the CLK signal available to the system.
When in power-save the ALE strobe will be stopped high
and the address lines [AD(0 – 7), A(8 – 15)] will indicate the
next machine address. When PS returns high, the opcode
fetch (or M1 cycle) of the CPU begins in a normal manner.
Note this M1 cycle could also be an interrupt acknowledge
cycle if the NSC800 was interrupted simultaneously with PS
(i.e. PS has priority over a simultaneously occurring interrupt). However, interrupts are not accepted during power
save. Figure 14 illustrates the power save timing.
TL/C/5171 – 74
FIGURE 13. NSC800 Signals During Power-On and Manual Reset
19
9.0 Timing and Control (Continued)
TL/C/5171 – 28
FIGURE 14. NSC800 Power-Save
TL/C/5171 – 22
*S0, S1 during BREQ will indicate same machine cycle as during the cycle when BREQ was accepted.
tZ e time states during which bus and control signals are in high impedance mode.
FIGURE 15. Bus Acknowledge Cycle
In the event BREQ is asserted (low) at the end of an instruction cycle and PS is active simultaneously, the following occurs:
1. The NSC800 will go into BACK cycle.
9.6 INTERRUPT CONTROL
The NSC800 has five interrupt/restart inputs, four are maskable (RSTA, RSTB, RSTC, and INTR) and one is non-maskable (NMI). NMI has the highest priority of all interrupts; the
user cannot disable NMI. After recognizing an active input
on NMI, the CPU stops before the next instruction, pushes
the PC onto the stack, and jumps to address X’0066, where
the user’s interrupt service routine is located (i.e., restart to
memory location X’0066). NMI is intended for interrupts requiring immediate attention, such as power-down, control
panel, etc.
RSTA, RSTB and RSTC are restart inputs, which, if enabled,
execute a restart to memory location X’003C, X’0034, and
X’002C, respectively. Note that the CPU response to the
NMI and RST (A, B, C) request input is basically identical,
except for the restored memory location. Unlike NMI, however, restart request inputs must be enabled.
2. Upon completion of BACK cycle if PS is still active the
CPU will go into power-save mode.
9.5 BUS ACCESS CONTROL
Figure 15 illustrates bus access control in the NSC800. The
external device controller produces an active BREQ signal
that requests the bus. When the CPU responds with BACK
then the bus and related control strobes go to high impedance (TRI-STATE) and the RFSH signal remains high. It
should be noted that (1) BREQ is sampled at the last t state
of any M machine cycle only. (2) The NSC800 will not acknowledge any interrupt/restart requests, and will not peform any dynamic RAM refresh functions until after BREQ
input signal is inactive high. (3) BREQ signal has priority
over all interrupt request signals, should BREQ and interrupt
request become active simultaneously. Therefore, interrupts
latched at the end of the instruction cycle will be serviced
after a simultaneously occurring BREQ. NMI is latched during an active BREQ.
Figure 16 illustrates NMI and RST interrupt machine cycles.
M1 cycle will be a dummy opcode fetch cycle followed by
M2 and M3 which are stack push operations. The following
instruction then starts from the interrupts restart location.
Note: RD does not go low during this dummy opcode fetch. A unique indication of INTA can be decoded using 2 ALEs and RD.
20
9.0 Timing and Control (Continued)
TL/C/5171 – 24
Note 1: This is the only machine cycle that does not have an RD, WR, or INTA strobe but will accept a wait strobe.
FIGURE 16. Non-Maskable and Restart Interrupt Machine Cycle
dress. The first byte of each entry in the table is the least
significant (low-order) portion of the address. The programmer must obviously fill this table with the desired addresses
before any interrupts are to be accepted.
Note that the programmer can change this table at any time
to allow peripherals to be serviced by different service routines. Once the interrupting device supplies the lower portion of the pointer, the CPU automatically pushes the program counter onto the stack, obtains the starting address
from the table and does a jump to this address.
The interrupts have fixed priorities built into the NSC800 as:
NMI
0066
(Highest Priority)
RSTA
003C
RSTB
0034
RSTC
002C
INTR
0038
(Lowest Priority)
Interrupt Enable, Interrupt Disable. The NSC800 has two
types of interrupt inputs, a non-maskable interrupt and four
software maskable interrupts. The non-maskable interrupt
(NMI) cannot be disabled by the programmer and will be
accepted whenever a peripheral device requests an interrupt. The NMI is usually reserved for important functions
that must be serviced when they occur, such as imminent
power failure. The programmer can selectively enable or
disable maskable interrupts (INT, RSTA, RSTB and RSTC).
This selectivity allows the programmer to disable the maskable interrupts during periods when timing constraints don’t
allow program interruption.
There are two interrupt enable flip-flops (IFF1 and IFF2) on
the NSC800. Two instructions control these flip-flops. Enable Interrupt (EI) and Disable Interrupt (DI). The state of
IFF1 determines the enabling or disabling of the maskable
interrupts, while IFF2 is used as a temporary storage location for the state of IFF1.
The NSC800 also provides one more general purpose interrupt request input, INTR. When enabled, the CPU responds
to INTR in one of the three modes defined by instruction
IM0, IM1, and IM2 for modes 0, 1, and 2, respectively. Following reset, the CPU automatically enables mode 0.
Interrupt (INTR) Mode 0: The CPU responds to an interrupt
request by providing an INTA (interrupt acknowledge)
strobe, which can be used to gate an instruction from a
peripheral onto the data bus. The CPU inserts two wait
states during the first INTA cycle to allow the interrupting
device (or its controller) ample time to gate the instruction
and determine external priorities (Figure 18 ). This can be
any instruction from one to four bytes. The most popular
instruction is one-byte call (restart instruction) or a threebyte call (CALL NN instruction). If it is a three-byte call, the
CPU issues a total of three INTA strobes. The last two
(which do not include wait states) read NN.
Note: If the instruction stored in the ICU doesn’t require the PC to be
pushed onto the stack (eq. JP nn), then the PC will not be pushed.
Interrupt (INTR) Mode 1: Similar to restart interrupts except the restart location is X’0038 (Figure 18 ).
Interrupt (INTR) Mode 2: With this mode, the programmer
maintains a table that contains the 16-bit starting address of
every interrupt service routine. This table can be located
anywhere in memory. When the CPU accepts a Mode 2
interrupt (Figure 17 ), it forms a 16-bit pointer to obtain the
desired interrupt service routine starting address from the
table. The upper 8 bits of this pointer are from the contents
of the I register. The lower 8 bits of the pointer are supplied
by the interrupting device with the LSB forced to zero. The
programmer must load the interrupt vector prior to the interrupt occurring. The CPU uses the pointer to get the two
adjacent bytes from the interrupt service routine starting address table to complete 16-bit service routine starting ad21
9.0 Timing and Control (Continued)
A reset to the CPU will force both IFF1 and IFF2 to the reset
state disabling maskable interrupts. They can be enabled by
an EI instruction at any time by the programmer. When an EI
instruction is executed, any pending interrupt requests will
not be accepted until after the instruction following EI has
been executed. This single instruction delay is necessary in
situations where the following instruction is a return instruction and interrupts must not be allowed until the return has
been completed. The EI instruction sets both IFF1 and IFF2
to the enable state. When the CPU accepts an interrupt,
both IFF1 and IFF2 are automatically reset, inhibiting further
interrupts until the programmer wishes to issue a new EI
instruction. Note that for all the previous cases, IFF1 and
IFF2 are always equal.
The function of IFF2 is to retain the status of IFF1 when a
non-maskable interrupt occurs. When a non-maskable interrupt is accepted, IFF1 is reset to prevent further interrupts
until reenabled by the programmer. Thus, after a non-maskable interrupt has been accepted, maskable interrupts are
disabled but the previous state of IFF1 is saved by IFF2
TL/C/5171 – 27
FIGURE 17. Interrupt Mode 2
22
23
FIGURE 18. Interrupt Acknowledge Machine Cycle
Note 2: A jump to the appropriate address occurs here in mode 1 and mode 2. The CPU continues gathering data from the interrupting peripheral in mode 0 for a total of 2–4
machine cycles. In mode 0 cycles M2–M4 have only 1 wait state.
Note 1: t5 will only occur in mode 1 and mode 2. During t5 the stack pointer is decremented.
*tW is the CPU generated WAIT state in response to an interrupt request.
TL/C/5171 – 25
9.0 Timing and Control (Continued)
9.0 Timing and Control (Continued)
so that the complete state of the CPU just prior to the nonmaskable interrupt may be restored. The method of restoring the status of IFF1 is through the execution of a Return
Non-Maskable Interrupt (RETN) instruction. Since this instruction indicates that the non-maskable interrupt service
routine is completed, the contents of IFF2 are now copied
back into IFF1, so that the status of IFF1 just prior to the
acceptance of the non-maskable interrupt will be automatically restored.
Operation
Initialize
IFF1
0
IFF2
0
1
1
Interrupt Enabled after
next instruction
0
0
Interrupt Disable and INTR
Being Serviced
EI
1
1
RET
1
1
Interrupt Enabled after
next instruction
Interrupt Enabled
0
1
Interrupt Disabled
1
1
Interrupt Enabled
0
0
Interrupt Disabled
0
0
Interrupt Disabled and NMI
Being Serviced
0
0
Interrupt Disabled and INTR
Being Serviced
EI
1
1
RET
1
1
Interrupt Enabled after
next instruction
Interrupt Enabled
#
#
#
EI
#
#
#
Figure 19 depicts the status of the flip flops during a sample
series of interrupt instructions.
Interrupt Control Register. The interrupt control register
(ICR) is a 4-bit, write only register that provides the programmer with a second level of maskable control over the four
maskable interrupt inputs.
The ICR is internal to the NSC800 CPU, but is addressed
through the I/O space at I/O address port X’BB. Each bit in
the register controls a mask bit dedicated to each maskable
interrupt, RSTA, RSTB, RSTC and INTR. For an interrupt
request to be accepted on any of these inputs, the corresponding mask bit in the ICR must be set ( e 1) and IFF1
and IFF2 must be set. This provides the programmer with
control over individual interrupt inputs rather than just a system wide enable or disable.
INTR
#
#
#
#
#
#
NMI
#
#
#
RETN
#
TL/C/5171–26
Bit
0
1
2
3
Name
IEI
IEC
IEB
IEA
Comment
Interrupt Disabled
INTR
#
#
#
Function
Interrupt Enable for INTR
Interrupt Enable for RSTC
Interrupt Enable for RSTB
Interrupt Enable for RSTA
NMI
#
#
#
For example: In order to enable RSTB, CPU interrupts must
be enabled and IEB must be set.
At reset, IEI bit is set and other mask bits IEA, IEB, IEC are
cleared. This maintains the software compatibility between
NSC800 and Z80A.
Execution of an I/O block move instruction will not affect
the state of the interrupt control bits. The only two instructions that will modify this write only register are OUT (C), r
and OUT (N), A.
RETN
#
#
#
#
#
#
FIGURE 19. IFF1 and IFF2 States Immediately after the
Operation has been Completed
24
NSC800 SOFTWARE
10.0 Introduction
11.3 IMMEDIATE
This chapter provides the reader with a detailed description
of the NSC800 software. Each NSC800 instruction is described in terms of opcode, function, flags affected, timing,
and addressing mode.
The most straightforward way of introducing data to the
CPU registers is via immediate addressing, where the data
is contained in an additional byte of multi-byte instructions.
Example:
Instruction: Load the E register with the constant value
X’7C.
Mnemonic: LD
E,X’7C
Opcode:
11.0 Addressing Modes
The following sections describe the addressing modes supported by the NSC800. Note that particular addressing
modes are often restricted to certain types of instructions.
Examples of instructions used in the particular addressing
modes follow each mode description.
The 10 addressing modes and 158 instructions provide a
flexible and powerful instruction set.
11.1 REGISTER
The most basic addressing mode is that which addresses
data in the various CPU registers. In these cases, bits in the
opcode select specific registers that are to be addressed by
the instruction.
Example:
Instruction: Load register B from register C
Mnemonic: LD
B,C
Opcode:
TL/C/5171 – 52
In this instruction, the E register is addressed with register
addressing, while the constant X’7C is immediate data in the
second byte of the instruction.
11.4 IMMEDIATE EXTENDED
As immediate addressing allows 8 bits of data to be supplied by the operand, immediate extended addressing allows 16 bits of data to be supplied by the operand. These
are in two additional bytes of the instruction.
Example:
Instruction: Load the 16-bit IX register with the constant
value X’ABCD.
Mnemonic: LD
IX,X’ABCD
Opcode:
TL/C/5171 – 50
In this instruction, both the B and C registers are addressed
by opcode bits.
11.2 IMPLIED
The implied addressing mode is an extension to the register
addressing mode. In this mode, a specific register, the accumulator, is used in the execution of the instruction. In particular, arithmetic operations employ implied addressing, since
the A register is assumed to be the destination register for
the result without being specifically referenced in the opcode.
Example:
Instruction: Subtract the contents of register D from the
Accumulator (A register)
Mnemonic: SUB
D
Opcode:
TL/C/5171 – 53
In this instruction, register addressing selects the IX register, while the 16-bit quanity X’ABCD is immediate data supplied as immediate extended format.
TL/C/5171 – 51
In this instruction, the D register is addressed with register
addressing, while the use of the A register is implied by the
opcode.
25
11.0 Addressing Modes (Continued)
11.5 DIRECT ADDRESSING
Direct addressing is the most straightforward way of addressing supplies a location in the memory space. Direct
addressing, 16-bits of memory address information in two
bytes of data as part of the instruction. The memory address
could be either data, source of destination, or a location for
program execution, as in program control instructions.
Example:
Instruction: Jump to location X’0377
Mnemonic: JP
X’0377
Opcode:
1
1
0
0
0
0
1
1
0
1
1
1
0
1
1
1
0
0
0
0
0
0
1
1
Indexed addressing is particularly useful in dealing with lists
of data.
Example:
Instruction: Increment the data in memory location X’1020.
The IY register contains X’1000.
Mnemonic: INC
(IY a X’20)
Opcode:
ÐDefines jump opcode
(
ÐConstant X’0377
This instruction loads the Program Counter (PC) is loaded
with the constant in the second and third bytes of the instruction. The program counter contents are transferred via
direct addressing.
TL/C/5171 – 54
The indexed addressing mode uses the contents of index
registers IX or IY along with the displacement to form a
pointer to memory.
11.6 REGISTER INDIRECT
Next to direct addressing, register indirect addressing provides the second most straightforward means of addressing
memory. In register indirect addressing, a specified register
pair contains the address of the desired memory location.
The instruction references the register pair and the register
contents define the memory location of the operand.
Example:
Instruction: Add the contents of memory location X’0254 to
the A register. The HL register contains X’0254.
Mnemonic: ADD
A,(HL)
Opcode
1
0
0
0
0
1
1
11.8 RELATIVE
Certain instructions allow memory locations to be addressed as a position relative to the PC register. These instructions allow jumps to memory locations which are offsets around the program counter. The offset, together with
the current program location, is determined through a displacement byte included in the instruction. The formation of
this displacement byte is explained more fully in the ‘‘Instructions Set’’ section.
Example:
Instruction: Jump to a memory location 7 bytes beyond the
current location.
Mnemonic: JR
$a7
0
This instruction uses implied addressing of the A and HL
registers and register indirect addressing to access the data
pointed to by the HL register.
Opcode:
11.7 INDEXED
The most flexible mode of memory addressing is the indexed mode. This is similar to the register indirect mode of
addressing because one of the two index registers (IX or IY)
contains the base memory address. In addition, a byte of
data included in the instruction acts as a displacement to
the address in the index register.
0
0
0
1
1
0
0
0
ÐDefines relative jump
opcode
0
0
0
0
0
1
0
1
ÐDisplacement to be
applied to the PC
The program will continue at a location seven locations past
the current PC.
26
11.0 Addressing Modes (Continued)
Program execution continues at location X’0028 after execution of a single-byte call employing modified page zero
addressing.
11.9 MODIFIED PAGE ZERO
A subset of NSC800 instructions (the Restart instructions)
provides a code-efficient single-byte instruction that allows
CALLs to be performed to any one of eight dedicated locations in page zero (locations X’0000 to X’00FF). Normally, a
CALL is a 3-byte instruction employing direct memory addressing.
Example:
Instruction: Perform a restart call to location X’0028.
Mnemonic: RST
X’28
Opcode:
11.10 BIT
The NSC800 allows setting, resetting, and testing of individual bits in registers and memory data bytes.
Example:
Operation: Set bit 2 in the L register
Mnemonic: SET
2,L
Opcode:
TL/C/5171 – 56
TL/C/5171 – 55
p
00H
08H
10H
18H
20H
28H
30H
38H
t
000
001
010
011
100
101
110
111
Bit addressing allows the selection of bit 2 in the L register
selected by register addressing.
27
12.0 Instruction Set
This section details the entire NSC800 instruction set in
terms of
#
#
#
#
#
The instructions are grouped in order under the following
functional headings:
#
#
#
#
#
#
#
#
#
#
#
Opcode
Instruction
Function
Timing
Addressing Mode
8-Bit Loads
16-Bit Loads
8-Bit Arithmetic
16-Bit Arithmetic
Bit Set, Reset, and Test
Rotate and Shift
Exchanges
Memory Block Moves and Searches
Input/Output
CPU Control
Program Control
12.1 Instruction Set Index
Alphabetical
Assembly
Mnemonic
Operation
Page
ADC A,m1
ADC A,n
ADC A,r
ADC HL,pp
ADD A,m1
ADD A,n
ADD A,r
ADD HL,pp
ADD IX,pp
ADD IY,pp
ADD ss,pp
AND m1
AND n
AND r
Add, with carry, memory location contents to Accumulator
Add, with carry, immediate data n to Accumulator
Add, with carry, register r contents to Accumulator
Add, with carry, register pair pp to HL
Add memory location contents to Accumulator
Add immediate data n to Accumulator
Add register r contents to Accumulator
Add register pair pp to HL
Add register pair pp to IX
Add register pair pp to IY
Add register pair pp to contents of register pair ss
Logical ‘AND’ memory contents to Accumulator
Logical ‘AND’ immediate data to Accumulator
Logical ‘AND’ register r contents to Accumulator
40
38
36
43
40
38
36
43
43
43
43
41
39
36
BIT b,m1
BIT b,r
Test bit b of location m1
Test bit b of register r
45
44
CALL cc,nn
CALL nn
CCF
CP m1
CP n
CP r
CPD
CPDR
56
56
38
42
40
37
50
51
CPL
Call subroutine at location nn if condition cc is true
Unconditional call to subroutine at location nn
Complement carry flag
Compare memory contents with Accumulator
Compare immediate data n with Accumulator
Compare register r to contents with Accumulator
Compare location (HL) and Accumulator, decrement HL and BC
Compare location (HL) and Accumulator, decrement HL and BC;
repeat until BC e 0
Compare location (HL) and Accumulator, increment HL, decrement BC
Compare location (HL) and Accumulator, increment HL, decrement BC;
repeat until BC e 0
Complement Accumulator (1’s complement)
DAA
DEC m1
DEC r
DEC rr
Decimal adjust Accumulator
Decrement data in memory location m1
Decrement register r contents
Decrement register pair rr contents
38
42
37
44
CPI
CPIR
28
50
51
37
12.1 Instruction Set Index (Continued)
Alphabetical
Assembly
Mnemonic
Operation
Page
DI
DJNZ,d
Disable interrupts
Decrement B and jump relative B
EI
EX (SP),ss
EX AF,A’F’
EX DE,HL
EXX
Enable interrupts
Exchange the location (SP) with register ss
Exchange the contents of AF and A’F’
Exchange the contents of DE and HL
Exchange the contents of BC, DE and HL with the contents
of B’C, D’E’ and H’L’, respectively
54
50
49
49
50
HALT
Halt (wait for interrupt or reset)
54
IM 0
IM 1
IM 2
IN A,(n)
IN r,(C)
INC m1
INC r
INC rr
IND
INDR
INI
INIR
Set interrupt mode 0
Set interrupt mode 1
Set interrupt mode 2
Load Accumulator with input from device (n)
Load register r with input from device (C)
Increment data in memory location m1
Increment register r
Increment contents of register pair rr
Load location (HL) with input from port (C), decrement HL and B
Load location (HL) with input from port (C), decrement HL and B; repeat until B e 0
Load location (HL) with input from port (C), increment HL, decrement B
Load location (HL) with input from port (C), increment HL, decrement B;
repeat until B e 0
54
55
55
52
52
42
37
43
52
54
52
53
JP cc,nn
JP nn
JP (ss)
JR d
JR kk,d
Jump to location nn, if condition cc is true
Unconditional jump to location nn
Unconditional jump to location (ss)
Unconditional jump relative to PC a d
Jump relative to PC a d, if kk true
55
55
55
55
55
LD A,I
LD A,m2
LD A,R
LD I,A
LD m1,n
LD m1,r
LD m2,A
LD (nn),rr
LD r,m1
LD r,n
LD R,A
LD rd,rs
LD rr,(nn)
LD rr,nn
LD SP,ss
LDD
LDDR
LDI
LDIR
Load Accumulator with register I contents
Load Accumulator from location m2
Load Accumulator with register R contents
Load register I with Accumulator contents
Load memory with immediate data n
Load memory from register r
Load memory from Accumulator
Load memory location nn with register pair rr
Load register r from memory
Load register with immediate data n
Load register R from Accumulator
Load destination register rd from source register rs
Load register pair rr from memory location nn
Load register pair rr with immediate data nn
Load SP from register pair ss
Load location (DE) with location (HL), decrement DE, HL and BC
Load location (DE) with location (HL), decrement DE, HL and BC; repeat until BC e 0
Load location (DE) with location (HL), increment DE and HL, decrement BC
Load location (DE) with location (HL), increment DE and HL, decrement BC;
repeat until BC e 0
32
33
32
32
33
32
33
34
33
32
32
32
35
34
34
50
51
50
51
NEG
NOP
Negate Accumulator (2’s complement)
No operation
38
54
i
0
29
54
56
12.1 Instruction Set Index (Continued)
Alphabetical
Assembly
Mnemonic
Operation
Page
41
39
37
54
53
OUT (C),r
OUT (n),A
OUTD
OUTI
Logical ‘OR’ of memory location contents and accumulator
Logical ‘OR’ of immediate data n and Accumulator
Logical ‘OR’ of register r and Accumulator
Load output port (C) with location (HL), decrement HL and B; repeat until B e 0
Load output port (C) with location (HL), increment HL, decrement B;
repeat until B e 0
Load output port (C) with register r
Load output port (n) with Accumulator
Load output port (C) with location (HL), decrement HL and B
Load output port (C) with location (HL), increment HL, decrement B
POP qq
PUSH qq
Load register pair qq with top of stack
Load top of stack with register pair qq
35
35
RES b,m1
RES b,r
RET
RET cc
RETI
RETN
RL m1
RL r
RLA
RLC m1
RLC r
RLCA
RLD
RR m1
RR r
RRA
RRC m1
RRC r
RRCA
RRD
RST P
Reset bit b of memory location m1
Reset bit b of register r
Unconditional return from subroutine
Return from subroutine, if cc true
Unconditional return from interrupt
Unconditional return from non-maskable interrupt
Rotate memory contents left through carry
Rotate register r left through carry
Rotate Accumulator left through carry
Rotate memory contents left circular
Rotate register r left circular
Rotate Accumulator left circular
Rotate digit left and right between Accumulator and memory (HL)
Rotate memory contents right through carry
Rotate register r right through carry
Rotate Accumulator right through carry
Rotate memory contents right circular
Rotate register r right circular
Rotate Accumulator right circular
Rotate digit right and left between Accumulator and memory (HL)
Restart to location P
44
44
56
56
56
57
47
45
45
47
45
45
49
48
46
48
47
45
46
49
57
SBC A,m1
SBC A,n
SBC A,r
SBC HL,pp
SCF
SET b,m1
SET b,r
SLA m1
SLA r
SRA m1
SRA r
SRL m1
SRL r
SUB m1
SUB n
SUB r
Subtract, with carry, memory contents from Accumulator
Subtract, with carry, immediate data n from Accumulator
Subtract, with carry, register r from Accumulator
Subtract, with carry, register pair pp from HL
Set carry flag
Set bit b in memory location m1 contents
Set bit b in register r
Shift memory contents left, arithmetic
Shift register r left, arithmetic
Shift memory contents right, arithmetic
Shift register r right, arithmetic
Shift memory contents right, logical
Shift register r right, logical
Subtract memory contents from Accumulator
Subtract immediate data n from Accumulator
Subtract register r from Accumulator
41
39
36
43
38
44
44
48
46
48
46
48
46
40
39
36
XOR m1
XOR n
XOR r
Exclusive ‘OR’ memory contents and Accumulator
Exclusive ‘OR’ immediate data n and Accumulator
Exclusive ‘OR’ register r and Accumulator
42
39
37
OR m1
OR n
OR r
OTDR
OTIR
30
52
53
53
52
12.0 Instruction Set (Continued)
12.3 ASSEMBLED OBJECT CODE NOTATION
Register Codes:
r
Register
rp
Register
rs
Register
000
B
00
BC
00
BC
001
C
01
DE
01
DE
010
D
10
HL
10
HL
011
E
11
SP
11
AF
12.2 INSTRUCTION SET MNEMONIC NOTATION
In the following instruction set listing, the notations used are
shown below.
b:
Designates one bit in a register or memory location.
Bit address mode uses this indicator.
cc:
Designates condition codes used in conditional
Jumps, Calls, and Return instruction; may be:
NZ e Non-Zero (Z flag e 0)
d:
kk:
m1:
Designates (HL), (IX a d) or (IY a d). Register indirect
or indexed address modes use this indicator.
m2:
Designates (BC), (DE) or (nn). Register indirect or direct address modes use this indicator.
Any 8-bit binary number.
Any 16-bit binary number.
Designates restart vectors and may be the hex values
0, 8, 10, 18, 20, 28, 30 or 38. Restart instructions
employing the modified page zero addressing mode
use this indicator.
Designates the BC, DE, SP or any 16-bit register used
as a destination operand in 16-bit arithmetic operations employing the register address mode.
Designates BC, DE, HL, A, F, IX, or IY during operations employing register address mode.
Designates A, B, C, D, E, H or L. Register addressing
modes use this indicator.
Designates BC, DE, HL, SP, IX or IY. Register addressing modes use this indicator.
Designates HL, IX or IY. Register addressing modes
use this indicator.
n:
nn:
p:
pp:
qq:
r:
rr:
ss:
XL:
Subscript L indicates the lower-order byte of a 16-bit
register.
XH:
Subscript H indicates the high-order byte of a 16-bit
register.
parentheses indicate the contents are considered a
pointer address to a memory or I/O location.
( ):
100
101
111
Z e Zero (Z flag e 1)
NC e Non-Carry (C flag e 0)
C e Carry (C flag e 1)
PO e Parity Odd or No Overflow (P/V e 0)
PE e Parity Even or Overflow (P/V e 1)
P e Positive (S e 0)
M e Negative (S e 1)
Designates an 8-bit signed complement displacement. Relative or indexed address modes use this
indicator.
Subset of cc condition codes used in conjunction with
conditional relative jumps; may be NZ, Z, NC or C.
H
L
A
pp
00
01
10
11
Conditions Codes:
cc
Mnemonic
000
NZ
001
Z
010
NC
011
C
100
PO
101
PE
110
P
111
M
kk
Mnemonic
00
NZ
01
Z
10
NC
11
C
Restart Addresses:
t
T
000
X’00
001
X’08
010
X’10
011
X’18
100
X’20
101
X’28
110
X’30
111
X’38
31
Register
BC
DE
IX
SP
qq
00
01
10
11
Register
BC
DE
HL
AF
True Flag Condition
Ze0
Ze1
Ce0
Ce1
P/V e 0
P/V e 1
Se0
Se1
True Flag Condition
Ze0
Ze1
Ce0
Ce1
12.4 8-Bit Loads
REGISTER TO REGISTER
LD
rd, rs
Load register rd with rs:
rd w rs
7 6 5 4 3 2 1
0
1
rd
No flags affected
0
7
6
5
4
3
2
1
0
1
1
1
0
1
1
0
1
0
1
0
1
1
1
1
1
Timing:
M cycles Ð 2
T states Ð 9 (4, 5)
Register
rs
Timing:
Addressing Mode:
M cycles Ð 1
T states Ð 4
Register
Addressing Mode:
LD
R, A
Load Refresh register (R) with contents of the Accumulator.
No flags affected
RwA
7 6 5 4 3 2 1 0
LD
A, I
Load Accumulator with the contents of the I register.
S: Set if negative result
AwI
Z: Set if zero result
H: Reset
P/V: Set according to IFF2 (zero if
interrupt occurs during operation)
N: Reset
C: Not affected
7 6 5 4 3 2 1 0
1
1
1
0
1
1
0
1
0
1
0
1
0
1
1
1
Timing:
1
1
0
1
1
0
1
0
1
0
0
0
1
1
1
Timing:
Addressing Mode:
1
0
1
1
0
1
0
1
0
0
1
1
1
1
M cycles Ð 2
T states Ð 9 (4, 5)
Register
Addressing Mode:
LD
r, n
Load register r with immediate data n.
No flags affected
rwn
7 6 5 4 3 2 1 0
0
0
r
1
1
0
n
Timing:
LD
I, A
Load Interrupt vector register (I) with the contents of A.
IwA
No flags affected
7 6 5 4 3 2 1 0
1
1
Timing:
M cycles Ð 2
T states Ð 9 (4, 5)
Register
Addressing Mode:
1
M cycles Ð 2
T states Ð 7 (4, 3)
Source Ð Immediate
Destination Ð Register
Addressing Mode:
REGISTER TO MEMORY
LD
m 1, r
Load memory from reigster r.
No flags affected
m1 w r
7 6 5 4 3 2 1 0
M cycles Ð 2
T states Ð 9 (4, 5)
Register
0
1
1
1
0
r
Timing:
LD
A, R
Load Accumulator with contents of R register.
AwR
S: Set if negative result
Z: Set if zero result
H: Reset
P/V: Set according to IFF2 (zero if
interrupt occurs during operation)
N: Reset
C: Not affected
Addressing Mode:
7
6
5
4
3
2
1
1
1
NX
1
1
1
0
0
1
1
1
0
LD (HL), r
M cycles Ð 2
T states Ð 7 (4,3)
Source Ð Register
Destination Ð Register Indirect
0
LD (IX a d), r(for NX e 0)
1
LD (IY a d), r(for NX e 1)
r
d
Timing:
Addressing Mode:
32
M cycles Ð 2
T states Ð 19 (4, 4, 3, 5, 3)
Source Ð Register
Destination Ð Indexed
12.4 8-Bit Loads (Continued)
LD
MEMORY TO REGISTER
m2, A
Load memory from the Accumulator.
LD
m2 w A
7 6 5
Load register r from memory location m1.
r w m1
No flags affected
7 6 5 4 3 2 1 0
4
3
2
1
No flags affected
0
0
0
0
0
0
0
1
0
LD (BC), A
0
0
0
1
0
0
1
0
LD (DE), A
0
Timing:
7
6
5
4
3
2
1
M cycles Ð 2
T states Ð 7 (4, 3)
Source Ð Register (Implied)
Destination Ð Register Indirect
0
0
0
1
1
0
0
1
0
Addressing Mode:
r, m1
1
r
1
1
Timing:
Addressing Mode:
7
6
5
4
3
2
1
1
1
NX
1
1
1
0
0
1
1
1
LD (nn), A
r
0
LD R, (HL)
M cyclesÐ2
T statesÐ7 (4, 3)
SourceÐRegister Indirect
DestinationÐRegister
0
LD r, (IX a d) (for NX e 0)
1
LD r, (IY a d) (for NX e 1)
0
n (low-order byte)
d
n (high-order byte)
Timing:
Timing:
M cycles Ð 4
T states Ð 3 (4, 3, 3, 3)
Source Ð Register (Implied)
Destination Ð Direct
Addressing Mode:
LD
Addressing Mode:
LD
m1, n
0
1
1
0
1
1
0
LD(HL), n
0
n
Timing:
Addressing Mode:
7 6
5
4 3 2 1 0
1 1 NX 1 1 1 0 1
A, m2
Load the Accumulator from memory location m2.
No flags affected
A w m2
7 6 5 4 3 2 1 0
LD A, (BC)
0 0 0 0 1 0 1 0
Load memory with immediate data.
No flags affected
m1 w n
7 6 5 4 3 2 1 0
0
M cyclesÐ5
T statesÐ19 (4, 4, 3, 5, 3)
SourceÐIndexed
DestinationÐRegister
0
0
1
1
0
1
0
Timing:
M cyclesÐ3
T statesÐ10 (4, 3, 3)
SourceÐImmediate
DestinationÐRegister Indirect
7
6
5
4
3
2
1
0
0
1
1
1
0
1
0
Addressing Mode:
LD (IX a d), n(for NX e 0)
LD A, (DE)
M cyclesÐ2
T statesÐ7 (4, 3)
SourceÐRegister Indirect
DestinationÐRegister (Implied)
0
LD A, (nn)
LD (IY a d), n(for NX e 1)
n (low-order byte)
0 0
1
1 0 1 1 0
n (high-order byte)
d
Timing:
n
Addressing Mode:
Timing:
Addressing Mode:
M cyclesÐ5
T statesÐ19 (4, 4, 3, 5, 3)
SourceÐImmediate
DestinationÐIndexed
33
M cyclesÐ4
T statesÐ13 (4, 3, 3, 3)
SourceÐImmediate Extended
DestinationÐRegister (Implied)
12.5 16-Bit Loads
REGISTER TO REGISTER
REGISTER TO MEMORY
LD
rr, nn
Load 16-bit register pair with immediate data.
rr, w nn
No flags affected
7 6 5 4 3 2 1 0
LD BC, nn
LD
0
0
rp
0
0
0
1
n (low-order byte)
(nn), rr
Load memory location nn with contents of 16-bit register, rr.
(nn) w rrL
No flags affected
(nn a 1) w rrH
7 6 5 4 3
LD DE, nn
LD HL, nn
LD SP, nn
0
0
1
0
0
2
1
0
0
1
0
LD (nn), HL
(note an alternate
opcode below)
n (low-order byte)
n (high-order byte)
Timing:
Addressing Mode:
7
6
5
4
3
2
1
1
1
NX
1
1
1
0
0
0
1
0
0
0
0
n (high-order byte)
M cyclesÐ3
T statesÐ10 (4, 3, 3)
SourceÐImmediate Extended
DestinationÐRegister
0
LD IX, nn (for NX e 0)
1
LD IY, nn (for NX e 1)
Timing:
Addressing Mode:
7
6
5
4
3
2
1
1
1
1
0
1
1
0
0
1
0
0
1
1
rp
M cyclesÐ5
T statesÐ16 (4, 3, 3, 3, 3)
SourceÐRegister
DestinationÐDirect
0
LD (nn), BC
LD (nn), DE
1
LD (nn), HL
LD (nn), SP
1
n (low-order byte)
n (low-order byte)
n (high-order byte)
Timing:
M cyclesÐ4
T statesÐ14 (4, 4, 3, 3)
SourceÐImmediate Extended
DestinationÐRegister
Addressing Mode:
n (high-order byte)
Timing:
Addressing Mode:
LD
SP, ss
Load the SP from 16-bit register ss.
No flags affected
SP w ss
7 6 5 4 3 2 1 0
1
1
1
1
1
0
0
Timing:
Addressing Mode:
7
6
5
4
3
2
1
1
1
NX
1
1
1
0
1
1
1
1
1
0
0
Timing:
Addressing Mode:
1
LD SP, HL
M cyclesÐ1
T statesÐ6
SourceÐRegister
DestinationÐRegister (Implied)
0
LD SP, IX (for NX e 0)
1
LD SP, IY (for NX e 1)
7
6
5
4
3
2
1
1
1
NX
1
1
1
0
0
0
1
0
0
0
1
M cyclesÐ6
T statesÐ20 (4, 4, 3, 3, 3, 3)
SourceÐRegister
DestinationÐDirect
0
LD (nn), IX (for NX e 0)
1
LD (nn) IY (for NX e 1)
0
n (low-order byte)
n (high-order byte)
Timing:
Addressing Mode:
1
M cyclesÐ2
T statesÐ10 (4, 6)
SourceÐRegister
DestinationÐRegister (Implied)
34
M cyclesÐ6
T statesÐ20 (4, 4, 3, 3, 3, 3)
SourceÐRegister
DestinationÐDirect
12.5 16-Bit Loads (Continued)
PUSH
qq
Push the contents of register pair qq onto the memory
stack.
(SP – 1) w qqH
No flags affected
(SP – 2) w qqL
SP w SP b 2
7 6 5 4 3 2 1 0 PUSH BC
1 1
rs
0 1 0 1 PUSH DE
Addressing Mode:
7
6
5
4
3
2
1
1
1
NX
1
1
1
0
1
1
1
0
0
1
0
Timing:
Addressing Mode:
6
5
4
3
2
1
0
LD BC, (nn)
1
1
0
1
1
0
1
LD DE, (nn)
0
1
0
0
1
1
LD HL, (nn)
LD SP, (nn)
rp
n (low-order byte)
n (high-order byte)
PUSH HL
PUSH AF
Timing:
7
1
Timing:
M cyclesÐ3
T statesÐ11 (5, 3, 3)
SourceÐRegister
DestinationÐRegister Indirect
(Stack)
0
PUSH IX (for NX e 0)
1
PUSH IY (for NX e 1)
Addressing Mode:
7
6
5
4
3
2
1
1
1
NX
1
1
1
0
0
0
1
0
1
0
1
n (low-order byte)
n (high-order byte)
M cyclesÐ3
T statesÐ15 (4, 5, 3, 3)
SourceÐRegister
DestinationÐRegister Indirect
(Stack)
Timing:
M cyclesÐ6
T statesÐ20 (4, 4, 3, 3, 3, 3)
SourceÐDirect
DestinationÐRegister
Addressing Mode:
POP
qq
Pop the contents of the memory stack to register qq.
No flags affected
qqL w (SP)
qqH w (SP a 1)
SP w SP a 2
7 6 5 4 3 2 1 0 POP BC
1 1
rs
0 0 0 1 POP DE
POP HL
POP AF
LD
rr, (nn)
Load 16-bit register from memory location nn.
rrL w (nn)
No flags affected
rrH w (nn a 1)
7 6 5 4 3 2 1 0
LD HL, (nn)
0 0 1 0 1 0 1 0
(note an alternate
opcode below)
n (low-order byte)
Timing:
n (high-order byte)
Addressing Mode:
0
1
MEMORY TO REGISTER
Timing:
M cyclesÐ6
T statesÐ20 (4, 4, 3, 3, 3, 3)
SourceÐDirect
DestinationÐRegister
0
LD IX, (nn)(for NX e 0)
1
LD IY, (nn) (for NX e 1)
Addressing Mode:
M cyclesÐ5
T statesÐ16 (4, 3, 3, 3, 3)
SourceÐDirect
DestinationÐRegister
7
6
5
4
3
2
1
1
1
NX
1
1
1
0
1
1
1
0
0
0
0
Timing:
Addressing Mode:
35
M cyclesÐ3
T statesÐ10 (4, 3, 3)
SourceÐRegister Indirect
(Stack)
DestinationÐRegister
0
POP IX (for NX e 0)
1
POP IY (for NX e 1)
1
M cyclesÐ4
T statesÐ14 (4, 4, 3, 3)
SourceÐRegister Indirect
(Stack)
DestinationÐRegister
12.6 8-Bit Arithmetic
REGISTER ADDRESSING ARITHMETIC
Op
Hex
Hex
Value
Value Number
C
H
C
In
In
Added
Before
Before
After
Upper
Lower
To
DAA
DAA
DAA
Digit
Digit
Byte
(Bits 7-4)
(Bits 3-0)
ADD
ADC
INC
0
0
0
0
0
0
1
1
1
0-9
0-8
0-9
A-F
9-F
A-F
0-2
0-2
0-3
0
0
1
0
0
1
0
0
1
0-9
A-F
0-3
0-9
A-F
0-3
0-9
A-F
0-3
00
06
06
60
66
66
60
66
66
0
0
0
1
1
1
1
1
1
SUB
SBC
DEC
NEG
0
0
1
1
0-9
0-8
7-F
6-F
0
1
0
1
0-9
6-F
0-9
6-F
00
FA
A0
9A
0
0
1
1
1
0
0
0
0
Addressing Mode:
6
5
4
3
0
0
0
1
2
1
0
r
Timing:
M cyclesÐ1
T statesÐ4
SourceÐRegister
DestinationÐImplied
Addressing Mode:
SUB
r
Subtract the contents of register r from the Accumulator.
S: Set if result is negative
AwAbr
Z: Set if result is zero
H: Set if borrow from bit 4
P/V: Set if result exceeds 8-bit 2’s
complement range
N: Set
C: Set according to borrow
7 6 5 4 3 2 1 0
1
0
0
1
0
r
Timing:
M cyclesÐ1
T statesÐ4
SourceÐRegister
DestinationÐImplied
Addressing Mode:
ADD
A, r
Add contents of register r to the
Accumulator.
A w Aar
S: Set if negative result
Z: Set if zero result
H: Set if carry from bit 3
P/V: Set according to overflow
condition
N: Reset
C: Set if carry from bit 7
7 6 5 4 3 2 1 0
Timing:
7
1
SBC
A, r
Subtract contents of register r and the carry bit C from the
Accumulator.
A w A b r b CY
S: Set if result is negative
Z: Set if result is zero
H: Set if borrow from bit 4
P/V: Set if result exceeds 8-bit 2’s
complement range
N: Set
C: Set according to borrow
7 6 5 4 3 2 1 0
r
M cyclesÐ1
T statesÐ4
SourceÐRegister
DestinationÐImplied
1
0
0
1
1
Timing:
Addressing Mode:
ADC
A, r
Add contents of register r, plus the carry flag, to the Accumulator.
A w A a r a CY
S: Set if negative result
Z: Set if zero result
H: Set if carry from bit 3
P/V: Set if result exceeds 2’s complement range
N: Reset
C: Set if carry from bit 7
r
M cyclesÐ1
T statesÐ4
SourceÐRegister
DestinationÐImplied
AND
r
Logically AND the contents of the r register and the Accumulator.
AwA!r
S: Set if result is negative
Z: Set if result is zero
H: Set
P/V: Set if result parity is even
N: Reset
C: Reset
36
12.6 8-Bit Arithmetic (Continued)
7
6
5
4
3
1
0
1
0
0
2
1
0
r
7
6
0
0
5
4
3
r
Timing:
M cyclesÐ1
Timing:
Addressing Mode:
T statesÐ4
SourceÐRegister
DestinationÐImplied
Addressing Mode:
OR
r
Logically OR the contents of the r register and the Accumulator.
AwA¶r
S: Set if result is negative
7
6
5
4
3
1
0
1
1
0
r
1
M cyclesÐ1
T statesÐ4
SourceÐRegister
DestinationÐImplied
Addressing Mode:
0
1
0
1
Timing:
Addressing Mode:
INC
r
Increment register r.
rwra1
0
0
M cyclesÐ1
T statesÐ4
SourceÐRegister
DestinationÐRegister
0
1
1
1
r
Timing:
M cyclesÐ1
T statesÐ4
SourceÐRegister
DestinationÐImplied
Addressing Mode:
XOR
r
Logically exclusively OR the contents of the r register with
the Accumulator.
AwA Z r
S: Set if result is negative
Z: Set if result is zero
H: Reset
P/V: Set if result parity is even
N: Reset
C: Reset
7 6 5 4 3 2 1 0
1
1
0
CP
r
Compare the contents of register r with the Accumulator
and set the flags accordingly.
Abr
S: Set if result is negative
Z: Set if result is zero
H: Set if borrow from bit 4
P/V: Set if result exceeds 8-bit 2’s
complement range
N: Set
C: Set according to borrow
7 6 5 4 3 2 1 0
Z: Set if result is zero
H: Reset
P/V: Set if result parity is even
N: Reset
C: Reset
2 1 0
Timing:
2
1
DEC
r
Decrement the contents of register r.
S: Set if result is negative
rwrb1
Z: Set if result is zero
H: Set according to a borrow from
bit 4
P/V: Set only if r was X’80 prior to
operation
N: Set
C: N/A
7 6 5 4 3 2 1 0
r
M cyclesÐ1
T statesÐ4
SourceÐRegister
DestinationÐImplied
0
0
r
Timing:
Addressing Mode:
1
0
1
M cyclesÐ1
T statesÐ4
SourceÐRegister
DestinationÐRegister
CPL
Complement the Accumulator (1’s complement).
S: N/A
AwA
Z: N/A
H: Set
P/V: N/A
N: Set
C: N/A
S: Set if result is negative
Z: Set if result is zero
H: Set if carry from bit 3
P/V: Set only if r was X’7F before
operation
N: Reset
C: N/A
37
12.6 8-Bit Arithmetic (Continued)
7
6
5
4
3
2
1
0
DAA
0
0
1
0
1
1
1
1
Adjust the Accumulator for BCD addition and subtraction
operations. To be executed after BCD data has been operated upon the standard binary ADD, ADC, INC, SUB, SBC,
DEC or NEG instructions (see ‘‘Register Addressing Arithmetic’’ table).
ÐÐÐ
S: Set according to bit 7 of result
Z: Set if result is zero
H: Set according to instructions
P/V: Set according to parity of result
N: N/A
C: Set according to instructions
7 6 5 4 3 2 1 0
Timing:
M cyclesÐ1
T statesÐ4
Implied
Addressing Mode:
NEG
Negate the Accumulator (2’s complement).
Aw0bA
S: Set if result is negative
Z: Set if result is zero
H: Set according to borrow from
bit 4
P/V: Set only if Accumulator was
X’80 prior to operation
N: Set
C: Set only if Accumulator was not
X’00 prior to operation
7 6 5 4 3 2 1 0
1
1
1
0
1
1
0
1
0
1
0
0
0
1
0
0
Timing:
0
0
1
1
1
1
1
Timing:
SCF
Set the carry flag.
CY w 1
7
6
5
4
3
0
0
1
1
0
1
Timing:
Addressing Mode:
1
1
1
M cyclesÐ1
T statesÐ4
Implied
ADD
A, n
Add the immediate data n to the Accumulator.
AwAan
S: Set if result is negative
Z: Set if result is zero
H: Set if carry from bit 3
P/V: Set if result exceeds 8-bit 2’s
complement range
N: Reset
C: Set if carry from bit 7
7 6 5 4 3 2 1 0
1
1
0
0
0
1
1
0
n
Timing:
1
S: N/A
Z: N/A
H: Reset
P/V: N/A
N: Reset
C: Set
2 1 0
1
0
IMMEDIATELY ADDRESSED ARITHMETIC
Addressing Mode:
M cyclesÐ1
T statesÐ4
Implied
Addressing Mode:
0
Addressing Mode:
CCF
Complement the carry flag.
CY w CY
S: N/A
Z: N/A
H: Previous carry
P/V: N/A
N: Reset
C: Complement of previous carry
7 6 5 4 3 2 1 0
0
1
Timing:
M cyclesÐ2
T statesÐ8 (4, 4)
Implied
Addressing Mode:
0
M cyclesÐ2
T statesÐ7 (4, 3)
SourceÐImmediate
DestinationÐImplied
ADC
A, n
Add, with carry, the immediate data n and the Accumulator.
S: Set if result is negative
A w A a n a CY
Z: Set if result is zero
H: Set if carry from bit 3
P/V: Set if result exceeds 8-bit 2’s
complement range
N: Reset
C: Set according to carry from bit
7
1
M cyclesÐ1
T statesÐ4
Implied
38
12.6 8-Bit Arithmetic (Continued)
7
6
5
4
3
2
1
0
AND
1
1
0
0
1
1
1
0
The immediate data n is logically AND’ed to the Accumulator.
AwA!n
S: Set if result is negative
Z: Set if result is zero
H: Set
P/V: Set if result parity is even
N: Reset
C: Reset
7 6 5 4 3 2 1 0
n
Timing:
M cyclesÐ2
T statesÐ7 (4, 3)
SourceÐImmediate
DestinationÐImplied
Addressing Mode:
SUB
n
Subtract the immediate data n from the Accumulator.
S: Set if result is negative
AwAbn
Z: Set if result is zero
H: Set if borrow from bit 4
P/V: Set if result exceeds 8-bit 2’s
complement range
N: Set
C: Set according to borrow
condition
7 6 5 4 3 2 1 0
1
1
0
1
0
1
1
1
6
5
4
3
1
1
0
1
1
1
1
1
Addressing Mode:
1
1
1
0
1
0
M cyclesÐ2
T statesÐ7 (4, 3)
SourceÐImmediate
DestinationÐImplied
1
1
0
n
Timing:
Addressing Mode:
M cyclesÐ2
T statesÐ7 (4, 3)
SourceÐImmediate
DestinationÐImplied
XOR
n
The immediate data n is exclusively OR’ed with the Accumulator.
AwA Z n
S: Set if result is negative
Z: Set if result is zero
0
H: Reset
P/V: Set if result parity is even
N: Reset
C: Reset
n
Timing:
1
OR
n
The immediate data n is logically OR’ed to the contents of
the Accumulator.
AwA¶s
S: Set if result is negative
Z: Set if result is zero
H: Reset
P/V: Set if result parity is even
N: Reset
C: Reset
7 6 5 4 3 2 1 0
SBC
A, n
Subtract, with carry, the immediate data n from the Accumulator.
A w A b n b CY
S: Set if result is negative
7
0
Addressing Mode:
0
Z: Set if result is zero
H: Set if borrow from bit 4
P/V: Set if result exceeds 8-bit 2’s
complement range
N: Set
C: Set according to borrow
condition
2 1 0
0
Timing:
M cyclesÐ2
T statesÐ7 (4, 3)
SourceÐImmediate
DestinationÐImplied
Addressing Mode:
1
n
n
Timing:
1
n
M cyclesÐ2
T statesÐ7 (4, 3)
SourceÐImmediate
DestinationÐImplied
39
12.6 8-Bit Arithmetic (Continued)
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
1
1
1
0
1
1
1
0
1
1
NX
1
1
1
0
1
1
0
0
0
0
1
1
0
n
Timing:
M cyclesÐ2
T statesÐ7 (4, 3)
SourceÐImmediate
DestinationÐImplied
Addressing Mode:
7
6
5
4
3
1
1
1
1
1
1
1
M cyclesÐ5
T statesÐ19 (4, 4, 3, 5, 3)
SourceÐIndexed
DestinationÐImplied
Addressing Mode:
ADC
A, m1
Add the contents of the memory location m1 plus the carry
to the Accumulator.
A w A a m1 a CY S: Set if result is negative
Z: Set if result is zero
H: Set if carry from bit 3
P/V: Set if result exceeds 8-bit 2’s
complement range
N: Reset
C: Set according to carry from bit
7
7 6 5 4 3 2 1 0
0
1
n
0
0
0
1
1
1
Timing:
Timing:
M cyclesÐ2
T statesÐ7 (4, 3)
Immediate
Addressing Mode:
Addressing Mode:
MEMORY ADDRESSED ARITHMETIC
7 6
ADD
A, m1
Add the contents of the memory location m1 to the Accumulator.
A w A a m1
S: Set if result is negative
1 1 NX 1 1 1 0 1
7
6
5
4
3
Z: Set if result is zero
H: Set if carry from bit 3
P/V: Set if result exceeds 8-bit 2’s
complement range
N: Reset
C: Set according to carry from bit
7
2 1 0
1
0
0
0
0
1
Timing:
Addressing Mode:
1
0
ADD A, (IY a d) (for NX e 1)
d
Timing:
CP
n
Compare the immediate data n with the contents of the Accumulator via subtraction and return the appropriate flags.
The contents of the Accumulator are not affected.
Abn
S: Set if result is negative
Z: Set if result is zero
H: Set if borrow from bit 4
P/V: Set if result exceeds 8-bit 2’s
complement range
N: Set
C: Set according to borrow condition
2 1 0
ADD A, (IX a d) (for NX e 0)
1 0
5
0
4 3 2 1 0
0
ADC A, (HL)
M cyclesÐ2
T statesÐ7 (4, 3)
SourceÐRegister Indirect
DestinationÐImplied
ADC A, (IX a d) (for NX e 0)
ADC A, (IY a d) (for NX e 1)
0 1 1 1 0
d
Timing:
Addressing Mode:
M cyclesÐ5
T statesÐ19 (4, 4, 3, 5, 3)
SourceÐIndexed
DestinationÐImplied
SUB
m1
Subtract the contents of memory location m1 from the Accumulator.
A w A b m1
S: Set if result is negative
Z: Set if result is zero
H: Set if borrow from bit 4
P/V: Set if result exceeds 8-bit 2’s
complement range
N: Set
C: Set according to borrow condition
ADD A, (HL)
M cyclesÐ2
T statesÐ7 (4, 3)
SourceÐRegister Indirect
DestinationÐImplied
40
12.6 8-Bit Arithmetic (Continued)
7
6
5
4
3
2
1
0
1
0
0
1
0
1
1
0
Timing:
AND
SUB (HL)
M cyclesÐ2
Addressing Mode:
7
6
5
4
3
2
1
1
1
NX
1
1
1
0
1
0
0
1
0
1
1
T statesÐ7 (4, 3)
SourceÐRegister Indirect
DestinationÐImplied
0
SUB (IX a d) (for NX e 0)
1
SUB (IY a d) (for NX e 1)
0
1
d
M cyclesÐ5
T statesÐ19 (4, 4, 3, 5, 3)
SourceÐIndexed
DestinationÐImplied
Addressing Mode:
7
6
5
4
3
Z: Set if result is zero
H: Set if carry from bit 3
P/V: Set if result exceeds 8-bit 2’s
complement range
N: Set
C: Set according to borrow
condition
2 1 0
1
0
0
1
1
1
1
Timing:
Addressing Mode:
4 3 2 1 0
1 1 NX 1 1 1 0 1
1 0
0
1
0
0
1
1
Addressing Mode:
SBC
A, m1
Subtract, with carry, the contents of memory location m1
from the Accumulator.
A w A b m1 b CY S: Set if result is negative
5
0
Timing:
Timing:
7 6
m1
The data in memory location m1 is logically AND’ed to the
Accumulator.
A w A ! m1
S: Set if result is negative
Z: Set if result is zero
H: Set
P/V: Set if result parity is even
N: Reset
C: Reset
7 6 5 4 3 2 1 0
0
5
4
3
2
1
1
NX
1
1
1
0
1
0
1
0
0
1
1
Timing:
0
M cyclesÐ5
T statesÐ19 (4, 4, 3, 5, 3)
SourceÐIndexed
DestinationÐImplied
Addressing Mode:
OR
m1
The data in memory location m1 is logically OR’ed with the
Accumulator.
A w A ¶ m1
S: Set if result is negative
Z: Set if result is zero
H: Reset
P/V: Set if result parity is even
N: Reset
C: Reset
7 6 5 4 3 2 1 0
SBC A, (HL)
M cyclesÐ2
T statesÐ7 (4, 3)
SourceÐRegister Indirect
DestinationÐImplied
SBC A, (IX a d) (for NX e 0)
SBC A, (IY a d) (for NX e 1)
1
0
1
1
0
1
1
Timing:
d
Addressing Mode:
6
1
AND (HL)
M cyclesÐ2
T statesÐ7 (4, 3)
SourceÐRegister Indirect
DestinationÐImplied
0
AND (IX a d) (for NX e 0)
1
AND (IY a d) (for NX e 1)
d
1 1 1 1 0
Timing:
7
0
Addressing Mode:
M cyclesÐ5
T statesÐ19 (4, 4, 3, 5, 3)
SourceÐIndexed
DestinationÐImplied
7
6
5
4
3
2
1
1
1
NX
1
1
1
0
1
0
1
1
0
1
1
0
OR (HL)
M cyclesÐ2
T statesÐ7 (4, 3)
SourceÐRegister Indexed
DestinationÐImplied
0
OR (IX a d) (for NX e 0)
1
OR (IY a d) (for NX e 1)
0
d
Timing:
Addressing Mode:
41
M cyclesÐ5
T statesÐ19 (4, 4, 3, 5, 3)
SourceÐIndexed
DestinationÐImplied
12.6 8-Bit Arithmetic (Continued)
XOR
Timing:
m1
T statesÐ19 (4, 4, 3, 5, 3)
The data in memory location m1 is exclusively OR’ed with
the data in the Accumulator.
A w A Z m1
S: Set if result is negative
7
6
5
4
3
Z: Set if result is zero
H: Reset
P/V: Set if result parity is even
N: Reset
C: Reset
2 1 0
1
0
1
0
1
1
1
Timing:
Addressing Mode:
7
6
5
4
3
2
1
1
1
NX
1
1
1
0
1
0
1
0
1
1
1
0
Addressing Mode:
INC
XOR (HL)
M cyclesÐ2
T statesÐ7 (4, 3)
SourceÐRegister Indexed
DestinationÐImplied
0
XOR (IX a d) (for NX e 0)
1
XOR (IY a d) (for NX e 1)
0
7
6
5
4
3
1
0
1
1
1
1
0
7
6
5
4
3
2
1
1
1
NX
1
1
1
0
1
0
1
1
1
1
1
1
0
1
0
7
6
5
4
3
2
1
1
1
NX
1
1
1
0
0
0
1
1
0
1
0
0
INC (HL)
M cyclesÐ3
T statesÐ11 (4, 4, 3)
SourceÐRegister Indexed
DestinationÐRegister Indexed
0
INC (IX a d) (for NX e 0)
1
INC (IY a d) (for NX e 1)
0
d
Timing:
Addressing Mode:
DEC
M cyclesÐ6
T statesÐ23 (4, 4, 3, 5, 4, 3)
SourceÐIndexed
DestinationÐIndexed
m1
Decrement data in memory location m1.
S: Set if result is negative
m1 w m1 b 1
Z: Set if result is zero
H: Set according to borrow from
bit 4
P/V: Set only if m1 was X’80 before
operation
N: Set
CP (HL)
M cyclesÐ2
Addressing Mode:
1
Addressing Mode:
0
Z: Set if result is zero
H: Set if borrow from bit 4
P/V: Set if result exceeds 8-bit 2’s
complement range
N: Set
C: Set according to borrow
condition
2 1 0
1
0
Timing:
CP
m1
Compare the data in memory location m1 with the data in
the Accumulator via subtraction.
A b m1
S: Set if result is negative
Timing:
m1
Increment data in memory location m1.
m1 w m1 a 1
S: Set if result is negative
Z: Set if result is zero
H: Set according to carry from bit
3
P/V: Set if data was X’7F before operation
N: Reset
C: N/A
7 6 5 4 3 2 1 0
M cyclesÐ5
T statesÐ19 (4, 4, 3, 5, 3)
SourceÐIndexed
DestinationÐImplied
Addressing Mode:
SourceÐIndexed
DestinationÐImplied
d
Timing:
M cyclesÐ5
C: N/A
T statesÐ7 (4, 3)
SourceÐRegister Indirect
DestinationÐImplied
0
CP (IX a d) (for NX e 0)
1
CP (IY a d) (for NX e 1)
0
d
42
P/V: Set if result exceeds 16-bit 2’s
complement range
12.6 8-Bit Arithmetic (Continued)
7
6
5
4
3
2
1
0
0
0
1
1
0
1
0
1
Timing:
M cycles Ð 3
T states Ð 11 (4, 4, 3)
Source Ð Register Indexed
Destination Ð Register Indexed
Addressing Mode:
7 6
5
4 3 2 1 0
1
7
6
5
4
3
2
C: Set if carry out of bit 15
1 0
1
1
1
0
1
1
0
0
1
1
0
1
pp
Timing:
Addressing Mode:
DEC (IY a d) (for NX e 1)
1 0 1 0 1
M cycles Ð 6
T states Ð 23 (4, 4, 3, 5, 4, 3)
Source Ð Indexed
Destination Ð Indexed
Addressing Mode:
7
6
5
4
3
S: Set if result is negative
Z: Set if result is zero
H: Set according to borrow from
bit 12
P/V: Set if result exceeds 16-bit 2’s
complement range
N: Set
C: Set according to borrow condition
2 1 0
1
1
1
0
1
1
0
1
0
1
0
0
1
0
12.7 16-Bit Arithmetic
ADD
ss, pp
Add the contents of the 16-bit register rp or pp to the contents of the 16-bit register ss.
ss w ss a rp
S: N/A
or
ss
w ss a pp
7
6
0
0
5
4
rp
Z: N/A
H: Set if carry from bit 11
P/V: N/A
N: Reset
C: Set if carry from bit 15
3 2 1 0
1
Timing:
Addressing Mode:
7
6
5
4
3
1
1
NX
1
1
0
0
pp
1
Timing:
Addressing Mode:
0
0
1
0
pp
Timing:
ADD HL, rp
M cycles Ð 4
T states Ð 15 (4, 4, 4, 3)
Source Ð Register
Destination Ð Register
Addressing Mode:
M cycles Ð 3
T states Ð 11 (4, 4, 3)
Source Ð Register
Destination Ð Register
2 1 0
ADD IX, pp (for NX e 0)
1 0 1
ADD IY, pp (for NX e 1)
0
0
SBC
HL, pp
Subtract, with carry, the contents of the 16-bit pp register
from the 16-bit HL register.
HL w HL b pp b CY
d
Timing:
1
M cycles Ð 4
T states Ð 15 (4, 4, 4, 3)
Source Ð Register
Destination Ð Register
DEC (IX a d) (for NX e 0)
1 1 NX 1 1 1 0 1
0 0
N: Reset
DEC (HL)
INC
rr
Increment the contents of the 16-bit register rr.
No flags affected
rr w rr a 1
7 6 5 4 3 2 1 0 INC BC
0 0
rp
0 0 1 1 INC DE
INC HL
INC SP
1
M cycles Ð 4
T states Ð 15 (4, 4, 4, 3)
Source Ð Register
Destination Ð Register
Timing:
Addressing Mode:
7 6 5 4 3
ADC
HL, pp
The contents of the 16-bit register pp are added, with the
carry bit, to the HL register.
HL w HL a pp a CY
1
NX
1
1
1
0
0
0
1
0
0
0
1
Addressing Mode:
43
1
1
Timing:
S: Set if result is negative
Z: Set if result is zero
H: Set according to carry out of bit
11
2
M cycles Ð 1
T states Ð 6
Register
0
INC IX (for NX e 0)
1
INC IY (for NX e 1)
1
M cycles Ð 2
T states Ð 10 (4, 6)
Register
12.7 16-Bit Arithmetic (Continued)
7
6
5
4
3
2
1
0
DEC
rr
Decrement the contents of the 16-bit register rr.
1
1
0
0
1
0
1
1
rr w rr b 1
7 6 5 4
0
1
0
0
rp
3
2
1
1
0
1
No flags affected
0 DEC BC
1 DEC DE
DEC HL
DEC SP
b
r
Timing:
M cycles Ð 2
T states Ð 8 (4, 4)
Bit/Register
Addressing Mode:
MEMORY
Timing:
Addressing Mode:
7 6 5 4 3
2
1
1
1
NX
1
1
1
0
0
0
1
0
1
0
1
Timing:
SET
M cycles Ð 1
T states Ð 6
Register
0
DEC IX (for NX e 0)
1
DEC IY (for NX e 1)
1
1
1
1
1
0
0
1
b
0
1
1
1
1
0
Timing:
M cycles Ð 2
T states Ð 10 (4, 6)
Register
Addressing Mode:
b, m1
Bit b in memory location m1 is set.
No flags affected
m1b w 1
7 6 5 4 3 2 1 0
Addressing Mode:
7 6 5 4 3 2 1 0
12.8 Bit Set, Reset, and Test
SET b, (HL)
M cycles Ð 4
T states Ð 15 (4, 4, 4, 3)
Bit/Register Indirect
SET b, (IX a d) (for NX e 0)
1 1 NX 1 1 1 0 1
SET b, (IY a d) (for NX e 1)
REGISTER
SET
b, r
Bit b in register r is set.
Rb w 1
7 6 5 4 3 2 1
1
1
0
0
1
0
1
1 1
0
0 1 0 1 1
d
No flags affected
0
1 1
1
b
1 1 0
Timing:
1
1
b
Timing:
Addressing Mode:
M cycles Ð 2
T states Ð 8 (4, 4)
Bit/Register
RES
b, r
Bit b in register r is reset.
rb w 0
7 6 5 4 3 2 1
No flags affected
0
1
1
0
0
M cycles Ð 6
T states Ð 23 (4, 4, 3, 5, 4, 3)
Bit/Indexed
r
1
0
1
Addressing Mode:
RES
b, m1
Bit b in memory location m1 is reset.
No flags affected
m1b w 0
7 6 5 4 3 2 1 0
1
1
1
1
0
0
0
1
b
0
1
1
1
Timing:
1
0
b
Timing:
Addressing Mode:
r
Addressing Mode:
7 6 5 4 3 2 1 0
M cycles Ð 2
T states Ð 8 (4, 4)
Bit/Register
1 1 NX 1 1 1 0 1
BIT
b, r
Bit b in register r is tested with the result put in the Z flag.
Z w rb
S: Undefined
Z: Inverse of tested bit
H: Set
P/V: Undefined
N: Reset
C: N/A
1 1
0
1
RES b, (HL)
0
M cycles Ð 4
T states Ð 15 (4, 4, 4, 3)
Bit/Register Indirect
RES b, (IX a d) (for NX e 0)
RES b, (IY a d) (for NX e 1)
0 1 0 1 1
d
1 0
b
Timing:
Addressing Mode:
44
1 1 0
M cycles Ð 6
T states Ð 23 (4, 4, 3, 5, 4, 3)
Bit/Indexed
12.8 Bit Set, Reset, and Test (Continued)
7
6
5
4
3
2
1
0
BIT
0
0
0
0
0
1
1
1
B, m1
Bit b in memory location m1 is tested via the Z flag.
w m1b
S: Undefined
Z: Inverse of tested bit
H: Set
P/V: Undefined
N: Reset
C: N/A
7 6 5 4 3 2 1 0
Timing:
M cycles Ð 1
Z
1
1
0
1
0
0
1
b
0
1
1
1
1
0
RLCA
T states Ð 4
Addressing Mode:
Implied
(Note RLCA does not affect S, Z, or P/V flags.)
RL
r
Rotate register r left through carry.
BIT b, (HL)
TL/C/5171 – 58
Timing:
Addressing Mode:
7 6 5 4 3
2
1
1
1
NX
1
1
1
0
1
1
0
0
1
0
1
M cycles Ð 3
T states Ð 12 (4, 4, 4)
Bit/Register Indirect
0
BIT b, (IX a d) (for NX e 0)
1
BIT b, (IY a d) (for NX e 1)
1
d
0
1
b
1
1
0
Timing:
M cycles Ð 5
T states Ð 20 (4, 4, 3, 5, 4)
Bit/Indexed
Addressing Mode:
7
6
5
4
3
S: Set if result is negative
Z: Set if result is zero
H: Reset
P/V: Set if result parity is even
N: Reset
C: Set according to bit 7 of r
2 1 0
1
1
0
0
1
0
0
0
0
1
0
1
r
Timing:
Addressing Mode:
7 6 5 4 3
12.9 Rotate and Shift
0
REGISTER
0
0
1
0
1
RL r
(Note alternate for
A register below)
2
1
M cycles Ð 2
T states Ð 8 (4, 4)
Register
0
1
1
1
RLA
Timing:
M cycles Ð 1
T states Ð 4
Addressing Mode:
Implied
(Note RLA does not affect S, Z, or P/V flags.)
RLC
r
Rotate register r left circular.
RRC
r
Rotate register r right circular.
TL/C/5171 – 57
7
6
5
4
3
S: Set if result is negative
Z: Set if result is zero
H: Reset
P/V: Set if result parity is even
N: Reset
C: Set according to bit 7 of r
2 1 0
1
1
0
0
1
0
0
0
0
0
0
1
1
r
TL/C/5171 – 59
S: Set if result is negative
Z: Set if result is zero
H: Reset
P/V: Set if result parity is even
N: Reset
C: Set according to bit 0 of r
RLC r
(Note alternate for
A register below)
Timing:
Addressing Mode:
M cycles Ð 2
T states Ð 8 (4, 4)
Register
45
12.9 Rotate and Shift (Continued)
7
6
5
4
3
2
1
0
1
1
0
0
1
0
1
1
0
0
0
0
1
r
0
0
0
0
1
N: Reset
(Note alternate for
A register below)
Timing:
Addressing Mode:
7 6 5 4 3
P/V: Set if result parity is even
RRC r
2
1
M cycles Ð 2
T states Ð 8 (4, 4)
Register
0
1
1
1
7
6
5
4
3
2
C: Set according to bit 7 of r
1 0
1
1
0
0
1
0
1
0
0
1
0
0
r
Timing:
M cycles Ð 2
T states Ð 8 (4, 4)
Register
Addressing Mode:
RRCA
1
SRA
r
Shift register r right arithmetic.
Timing:
M cycles Ð 1
T states Ð 4
Addressing Mode:
Implied
(Note RRCA does not affect S, Z, or P/V flags.)
RR
r
Rotate register r right through carry.
TL/C/5171 – 62
7
6
5
4
3
S: Set if result is negative
Z: Set if result is zero
H: Reset
P/V: Set if result parity is even
N: Reset
C: Set according to bit 0 of r
2 1 0
1
1
0
0
1
0
0
0
1
0
1
TL/C/5171–60
7
6
5
4
S: Set if result is negative
Z: Set if result is zero
H: Reset
P/V: Set if result parity is even
N: Reset
C: Set according to bit 0 of r
3
2
1
0
1
1
0
0
1
0
0
0
1
1
0
0
0
Timing:
0
1
1
1
r
Timing:
Addressing Mode:
7 6 5 4 3
0
1
1
1
1
M cycles Ð 2
T states Ð 8 (4, 4)
Register
Addressing Mode:
SRL
r
Shift register r right logical.
(Note alternate for
A register below)
2
1
r
Timing:
RR r
M cycles Ð 2
T states Ð 8 (4, 4)
Register
0
1
TL/C/5171 – 63
7
6
5
4
3
S: Reset
Z: Set if result is zero
H: Reset
P/V: Set if result parity is even
N: Reset
C: Set according to bit 0 of r
2 1 0
1
1
0
0
1
0
0
0
1
1
1
RRA
M cycles Ð 1
T states Ð 4
Addressing Mode:
Implied
(Note RRA does not affect S, Z, or P/V flags.)
SLA
r
Shift register r left arithmetric.
Timing:
TL/C/5171–61
Addressing Mode:
S: Set if result is negative
Z: Set if result is zero
H: Reset
46
1
1
r
M cycles Ð 2
T states Ð 8 (4, 4)
Register
12.9 Rotate and Shift (Continued)
MEMORY
7
6
5
4
3
2
1
0
RLC
1
1
0
0
1
0
1
1
0
0
0
1
0
1
1
0
m1
Rotate date in memory location m1 left circular.
Timing:
Addressing Mode:
7 6 5 4 3
TL/C/5171 – 64
7
6
5
4
3
S: Set if result is negative
Z: Set if result is zero
H: Reset
P/V: Set if result parity is even
N: Reset
C: Set according to bit 7 of m1
2 1 0
1
1
0
0
1
0
1
1
0
0
0
0
0
1
1
0
Timing:
Addressing Mode:
7 6 5 4 3
2
1
1
1
NX
1
1
1
0
1
1
0
0
1
0
1
RL (HL)
M cycles Ð 4
T states Ð 15 (4, 4, 4, 3)
Register Indirect
0
RL (IX a d) (for NX e 0)
1
RL (IY a d) (for NX e 1)
2
1
1
1
NX
1
1
1
0
1
1
0
0
1
0
1
1
0
1
1
0
d
0
0
0
1
Timing:
RLC (HL)
M cycles Ð 6
T states Ð 23 (4, 4, 3, 5, 4, 3)
Indexed
Addressing Mode:
RRC
m1
Rotate the data in memory location m1 right circular.
M cycles Ð 4
T states Ð 15 (4, 4, 4, 3)
Register indirect
0
RLC (IX a d) (for NX e 0)
1
RLC (IY a d) (for NX e 1)
1
TL/C/5171 – 66
d
0
0
0
0
0
Timing:
Addressing Mode:
1
1
7
6
5
4
3
2
S: Set if result is negative
Z: Set if result is zero
H: Reset
P/V: Set if result parity is even
N: Reset
C: Set according to bit 0 of m1
1 0
1
1
0
0
1
0
1
1
0
0
0
0
1
1
1
0
0
M cycles Ð 6
T states Ð 23 (4, 4, 3, 5, 4, 3)
Indexed
RL
m1
Rotate the data in memory location m1 left though carry.
Timing:
RRC (HL)
M cycles Ð 4
T states Ð 15 (4, 4, 4, 3)
Addressing Mode:
Register Indirect
7 6 5 4 3 2 1 0
RRC (IX a d) (for NX e 0)
1 1 NX 1 1 1 0 1
RRC (IY a d) (for NX e 1)
TL/C/5171 – 65
S: Set if result is negative
Z: Set if result is zero
H: Reset
P/V: Set if result parity is even
N: Reset
C: Set according to bit 7 of m1
1 1
0
0 1 0 1 1
d
0 0
0
0 1 1 1 0
Timing:
Addressing Mode:
47
M cycles Ð 6
T states Ð 23 (4, 4, 3, 5, 4, 3)
Indexed
12.9 Rotate and Shift (Continued)
RR
7 6
m1
5
4 3 2 1 0
1 1 NX 1 1 1 0 1
Rotate the data in memory location m1 right through the
carry.
1 1
0
SLA (IX a d) (for NX e 0)
SLA (IY a d) (for NX e 1)
0 1 0 1 1
d
0 0
1
0 0 1 1 0
Timing:
M cycles Ð 6
T states Ð 23 (4, 4, 3, 5, 4, 3)
Indexed
TL/C/5171–67
7
6
5
4
3
2
S: Set if result is negative
Z: Set if result is zero
H: Reset
P/V: Set if result parity is even
N: Reset
C: Set according to bit 0 of m1
1 0
1
1
0
0
1
0
1
0
0
0
1
1
1
1
1
Addressing Mode:
7 6 5 4 3 2 1 0
1 1 NX 1 1 1 0 1
0
SRA
m1
Shift the data in memory location m1 right arithmetic.
RR (HL)
TL/C/5171 – 69
7
6
5
S: Set if result is negative
Z: Set if result is zero
H: Reset
P/V: Set if result parity is even
N: Reset
C: Set according to bit 0 of m1
4 3 2 1 0
1
1
0
0
1
0
1
1
0
0
1
0
1
1
1
0
0
Timing:
1 1
Addressing Mode:
M cycles Ð 4
T states Ð 15 (4, 4, 4, 3)
Register Indirect
RR (IX a d) (for NX e 0)
RR (IY a d) (for NX e 1)
0 1 0 1 1
d
Timing:
0 0
0
1 1 1 1 0
Timing:
Addressing Mode:
SLA
Addressing Mode:
7 6 5 4 3 2 1 0
M cycles Ð 6
T states Ð 23 (4, 4, 3, 5, 4, 3)
Indexed
1 1 NX 1 1 1 0 1
m1
1 1
Shift the data in memory location m1 left arithmetic.
0
SRA (HL)
M cycles Ð 4
T states Ð 15 (4, 4, 4, 3)
Register Indirect
SRA (IX a d) (for NX e 0)
SRA (IY a d) (for NX e 1)
0 1 0 1 1
d
0 0
1
0 1 1 1 0
Timing:
TL/C/5171–68
7
6
5
4
3
2
S: Set if result is negative
Z: Set if result is zero
H: Reset
P/V: Set if result parity is even
N: Reset
C: Set according to bit 7 of m1
1 0
1
1
0
0
1
0
1
1
0
0
1
0
0
1
1
0
Timing:
Addressing Mode:
Addressing Mode:
SRL
M cycles Ð 6
T states Ð 23 (4, 4, 3, 5, 4, 3)
Indexed
m1
Shift right logical the data in memory location m1.
SLA (HL)
TL/C/5171 – 70
S: Reset
Z: Set if result is zero
H: Reset
P/V: Set if result parity is even
N: Reset
C: Set according to bit 0 of m1
M cycles Ð 4
T states Ð 15 (4, 4, 4, 3)
Register Indirect
48
12.9 Rotate and Shift (Continued)
7
6
5
4
3
2
1
0
1
1
0
0
1
0
1
1
0
0
1
1
1
1
1
0
Timing:
Addressing Mode:
7 6 5 4 3 2 1 0
RRD
SRL (HL)
M cycles Ð 4
T states Ð 15 (4, 4, 4, 3)
Register Indirect
0
TL/C/5171 – 72
SRL (IX a d) (for NX e 0)
1 1 NX 1 1 1 0 1
1 1
Rotate digit right and left between the Accumulator and
memory (HL).
7
6
5
4
3
S: Set if result is negative
Z: Set if result is zero
H: Reset
P/V: Set if result parity is even
N: Reset
C: N/A
2 1 0
1
1
1
0
1
1
0
0
1
1
0
0
1
1
SRL (IY a d) (for NX e 1)
0 1 0 1 1
d
0 0
1
1 1 1 1 0
Timing:
M cycles Ð 6
T states Ð 23 (4, 4, 3, 5, 4, 3)
Indexed
Addressing Mode:
REGISTER/MEMORY
Timing:
RLD
Rotate digit left and right between the Accumulator and
memory (HL).
1
1
M cycles Ð 5
T states Ð 18 (4, 4, 3, 4, 3)
Implied/Register Indirect
Addressing Mode:
12.10 Exchanges
REGISTER/REGISTER
EX
DE, HL
Exchange the contents of the 16-bit register pairs DE and
HL.
DE Ý HL
No flags affected
7 6 5 4 3 2 1 0
TL/C/5171 – 71
7
6
5
4
3
S: Set if result is negative
Z: Set if result is zero
H: Reset
P/V: Set if result parity is even
N: Reset
C: N/A
2 1 0
1
1
1
0
1
1
0
1
0
1
1
0
1
1
1
1
Timing:
Addressing Mode:
1
1
1
0
1
0
1
Timing:
1
M cycles Ð 1
T states Ð 4
Register
Addressing Mode:
EX
AF, A’F’
The contents of the Accumulator and flag register are exchanged with their corresponding alternate registers, that is
A and F are exchanged with A’ and F’.
A Ý A’
No flags affected
M cycles Ð 5
T states Ð 18 (4, 4, 3, 4, 3)
Implied/Register Indirect
F Ý F’
7 6 5
0
0
0
4
3
2
1
0
0
1
0
0
0
Timing:
Addressing Mode:
49
M cycles Ð 1
T states Ð 4
Register
LDD
12.10 Exchanges (Continued)
Move data from memory location (HL) to memory location
(DE), and decrement memory pointer and byte counter BC.
EXX
Exchange the contents of the BC, DE, and HL registers with
their corresponding alternate register.
BC Ý B’C’
No flags affected
Ý D’E’
HL Ý H’L’
7 6 5 4
DE
1
1
0
1
3
2
1
0
1
0
0
1
Timing:
M cycles Ð 1
T states Ð 4
Implied
Addressing Mode:
REGISTER/MEMORY
(SP a 1) Ý SSH
7 6 5 4 3 2 1
1
1
0
0
0
1
Addressing Mode:
7 6 5 4 3 2 1 0
5
4
3
2
1
1
1
0
1
1
0
1
1
0
1
0
1
0
0
EX (SP), HL
EX (SP), IX (for NX e 0)
EX (SP),IY (for NX e 1)
0 0 0 1 1
Timing:
M cycles Ð 6
T states Ð 23 (4, 4, 3, 4, 3, 5)
Register/Register Indirect
Addressing Mode:
12.11 Memory Block Moves and
Searches
1
1
0
1
1
0
1
0
1
0
0
0
0
Timing:
Addressing Mode:
LDI
Move data from memory location (HL) to memory location
(DE), increment memory pointers, and decrement byte
counter BC.
(DE) w (HL)
S: N/A
w DE a 1
w HL a 1
w BC b 1
7
6
5
4
3
2
1
1
1
1
0
1
1
0
1
1
0
1
0
0
0
0
Timing:
Addressing Mode:
i 0,
0
1
1
M cycles Ð 4
T states Ð 16 (4, 4, 3, 5)
Register Indirect
CPD
Compare data in memory location (HL) to the Accumulator,
and decrement the memory pointer and byte counter. The Z
flag is set if the comparison is equal.
A b (HL)
S: Set if result is negative
Z: N/A
H: Reset
P/V: Set if BC b1
wise reset
N: Reset
C: N/A
0
other-
M cycles Ð 4
T states Ð 16 (4, 4, 3, 5)
Register Indirect
1
SINGLE OPERATIONS
DE
HL
BC
i 0,
CPI
Compare data in memory location (HL) to the Accumulator,
increment the memory pointer, and decrement the byte
counter. The Z flag is set if the comparison is equal.
A b (HL)
S: Set if result of comparison subtract is negative
HL w HL a 1
BC w BC b 1
Z: Set if result of comparison is
Zw1
zero
if A e (HL)
H: Set according to borrow from
bit 4
P/V: Set if BC b 1 i 0, otherwise
reset
N: Set
C: N/A
7 6 5 4 3 2 1 0
M cycles Ð 5
T states Ð 19 (4, 3, 4, 3, 5)
Register/Register Indirect
1 1 NX 1 1 1 0 1
1
6
1
Addressing Mode:
0
1
Timing:
1 1
7
S: N/A
Z: N/A
H: Reset
P/V: Set if BC b1
wise reset
N: Reset
C: N/A
0
Timing:
EX
(SP), ss
Exchange the two bytes at the top of the external memory
stack with the 16-bit register ss.
(SP) Ý SSL
No flags affected
1
w (HL)
w DE b 1
w HL b 1
w BC b 1
(DE)
DE
HL
BC
HL w HL b 1
BC w BC b 1
Zw1
if A e (HL)
other-
0
M cycles Ð 4
T states Ð 16 (4, 4, 3, 5)
Register Indirect
50
Z: Set if result of comparison is
zero
H: Set according to borrow from
bit 4
P/V: Set if BC b 1 i 0, otherwise
reset
N: Set
C: N/A
12.11 Memory Block Moves and Searches (Continued)
7
6
5
4
3
2
1
0
CPIR
1
1
1
0
1
1
0
1
1
0
1
0
1
0
0
1
Compare data in memory location (HL) to the Accumulator,
increment the memory, decrement the byte counter BC, and
repeat until BC e 0 or (HL) equals A.
A b (HL)
S: Set if sign of subtraction performed for comparison is negaHL w HL a 1
tive
BC w BC b 1
Z: Set if A e (HL), otherwise reset
Repeat until BC e 0
H:
Set according to borrow from
or A e (HL)
bit 4
P/V: Set if BC b 1 i 0, otherwise
reset
N: Set
C: N/A
7 6 5 4 3 2 1 0
Timing:
M cycles Ð 4
T states Ð 16 (4, 4, 3, 5)
Register Indirect
Addressing Mode:
REPEAT OPERATIONS
LDIR
Move data from memory location (HL) to memory location
(DE), increment memory pointers, decrement byte counter
BC, and repeat until BC e 0.
(DE) w (HL)
DE w DE a 1
HL w HL a 1
BC w BC b 1
Repeat until
BC e 0
7 6 5 4 3
S: N/A
Z: N/A
H: Reset
P/V: Reset
N: Reset
C: N/A
2 1 0
1
1
1
0
1
1
0
1
1
0
1
1
0
0
0
0
3
2
1
1
0
1
1
0
1
1
0
1
1
1
0
0
0
1
0
1
0
1
1
0
For BC
1
0
0
1
i
0
1
0
CPDR
Compare data in memory location (HL) to the contents of
the Accumulator, decrement the memory pointer and byte
counter BC, and repeat until BC e 0, or until (HL) equals
the Accumulator.
A b (HL)
S: Set if sign of subtraction performed for comparison is negaHL w HL b 1
tive
BC w BC b 1
Z: Set according to equality of A
Repeat until BC e 0
and (HL), set if true
e
or A
(HL)
H: Set according to borrow from
bit 4
P/V: Set if BC b 1 i 0, otherwise
reset
N: Set
C: N/A
7 6 5 4 3 2 1 0
LDDR
Move data from memory location (HL) to memory location
(DE), decrement memory pointers and byte counter BC, and
repeat until BC e 0.
(DE) w (HL)
S: N/A
Z: N/A
DE w DE b 1
H: Reset
HL w HL b 1
BC w BC b 1
P/V: Reset
1
1
M cycles Ð 5
T states Ð 21 (4, 4, 3, 5, 5)
M cycles Ð 4
For BC e 0
T states Ð 16 (4, 4, 3, 5)
Addressing Mode:
Register Indirect
(Note that each repeat is accomplished by a decrement of
the PC, so that refresh, etc. continues for each cycle.)
For BC i 0 M cycles Ð 5
T states Ð 21 (4, 4, 3, 5, 5)
For BC e 0 M cycles Ð 4
T states Ð 16 (4, 4, 3, 5)
Addressing Mode:
Register Indirect
(Note that each repeat is accomplished by a decrement of
the BC, so that refresh, etc. continues for each cycle.)
N: Reset
C: N/A
1 0
1
Timing:
Timing:
Repeat until
BC e 0
7 6 5 4
1
1
1
1
1
0
1
Timing:
0
1
1
1
0
For BC i 0 M cycles Ð 5
T states Ð 21 (4, 4, 3, 5, 5)
For BC e 0 M cycles Ð 4
T states Ð 16 (4, 4, 3, 5)
Addressing Mode:
Register Indirect
(Note that each repeat is accomplished by a decrement of
the BC, so that refresh, etc. continues for each cycle.)
51
i
0
0
1
0
1
M cycles Ð 5
T states Ð 21 (4, 4, 3, 5, 5)
For BC e 0
M cycles Ð 4
T states Ð 16 (4, 4, 3, 5)
Addressing Mode:
Register Indirect
(Note that each repeat is accomplished by a decrement of
the BC, so that refresh, etc. continues for each cycle.)
Timing:
For BC
1
12.12 Input/Output
IN
P/V: Undefined
A, (n)
N: Set
Input data to the Accumulator from the I/O device at address N.
A w (n)
No flags affected
7 6 5 4 3 2 1 0
1
1
0
1
1
0
1
0
1
1
0
1
r
1
0
1
0
0
0
Timing:
0
1
1
0
2
1
1
1
1
0
1
1
0
1
1
0
1
0
0
0
1
0
BwBb1
HL w HL a 1
1
r
Timing:
Addressing Mode:
7
6
5
4
3
Z: Set if Bb1 e 0, otherwise reset
H: Undefined
P/V: Undefined
N: Set
C: N/A
2 1 0
1
1
1
0
1
1
0
1
1
0
1
0
0
0
1
1
M cycles Ð 4
T states Ð 16 (4, 5, 3, 4)
Implied/Source Ð Register Indirect
Destination Ð Register Indirect
Addressing Mode:
1
0
1
IND
Input data from I/O device at port address (C) to memory
location (HL), and decrement HL memory pointer and byte
counter B.
(HL) w (C)
S: Undefined
0
0
1
HL w HL b 1
BwBb1
M cycles Ð 3
T states Ð 12 (4, 4, 4)
Source Ð Register
Destination Ð Register Indirect
INI
Input data from the I/O device addressed by the contents of
register C to the memory location pointed to by the contents
of the HL register. The HL pointer is incremented and the
byte counter B is decremented.
(HL) w (C)
S: Undefined
BwBb1
HL w HL a 1
M cycles Ð 4
T states Ð 16 (4, 5, 3, 4)
Implied/Source Ð Register Indirect
Destination Ð Register Indirect
Timing:
OUT
(C), r
Output register r to the I/O device addressed by the contents of register C.
(C) w r
No flags affected
7 6 5 4 3 2 1 0
1
3
OUTI
Output data from memory location (HL) to the I/O device at
port address (C), increment the memory pointer, and decrement the byte counter B.
(C) w (HL)
S: Undefined
M cycles Ð 3
T states Ð 12 (4, 4, 4)
Source Ð Register Indirect
Destination Ð Register
Addressing Mode:
1
4
Addressing Mode:
IN
r, (C)
Input data to register r from the I/O device addressed by the
contents of register C. If r e 110 only flags are affected.
S: Set if result is negative
r w (C)
Z: Set if result is zero
H: Reset
P/V: Set if result parity is even
N: Reset
C: N/A
7 6 5 4 3 2 1 0
1
5
Timing:
M cycles Ð 3
T states Ð 11 (4, 3, 4)
Source Ð Direct
Destination Ð Register
Addressing Mode:
1
6
1
n
Timing:
C: N/A
0
7
7
6
5
4
3
Z: Set if Bb1 e 0, otherwise reset
H: Undefined
P/V: Undefined
N: Set
C: N/A
2 1 0
1
1
1
0
1
1
0
1
1
0
1
0
1
0
1
0
Timing:
Addressing Mode:
Z: Set if Bb1 e 0, otherwise reset
H: Undefined
52
M cycles Ð 4
T states Ð 16 (4, 5, 3, 4)
Implied/Source Ð Register Indirect
Destination Ð Register Indirect
12.12 Input/Output (Continued)
OUT
(n), A
Output the Accumulator to the I/O device at address n.
7
6
5
4
3
2
1
0
1
1
1
0
1
1
0
1
(n) w A
7 6 5
1
0
1
1
0
0
1
0
1
1
0
4
3
2
1
No flags affected
0
1
0
0
1
1
Timing:
M cycles Ð 5
T states Ð 21 (4, 5, 3, 4, 5)
M cycles Ð 4
For B e 0
T states Ð 16 (4, 5, 3, 4)
Addressing Mode:
Implied/Source Ð Register Indirect
Destination Ð Register Indirect
(Note that at the end of each data transfer cycle, interrupts
may be recognized and two refresh cycles will be performed.)
n
Timing:
M cycles Ð 3
T states Ð 11 (4, 3, 4)
Source Ð Register
Destination Ð Direct
Addressing Mode:
OUTD
Data is output from memory location (HL) to the I/O device
at port address (C), and the HL memory pointer and byte
counter B are decremented.
(C) w (HL)
S: Undefined
BwBb1
HL w HL b 1
7
6
5
4
3
Z: Set if Bb1 e 0, otherwise reset
H: Undefined
P/V: Undefined
N: Set
C: N/A
2 1 0
1
1
1
0
1
1
0
1
1
0
1
0
1
0
1
1
Timing:
Addressing Mode:
i
0
OTIR
Data is output to the I/O device at port address (C) from
memory location (HL), the HL memory pointer is incremented, and the byte counter B is decremented. The cycles are
repeated until B e 0.
(Note that B is tested for zero after it is decremented. By
loading B initially with zero, 256 data transfers will take
place.)
(C) w (HL)
S: Undefined
HL w HL a 1
BwBb1
Repeat until B e 0
M cycles Ð 4
T states Ð 16 (4, 5, 3, 4)
Implied/Source Ð Register Indirect
Destination Ð Register Indirect
INIR
Data is input from the I/O device at port address (C) to
memory location (HL), the HL memory pointer is incremented, and the byte counter B is decremented. The cycle is
repeated until B e 0.
(Note that B is tested for zero after it is decremented. By
loading B initially with zero, 256 data transfers will take
place.)
(HL) w (C)
S: Undefined
HL w HL a 1
BwBb1
Repeat until B e 0
For B
7
6
5
4
3
H: Undefined
Z: Set
P/V: Undefined
N: Set
C: N/A
2 1 0
1
1
1
0
1
1
0
1
1
0
1
1
0
0
1
1
Timing:
M cycles Ð 5
T states Ð 21 (4, 5, 3, 4, 5)
M cycles Ð 4
For B e 0
T states Ð 16 (4, 5, 3, 4)
Addressing Mode:
Implied/Source Ð Register Indirect
Destination Ð Register Indirect
(Note that at the end of each data transfer cycle, interrupts
may be recognized and two refresh cycles will be performed.)
Z: Set
H: Undefined
P/V: Undefined
N: Set
C: N/A
53
For B
i
0
12.12 Input/Output (Continued)
12.13 CPU Control
INDR
Data is input from the I/O device at address (C) to memory
location (HL), then the HL memory pointer is byte counter B
are decremented. The cycle is repeated until B e 0.
(Note that B is tested for zero after it is decremented. By
loading B initially with zero, 256 data transfers will take
place.)
(HL) w (C)
S: Undefined
NOP
HL w HL b 1
BwBb1
Repeat until B e 0
Addressing Mode:
7
6
5
4
3
Z: Set
H: Undefined
P/V: Undefined
N: Set
C: N/A
2 1 0
1
1
1
0
1
1
0
1
1
0
1
1
0
0
1
0
Timing:
For B
The CPU performs no operation.
ÐÐÐ
7 6 5
0
7
6
5
4
3
1
1
1
0
1
1
0
1
1
0
1
1
1
0
1
1
Timing:
For B
0
No flags affected
0
0
0
0
0
0
M cycles Ð 1
T states Ð 4
N/A
1
1
1
0
1
1
0
M cycles Ð 1
T states Ð 4
N/A
Addressing Mode:
DI
Disable system level interrupts.
No flags affected
IFF1 w 0
IFF2 w 0
7 6 5 4 3 2 1 0
1
1
1
1
0
0
1
Timing:
1
M cycles Ð 1
T states Ð 4
N/A
Addressing Mode:
EI
The system level interrupts are enabled. During execution of
this instruction, and the next one, the maskable interrupts
will be disabled.
IFF1 w 1
No flags affected
IFF2 w 1
7 6 5 4
1
1
1
1
3
2
1
0
1
0
1
1
Timing:
M cycles Ð 1
T states Ð 4
N/A
Addressing Mode:
IM
0
The CPU is placed in interrupt mode 0.
ÐÐÐ
No flags affected
7 6 5 4 3 2 1 0
M cycles Ð 5
T states Ð 21 (4, 5, 3, 4, 5)
M cycles Ð 4
For B e 0
T states Ð 16 (4, 5, 3, 4)
Addressing Mode:
Implied/Source Ð Register Indirect
Destination Ð Register Indirect
(Note that after each data transfer cycle the NSC800 will
accept interrupts and perform two refresh cycles.)
i
1
Timing:
0
Z: Set
H: Undefined
P/V: Undefined
N: Set
C: N/A
2 1 0
2
HALT
The CPU halts execution of the program. Dummy op-code
fetches are performed from the next memory location to
keep the refresh circuits active until the CPU is interrupted
or reset from the halted state.
ÐÐÐ
No flags affected
7 6 5 4 3 2 1 0
OTDR
Data is output from memory location (HL) to the I/O device
at port address (C), then the HL memory pointer and byte
counter B are decremented. The cycle is repeated until B e
0.
(Note that B is tested for zero after it is decremented. By
loading B initially with zero, 256 data transfers will take
place.)
(C) w (HL)
S: Undefined
HL w HL b 1
BwBb1
Repeat until B e 0
0
3
Timing:
M cycles Ð 5
T states Ð 21 (4, 5, 3, 4, 5)
M cycles Ð 4
For B e 0
T states Ð 16 (4, 5, 3, 4)
Addressing Mode:
Implied/Source Ð Register Indirect
Destination Ð Register Indirect
(Note that after each data transfer cycle, interrupts may be
recognized and two refresh cycles are performed.)
i
0
4
0
1
1
1
0
1
1
0
1
0
1
0
0
0
1
1
0
Timing:
Addressing Mode:
54
M cycles Ð 2
T states Ð 8 (4, 4)
N/A
12.13 CPU Control (Continued)
7
6
5
4
3
2
1
0
IM
1
The CPU is placed in interrupt mode 1.
1
1
NX
1
1
1
0
1
ÐÐÐ
7 6 5
1
1
1
0
1
0
0
1
4
3
2
1
No flags affected
0
1
1
1
0
1
1
0
1
0
1
0
1
0
1
1
0
Timing:
M cycles Ð 2
T states Ð 8 (4, 4)
Register Indirect
Addressing Mode:
Timing:
JP
cc, nn
Conditionally jump to program location nn based on testable
flag states.
If cc true,
No flags affected
PC w nn,
M cycles Ð 2
T states Ð 8 (4, 4)
N/A
Addressing Mode:
IM
2
The CPU is placed in interrupt mode 2.
ÐÐÐ
No flags affected
7 6 5 4 3 2 1 0
1
1
1
0
1
1
0
1
0
1
0
1
1
1
1
0
Timing:
otherwise continue
7 6 5 4 3 2
1
0
0
0
1
0
1
1
0
1
Timing:
Addressing Mode:
0
M cycles Ð 3
T states Ð 10 (4, 3, 3)
Direct
0
1
1
0
0
Timing:
1
0
M cycles Ð 3
T states Ð 12 (4, 3, 5)
PC Relative
Addressing Mode:
JR
kk, d
Conditionally jump to program location calculated with respect to the program counter and the displacement d,
based on limited testable flag states.
If kk true,
No flags affected
PC w PC a d,
M cycles Ð 3
T states Ð 10 (4, 3, 3)
Direct
0
0
db2
JP
(ss)
Unconditional jump to program location pointed to by register ss.
PC w ss
No flags affected
7 6 5 4 3 2 1 0
1
0
1
n (high-order byte)
Addressing Mode:
0
1
JR
d
Unconditional jump to program location calculated with respect to the program counter and the displacement d.
PC w PC a d
No flags affected
7 6 5 4 3 2 1 0
n (low-order byte)
Timing:
1
Addressing Mode:
JP
nn
Unconditional jump to program location nn.
PC w nn
No flags affected
7 6 5 4 3 2 1 0
0
0
n (high-order byte)
JUMPS
1
cc
Timing:
12.14 Program Control
1
1
n (low-order byte)
M cycles Ð 2
T states Ð 8 (4, 4)
N/A
Addressing Mode:
JP (IX) (for NX e 0)
JP (IY) (for NX e 1)
otherwise continue
7 6 5 4 3 2
0
0
1
kk
0
1
0
0
0
JP (HL)
db2
M cycles Ð 1
T states Ð 4
Register Indirect
Timing:
if kk met
(true)
if kk not met
(not true)
Addressing Mode:
55
M cycles Ð 3
T states Ð 12 (4, 3, 5)
M cycles Ð 2
T states Ð 7 (4, 3)
PC Relative
12.14 Program Control (Continued)
RETURNS
DJNZ
d
Decrement the B register and conditionally jump to program
location calculated with respect to the program counter and
the displacement d, based on the contents of the B register.
BwBb1
No flags affected
If B e 0 continue,
else PC w PC a d
7 6 5 4 3 2
0
0
0
1
0
0
1
0
0
0
RET
Unconditional return from subroutine or other return to program location pointed to by the top of the stack.
PCL w (SP)
No flags affected
PCH w (SP a 1)
SP w SP a 2
7 6 5 4 3 2
1
If B
i
0
M cycles Ð 3
T states Ð 13 (5, 3, 5)
M cycles Ð 2
T states Ð 8 (5, 3)
PC Relative
If B e 0
Addressing Mode:
0
0
1
1
0
1
1
0
1
0
0
0
If cc true
w (SP a 1)
SP w SP a 2
7 6 5 4 3 2
PCH
0
0
n (high-order byte)
If cc true
If cc not true
M cycles Ð 5
T states 17 (4, 3, 4, 3, 3)
M cycles Ð 3
T states Ð 10 (4, 3, 3)
Direct
56
0
1
1
0
1
1
0
1
0
1
0
0
1
1
0
1
Addressing Mode:
0
1
1
Timing:
1
M cycles Ð 3
T states Ð 11 (5, 3, 3)
M cycles Ð 1
T states Ð 5
Register Indirect
RETI
Unconditional return from interrupt handling subroutine.
Functionally identical to RET instruction. Unique opcode allows monitoring by external hardware.
PCL w (SP)
No flags affected
n (low-order byte)
Addressing Mode:
cc
If cc not true
CALL
cc, nn
Conditional call to subroutine at location nn based on testable flag stages.
If cc true,
No flags affected
(SP b 1) w PCH
(SP b 2) w PCL
SP w SP b 2
PC w nn,
else continue
7 6 5 4 3 2
1
1
M Cycles Ð 5
T states Ð 17 (4, 3, 4, 3, 3)
Direct
Addressing Mode:
Timing:
0
1
Addressing Mode:
Timing:
cc
1
0
M cycles Ð 3
T states Ð 10 (4, 3, 3)
Register Indirect
Timing:
n (high-order byte)
1
0
w (SP a 1)
SP w SP a 2,
else continue
7 6 5 4 3 2
n (low-order byte)
1
1
PCH
CALL
nn
Unconditional call to subroutine at location nn.
(SP b 1) w PCH
No flags affected
(SP b 2) w PCL
SP w SP b 2
PC w nn
7 6 5 4 3 2 1 0
1
0
Addressing Mode:
RET
cc
Conditional return from subroutine or other return to program location pointed to by the top of the stack.
If cc true,
No flags affected
PCL w (SP)
CALLS
1
0
Timing:
db2
Timing:
1
M cycles Ð 4
T states Ð 14 (4, 4, 3, 3)
Register Indirect
12.14 Program Control (Continued)
RESTARTS
RETN
Unconditional return from non-maskable interrupt handling
subroutine. Functionally similar to RET instruction, except
interrupt enable state is restored to that prior to non-maskable interrupt.
PCL w (SP)
No flags affected
PCH w (SP a 1)
SP w SP a 2
IFF1 w IFF2
7 6 5 4 3 2
1
0
1
1
1
0
0
0
1
0
Timing:
Addressing Mode:
1
1
1
0
0
1
0
RST
P
The present contents of the PC are pushed onto the memory stack and the PC is loaded with dedicated program locations as determined by the specific restart executed.
(SP b 1) w PCH
No flags affected
(SP b 2) w PCL
SP w SP b 2
PCH w 0
PCL w P
7 6
1
1
1
Timing:
M cycles Ð 4
T states Ð 14 (4, 4, 3, 3)
Register Indirect
4
t
3
2
1
0
1
1
1
M cycles Ð 3
T states Ð 11 (5, 3, 3)
Modified Page Zero
Addressing Mode:
57
5
p
00H
08H
10H
18H
20H
28H
30H
38H
t
000
001
010
011
100
101
110
111
12.15 Instruction Set: Alphabetical Order
ADC
ADC
ADC
ADC
ADC
ADC
ADC
ADC
ADC
ADC
ADC
ADC
ADC
ADC
ADC
ADD
ADD
ADD
ADD
ADD
ADD
ADD
ADD
ADD
ADD
ADD
ADD
ADD
ADD
ADD
ADD
ADD
ADD
ADD
ADD
ADD
ADD
ADD
AND
AND
AND
AND
AND
AND
AND
AND
AND
AND
AND
BIT
BIT
BIT
BIT
A, (HL)
A, (IX a d)
A, (IY a d)
A, A
A, B
A, C
A, D
A, E
A, H
A, L
A, n
HL, BC
HL, DE
HL, HL
HL, SP
A, (HL)
A, (IX a d)
A, (IY a d)
A, A
A, B
A, C
A, D
A, E
A, H
A, L
A, n
HL, BC
HL, DE
HL, HL
HL, SP
IX, BC
IX, DE
IX, IX
IX, SP
IY, BC
IY, DE
IY, IY
IY, SP
(HL)
(IX a d)
(IY a d)
A
B
C
D
E
H
L
n
0, (HL)
0, (IX a d)
0, (IY a d)
0, A
8E
DD 8Ed
FD 8Ed
8F
88
89
8A
8B
8C
8D
CE n
ED 4A
ED 5A
ED 6A
ED 7A
86
DD 86d
FD 86d
87
80
81
82
83
84
85
C6 n
09
19
29
39
DD 09
DD 19
DD 29
DD 39
FD 09
FD 19
FD 29
FD 39
A6
DD A6d
FD A6d
A7
A0
A1
A2
A3
A4
A5
E6 n
CB 46
DD CBd46
FD CBd46
CB 47
(nn) e address of memory location
d e signed displacement
nn e Data (16 bit)
d2 e d b 2
BIT
BIT
BIT
BIT
BIT
BIT
BIT
BIT
BIT
BIT
BIT
BIT
BIT
BIT
BIT
BIT
BIT
BIT
BIT
BIT
BIT
BIT
BIT
BIT
BIT
BIT
BIT
BIT
BIT
BIT
BIT
BIT
BIT
BIT
BIT
BIT
BIT
BIT
BIT
BIT
BIT
BIT
BIT
BIT
BIT
BIT
BIT
BIT
BIT
BIT
BIT
BIT
BIT
n e Data (8 bit)
58
0, B
0, C
0, D
0, E
0, H
0, L
1, (HL)
1, (IX a d)
1, (IY a d)
1, A
1, B
1, C
1, D
1, E
1, H
1, L
2, (HL)
2, (IX a d)
2, (IY a d)
2, A
2, B
2, C
2, D
2, E
2, H
2, L
3, (HL)
3, (IX a d)
3, (IY a d)
3, A
3, B
3, C
3, D
3, E
3, H
3, L
4, (HL)
4, (IX a d)
4, (IY a d)
4, A
4, B
4, C
4, D
4, E
4, H
4, L
5, (HL)
5, (IX a d)
5, (IY a d)
5, A
5, B
5, C
5, D
CB 40
CB 41
CB 42
CB 43
CB 44
CB 45
CB 4E
DD CBd4E
FD CBd4E
CB 4F
CB 48
CB 49
CB 4A
CB 4B
CB 4C
CB 4D
CB 56
DD CBd56
FD CBd56
CB 57
CB 50
CB 51
CB 52
CB 53
CB 54
CB 55
CB 5E
DD CBd5E
FD CBd5E
CB 5F
CB 58
CB 59
CB 5A
CB 5B
CB 5C
CB 5D
CB 66
DD CBd66
FD CBd66
CB 67
CB 60
CB 61
CB 62
CB 63
CB 64
CB 65
CB 6E
DD CBd6E
FD CBd6E
CB 6F
CB 68
CB 69
CB 6A
12.15 Instruction Set: Alphabetical Order (Continued)
BIT
BIT
BIT
BIT
BIT
BIT
BIT
BIT
BIT
BIT
BIT
BIT
BIT
BIT
BIT
BIT
BIT
BIT
BIT
BIT
BIT
BIT
BIT
CALL
CALL
CALL
CALL
CALL
CALL
CALL
CALL
CALL
CCF
CP
CP
CP
CP
CP
CP
CP
CP
CP
CP
CP
CPD
CPDR
CPI
CPIR
CPL
DAA
DEC
DEC
DEC
5, E
5, H
5, L
6, (HL)
6, (IX a d)
6, (IY a d)
6, A
6, B
6, C
6, D
6, E
6, H
6, L
7, (HL)
7, (IX a d)
7, (IY a d)
7, A
7, B
7, C
7, D
7, E
7, H
7, L
C, nn
M, nn
NC, nn
nn
NZ, nn
P, nn
PE, nn
PO, nn
Z, nn
(HL)
(IX a d)
(IY a d)
A
B
C
D
E
H
L
n
(HL)
(IX a d)
(IY a d)
CB 6B
CB 6C
CB 6D
CB 76
DD CBd76
FD CBd76
CB 77
CB 70
CB 71
CB 72
CB 73
CB 74
CB 75
CB 7E
DD CBd7E
FD CBd7E
CB 7F
CB 78
CB 79
CB 7A
CB 7B
CB 7C
CB 7D
DCnn
FCnn
D4nn
CDnn
C4nn
F4nn
ECnn
E4nn
CCnn
3F
BE
DD BEd
FD BEd
BF
B8
B9
BA
BB
BC
BD
FE n
ED A9
ED B9
ED A1
ED B1
2F
27
35
DD 35d
FD 35d
(nn) e Address of memory location
d e signed displacement
nn e Data (16 bit)
d2 e d b 2
DEC
DEC
DEC
DEC
DEC
DEC
DEC
DEC
DEC
DEC
DEC
DEC
DEC
DI
DJNZ
EI
EX
EX
EX
EX
EX
EXX
HALT
IM
IM
IM
IN
IN
IN
IN
IN
IN
IN
IN
INC
INC
INC
INC
INC
INC
INC
INC
INC
INC
INC
INC
INC
INC
INC
INC
IND
INDR
INI
n e Data (8 bit)
59
A
B
BC
C
D
DE
E
H
HL
IX
IY
L
SP
d2
(SP), HL
(SP), IX
(SP), IY
AF, A’F’
DE, HL
0
1
2
A, (C)
A, (n)
B, (C)
C, (C)
D, (C)
E, (C)
H, (C)
L, (C)
(HL)
(IX a d)
(IY a d)
A
B
BC
C
D
DE
E
H
HL
IX
IY
L
SP
3D
05
0B
0D
15
1B
1D
25
2B
DD 2B
FD 2B
2D
3B
F3
10 d2
FB
E3
DD E3
FD E3
08
EB
D9
76
ED 46
ED 56
ED 5E
ED78
DB n
ED 40
ED 48
ED 50
ED 58
ED 60
ED 68
34
DD 34d
FD 34d
3C
04
03
0C
14
13
1C
24
23
DD 23
FD 23
2C
33
ED AA
ED BA
ED A2
12.15 Instruction Set: Alphabetical Order (Continued)
INIR
JP
JP
JP
JP
JP
JP
JP
JP
JP
JP
JP
JP
JR
JR
JR
JR
JR
LD
LD
LD
LD
LD
LD
LD
LD
LD
LD
LD
LD
LD
LD
LD
LD
LD
LD
LD
LD
LD
LD
LD
LD
LD
LD
LD
LD
LD
LD
LD
LD
LD
LD
LD
(HL)
(IX)
(IY)
C, nn
M, nn
NC, nn
nn
NZ, nn
P, nn
PE, nn
PO, nn
Z, nn
C, d2
d2
NC, d2
NZ, d2
Z, d2
(BC), A
(DE), A
(HL), A
(HL), B
(HL), C
(HL), D
(HL), E
(HL), H
(HL), L
(HL), n
(IX a d), A
(IX a d), B
(IX a d), C
(IX a d), D
(IX a d), E
(IX a d), H
(IX a d), L
(IX a d), n
(IY a d), A
(IY a d), B
(IY a d), C
(IY a d), D
(IY a d), E
(IY a d), H
(IY a d), L
(IY a d), n
(nn), A
(nn), BC
(nn), DE
(nn), HL
(nn), IX
(nn), IY
(nn), SP
A, (BC)
A, (DE)
ED B2
E9
DD E9
FD E9
DAnn
FAnn
D2nn
C3nn
C2nn
F2nn
EAnn
E2nn
CAnn
38 d2
18 d2
30 d2
20 d2
28 d2
02
12
77
70
71
72
73
74
75
36 n
DD 77d
DD 70d
DD 71d
DD 72d
DD 73d
DD 74d
DD 75d
DD 36dn
FD 77d
FD 70d
FD 71d
FD 72d
FD 73d
FD 74d
FD 75d
FD 36dn
32nn
ED 43nn
ED 53nn
22nn
DD 22nn
FD 22nn
ED 73nn
0A
1A
(nn) e Address of memory location
d e signed displacement
nn e Data (16 bit)
d2 e d b 2
LD
LD
LD
LD
LD
LD
LD
LD
LD
LD
LD
LD
LD
LD
LD
LD
LD
LD
LD
LD
LD
LD
LD
LD
LD
LD
LD
LD
LD
LD
LD
LD
LD
LD
LD
LD
LD
LD
LD
LD
LD
LD
LD
LD
LD
LD
LD
LD
LD
LD
LD
LD
LD
n e Data (8 bit)
60
A, (HL)
A, (IX a d)
A, (IY a d)
A, (nn)
A, A
A, B
A, C
A, D
A, E
A, H
A, I
A, L
A, n
B, (HL)
B, (IX a d)
B, (IY a d)
B, A
B, B
B, C
B, D
B, E
B, H
B, L
B, n
BC, (nn)
BC, nn
C, (HL)
C, (IX a d)
C, (IY a d)
C, A
C, B
C, C
C, D
C, E
C, H
C, L
C, n
D, (HL)
D, (IX a d)
D, (IY a d)
D, A
D, B
D, C
D, D
D, E
D, H
D, L
D, n
DE, (nn)
DE, nn
E, (HL)
E, (IX a d)
E, (IY a d)
7E
DD 7Ed
FD 7Ed
3Ann
7F
78
79
7A
7B
7C
ED 57
7D
3E n
46
DD 46d
FD 46d
47
40
41
42
43
44
45
06 n
ED 4B
01nn
4E
DD 4Ed
FD 4Ed
4F
48
49
4A
4B
4C
4D
0E n
56
DD 56d
FD 56d
57
50
51
52
53
54
55
16 n
ED 5Bnn
11nn
5E
DD 5Ed
FD 5Ed
12.15 Instruction Set: Alphabetical Order (Continued)
LD
LD
LD
LD
LD
LD
LD
LD
LD
LD
LD
LD
LD
LD
LD
LD
LD
LD
LD
LD
LD
LD
LD
LD
LD
LD
LD
LD
LD
LD
LD
LD
LD
LD
LD
LD
LD
LD
LD
LD
LD
LD
LDD
LDDR
LDI
LDIR
NEG
NOP
OR
OR
OR
OR
OR
E, A
E, B
E, C
E, D
E, E
E, H
E, L
E, n
H, (HL)
H, (IX a d)
H, (IY a d)
H, A
H, B
H, C
H, D
H, E
H, H
H, L
H, n
HL, (nn)
HL, nn
I, A
IX, (nn)
IX, nn
IY, (nn)
IY, nn
L, (HL)
L, (IX a d)
L, (IY a d)
L, A
L, B
L, C
L, D
L, E
L, H
L, L
L, n
SP, (nn)
SP, HL
SP, IX
SP, IY
SP, nn
5F
58
59
5A
5B
5C
5D
1E n
66
DD 66d
FD 66d
67
60
61
62
63
64
65
26 n
2Ann
21nn
ED 47
DD 2Ann
DD 21nn
FD 2Ann
FD 21nn
6E
DD 6Ed
FD 6Ed
6F
68
69
6A
6B
6C
6D
2E n
ED 7Bnn
F9
DD F9
FD F9
31nn
ED A8
ED B8
ED A0
ED B0
ED n
00
B6
DD B6d
FD B6d
B7
B0
(HL)
(IX a d)
(IY a d)
A
B
(nn) e Address of memory location
d e signed displacement
nn e Data (16 bit)
d2 e d b 2
OR
OR
OR
OR
OR
OR
OTDR
OTIR
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUTD
OUTI
POP
POP
POP
POP
POP
POP
PUSH
PUSH
PUSH
PUSH
PUSH
PUSH
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
n e Data (8 bit)
61
C
D
E
H
L
n
(C), A
(C), B
(C), C
(C), D
(C), E
(C), H
(C), L
n, A
AF
BC
DE
HL
IX
IY
AF
BC
DE
HL
IX
IY
0, (HL)
0, (IX a d)
0, (IY a d)
0, A
0, B
0, C
0, D
0, E
0, H
0, L
1, (HL)
1, (IX a d)
1, (IY a d)
1, A
1, B
1, C
1, D
1, E
1, H
1, L
2, (HL)
2, (IX a d)
2, (IY a d)
B1
B2
B3
B4
B5
F6 n
ED BB
ED B3
ED 79
ED 41
ED 49
ED 51
ED 59
ED 61
ED 69
D3 n
ED AB
ED A3
F1
C1
D1
E1
DD E1
FD E1
F5
C5
D5
E5
DD E5
FD E5
CB 86
DD CBd86
FD CBd86
CB 87
CB 80
CB 81
CB 82
CB 83
CB 84
CB 85
CB 8E
DD CBd8E
FD CBd8E
CB 8F
CB 88
CB 89
CB 8A
CB 8B
CB 8C
CB 8D
CB 96
DD CBd96
FD CBd96
12.15 Instruction Set: Alphabetical Order (Continued)
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
2, A
2, B
2, C
2, D
2, E
2, H
2, L
3, (HL)
3, (IX a d)
3, (IY a d)
3, A
3, B
3, C
3, D
3, E
3, H
3, L
4, (HL)
4, (IX a d)
4, (IY a d)
4, A
4, B
4, C
4, D
4, E
4, H
4, L
5, (HL)
5, (IX a d)
5, (IY a d)
5, A
5, B
5, C
5, D
5, E
5, H
5, L
6, (HL)
6, (IX a d)
6, (IY a d)
6, A
6, B
6, C
6, D
6, E
6, H
6, L
7, (HL)
7, (IX a d)
7, (IY a d)
7, A
7, B
7, C
CB 97
CB 90
CB 91
CB 92
CB 93
CB 94
CB 95
CB 9E
DD CBd9E
FD CBd9E
CB 9F
CB 98
CB 99
CB 9A
CB 9B
CB 9C
CB 9D
CB A6
DD CBdA6
FD CBdA6
CB A7
CB A0
CB A1
CB A2
CB A3
CB A4
CB A5
CB AE
DD CBdAE
FD CBdAE
CB AF
CB A8
CB A9
CB AA
CB AB
CB AC
CB AD
CB B6
DD CBdB6
FD CBdB6
CB B7
CB B0
CB B1
CB B2
CB B3
CB B4
CB B5
CB BE
DD CBdBE
FD CBdBE
CB BF
CB B8
CB B9
(nn) e Address of memory location
d e signed displacement
nn e Data (16 bit)
d2 e d b 2
RES
RES
RES
RES
RET
RET
RET
RET
RET
RET
RET
RET
RET
RETI
RETN
RL
RL
RL
RL
RL
RL
RL
RL
RL
RL
RLA
RLC
RLC
RLC
RLC
RLC
RLC
RLC
RLC
RLC
RLC
RLCA
RLD
RR
RR
RR
RR
RR
RR
RR
RR
RR
RR
RRA
RRC
RRC
RRC
RRC
n e Data (8 bit)
62
7, D
7, E
7, H
7, L
C
M
NC
NZ
P
PE
PO
Z
(HL)
(IX a d)
(IY a d)
A
B
C
D
E
H
L
(HL)
(IX a d)
(IY a d)
A
B
C
D
E
H
L
(HL)
(IX a d)
(IY a d)
A
B
C
D
E
H
L
(HL)
(IX a d)
(IY a d)
A
CB BA
CB BB
CB BC
CB BD
C9
D8
F8
D0
C0
F0
E8
E0
C8
ED 4D
ED 45
CB 16
DD CBd16
FD CBd16
CB 17
CB 10
CB 11
CB 12
CB 13
CB 14
CB 15
17
CB 06
DD CBd06
FD CBd06
CB 07
CB 00
CB 01
CB 02
CB 03
CB 04
CB 05
07
ED 6F
CB 1E
DD CBd1E
FD CBd1E
CB 1F
CB 18
CB 19
CB 1A
CB 1B
CB 1C
CB 1D
1F
CB OE
DD CBd0E
FD CBd0E
CB 0F
12.15 Instruction Set: Alphabetical Order (Continued)
RRC
RRC
RRC
RRC
RRC
RRC
RRCA
RRD
RST
RST
RST
RST
RST
RST
RST
RST
SBC
SBC
SBC
SBC
SBC
SBC
SBC
SBC
SBC
SBC
SBC
SBC
SBC
SBC
SBC
SCF
SET
SET
SET
SET
SET
SET
SET
SET
SET
SET
SET
SET
SET
SET
SET
SET
SET
SET
SET
SET
SET
B
C
D
E
H
L
0
08H
10H
18H
20H
28H
30H
38H
A, (HL)
A, (IX a d)
A, (IY a d)
A, A
A, B
A, C
A, D
A, E
A, H
A, L
A, n
HL, BC
HL, DE
HL, HL
HL, SP
0, (HL)
0, (IX a d)
0, (IY a d)
0, A
0, B
0, C
0, D
0, E
0, H
0, L
1, (HL)
1, (IX a d)
1, (IY a d)
1, A
1, B
1, C
1, D
1, E
1, H
1, L
2, (HL)
CB 08
CB 09
CB 0A
CB 0B
CB 0C
CB 0D
0F
ED 67
C7
CF
D7
DF
E7
EF
F7
FF
9E
DD 9Ed
FD 9Ed
9F
98
99
9A
9B
9C
9D
DE n
ED 42
ED 52
ED 62
ED 72
37
CB C6
DD CBdC6
FD CBdC6
CB C7
CB C0
CB C1
CB C2
CB C3
CB C4
CB C5
CB CE
DD CBdCE
FD CBdCE
CB CF
CB C8
CB C9
CB CA
CB CB
CB CC
CB CD
CB D6
(nn) e Address of memory location
d e displacement
nn e Data (16 bit)
d2 e d b 2
SET
SET
SET
SET
SET
SET
SET
SET
SET
SET
SET
SET
SET
SET
SET
SET
SET
SET
SET
SET
SET
SET
SET
SET
SET
SET
SET
SET
SET
SET
SET
SET
SET
SET
SET
SET
SET
SET
SET
SET
SET
SET
SET
SET
SET
SET
SET
SET
SET
SET
SET
SET
SET
n e Data (8 bit)
63
2, (IX a d)
2, (IY a d)
2, A
2, B
2, C
2, D
2, E
2, H
2, L
3, (HL)
3, (IX a d)
3, (IY a d)
3, A
3, B
3, C
3, D
3, E
3, H
3, L
4, (HL)
4, (IX a d)
4, (IY a d)
4, A
4, B
4, C
4, D
4, E
4, H
4, L
5, (HL)
5, (IX a d)
5, (IY a d)
5, A
5, B
5, C
5, D
5, E
5, H
5, L
6, (HL)
6, (IX a d)
6, (IY a d)
6, A
6, B
6, C
6, D
6, E
6, H
6, L
7, (HL)
7, (IX a d)
7, (IY a d)
7, A
DD CBdD6
FD CBdD6
CB D7
CB D0
CB D1
CB D2
CB D3
CB D4
CB D5
CB DE
DD CBdDE
FD CBdDE
CB DF
CB D8
CB D9
CB DA
CB DB
CB DC
CB DD
CB E6
DD CBdE6
FD CBdE6
CB E7
CB E0
CB E1
CB E2
CB E3
CB E4
CB E5
CB EE
DD CBdEE
FD CBdEE
CB EF
CB E8
CB E9
CB EA
CB EB
CB EC
CB ED
CB F6
DD CBdF6
FD CBdF6
CB F7
CB F0
CB F1
CB F2
CB F3
CB F4
CB F5
CB FE
DD CBdFE
FD CBdFE
CB FF
12.15 Instruction Set: Alphabetical Order (Continued)
SET
SET
SET
SET
SET
SET
SLA
SLA
SLA
SLA
SLA
SLA
SLA
SLA
SLA
SLA
SRA
SRA
SRA
SRA
SRA
SRA
SRA
SRA
SRA
SRA
SRL
SRL
SRL
7, B
7, C
7, D
7, E
7, H
7, L
(HL)
(IX a d)
(IY a d)
A
B
C
D
E
H
L
(HL)
(IX a d)
(IY a d)
A
B
C
D
E
H
L
(HL)
(IX a d)
(IY a d)
CB F8
CB F9
CB FA
CB FB
CB FC
CB FD
CB 26
DD CBd26
FD CBd26
CB 27
CB 20
CB 21
CB 22
CB 23
CB 24
CB 25
CB 2E
DD CBd2E
FD CBd2E
CB 2F
CB 28
CB 29
CB 2A
CB 2B
CB 2C
CB 2D
CB 3E
DD CBd3E
FD CBd3E
SRL
SRL
SRL
SRL
SRL
SRL
SRL
SUB
SUB
SUB
SUB
SUB
SUB
SUB
SUB
SUB
SUB
SUB
XOR
XOR
XOR
XOR
XOR
XOR
XOR
XOR
XOR
XOR
XOR
A
B
C
D
E
H
L
(HL)
(IX a d)
(IY a d)
A
B
C
D
E
H
L
n
(HL)
(IX a d)
(IY a d)
A
B
C
D
E
H
L
n
CB 3F
CB 38
CB 39
CB 3A
CB 3B
CB 3C
CB 3D
96
DD 96d
FD 96d
97
90
91
92
93
94
95
D6 n
AE
DD AEd
FD AEd
AF
A8
A9
AA
AB
AC
AD
EE n
12.16 Instruction Set: Numerical Order
Op Code
Mnemonic
Op Code
Mnemonic
Op Code
Mnemonic
00
01nn
02
03
04
05
06n
07
08
09
0A
0B
0C
0D
0En
0F
10d2
11nn
12
13
14
NOP
LD BC,nn
LD (BC),A
INC BC
INC B
DEC B
LD B,n
RLCA
EX AF,A’F’
ADD HL,BC
LD A,(BC)
DEC BC
INC C
DEC C
LD C,n
RRCA
DJNZ d2
LD DE,nn
LD (DE),A
INC DE
INC D
15
16n
17
18d2
19
1A
1B
1C
1D
1En
1F
20d2
21nn
22nn
23
24
25
26n
27
28d2
29
DEC D
LD D,n
RLA
JR d2
ADD HL,DE
LD A,(DE)
DEC DE
INC E
DEC E
LD E,n
RRA
JR NZ,d2
LD HL,nn
LD (nn),HL
INC HL
INC H
DEC H
LD H, n
DAA
JR Z,d2
ADD HL,HL
2Ann
2B
2C
2D
2En
2F
30d2
31nn
32nn
33
34
35
36n
37
38
39
3Ann
3B
3C
3D
3En
LD HL,(nn)
DEC HL
INC L
DEC L
LD L,n
CPL
JR NC,d2
LD SP,nn
LD (nn),A
INC SP
INC (HL)
DEC (HL)
LD (HL),n
SCF
JR C,d2
ADD HL,SP
LD A,(nn)
DEC SP
INC A
DEC A
LD A,n
(nn) e Address of memory location
d e displacement
nn e Data (16 bit)
d2 e d b 2
n e Data (8 bit)
64
12.16 Instruction Set: Numerical Order (Continued)
Op Code
Mnemonic
Op Code
Mnemonic
Op Code
Mnemonic
3F
40
41
42
43
44
45
46
47
48
49
4A
4B
4C
4D
4E
4F
50
51
52
53
54
55
56
57
58
59
5A
5B
5C
5D
5E
5F
60
61
62
63
64
65
66
67
68
69
6A
6B
6C
6D
6E
6F
70
71
72
73
CCF
LD B,B
LD B,C
LD B,D
LD B,E
LD B,H
LD B,L
LD B,(HL)
LD B,A
LD C,B
LD C,C
LD C,D
LD C,E
LD C,H
LD C,L
LD C,(HL)
LD C,A
LD D,B
LD D,C
LD D,D
LD D,E
LD D,H
LD D,L
LD D,(HL)
LD D,A
LD E,B
LD E,C
LD E,D
LD E,E
LD E,H
LD E,L
LD E,(HL)
LD E,A
LD H,B
LD H,C
LD H,D
LD H,E
LD H,H
LD H,L
LD H,(HL)
LD H,A
LD L,B
LD L,C
LD L,D
LD L,E
LD L,H
LD L,L
LD L,(HL)
LD L,A
LD (HL),B
LD (HL),C
LD (HL),D
LD (HL),E
74
75
76
77
78
79
7A
7B
7C
7D
7E
7F
80
81
82
83
84
85
86
87
88
89
8A
8B
8C
8D
8E
8F
90
91
92
93
94
95
96
97
98
99
9A
9B
9C
9D
9E
9F
A0
A1
A2
A3
A4
A5
A6
A7
A8
LD (HL),H
LD (HL),L
HALT
LD (HL),A
LD A,B
LD A,C
LD A,D
LD A,E
LD A,H
LD A,L
LD A,(HL)
LD A,A
ADD A,B
ADD A,C
ADD A,D
ADD A,E
ADD A,H
ADD A,L
ADD A,(HL)
ADD A,A
ADC A,B
ADC A,C
ADC A,D
ADC A,E
ADC A,H
ADC A,L
ADC A,(HL)
ADC A,A
SUB B
SUB C
SUB D
SUB E
SUB H
SUB L
SUB (HL)
SUB A
SBC A,B
SBC A,C
SBC A,D
SBC A,E
SBC A,H
SBC A,L
SBC A,(HL)
SBC A,A
AND B
AND C
AND D
AND E
AND H
AND L
AND (HL)
AND A
XOR B
A9
AA
AB
AC
AD
AE
AF
B0
B1
B2
B3
B4
B5
B6
B7
B8
B9
BA
BB
BC
BD
BE
BF
C0
C1
C2nn
C3nn
C4nn
C5
C6n
C7
C8
C9
CAnn
CB00
CB01
CB02
CB03
CB04
CB05
CB06
CB07
CB08
CB09
CB0A
CB0B
CB0C
CB0D
CB0E
CB0F
CB10
CB11
CB12
XOR C
XOR D
XOR E
XOR H
XOR L
XOR (HL)
XOR A
OR B
OR C
OR D
OR E
OR H
OR L
OR (HL)
OR A
CP B
CP C
CP D
CP E
CP H
CP L
CP (HL)
CP A
RET NZ
POP BC
JP NZ,nn
JP nn
CALL NZ,nn
PUSH BC
ADD A,n
RST 0
RET Z
RET
JP Z,nn
RLC B
RLC C
RLC D
RLC E
RLC H
RLC L
RLC (HL)
RLC A
RRC B
RRC C
RRC D
RRC E
RRC H
RRC L
RRC (HL)
RRC A
RL B
RL C
RL D
(nn) e Address of memory location
d e displacement
nn e Data (16 bit)
d2 e d b 2
n e Data (8-bit)
65
12.16 Instruction Set: Numerical Order (Continued)
Op Code
Mnemonic
Op Code
Mnemonic
Op Code
Mnemonic
CB13
CB14
CB15
CB16
CB17
CB18
CB19
CB1A
CB1B
CB1C
CB1D
CB1E
CB1F
CB20
CB21
CB22
CB23
CB24
CB25
CB26
CB27
CB28
CB29
CB2A
CB2B
CB2C
CB2D
CB2E
CB2F
CB38
CB39
CB3A
CB3B
CB3C
CB3D
CB3E
CB3F
CB40
CB41
CB42
CB43
CB44
CB45
CB46
CB47
CB48
CB49
CB4A
CB4B
CB4C
CB4D
CB4E
RL E
RL H
RL L
RL (HL)
RL A
RR B
RR C
RR D
RR E
RR H
RR L
RR (HL)
RR A
SLA B
SLA C
SLA D
SLA E
SLA H
SLA L
SLA (HL)
SLA A
SRA B
SRA C
SRA D
SRA E
SRA H
SRA L
SRA (HL)
SRA A
SRL B
SRL C
SRL D
SRL E
SRL H
SRL L
SRL (HL)
SRL A
BIT 0,B
BIT 0,C
BIT 0,D
BIT 0,E
BIT 0,H
BIT 0,L
BIT 0,(HL)
BIT 0,A
BIT 1,B
BIT 1,C
BIT 1,D
BIT 1,E
BIT 1,H
BIT 1,L
BIT 1,(HL)
CB4F
CB50
CB51
CB52
CB53
CB54
CB55
CB56
CB57
CB58
CB59
CB5A
CB5B
CB5C
CB5D
CB5E
CB5F
CB60
CB61
CB62
CB63
CB64
CB65
CB66
CB67
CB68
CB69
CB6A
CB6B
CB6C
CB6D
CB6E
CB6F
CB70
CB71
CB72
CB73
CB74
CB75
CB76
CB77
CB78
CB79
CB7A
CB7B
CB7C
CB7D
CB7E
CB7F
CB80
CB81
CB82
BIT 1,A
BIT 2,B
BIT 2,C
BIT 2,D
BIT 2,E
BIT 2,H
BIT 2,L
BIT 2,(HL)
BIT 2,A
BIT 3,B
BIT 3,C
BIT 3,D
BIT 3,E
BIT 3,H
BIT 3,L
BIT 3,(HL)
BIT 3,A
BIT 4,B
BIT 4,C
BIT 4,D
BIT 4,E
BIT 4,H
BIT 4,L
BIT 4,(HL)
BIT 4,A
BIT 5,B
BIT 5,C
BIT 5,D
BIT 5,E
BIT 5,H
BIT 5,L
BIT 5,(HL)
BIT 5,A
BIT 6,B
BIT 6,C
BIT 6,D
BIT 6,E
BIT 6,H
BIT 6,L
BIT 6,(HL)
BIT 6,A
BIT 7,B
BIT 7,C
BIT 7,D
BIT 7,E
BIT 7,H
BIT 7,L
BIT 7,(HL)
BIT 7,A
RES 0,B
RES 0,C
RES 0,D
CB83
CB84
CB85
CB86
CB87
CB88
CB89
CB8A
CB8B
CB8C
CB8D
CB8E
CB8F
CB90
CB91
CB92
CB93
CB94
CB95
CB96
CB97
CB98
CB99
CB9A
CB9B
CB9C
CB9D
CB9E
CB9F
CBA0
CBA1
CBA2
CBA3
CBA4
CBA5
CBA6
CBA7
CBA8
CBA9
CBAA
CBAB
CBAC
CBAD
CBAE
CBAF
CBB0
CBB1
CBB2
CBB3
CBB4
CBB5
CBB6
RES 0,E
RES 0,H
RES 0,L
RES 0,(HL)
RES 0,A
RES 1,B
RES 1,C
RES 1,D
RES 1,E
RES 1,H
RES 1,L
RES 1,(HL)
RES 1,A
RES 2,B
RES 2,C
RES 2,D
RES 2,E
RES 2,H
RES 2,L
RES 2,(HL)
RES 2,A
RES 3,B
RES 3,C
RES 3,D
RES 3,E
RES 3,H
RES 3,L
RES 3,(HL)
RES 3,A
RES 4,B
RES 4,C
RES 4,D
RES 4,E
RES 4,H
RES 4,L
RES 4,(HL)
RES 4,A
RES 5,B
RES 5,C
RES 5,D
RES 5,E
RES 5,H
RES 5,L
RES 5,(HL)
RES 5,A
RES 6,B
RES 6,C
RES 6,D
RES 6,E
RES 6,H
RES 6,L
RES 6,(HL)
(nn) e Address of memory location
d e displacement
nn e Data (16 bit)
d2 e d b 2
n e Data (8-bit)
66
12.16 Instruction Set: Numerical Order (Continued)
Op Code
Mnemonic
Op Code
Mnemonic
Op Code
Mnemonic
CBB7
CBB8
CBB9
CBBA
CBBB
CBBC
CBBD
CBBE
CBBF
CBC0
CBC1
CBC2
CBC3
CBC4
CBC5
CBC6
CBC7
CBC8
CBC9
CBCA
CBCB
CBCC
CBCD
CBCE
CBCF
CBD0
CBD1
CBD2
CBD3
CBD4
CBD5
CBD6
CBD7
CBD8
CBD9
CBDA
CBDB
CBDC
CBDD
CBDE
CBDF
CBE0
CBE1
CBE2
CBE3
CBE4
CBE5
CBE6
CBE7
CBE8
CBE9
CBEA
CBEB
RES 6,A
RES 7,B
RES 7,C
RES 7,D
RES 7,E
RES 7,H
RES 7,L
RES 7,(HL)
RES 7,A
SET 0,B
SET 0,C
SET 0,D
SET 0,E
SET 0,H
SET 0,L
SET 0,(HL)
SET 0,A
SET 1,B
SET 1,C
SET 1,D
SET 1,E
SET 1,H
SET 1,L
SET 1,(HL)
SET 1,A
SET 2,B
SET 2,C
SET 2,D
SET 2,E
SET 2,H
SET 2,L
SET 2,(HL)
SET 2,A
SET 3,B
SET 3,C
SET 3,D
SET 3,E
SET 3,H
SET 3,L
SET 3,(HL)
SET 3,A
SET 4,B
SET 4,C
SET 4,D
SET 4,E
SET 4,H
SET 4,L
SET 4,(HL)
SET 4,A
SET 5,B
SET 5,C
SET 5,D
SET 5,E
CBEC
CBED
CBEE
CBEF
CBF0
CBF1
CBF2
CBF3
CBF4
CBF5
CBF6
CBF7
CBF8
CBF9
CBFA
CBFB
CBFC
CBFD
CBFE
CBFF
CCnn
CDnn
CEn
CF
D0
D1
D2nn
D3n
D4nn
D5
D6n
D7
D8
D9
DAnn
DBn
DCnn
DD09
DD19
DD21nn
DD22nn
DD23
DD29
DD2Ann
DD2B
DD34d
DD35d
DD36dn
DD39
DD46d
DD4Ed
DD56d
DD5Ed
SET 5,H
SET 5,L
SET 5,(HL)
SET 5,A
SET 6,B
SET 6,C
SET 6,D
SET 6,E
SET 6,H
SET 6,L
SET 6,(HL)
SET 6,A
SET 7,B
SET 7,C
SET 7,D
SET 7,E
SET 7,H
SET 7,L
SET 7,(HL)
SET 7,A
CALL Z,nn
CALL nn
ADC A,n
RST 8
RET NC
POP DE
JP NC,nn
OUT (n),A
CALL NC,nn
PUSH DE
SUB n
RST 10H
RET C
EXX
JP,C,nn
IN A,(n)
CALL C,nn
ADD IX,BC
ADD IX,DE
LD IX,nn
LD (nn),IX
INC IX
ADD IX,IX
LD IX,(nn)
DEC IX
INC (IX a d)
DEC (IX a d)
LD (IX a d),n
ADD IX,SP
LD B,(IX a d)
LD C,(IX a d)
LD D,(IX a d)
LD E,(IX a d)
DD66d
DD6Ed
DD70d
DD71d
DD72d
DD73d
DD74d
DD75d
DD77d
DD7Ed
DD86d
DD8Ed
DD96d
DD9Ed
DDA6d
DDAEd
DDB6d
DDBEd
DDCBd06
DDCBd0E
DDCBd16
DDCBd1E
DDCBd26
DDCBd2E
DDCBd3E
DDCBd46
DDCBd4E
DDCBd56
DDCBd5E
DDCBd66
DDCBd6E
DDCBd76
DDCBd7E
DDCBd86
DDCBd8E
DDCBd96
DDCBd9E
DDCBdA6
DDCBdAE
DDCBdB6
DDCBdBE
DDCBdC6
DDCBdCE
DDCBdD6
DDCBdDE
DDCBdE6
DDCBdEE
DDCBdF6
DDCBdFE
DDE1
DDE3
DDE5
DDE9
LD H,(IX a d)
LD L,(IX a d)
LD (IX a d),B
LD (IX a d),C
LD (IX a d),D
LD (IX a d),E
LD (IX a d),H
LD (IX a d),L
LD (IX a d),A
LD A,(IX a d)
ADD A,(IX a d)
ADC A,(IX a d)
SUB (IX a d)
SBC A,(IX a d)
AND (IX a d)
XOR (IX a d)
OR (IX a d)
CP (IX a d)
RLC (IX a d)
RRC (IX a d)
RL (IX a d)
RR (IX a d)
SLA (IX a d)
SRA (IX a d)
SRL (IX a d)
BIT 0,(IX a d)
BIT 1,(IX a d)
BIT 2,(IX a d)
BIT 3,(IX a d)
BIT 4,(IX a d)
BIT 5,(IX a d)
BIT 6,(IX a d)
BIT 7,(IX a d)
RES 0,(IX a d)
RES 1,(IX a d)
RES 2,(IX a d)
RES 3,(IX a d)
RES 4,(IX a d)
RES 5,(IX a d)
RES 6,(IX a d)
RES 7,(IX a d)
SET 0,(IX a d)
SET 1,(IX a d)
SET 2,(IX a d)
SET 3,(IX a d)
SET 4,(IX a d)
SET 5,(IX a d)
SET 6,(IX a d)
SET 7,(IX a d)
POP IX
EX (SP),IX
PUSH IX
JP (IX)
(nn) e Address of memory location
d e displacement
nn e Data (16 bit)
d2 e d b 2
n e Data (8-bit)
67
12.16 Instruction Set: Numerical Order (Continued)
Op Code
Mnemonic
Op Code
Mnemonic
Op Code
Mnemonic
DDF9
DEn
DF
E0
E1
E2nn
E3
E4nn
E5
E6n
E7
E8
E9
EAnn
EB
ECnn
ED40
ED41
ED42
ED43nn
ED44
ED45
ED46
ED47
ED48
ED49
ED4A
ED4Bnn
ED4D
ED50
ED51
ED52
ED53nn
ED56
ED57
ED58
ED59
ED5A
ED5Bnn
ED5E
ED60
ED61
ED62
ED67
ED68
ED69
ED6A
ED6F
ED72
ED73nn
ED78
ED79
ED7A
LD SP,IX
SCB A,n
RST 18H
RET PO
POP HL
JP PO,nn
EX (SP),HL
CALL PO,nn
PUSH HL
AND n
RST 20H
RET PE
JP (HL)
JP PE,nn
EX DE,HL
CALL PE,nn
IN B,(C)
OUT (C),B
SBC HL,BC
LD (nn),BC
NEG
RETN
IM 0
LD I,A
IN C,(C)
OUT (C),C
ADC HL,BC
LD BC,(nn)
RETI
IN D,(C)
OUT (C),D
SBC HL,DE
LD (nn),DE
IM 1
LD A,I
IN E,(C)
OUT (C), E
ADC HL,DE
LD DE,(nn)
IM 2
IN H,(C)
OUT (C),H
SBC HL,HL
RRD
IN L,(C)
OUT (C),L
ADC HL,HL
RLD
SBC HL,SP
LD (nn),SP
IN A,(C)
OUT (C),A
ADC HL,SP
ED7Bnn
EDA0
EDA1
EDA2
EDA3
EDA8
EDA9
EDAA
EDAB
EDB0
EDB1
EDB2
EDB3
EDB8
EDB9
EDBA
EDBB
EEn
EF
F0
F1
F2nn
F3
F4nn
F5
F6n
F7
F8
F9
FAnn
FB
FCnn
FD09
FD19
FD21nn
FD22nn
FD23
FD29
FD2Ann
FD2B
FD34d
FD35d
FD36dn
FD39
FD46d
FD4Ed
FD56d
FD5Ed
FD66d
FD6Ed
FD70d
FD71d
FD72d
LD SP,(nn)
LDI
CPI
INI
OUTI
LDD
CPD
IND
OUTD
LDIR
CPIR
INIR
OTIR
LDDR
CPDR
INDR
OTDR
XOR n
RST 28H
RET P
POP AF
JP P,nn
DI
CALL P,nn
PUSH AF
OR n
RST 30H
RET M
LD SP,HL
JP M,nn
EI
CALL M,nn
ADD IY,BC
ADD IY,DE
LD IY,nn
LD (nn),IY
INC IY
ADD IY,IY
LD IY,(nn)
DEC IY
INC (IY a d)
DEC (IY a d)
LD (IY a d),n
ADD IY,SP
LD B,(IY a d)
LD C,(IY a d)
LD D,(IY a d)
LD E,(IY a d)
LD H,(IY a d)
LD L,(IY a d)
LD (IY a d),B
LD (IY a d),C
LD (IY a d),D
FD73d
FD74d
FD75d
FD77d
FD7Ed
FD86d
FD8Ed
FD96d
FD9Ed
FDA6d
FDAEd
FDB6d
FDBEd
FDE1
FDE3
FDE5
FDE9
FDF9
FDCBd06
FDCBd0E
FDCBd16
FDCBd1E
FDCBd26
FDCBd2E
FDCBd3E
FDCBd46
FDCBd4E
FDCBd56
FDCBd5E
FDCBd66
FDCBd6E
FDCBd76
FDCBd7E
FDCBd86
FDCBd8E
FDCBd96
FDCBd9E
FDCBdA6
FDCBdAE
FDCBdB6
FDCBdBE
FDCBdC6
FDCBdCE
FDCBdD6
FDCBdDE
FDCBdE6
FDCBdEE
FDCBdF6
FDCBdFE
FEn
FF
LD (IY a d),E
LD (IY a d),H
LD (IY a d),L
LD (IY a d),A
LD A,(IY a d)
ADD A,(IY a d)
ADC A,(IY a d)
SUB (IY a d)
SBC A,(IY a d)
AND (IY a d)
XOR (IY a d)
OR (IY a d)
CP (IY a d)
POP IY
EX (SP), IY
PUSH IY
JP (IY)
LD SP,IY
RLC (IY a d)
RRC (IY a d)
RL (IY a d)
RR (IY a d)
SLA (IY a d)
SRA (IY a d)
SRL (IY a d)
BIT 0,(IY a d)
BIT 1,(IY a d)
BIT 2,(IY a d)
BIT 3,(IY a d)
BIT 4,(IY a d)
BIT 5,(IY a d)
BIT 6,(IY a d)
BIT 7,(IY a d)
RES 0,(IY a d)
RES 1,(IY a d)
RES 2,(IY a d)
RES 3,(IY a d)
RES 4,(IY a d)
RES 5,(IY a d)
RES 6,(IY a d)
RES 7,(IY a d)
SET 0,(IY a d)
SET 1,(IY a d)
SET 2,(IY a d)
SET 3,(IY a d)
SET 4,(IY a d)
SET 5,(IY a d)
SET 6,(IY a d)
SET 7,(IY a d)
CP n
RST 38H
(nn) e Address of memory location
d e displacement
nn e Data (16 bit)
d2 e d b 2
n e Data (8-bit)
68
13.0 Data Acquisition System
the need for battery operation or at least battery backup. At
some fixed times or at some particular time durations, the
system takes readings by selecting one of the analog input
channels, commands the A/D to perform a conversion,
reads the data, and then formats it for transmission; or, the
system checks the readings against set points and transmits a warning if the set points are exceeded. With the addition of the RTC, the host need not command the remote
system to take these readings each time it is necessary.
The NSC800 could simply set up the RTC to interrupt it at a
previously defined time and when the interrupt occurs, make
the readings. The resultant values could be stored in the
NSC810A for later correlation. In the example of temperature monitoring in a building, it might be desired to know the
high and low temperatures for a 12-hour period. After compiling the information, the system could dump the data to
the host over the communications link. Note from the schematic that the current for the communication link is supplied
by the host to remove the constant current drain from the
battery supply.
The required clocks for the two peripheral devices are generated by the two timers in the NSC810A. Through the use
of various divisors, the master clock generated by the
NSC800 is divided down to produce the clocks. Four examples are shown in the table following Figure 20 .
All the crystal frequencies are standard frequencies. The
various divisors listed are selected to produce, from the
master clock frequency of the NSC800, an exact 32,768 Hz
clock for the MM58167 and a clock within the operating
range of the A/D converter.
The MM58167 is a programmable real-time clock that is
microprocessor compatible. Its data format is BCD. It allows
the system to program its interrupt register to produce an
interrupt output either on a time of day match (which includes the day of the week, the date and month) and/or
every month, week, day, hour, minute, second, or tenth of a
second. With this capability added to the system, precise
time of day measurements are possible without having the
CPU do timekeeping. The interrupt output can be connected, through the use of one port bit of the NSC810A, to put
the CPU in the power-save mode and reenable it at a preset
time. The interrupt output is also connected to one of the
hardware restart inputs (RSTB) to enable time duration
measurements. This power-down mode of operation would
not be possible if the NSC800 had the duties of timekeep-
A natural application for the NSC800 is one that requires
remote operation. Since power consumption is low if the
system consists of only CMOS components, the entire
package can conceivably operate from only a battery power
source. In the application described herein, the only source
of power will be from a battery pack composed of a stacked
array of NiCad batteries (see Figure 20 ).
The application is that of a remote data acquisition system.
Extensive use is made of some of the other LSI CMOS components manufactured by National: notably the ADC0816
and MM58167. The ADC0816 is a 16-channel analog-todigital converter which operates from a 5V source. The
MM58167 is a microprocessor-compatible real-time clock
(RTC). The schematic for this system is shown in Figure 20 .
All the necessary features of the system are contained in six
integrated circuits: NSC800, NSC810A, NSC831, HN6136P,
ADC0816, and MM58167. Some other small scale integration CMOS components are used for normal interface requirements. To reduce component count, linear selection
techniques are used to generate chip selects for the
NSC810A and NSC831. Included also is a current loop communication link to enable the remote system to transfer data
collected to a host system.
In order to keep component count low and maximize effectiveness, many of the features of the NSC800 family have
been utilized. The RAM section of the NSC810A is used as
a data buffer to store intermediate measurements and as
scratch pad memory for calculations. Both timers contained
in the NSC810A are used to produce the clocks required by
the A/D converter and the RTC. The Power-Save feature of
the NSC800 makes it possible to reduce system power consumption when it is not necessary to collect any data. One
of the analog input channels of the A/D is connected to the
battery pack to enable the CPU to monitor its own voltage
supply and notify the host that a battery change is needed.
In operation, the NSC800 makes readings on various input
conditions through the ADC0816. The type of devices connected to the A/D input depends on the nature of the remote environment. For example, the duties of the remote
system might be to monitor temperature variations in a large
building. In this case, the analog inputs would be connected
to temperature transducers. If the system is situated in a
process control environment, it might be monitoring fluid
flow, temperatures, fluid levels, etc. In either case, operation
would be necessary even if a power failure occurred, thus
69
FIGURE 20. Remote Data Acquisition
TL/C/5171 – 34
13.0 Data Acquisition System (Continued)
70
13.0 Data Acquisition System (Continued)
signal which is connected to the RSTA interrupt input of the
NSC800.
When operating, the system shown consumes about 125
mw. When in the power-save mode, power consumption is
decreased to about 70 mw. If, as is likely, the system is in
the power-save mode most of the time, battery life can be
quite long depending on the amp-hour rating of the batteries
incorporated into the system. For example, if the battery
pack is rated at 5 amp-hours, the system should be able to
operate for about 400-500 hours before a battery charge or
change is required.
As shown in the schematic (refer to Figure 20 ), analog input
IN0 is connected to the battery source. In this way, the CPU
can monitor its own power source and notify the host that it
needs a battery replacement or charge. Since the battery
source shown is a stacked array of 7 NiCads producing
8.4V, the converter input is connected in the middle so that
it can take a reading on two or three of the cells. Since
NiCad batteries have a relatively constant voltage output
until very nearly discharged, the CPU can sense that the
‘‘knee’’ of the discharge curve has been reached and notify
the host.
ing. When in the power-save mode, the system power requirements are decreased by about 50%, thus extending
battery life.
Communication with the peripheral devices (MM58167 and
ADC0816) is accomplished through the I/O ports of the
NSC810A and NSC831. The peripheral devices are not connected to the bus of the NSC800 as they are not directly
compatible with a multiplexed bus structure. Therefore, additional components would be required to place them on the
microprocessor bus. Writing data into the MM58167 is performed by first putting the desired data on Port A, followed
by selecting the address of the internal register and applying
the chip select through the use of Port B. A bit set and clear
operation is performed to emulate a pulse on the bit of Port
B connected to the WR input of the MM58167. For a read
operation, the same sequence of operations is performed
except that Port A is set for the input mode of operation and
the RD line is pulsed. Similar techniques are used to read
converted data from the A/D converter. When a conversion
is desired, the CPU selects a channel and commands the
ADC0816 to start a conversion. When the conversion is
complete, the converter will produce an End-of-Conversion
Typical Timer Output Frequencies
Crystal Frequency
CPU Clock Output
Timer 0 Output
Timer 1 Output
2.097152 MHz
1.048576 MHz
262.144 kHz
divisor e 4
32.768 kHz
divisor e 8
3.276800 MHz
1.638400 MHz
327.680 kHz
divisor e 5
32.768 kHz
divisor e 10
4.194304 MHz
2.097152 MHz
262.144 kHz
divisor e 8
32.768 kHz
divisor e 8
4.915200 MHz
2.457600 MHz
491.520 kHz
divisor e 5
32.768 kHz
divisor e 15
71
14.0 NSC800M/883B MIL-STD-833
Class C Screening
Electrical testing is performed in accordance with
RESTS800X, which tests or guarantees all of the electrical
performance characteristics of the NSC800 data sheet. A
copy of the current revision of RETS800X is available upon
request.
National Semiconductor offers the NSC800D and NSC800E
with full class B screening per MIL-STD-883 for Military/
Aerospace programs requiring high reliability. In addition,
this screening is available for all of the key NSC800 peripheral devices.
100% Screening Flow
Test
MIL-STD-883 Method/Condition
Internal Visual
Stabilization Bake
Temperature Cycling
Constant Acceleration
Fine Leak
Gross Leak
Burn-In
2010B
1008 C 24 Hrs. @ a 150§ C
1010 C 10 Cycles b65§ C/ a 150§ C
2001 E 30,000 G’s, Y1 Axis
1014 A or B
1014C
1015 160 Hrs. @ a 125§ C (using
burn-in circuits shown below)
a 25§ C DC per RETS800X
10% Max
a 125§ C AC and DC per RETS800X
b 55§ C AC and DC per RETS800X
a 25§ C AC per RETS800X
5005
Final Electrical
PDA
QA Acceptance
Quality Conformance
External Visual
2009
Requirement
100%
100%
100%
100%
100%
100%
100%
100%
100%
100%
100%
Sample Per
Method 5005
100%
15.0 Burn-In Circuits
5241HR
NSC800E/883B (Leadless Chip Carrier)
5240HR
NSC800D/883B (Dual-In-Line)
TL/C/5171–32
Top View
TL/C/5171 – 33
All resistors 2.7 kX unless marked otherwise.
Note 1: All resistors are (/4W g 5% unless otherwise specified.
Note 2: All clocks 0V to 3V, 50% duty cycle, in phase with k 1 ms rise and fall time.
Note 3: Device to be cooled down under power after burn-in.
72
16.0 Ordering Information
NSC800
X
X
X
X
/A a e A a Reliability Screening
/883 e MIL-STD-883 Screening (Note 1)
I e Industrial Temperature (b40§ C to a 85§ C)
M e Military Temperature (b55§ C to a 125§ C)
MIL e Special Temperature (b55§ C to a 90§ C)
No Designation e Commercial Temperature (0§ C to a 70§ C)
b 4 e 4 MHz Clock
b 35 e 3.5 MHz Clock Output
b 3 e 2.5 MHz Clock Output
b 1 e 1 MHz Clock Output
D e Ceramic Package
N e Plastic Package
E e Ceramic Leadless Chip Carrier (LCC)
V e Plastic Leaded Chip Carrier (PCC)
Note 1: Do not specify a temperature option; all parts are screened to military temperature.
17.0 Reliability Information
Gate Count 2750
Transistor Count 11,000
73
Physical Dimensions inches (millimeters)
Molded Dual-In-Line Package (N)
Order Number NSC800N
NS Package Number N40A
Hermetic Dual-In-Line Package (D)
Order Number NSC800D
NS Package Number D40C
74
Physical Dimensions inches (millimeters) (Continued)
Leadless Chip Carrier Package (E)
Order Number NSC800E
NS Package Number E44A
75
NSC800 High-Performance Low-Power CMOS Microprocessor
Physical Dimensions inches (millimeters) (Continued)
Plastic Chip Carrier (V)
Order Number NSC800V
NS Package Number V44A
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DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL
SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or
systems which, (a) are intended for surgical implant
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failure to perform, when properly used in accordance
with instructions for use provided in the labeling, can
be reasonably expected to result in a significant injury
to the user.
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Corporation
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2. A critical component is any component of a life
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be reasonably expected to cause the failure of the life
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