DP83241 CDD TM Device (FDDI Clock Distribution Device) General Description Features The CDD device is a clock generation and distribution device intended for use in FDDI (Fiber Distributed Data Interface) networks. The device provides the complete set of clocks required to convert byte wide data to serial format for fiber medium transmission and to move byte wide data between the PLAYERTM and BMACTM devices in various station configurations. 12.5 MHz and 125 MHz differential ECL clocks are generated for the conversion of data to serial format and 12.5 MHz and 25 MHz TTL clocks are generated for the byte wide data transfers. Y Y Y Y Y Y Y Y Y Provides 12.5 MHz and 25 MHz TTL clocks 12.5 MHz and 125 MHz ECL clocks 5 phase TTL local byte clocks eliminate clock skew problems in concentrators Internal VCO requires no varactors, coils or adjustments Option for use of High Q external VCO 125 MHz clock generated from a 12.5 MHz crystal External PLL synchronizing reference for concentrator configurations 28-pin PLCC package BiCMOS processing TL/F/10385 – 1 FIGURE 1-1. FDDI Chip Set Block Diagram TRI-STATEÉ is a registered trademark of National Semiconductor Corporation. BMACTM , BSITM , CDDTM , CRDTM and PLAYERTM are trademarks of National Semiconductor Corporation. C1995 National Semiconductor Corporation TL/F/10385 RRD-B30M105/Printed in U. S. A. DP83241 CDD Device (FDDI Clock Distribution Device) February 1991 Table of Contents 5.0 DETAILED INFORMATION 1.0 FDDI CHIP SET OVERVIEW 5.1 External Components 2.0 FUNCTIONAL DESCRIPTION 5.2 Concentrator and Dual Attach Station Configurations 3.0 PIN DESCRIPTIONS 5.3 Layout Recommendations 4.0 ELECTRICAL CHARACTERISTICS 5.4 Input and Output Schematics 4.1 Absolute Maximum Ratings 5.5 System Debugging Flowchart 4.2 Recommended Operating Conditions 5.6 AC Test Circuits 4.3 DC Electrical Characteristics 4.4 AC Electrical Characteristics 2 1.0 FDDI Chip Set Overview DP83261 BMAC TM Device Media Access Controller National Semiconductor’s FDDI chip set consists of five components as shown in Figure 1-1. For more information about the other devices in the chip set, consult the appropriate data sheets and application notes. The BMAC device implements the Timed Token Media Access Control protocol defined by the ANSI FDDI X3T9.5 MAC Standard. DP83231 CRD TM Device Clock Recovery Device Features # All of the standard defined ring service options # Full duplex operation with through parity # Supports all FDDI Ring Scheduling Classes (Synchro- The Clock Recovery Device extracts a 125 MHz clock from the incoming bit stream. nous, Asynchronous, etc.) Features # Supports Individual, Group, Short, Long, and External # PHY Layer loopback test # Crystal controlled # Clock locks in less than 85 ms Addressing # # # # DP83241 CDD TM Device Clock Distribution Device From a 12.5 MHz reference, the Clock Distribution Device synthesizes the 125 MHz, 25 MHz and 12.5 MHz clocks required by the BSI, BMAC, and PLAYER devices. # Multi-frame streaming interface DP83265 BSI TM Device System Interface DP83251/55 PLAYER TM Device Physical Layer Controller The BSI Device implements an interface between the National FDDI BMAC device and a host system. The PLAYER device implements the Physical Layer (PHY) protocol as defined by the ANSI FDDI PHY X3T9.5 Standard. Features # # # # # # # # # # # Features # # # # # # # # Generates Beacon, Claim, and Void frames internally Extensive ring and station statistics gathering Extensions for MAC level bridging Separate management port that is used to configure and control operation 4B/5B encoders and decoders Framing logic Elasticity Buffer, Repeat Filter, and Smoother Line state detector/generator Link error detector Configuration switch Full duplex operation Separate management port that is used to configure and control operation. In addition, the DP83255 contains an additional PHYÐData.request and PHYÐData.indicate port required for concentration and dual attach stations. 3 32-bit wide Address/Data path with byte parity Programmable transfer burst sizes of 4 or 8 32-bit words Interfaces to low-cost DRAMs or directly to system bus Provides 2 Output and 3 Input Channels Supports Header/Info splitting Efficient data structures Programmable Big or Little Endian alignment Full Duplex data path allows transmission to self Comfirmation status batching services Receive frame filtering services Operates from 12.5 MHz to 25 MHz synchronously with host system 2.0 Functional Description mon reference signal. The VCO SEL input provides the option to use the internally provided VCO or an external LC voltage controlled oscillator. Although the stability of the internal VCO should be adequate for most applications the external VCO option provides the means of obtaining the maximum possible oscillator Q. The PHASE SEL input pin provides the option of selecting whether the five phase LBC outputs are phase offset 36 degrees or 72 degrees (8 ns or 16 ns). The phase locked loop (PLL) elements, with the exception of the loop filter which consist of two capacitors and a resistor, are fully contained within the device. The internal VCO associated with the PLL has been implemented totally within the device and requires no external LC oscillator tank coils, capacitors, or varactors. The external VCO option does provide a means of using these conventional LC oscillator techniques if desired. The CDD device clocks are all generated from and phase aligned to either a 12.5 MHz crystal oscillator or a TTL input reference source using digital phase locked loop techniques. The architecture of the Clock Distribution Device ensures that the output clocks which are generated have frequency tolerances identical to the 50 PPM crystal reference. When the reference input signal is a backplane signal, the matching of the phase comparator input path delays guarantees phase alignment within 3 ns. The phase locked loop generates the desired clocks as shown in the device Block Diagram. One of the Local Byte Clock (LBC) phases is connected to the FEEDBK IN input of the phase comparator where its phase and frequency are compared against that of the selected input reference signal. Any phase error between these signals results in a correction of the voltage into the Voltage Controlled Oscillator (VCO) which is proportional to the amount of phase error. The correction voltage tends to drive the frequency of the VCO in the direction which, when divided down, minimizes the LBC to reference signal phase difference. When the phase transition of the LBC occurs before that of the reference input the VCO frequency is sensed as being too fast and produces a negative going correction to the VCO input. This in turn slows down the VCO’s frequency and delays the subsequent LBC phase transitions. The device’s differential 125 MHz ECL transmit clock and differential 12.5 MHz ECL load strobe are used by the PLAYER device to convert data from byte wide NRZ format to serial NRZI format for fiber medium transmission. A 12.5 MHz TTL local byte clock is provided for use by the PLAYER and the BMAC devices. Five phases of the local byte clock are provided for use in large multi-board concentrator configurations to aid in cancelling out backplane delays. A 25 MHz Local Symbol Clock (LSC) is provided which is in phase with the local byte clocks and has a 40% HIGH and 60% LOW duty cycle. The device provides three user-selectable features. The REF SEL input provides the option to lock the device’s outputs to a crystal oscillator or to an external TTL signal (REF IN). The REF IN signal is particularly useful in concentrators where multiple boards need to be phase locked to a com- Connection Diagram 28-Pin PLCC Package TL/F/10385 – 25 Order Number DP83241BV See NS Package Number V28A FIGURE 2-1. DP83241 Pinout Block Diagram TL/F/10385 – 3 FIGURE 2-2. DP83241 Block Diagram 4 3.0 Pin Descriptions Symbol Pin No. I/O Description DVCC 16 Digital VCC: Positive power supply for all the internal circuitry intended for operation at 5V g 5% relative to GND. A bypass capacitor should be placed as close as possible across the DVCC and DGND pins. EXTVCC 28 External VCC: Positive power supply for all the output buffers intended for operation at 5V g 5% relative to GND. A bypass capacitor should be placed as close as possible across the EXTVCC and EXTGND pins. DGND 15 Digital Ground: Internal circuit power supply return. EXTGND 1 External Ground: Output buffer power supply return. AGND 14 Analog Ground: Substrate ground used to ensure proper device biasing and isolation. AVCC 18 Analog VCC: Positive power supply for the critical analog circuitry, intended for a 5V operation g 5% relative to Ground. A bypass cap should be placed as close as possible between AVCC and AGND. XTL IN 8 XTL OUT 6 REF IN 5 I Reference Input: TTL compatible input for use as the PLL’s phase comparator reference frequency input when the REF SEL is at a logic HI level. This input is for use in concentrator configurations where there are multiple CDD devices at a given site requiring synchronization. FEEDBK IN 4 I Feedback Input: TTL compatible input for use as the PLL’s phase comparator feedback input to close the loop. This input is intended to be driven from one of the LBCs (Local Byte Clocks). This input is designed to provide the same frequency and within 2 ns of the same phase as REF IN when REF IN is in active operation. REF SEL 9 I Reference Select: TTL compatible input which selects either the crystal oscillator inputs XTL IN and XTL OUT or the REF IN inputs as the reference frequency inputs for the PLL. The crystal oscillator inputs are selected when REF SEL is at a logic LOW level and the REF IN input is selected as the reference frequency when REF SEL is at a logic HI level. FILTER 10 O Filter: Low pass PLL loop filter pin. A three element filter, consisting of one capacitor in parallel with a resistor and another capacitor, should be connected between this pin and ground. VCO SEL 17 I VCO Select: TTL compatible input used to select either the internal VCO or an external VCO through the XVCO IN and XVCO INB pins. The internal VCO is selected when the VCO SEL pin is at a logic HIGH level and the external VCO is selected when at a logic LOW level. XVCO IN, XVCO INB 13, 12 I External VCO Inputs: Differential inputs for use with an external VCO. These inputs are D.C. biased to approximately one half VCC, and can be connected to either a full differential VCO, or a single-ended VCO. To use a single-ended VCO, couple the signal into one of the inputs through a series low value capacitor and bypass the other input to GND through a 0.01 mF capacitor. When not in use, ground one input, and let the other float. I External Crystal Oscillator Input: XTL IN can also be used as a CMOS compatible reference frequency input for the PLL. This input is selected when REF SEL is at a logical LOW level. The component connections required for oscillator operation are shown in the application diagrams. External Crystal Oscillator Output: XTL OUT is not intended for use as a logic drive output pin. 5 3.0 Pin Descriptions (Continued) Symbol Pin No. I/O VCO RST 11 I VCO Reset: TTL compatible input used to reset the internal VCO on system power up. This input stops the VCO from oscillating when at a logic HI level thereby reinitializing each of the gates in the ring oscillator. TXC a , TXCb 3, 2 O Transmit Clock: 100K ECL compatible differential outputs for use at 125 MHz as the fiber medium Transmit Clock (TXC) source for the PLAYER device. TBC a , TBCb 27, 26 O Transmit Byte Clock: 100K ECL compatible differential outputs for use at 12.5 MHz as a load strobe or transmit byte clock by the PLAYER device to convert byte wide data to serial format for fiber medium transmission. These outputs are positioned to transition on the falling edge of the TXC a clock output to provide the maximum setup and hold margin. They are also phase coherent with the TTL LBC1 output, but the phase transition occurs approximately 10 ns earlier. 25, 24, 23, 22, 21 O Local Byte Clocks: TTL compatible local byte clock outputs which are phase locked to crystal oscillator reference signals. These outputs have a 50% duty cycle waveform at 12.5 MHz. The PHASE SEL input determines whether the five phase outputs are phase offset by 8 ns or 16 ns. LSC 20 O Local Symbol Clock: TTL compatible 25 MHz output for driving the BMAC device. This output’s negative phase transition is aligned with the LBC1 output transitions and has a 40% HI and 60% LOW duty cycle. PHASE SEL 19 I Phase Select: TTL compatible input used to select either a 8 ns or 16 ns phase offset between the 5 local byte clocks. The LBC’s are phase offset 8 ns apart when PHASE SEL is at a logic LOW level and 16 ns apart when at a logic HI level. LBC1 thru 5 Description 6 4.0 Electrical Characteristics 4.1 ABSOLUTE MAXIMUM RATINGS ECL Signals Output Current If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/Distributors for availability and specifications. b 65§ C to a 150§ C Storage Temperature TTL Signals Inputs Outputs b 50 mA Supplies EXTVCC to EXTGND DVCC to DGND AVCC to AGND ESD Protection b 0.5V to a 5.5V b 0.5V to a 5.5V b 0.5V to a 7V b 0.5V to a 7V b 0.5V to a 7V 1500V 4.2 RECOMMENDED OPERATING CONDITIONS Symbol Parameter VCC to GND Power Supply VIH High Level Input Voltage VIL Low Level Input Voltage Min Typ Max Units 4.75 5.0 5.25 V TTL 2.0 ECL VCC b 1.165 VCC b 0.880 VCC b 1.810 VCC b 1.475 V TTL 0.8 ECL V IOH High Level Output Current TTL Outputs (Note 1) b 0.4 mA IOL Low Level Output Current TTL Outputs (Note 1) 8.0 mA FVCO VCO Frequency (INT or EXT) 250 MHz FREF Reference Input Frequency 12.5 MHz TA Operating Temperature 0 25 70 §C Max Units b 1.5 V Note 1: TTL outputs include LBC1, LBC2, LBC3, LBC4, LBC5 and LSC. 4.3 DC ELECTRICAL CHARACTERISTICS Symbol Parameter Conditions VIC Input Clamp Voltage IIN e 18 mA VOH High Level Output Voltage TTL Outputs: IOH e b400 mA VOL Low Level Output Voltage ECL Outputs: 50X Load to VCC b 2V Min VCC b 2 VCC b 1025 TTL Outputs: IOL e 8 mA ECL Outputs: 50X Load to VCC b 2V VCC b 1810 V VCC b 880 mV 0.5 V VCC b 1620 mV 100 mA II Max High Level Input Current TTL Inputs: VIN e 7V IIH High Level Input Current TTL Inputs: VIN e 2.7V b 20 20 mA IIL Low Level Input Current TTL Inputs: VIN e 0.4V b 20 20 mA IFilter Charge Pump Current Source b 0.7 a 0.7 mA 0.2 0.7 mA b 250 250 nA 170* mA Sink TRI-STATEÉ ICC Supply Current *Includes 60 mA due to external ECL termination of two differential signals. For 100k ECL output buffers, output levels are specified as: VOHÐMax e VCC b 0.88V VOLÐMax e VCC b 1.62V Since the outputs are differential, the average output level is VCC b 1.25V. The test load per output is 50X at VCC b 2V. The external load current through this 50X resistor is thus: IÐLoad e [(VCC b 1.25) b (VCC b 2)]/50 Amps e 0.015 Amps e 15 mA There are 2 pairs of differential ECL signals, so the total ECL current is 60 mA. 7 4.0 Electrical Characteristics (Continued) 4.4 AC ELECTRICAL CHARACTERISTICS Symbol Parameter T1 TBC to TXC T2 TBC to LBC1 TPhase1 LBC1 to LBC2 TPhase2 TPhase3 TPhase4 Conditions Min Max Units b 1.5 1.5 ns 10 20 ns PHASE SEL e Low 3 13 ns PHASE SEL e High 43 53 ns PHASE SEL e Low 11 21 ns PHASE SEL e High 11 21 ns PHASE SEL e Low 19 29 ns PHASE SEL e High 59 69 ns PHASE SEL e Low 27 37 ns PHASE SEL e High 27 37 ns b4 6 ns (Note 1) LBC1 to LBC3 LBC1 to LBC4 LBC1 to LBC5 T3 LSC to LBC1 T4 LSC Positive Pulse Width 12 19 ns T5 REF IN to FEEDBK IN In Lock (Note 1) b3 3 ns T6 TXC Positive Pulse Width (Note 1) 3.5 4.5 ns T7 LBC Positive Pulse Width 35 45 ns Note 1: These parameters are not tested, but are assured by correlation with characterization data. TL/F/10385 – 4 FIGURE 4-1. AC Timing Waveforms 8 4.0 Electrical Characteristics (Continued) 4.4 AC ELECTRICAL CHARACTERISTICS (Continued) TL/F/10385 – 5 FIGURE 4-2. Typical Clock Relationships 9 Loop Filter Calculations Let us now design an example system with the following characteristics: Several constants need to be known in order to determine the loop filter components. They are the loop divide ratio, N, the phase detector gain, Kp, the VCO gain, Ko, the loop bandwidth, Wo, and the phase margin, w. The constants Kp and Ko for the DP83241 are fixed at 80 mA/rad and 0.8 Grad/V respectively. N is equal to the VCO frequency divided by the reference frequency. wo is recommended to be less than 1/20th of the reference frequency (times 2q rads). Having found all these constants, the following equations are used to find the component values: For w e 57§ phase margin: # 12.5 MHz Crystal reference. # 250 MHz VCO. Since the VCO is twenty times the frequency of the reference frequency, we get N e 20. We will set wo to be 1/30th of the reference frequency or 2.62 x 106 Rad. From these values we get: C1 e 1400 pF, C2 e 140 pF, and R1 e 900X Let us now design an example system with the following characteristics: R1 e (1.1 N wo)/(Kp Ko) C1 e (3 Kp Ko)/(N wo2) # 12.5 MHz Crystal reference. # 250 MHz External VCO with a gain of 40 MRad/V. C2 e (0.3 Kp Ko(/(N wo2) For a phase margin other than 57§ : R1 e (Cosec w a 1) ((N wo/2 Kp Ko)) C1 e (Tan w) ((2 Kp Ko)/(N wo2)) C2 e (Sec w b Tan w) ((Kp Ko/(N wo2)) The component equations above are not meant to provide optimal solutions for all implementations. We will set wo to be 1/78th of the reference frequency or 1.0 x 106 Rad. From these values we get: C1 e 470 pF, C2 e 47 pF, and R1 e 6.8 kX. TL/F/10385 – 27 10 5.0 Detailed Information 5.1 EXTERNAL COMPONENTS The Filter components are based on a 12.5 MHz Crystal and a 250 MHz VCO. TL/F/10385 – 6 All component values g 10%. FIGURE 5-1. General Wiring Diagram The Filter components are based on a 12.5 MHz Crystal and an external 250 MHz VCO with a gain of 40 MRad/V. All component values g 10%. FIGURE 5-2. General Wiring Diagram with an External VCO 11 TL/F/10385 – 7 5.0 Detailed Information (Continued) TABLE 5-1. Special External Components Crystal Resonator: Part Ý: Manufacturer: Key Specifications: C5410N NEL 12.5000 MHz Center Frequency, 20 PPM Accuracy, 0§ C to a 70§ C 15 pF Load Capacitance Varactor Diode: PartÝ: Manufacturer: Key Specifications: MV2105 Motorola Cap Tolerance g 10% VHF NPN Transistor: PartÝ: Manufacturer: Key Specifications: PN3563 National Semiconductor Inductor: PartÝ: Manufacturer: Key Specifications: 1(/2 Turns period and the skew between the CDD devices on the two boards is minimal. In a larger concentrator configuration where this skew becomes too large, the data setup time of the downstream station will be directly impacted. One way to avoid this problem is to latch data into the next station. The strobe for the latch will be supplied by one of the LBC outputs from the upstream station’s CDD device. An LBC output phase is chosen that occurs after the physical layer data is stable. Assuming that the data and LBC flight times are equal, the LBC output will latch data for the next station. The LBC output phase should be selected to give the optimum setup and hold time for the receiving station’s physical layer function. 5.2 CONCENTRATOR AND DUAL ATTACH STATION CONFIGURATIONS 5.2.1 Concentrator Applications An application where many of the features of the CDD device are used is a FDDI concentrator. A concentrator is used to connect several workstations and peripherals to a single node in the network. A concentrator provides the ability to easily bypass or insert multiple stations into the network. The CDD device in each station is driven from a common oscillator instead of each CDD device being driven by its own crystal. In a small concentrator, the same LBC phase can be used in each station since the data flight time from one board to another is small compared to the LBC TL/F/10385 – 8 FIGURE 5-3. Small Concentrator Application 12 5.0 Detailed Information (Continued) TL/F/10385 – 9 FIGURE 5-4. Large Concentrator Application TL/F/10385 – 10 Ta Tb Tc Td e Time to latch data out of the Physical Layer (Board 1) e Data flight time e Latch delay e Ideal setup time for incoming data e Td1 a Td2 a Td3 Td1 e Reference error between CDD devices Td2 e Minimum phase resolution of CDD device e 8 ns Td3 e Setup time FIGURE 5-5. Large Concentrator Timing 13 5.0 Detailed Information (Continued) needed at the CDD device for this method of routing the ECL signals. The value of this resistor can be calculated from the following equation: 5.2.2 CDD Device Driving Multiple PLAYER Devices In a FDDI concentrator or dual attach station, it may be necessary for a single DP83241 Clock Distribution Device (CDD device) to drive multiple DP83251/55 PLAYER devices. Since these PLAYER devices will be running synchronously to each other they must have the same clocks. The easiest way to accomplish this is to have one CDD device drive multiple PLAYER devices. We are only concerned with the ECL outputs being able to drive multiple loads. The conventional way of directly wiring the one output to many inputs will not work. If the ECL signals are split into multiple traces then reflections will result which may ruin the signal’s integrity. An appropriate method, where individual traces with a series resistor connected to each load, is used instead. The series resistor should match the line impedance and be placed as close to the CDD device as possible. The resistor will act as a voltage divider and cut the voltage level of the signal in half. When this modified signal reaches the input of the unterminated gate, reflections will cause the signal to double and the receiving input will see the full voltage swing. The reflection will then travel back towards the CDD device, but the series resistance will stop this action. An emitter pulldown resistor is Re (Max) e 10 Zo b RS n Where: Re (Max) Ð Largest emitter pulldown resistor that can be used n Ð Number of parallel lines being driven Zo Ð Trace impedance RS Ð Series damping resistor Another method for sending the ECL signal to multiple players is to route the ECL signal as a bus line and have each load connected to the bus. The ECL bus line must be terminated only at the very end with a matching impedance (e.g.: a 50X line will be terminated with a 50X load to VCC b 2V). It is preferred that the input pin be directly connected to the bus and not have a signal tap connected to the bus. However, if a tap off the bus is necessary, the shortest possible tap is recommended. TL/F/10385 – 12 FIGURE 5-7. CDD Device Driving Four PLAYER Devices in Parallel 14 5.0 Detailed Information (Continued) As with any high speed signal, the routing of the signal must be carefully done. Sharp corners and other changes in trace impedance should be avoided to reduce reflections in high speed signal traces. Traces longer then one inch should have a series or parallel termination scheme. Further system considerations can be found in National’s F100K Design Guide. If these methods are followed the DP83241 signals will be able to drive multiple DP83251/55 PLAYER devices without any problems. The most conservative method for routing the ECL signals to multiple loads is to use the F100115 Quad Low Skew Driver. This device takes a differential ECL signal and outputs four of the same differential signals with a skew between them of less than 75 ps. Two of these devices will allow the CDD device to drive four PLAYER devices. This setup allows the ECL signals to be routed in a point to point configuration to each PLAYER device. TL/F/10385 – 13 FIGURE 5-8. Proper Bus Line Termination and Connections TL/F/10385 – 14 § Parallel Termination FIGURE 5-9. CDD Device Driving Four PLAYER Devices Using Two F100115 Quad Low Skew Drivers 15 5.0 Detailed Information (Continued) 5.3 LAYOUT RECOMMENDATIONS # The part should be bypassed between the EXTVCC and EXTGND as close to the chip as possible (preferably under the chip using chip caps). The part should also be bypassed between the DVCC and DGND as close to the chip as possible. # The external crystal circuitry should be connected to # The part should be bypassed between AVCC and AGND isolated branch of the DGND pin, connected through a ferrite bead or small inductor. Ground on an isolated branch off of the DGND pin. # The DGND pin should be connected to Ground off of an isolated branch of the EXTGND pin, connected through a ferrite bead or small inductor. # The AGND pin should be connected to Ground off of an as close to the chip as possible. # No TTL logic lines should pass through the external crys- # If the part is being driven by an external reference, the tal or filter circuitry areas to avoid the possibility of noise due to crosstalk. # If using a multilayered board with dedicated VCC and XTL IN pin should be tied to either GND or VCC. # The filter circuitry should be connected to Ground on an Ground planes, ensure that the external crystal circuitry has its own small isolated ground island that is connected to the AGND, DGND and EXTGND pins as described above. isolated branch off of the AGND pin. # The DVCC pin should be connected to VCC on an isolated branch off of the EXTVCC pin, preferably being connected through a ferrite bead or small inductor. # See Figure 5.1 for component values. # For best performance tie the VCORST pin to AGND. # The AVCC pin should be connected to VCC on an isolated branch off of the DVCC pin, preferably being connected through a ferrite bead or small inductor. This drawing was done with convenience in mind. TL/F/10385 – 15 Note: Pin 7 need not be hooked up. FIGURE 5-10. Recommended Layout 16 5.0 Detailed Information (Continued) 5.4 INPUT AND OUTPUT SCHEMATICS XVCO IN, XVCO INB XTL IN, XTL OUT TL/F/10385 – 17 TL/F/10385 – 16 Filter TTL Outputs: LBC1 – LBC5, Symbol Clock TL/F/10385 – 18 CMOS Inputs: REF IN, FEEDBK IN, PHASE SEL, VCO RST, VCO SEL TL/F/10385 – 19 Typical ESD Structure TXC a , TXCb, TBC a , TBCb TL/F/10385 – 21 TL/F/10385 – 22 TL/F/10385 – 20 17 5.0 Detailed Information (Continued) 5.5 SYSTEM DEBUGGING FLOWCHART TL/F/10385 – 23 Note 1: If the crystal oscillator is chosen as the input reference source then the XTL OUT pin should be checked for the correct frequency of oscillation. If the oscillator fails to oscillate then the DC voltage on these pins should be checked and be equal to approximately VCC d 2 (with or without the crystal oscillator present). 5.6 AC TEST CIRCUITS TL/F/10385 – 26 FIGURE 5-12. Switching Test Circuit for All ECL Output Signals TL/F/10385–24 FIGURE 5-11. Switching Test Circuit for All TTL Output Signals 18 19 DP83241 CDD Device (FDDI Clock Distribution Device) Physical Dimensions inches (millimeters) Plastic Chip Carrier (V) Order Number DP83241BV NS Package Number V28A LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. National Semiconductor Corporation 1111 West Bardin Road Arlington, TX 76017 Tel: 1(800) 272-9959 Fax: 1(800) 737-7018 2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. National Semiconductor Europe Fax: (a49) 0-180-530 85 86 Email: cnjwge @ tevm2.nsc.com Deutsch Tel: (a49) 0-180-530 85 85 English Tel: (a49) 0-180-532 78 32 Fran3ais Tel: (a49) 0-180-532 93 58 Italiano Tel: (a49) 0-180-534 16 80 National Semiconductor Hong Kong Ltd. 13th Floor, Straight Block, Ocean Centre, 5 Canton Rd. Tsimshatsui, Kowloon Hong Kong Tel: (852) 2737-1600 Fax: (852) 2736-9960 National Semiconductor Japan Ltd. Tel: 81-043-299-2309 Fax: 81-043-299-2408 National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications.